UG120

UG01 ATMEL | Alldatasheet

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/C0068High performance ULC family suitable for medium- to large-sized CPLDs and FPGAs /C0068Conversions to over 200,000 FPGA gates /C0068Pin counts to over 300 pins /C0068Any pin-out matched due to limited number of dedicated pads /C0068Advanced 0.6-µm (drawn)/0.45-µm (effective) feature size /C0068Triple-layer or dual-layer metal CMOS technology /C0068High speed performance: – 250-ps typical cell delay – 350-MHz toggle rate /C0068Full range of packages: DIP, SOIC, LCC/PLCC, PQFP/TQFP, PGA/PPGA /C00683.3V and/or 5.0V operation. /C0068Low quiescent current: 0.4 nA/gate /C0068Available in commercial, industrial, automotive, military and space grades. 0.6µm ULC Series

5–2 Rev. B – 25 May. 98 Product Outline Part Number Full programmables Pads Equivalent FPGA Gates Maximum Drive UG01 30 3300 N/A UG04 48 7500 310 UG09 72 15800 790 UG14 88 24300 1210 UG20 104 34800 1740 UG33 130 46000 2880 UG42 146 58600 3660 UG52 162 63700 4550 UG70 188 85800 6130 UG90 212 108500 7750 UG120 244 145100 10360 UG140 264 156800 12250 Architecture The basic element of the UG family is called a cell. One cell can typically implement between two to three FPGA gates. Cells are located contiguously through out the core of the device, with routing resources provided in two or three metal layers above the cells. Some cell blockage does occur due to routing, and utilization will be significantly greater with three metal routing than two. The sizes listed in the Product Outline are estimated usable amounts using three metal layers. I/O cells are provided at each pad, and may be configured as inputs, outputs, I/Os, V DD or VSS as required to match any FPGA or PLD pinout. Special function cells and pins are located in the corners which typically are unused. In order to improve noise immunity within the device, separate V DD and V SS busses are provided for the internal cells and the I/O cells. I/O Options Inputs Each input can be programmed as TTL, CMOS, or Schmitt Trigger, with or without a pull up or pull down resistor. Fast Output Buffer Fast output buffers are able to source or sink 3 to 12 mA according to the chosen option. 24mA achievable, using 2 pads. Slew Rate Controlled Output Buffer In this mode, the p- and n-output transistor commands are delayed, so that they are never set “ON ” simultaneously, resulting in a low switching current and low noise. These buffer are dedicated to very high load drive. 3.3V Compatibility The UG series of ULCs is fully capable of supporting high-performance operation at 3.3V or 5.0V . The performance specifications of any given ULC design however, must be explicitly specified as 3.3V , 5.0V or both. Power Supply and Noise Protection In order to improve the noise immunity of the UG series, several mechanisms have been implemented inside the UG devices. Two kinds of protection have been added: one to limit the I/O buffer switching noise and the other to protect the I/O buffers against the switching noise coming from the core. I/O buffers switching protection Three features are implemented to limit the noise generated by the switching current: The power supplies of the input and output buffer are separated. The rise and fall times of the output buffers can be controlled. The number of buffers that are connected on the same power supply line is limited.

5–3Rev. B – 25 May. 98 Core switching current protection This noise disturbance is caused by a large number of gates switching simultaneously. To allow this without impacting the functionality of the circuit, three new features have been added: Some decoupling capacitors are integrated directly on the silicon to reduce the power supply drop. A power supply network has been implemented in the matrix. This solution lessens the parasitic elements such as inductance and resistance and constitutes an artificial V DD and VSS plane. One mesh of the network supplies approximately 150 cells. A low-pass filter has been added between the core and the inputs of the output buffers. This limits the transmission of the noise coming from the ground or the V DD supply of the core via the output buffers. Absolute Maximum Ratings Recommended Operating Range Operating Temperature DC Characteristics Parameter Symbol Base Part TA = Commercial Min Typ Max Unit V OH IOH = 24, 12, 6, 3 depending on buffer2.4 Output V oltage V OL IOL = –24, –12, –6, –3 depending on buffer 0.4 V IH 2.0 V Input V oltage V IL 0.8 V IN = VSS –5 –1 V IN = VDD 1 5 Input Leakage Current IIX V IN = VSS, with pull-up –100 –40 µA V IN = VDD , with pull-down 40 100 µ Output Leakage Current IOZ V OUT = VSS or VDD –5 /C00341 5 V OUT = VDD 90 160 Output Short Circuit Current IOS V OUT = VSS –130 –60 mA Standby Current ICCSB V DD = 5.25 V , VIN = VSS 0.4 1 nA/Gate Operating Current IDDOP 0.3 0.4 µA/Gate/ MHz Input Capacitance C IN V DD = 5.0 V , VIN = 2.0 V 2.5 Output Capacitance C OUT V OUT = 2.0 V 2 pF Notes: a. IOH = 24, 12, 6,3. Selection determined by FPGA or PLD data sheet requirements.

5–4 Rev. B – 25 May. 98 Internal Timing Characteristics These timing parameters for selected macro cells are provided for information only. Only pin-to-pin timing characteristics are guaranteed for ULCs, and the actual specification is determined by the original FPGA or PLD data sheet plus any specific parameters that are agreed to separately by Atmel Wireless & Microcontrollers. Conditions: V DD = 5 V , Typical Process, Statistical Wire Length. All delays measured at VIN/VOUT = 2.5 V . Macro Type Parameter Symbol Min Max a Max b Units 2-Input NAND NAND2 0.39 0.56 4-Input NAND NAND4 0.68 0.88 Inverter INV Propagation Time tPD 0.41 0.68 ns 0.74 0.99 Inverting Tri-State Buffer TRISTAN Enable Time tEN 0.69 0.97 Setup Time tSU 0.60 Hold Time tH 0.00 Pulse Width tPW Resetable Latch LATCHR Propagation Time tDQ 0.97 1.25 Enable Time tEN 1.22 1.49 Reset Time tRN 0.87 1.10 Setup Time tSU 0.40 Hold Time tH 0.00 D Flip-Flop with Reset FDFFR Pulse Width tPW 0.60 Clock Delay Time tCQ 0.95 1.22 Reset Time tRN 0.81 0.94 TTL Compatible Input tPLH 0.80 0.95TTL Compatible Input Buffer BUFINTTL tPHL 0.68 0.74 ns TTL Compatible I/O Buffer tPLH 0.80 0.95TTL Compatible I/O Buffer Input Mode BIOT12 tPHL 0.68 0.74 Propagation Time tPLH 2.97 8.18 Output Buffer BOUT6 tPHL 1.96 4.23 tPLH 2.49 6.42 tPLH 1.74 3.47 TTL Compatible I/O Buffer BIOT12 tPZH 3.27 7.17 Enable Time tPZL 1.60 3.30 tPLH 2.49 6.42 Propagation Time tPHL 1.74 3.47 Tri-State Output Buffer B3STA12 tPZH 3.27 7.17 Enable Time tPZL 1.60 3.30 Notes a. Fan-outs are three internal loads for NAND2 and NAND4, four loads for all other internal macros and input buffers. Loading of BOUT6 is 20 pF , BIOT12 and B3STA12 are 30 pF . b. Fan-outs are six internal loads for NAND2, seven loads for NAND4, nine loads for all other internal macros and eight for the input buffer. Loading of B OUT6 is 80 pF , BIOT12 and B3STA12 are 120 pF .

5–5Rev. B – 25 May. 98 Derating Factors: tP = KP x Kt x KV x tNOMINAL Process Process Best Nominal Worst K P 0.82 1.00 1.28 Ambient Temperature /C0095C TA –55 –40 0 25 70 85 125 Supply Voltage External Timing Characteristics (Over the Operating Range) These timing parameters are provided for information only. Actual pin-to-pin timing characteristics guaranteed for ULCs are determined by the original FPGA or PLD data sheet plus any specific parameters that are agreed to separately by Atmel Wireless & Microcontrollers. Max Parameter Symbol Base Part SSO Min Typ Max Unit UG01 5.0 7.5 UG04 –UG09 6.0 9.0 Propagation Time tPD UG14 –UG20 7.0 10.5 UG33 –UG90 8.5 13.0 UG120 –UG140 9.5 14.5 UG01 32 6.5 10.0 UG04 –UG09 50 7.5 11.5 Clock Delay Time tCO UG14 –UG20 100 8.5 13.0 UG33 –UG90 220 10.0 15.0 ns UG120 –UG140 300 11.0 16.5 Hold Time tH 0.0 UG01 32 6.5 10.0 UG04 –UG09 50 7.5 11.5 Output Enable Time tEN UG14 –UG20 100 8.5 13.0 UG33 –UG90 220 10.0 15.0 UG120 –UG140 300 11.0 16.5

5–6 Rev. B – 25 May. 98 Power Consumption Static Power Consumption for UG Series ULCs There are three main factors to consider: – Leakage in the core: – PLC = VDD * ICCSB * number of used gates – Leakage in inputs and tri-stated outputs: – PLIO = VDD * (IIX * N + IOZ * M) – where: N = number of inputs – M = number of tri-stated outputs – Care must be taken to include the appropriate figure for pins with pull-ups or pull-downs. In practice, the static consumption calculation is typically done to determine the standby current of a device; in this case only those pins sourcing current should be included, i.e. where V IN or V OUT = VDD . – Dc power dissipation in driving I/O buffers due to resistive loads: – In practice, the static consumption calculation is typically done to determine the standby current of a device, and under circumstances where all of the outputs are tri-stated or in input mode. So this term is zero. – Global formula for static consumption: – P SB = PLC + PLIO Dynamic Power Consumption for UG Series ULCs There are four main factors to consider: – Static power dissipation is negligible compared to dynamic and can be ignored. – Dc power dissipation in I/O buffers due to resistive loads: – P1 (mW) = VOL * Σn (DLn * IOLn ) + ( VDD – VOH ) * Σn (DHn * IOHn ) – where: Σn is a summation over all of the outputs and I/Os. – IOLn and IOHn are the appropriate values for driver n – D Ln = percentage of time n is being driven to VOL – D Hn = percentage of time n is being driven to V OH – It is difficult to obtain an exact value for this factor, since it is determined primarily by external system parameters. However, in practice this can be simplified to one of two cases where the device is either driving CMOS loads or driving TTL loads. CMOS loads can be approximated as purely capacitive loads, allowing this term to be treated as zero. TTL loads source significant current in the low state, but not the high state, allowing the second summation to be ignored. If a 50% duty cycle is assumed for dynamic outputs driving TTL loads, this can be approximated as: – P 1 (mW) = VOL * (Σn * IOLn /2 + Σm * IOLm ) (TTL loads) – where n are dynamic outputs and m are static low outputs. – Dynamic power dissipation for the internal gates: – P2 (mW) = VDD * IDDOP * Σg (Nf * fg)/1000 – where: N f = number of gates toggling at frequency fg – fg = clock frequency of internal logic in MHz – Note: If the actual toggle rates are not known, a rule of thumb is to assume that the average used gate is toggling at one half of the input clock frequency. – Dynamic power dissipation in the outputs: – P3 (mW) = VDD 2 * Σn fn * (COUT + Cn)/1000 – where: fn = clocking frequency in MHz of output n – C n = output load capacitance in pF of output n – C OUT = output capacitance from DC Characteristics – Global formula for dynamic consumption: – P = P1 + P2 + P3 Example: Static calculation – A 100-pin ULC with 3000 used gates, 10 inputs, 20 I/Os in input mode, 40 outputs all tri-stated. No pull-ups or pull-downs. Half of the pins are at V DD , half at VSS. Input clock is not toggling. For this example only the current calculation is desired, so the VDD term in the equations is dropped. – PLC = 1 * 3000 = 3 mA – PSB = 3 + 105 = 108 mA Dynamic Calculation – We take a 16-bit resettable ripple counter which is approximately 100 gates, operating at a clock frequency of 33 MHz, which gives an average clock frequency of 33 MHz/16 for each bit and each output. There are no static outputs on this device. Operation is at 5 V , and 6-mA outputs are used and loaded at 25 pF. The output buffers are driving CMOS loads.

conditions during transitions. Figure 5. Typical ULC Test Conditions