ATAR862-4

ATAR862-4 ATMEL | Alldatasheet

Document overview

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Technical content

Features

• Single Package Fully-integrated ROM Mask 4-bit Microcontroller with RF Transmitter
• Low Power Consumption in Sleep Mode (< 1 µA Typically)
• Maximum Output Power (10 dBm) with Low Supply Current (9.5 mA Typically)
• 2.0 V to 4.0 V Operation Voltage for Single Li-cell Power Supply
• -40°C to +125°C Operation Temperature
• SSO24 Package
• About Seven External Components
• Flash Controller for Application Program Available

Description

The ATAR862-4 is a single package triple-chip circuit. It combines a UHF ASK/FSK transmitter with a 4-bit microcontroller and a 512-bit EEPROM. It supports highly inte- grated solutions in car access and tire pressure monitoring applications, as well as manifold applications in the industrial and consumer segment. It is available for the frequency range of 429 MHz to 439 MHz with data rates up to 32 kbaud. For further frequency ranges such as 310 MHz to 330 MHz and 868 MHz to 928 MHz separate data sheets are available. The device contains a ROM mask version microcontroller and an additional data EEPROM. Figure 1. Application Diagram

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Figure 2. Pinning SSO24

1 XTAL Connection for crystal

2 VS Supply voltage ESD protection circuitry (see Figure 8)

3 GND Ground ESD protection circuitry (see Figure 8)

4 ENABLE Enable input

4552B–4BMCU–02/03

21 CLK Clock output signal for microcontroller

The clock output frequency is set by the crystal to fXTAL/4

22 PA_ENABLE Switches on power amplifier, used for

Emitter of antenna output stage Open collector antenna output Pin Description: RF Part (Continued) Pin Symbol Function Configuration CLK VS 100 100 PA_ENABLE 50k Uref=1.1V 20 mA ANT1 ANT2 Pin Description: Microcontroller Part Name Type Function Alternate Function Pin-No. Reset State VDD – Supply voltage – 13 NA VSS – Circuit ground – 12 NA BP20 I/O Bi-directional I/O line of Port 2.0 NTE-test mode enable, see also section "Master Reset" 7 Input BP40 I/O Bi-directional I/O line of Port 4.0 SC-serial clock or INT3 external interrupt input 14 Input BP41 I/O Bi-directional I/O line of Port 4.1 VMI voltage monitor input or T2I external clock input Timer 2 9 Input BP42 I/O Bi-directional I/O line of Port 4.2 T2O Timer 2 output 10 Input BP43 I/O Bi-directional I/O line of Port 4.3 SD serial data I/O or INT3-external interrupt input 11 Input BP50 I/O Bi-directional I/O line of Port 5.0 INT6 external interrupt input 17 Input BP52 I/O Bi-directional I/O line of Port 5.2 INT1 external interrupt input 16 Input BP53 I/O Bi-directional I/O line of Port 5.3 INT1 external interrupt input 15 Input BP60 I/O Bi-directional I/O line of Port 6.0 T3O Timer 3 output 20 Input BP63 I/O Bi-directional I/O line of Port 6.3 T3I Timer 3 input 6 Input OSC1 I Oscillator input 4-MHz crystal input or 32-kHz crystal input or external clock input or external trimming resistor input 18 Input OSC2 O Oscillator output 4-MHz crystal output or 32-kHz crystal output or external clock input 19 Input NRESET I/O Bi-directional reset pin – 5 I/O

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4552B–4BMCU–02/03 UHF ASK/FSK Transmitter Block

• Integrated PLL Loop Filter
• ESD Protection (4 kV HBM/200 V MM, Except Pin 2: 4 kV HBM/100 V MM) also at ANT1/ANT2
• Maximum Output Power (10 dBm) with Low Supply Current (9.5 mA Typically)
• Modulation Scheme ASK/FSK – FSK Modulation is Achieved by Connecting an Additional Capacitor between the XTAL Load Capacitor and the Open- drain Output of the Modulating Microcontroller
• Easy to Design-in Due to Excellent Isolation of the PLL from the PA and Power Supply
• Supply Voltage 2.0 V to 4.0 V in the Temperature Range of -40°C to +125°C
• Single-ended Antenna Output with High Efficient Power Amplifier
• External CLK Output for Clocking the Microcontroller
• 125°C Operation for Tire Pressure Systems

The PLL transmitter block has been developed for the demands of RF low-cost transmission systems, at data rates up to 32 kbaud. The transmitting frequency range is 429 MHz to 439 MHz. It can be used in both FSK and ASK systems.

Figure 3. Block Diagram

4 K x 8 bit

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4552B–4BMCU–02/03 General Description The fully-integrated PLL transmitter that allows particularly simple, low-cost RF minia- ture transmitters to be assembled. The VCO is locked to 32 f XTAL, thus, a 13.56 MHz crystal is needed for a 433.92 MHz transmitte r. All other PLL and VCO peripheral ele- ments are integrated. The XTO is a series resonance oscillator so that only one capacitor together with a crystal connected in series to GND are needed as external elements. The crystal oscillator together with the PLL needs maximum < 1 ms until the PLL is locked and the CLK output is stable. A wait time of /g1791 ms until the CLK is used for the microcontroller and the PA is switched on. The power amplifier is an open-collector output delivering a current pulse which is nearly independent from the load impedance. The delivered output power is controlled via the connected load impedance. This output configuration enables a simple matching to any kind of antenna or to 50/g87. A high power efficiency of /g104=P out/(IS,PA V S) of 36% for the power amplifier results when an optimized load impedance of ZLoad = (166 + j223) /g87 is used at 3 V supply voltage. Functional If ENABLE = L and PA_ENABLE = L, the circuit is in standby mode consuming only a very small amount of current so that a lithium cell used as power supply can work for several years. With ENABLE = H, the XTO, PLL and the CLK driver are switched on. If PA_ENABLE remains L, only the PLL and the XTO are running and the CLK signal is delivered to the microcontroller. The VCO locks to 32 times the XTO frequency. With ENABLE = H and PA_ENABLE = H, the PLL, XTO, CLK driver and the power amplifier are on. With PA_ENABLE, the power amplifier can be switched on and off, which is used to perform the ASK modulation. ASK Transmission The PLL transmitter block is activated by ENABLE = H. PA_ENABLE must remain L for t /g1791 ms, then the CLK signal can be taken to clock the microcontroller and the output power can be modulated by means of pin PA_ENABLE. After transmission, PA_ENABLE is switched to L and the microcontroller switches back to internal clocking. The PLL transmitter block is switched back to standby mode with ENABLE = L. FSK Transmission The PLL transmitter block is activated by ENABLE = H. PA_ENABLE must remain L for t /g1791 ms, then the CLK signal can be taken to clock the microcontroller and the power amplifier is switched on with PA_ENABLE = H. The chip is then ready for FSK modula- tion. The microcontroller starts to switch on and off the capacitor between the XTAL load capacitor and GND with an open-drain output port, thus changing the reference fre- quency of the PLL. If the switch is closed, the output frequency is lower than if the switch is open. After transmission PA_ENABLE is switched to L and the microcontroller switches back to internal clocking. The PLL transmitter block is switched back to standby mode with ENABLE = L. The accuracy of the frequency deviation with XTAL pulling method is about ±25% when the following tolerances are considered.

Figure 4. Tolerances of Frequency Modulation CMOS compatible if the load capacitance is lower than 10 pF. of the transmission IC, so the message can be sent with crystal accuracy. low resistive path to VS to deliver the DC current. power amplifier is compensated by the load impedance. application for a power amplifier. parallel imaginary part should be kept constant. Also the damping of the cable used to measure the output power must be calibrated.

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Figure 5. Output Power Measurement have the possibility to realize the ZLoad,opt by using standard valued capacitors. as possible to the pins ANT1 and ANT2. 15 pF load-capacitance crystal.

Figure 6. ASK Application Circuit

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Figure 7. FSK Application Circuit

4552B–4BMCU–02/03 Figure 8. ESD Protection Circuit

Electrical Characteristics

VS = 2.0 V to 4.0 V, Tamb = -40/g176C to 125/g176C unless otherwise specified. Typical values are given at VS = 3.0 V and Tamb = 25/g176C. All parameters are referred to GND (Pin 7). Parameters Test Conditions Symbol Min. Typ. Max. Unit Supply current Power down, VENABLE < 0.25 V, -40/g176C to 85/g176C VPA-ENABLE < 0.25 V, -85/g176C to +125/g176C VPA-ENABLE < 0.25 V, 25/g176C (100% correlation tested) IS_Off <10 350 nA µA nA Supply current Power up, PA off, V S = 3 V VENABLE > 1.7 V , VPA - E N AB L E<0 . 2 5V IS 3.7 4.8 mA Supply current Power up, V S = 3.0 V VENABLE > 1.7 V , VPA - E N AB L E>1 . 7V IS_Transmit 91 1 . 6 m A Output power V S = 3.0 V , Tamb =2 5/g176C f = 433.92 MHz, ZLoad = (166 + j233) /g87 PRef 5.5 7.5 10 dBm

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4552B–4BMCU–02/03 Output power variation for the full temperature range Tamb = -40/g176C to +85/g176C VS = 3.0 V VS = 2.0 V /g68PRef /g68PRef -1.5 -4.0 dB dB Output power variation for the full temperature range Tamb = -40/g176C to +125/g176C VS = 3.0 V VS = 2.0 V POut = PRef + /g68PRef /g68PRef /g68PRef -2.0 -4.5 dB dB Achievable output-power range Selectable by load impedance P Out_typ 07 . 5 d B m Spurious emission f CLK = f0/128 Load capacitance at Pin CLK = 10 pF fO ± 1/g180fCLK fO ± 4 /g180fCLK other spurious are lower -55 -52 dBc dBc Oscillator frequency XTO (= phase comparator frequency) fXTO = f0/32 fXTAL = resonant frequency of the XTAL, CM /g163 10 fF , load capacitance selected accordingly Tamb = -40/g176C to +85/g176C Tamb = -40/g176C to +125/g176C fXTO -30 -40 fXT AL +30 +40 ppm ppm PLL loop bandwidth 250 kHz Phase noise of phase comparator Referred to fPC = fXT0, 25 kHz distance to carrier -116 -110 dBc/Hz In loop phase noise PLL 25 kHz distance to carrier -86 -80 dBc/Hz Phase noise VCO at 1 MHz at 36 MHz -94 -125 -90 -121 dBc/Hz dBc/Hz Frequency range of VCO f VCO 429 439 MHz Clock output frequency (CMOS microcontroller compatible) f0/128 MHz Voltage swing at Pin CLK C Load /g163 10 pF V 0h V0l VS /g1800.8 VS /g1800.2 V V Series resonance R of the crystal Rs 110 /g87 Capacitive load at Pin XT0 7p F FSK modulation frequency rate Duty cycle of the modulation signal = 50% 03 2 k H z ASK modulation frequency rate Duty cycle of the modulation signal = 50% 03 2 k H z ENABLE input Low level input voltage High level input voltage Input current high VIl VIh IIn 1.7 0.25 V V µA PA_ENABLE input Low level input voltage High level input voltage Input current high V Il VIh IIn 1.7 0.25 V V µA Electrical Characteristics (Continued) VS = 2.0 V to 4.0 V, Tamb = -40/g176C to 125/g176C unless otherwise specified. Typical values are given at VS = 3.0 V and Tamb = 25/g176C. All parameters are referred to GND (Pin 7). Parameters Test Conditions Symbol Min. Typ. Max. Unit

• 4-Kbyte ROM, 256 x 4-bit RAM
• 16 Bi-directional I/Os
• Up to Seven External/Internal Interrupt Sources
• Multifunction Timer/Counter – IR Remote Control Carrier Generator – Biphase-, Manchester- and Pulse-width Modulator and Demodulator – Phase Control Function
• Programmable System Clock with Prescaler and Five Different Clock Sources
• Supply-voltage Range (2.0 V to 4.0 V)
• Very Low Sleep Current (< 1 µA)
• 32 x 16-bit EEPROM (ATAR892 Only)
• Synchronous Serial Interface (2-wire, 3-wire)
• Watchdog, POR and Brown-out Function
• Voltage Monitoring Inclusive Lo_BAT Detect
• Flash Controller T48C862 Available (SSO24) Description The ATAR862-4 is a member of Atmel’s family of 4-bit single-chip microcontrollers. It offers highest integration for IR and RF data communication, remote-control and phase- control applications. The ATAR862-4 is suitable for the transmitter side as well as the receiver side. It contains ROM, RAM, par allel I/O ports, two 8-bit programmable multi- function timer/counters with modulator and demodulator function, voltage supervisor, interval timer with watchdog function and a sophisticated on-chip clock generation with external clock input, integrated RC-oscillator, 32-kHz and 4-MHz crystal-oscillators. The ATAR862-4 has an EEPROM as a third chip in one package.

Figure 9. Block Diagram

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Table 1. Available Variants of M4xCx9x events. The MARC4 is designed for the high-level programming language qFORTH. high-level language programming without any loss of efficiency or code density. Figure 10. MARC4 Core

tines accessible with single byte instructions (SCALL). also be held in ROM and are accessed via the MARC4’s built-in table instruction. Figure 11. ROM Map of the Microcontroller Block address registers SP, RP, X and Y. counts. The return stack can also be used as a temporary storage area. definable location and maximum depth.

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Figure 12. RAM Map to fetch 8-bit wide ROM constants. Figure 13. Programming Mode l

4552B–4BMCU–02/03 RAM Address Registers The RAM is addressed with the four 8-bit wide RAM address registers: SP, RP, X and Y. These registers allow access to any of the 256 RAM nibbles. Expression Stack Pointer (SP) The stack pointer contains the address of the next-to-top 4-bit item (TOS-1) of the expression stack. The pointer is automatically pre-incremented if a nibble is moved onto the stack or post-decremented if a nibble is removed from the stack. Every post-decre- ment operation moves the item (TOS-1) to the TOS register before the SP is decremented. After a reset, the stack pointer has to be initialized with ">SP S0" to allo- cate the start address of the expression stack area. Return Stack Pointer (RP) The return stack pointer points to the top element of the 12-bit wide return stack. The pointer automatically pre-increments if an el ement is moved onto the stack, or it post- decrements if an element is removed from the stack. The return stack pointer incre- ments and decrements in steps of 4. This means that every time a 12-bit element is stacked, a 4-bit RAM location is left unwritten. This location is used by the qFORTH compiler to allocate 4-bit variables. After a reset the return stack pointer has to be initial- ized via ">RP FCh". RAM Address Registers (X and Y) The X and Y registers are used to address any 4-bit item in the RAM. A fetch operation moves the addressed nibble onto the TOS. A store operation moves the TOS to the addressed RAM location. By using either the pre-increment or post-decrement address- ing mode arrays in the RAM can be compared, filled or moved. Top of Stack (TOS) The top of stack register is the accumulator of the MARC4. All arithmetic/logic, memory reference and I/O operations use this register. The TOS register receives data from the ALU, ROM, RAM or I/O bus. Condition Code Register (CCR) The 4-bit wide condition code r egister contains the branch, the carry and the interrupt enable flag. These bits indicate the current state of the CPU. The CCR flags are set or reset by ALU operations. The instructions SET_BCF, TOG_BF, CCR! and DI allow direct manipulation of the condition code register. Carry/Borrow (C) The carry/borrow flag indicates that the borrowing or carrying out of arithmetic logic unit (ALU) occurred during the last arithmetic operation. During shift and rotate operations, this bit is used as a fifth bit. Boolean operations have no effect on the C-flag. Branch (B) The branch flag controls the conditional program branching. Should the branch flag has been set by a previous instruction, a condi tional branch will cause a jump. This flag is affected by arithmetic, logic, shift, and rotate operations. Interrupt Enable (I) The interrupt enable flag globally enables or disables the triggering of all interrupt rou- tines with the exception of the non-maskable reset. After a reset or while executing the DI instruction, the interrupt enable flag is reset, thus disabling all interrupts. The core will not accept any further interrupt requests until the interrupt enable flag has been set again by either executing an EI or SLEEP instruction.

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Figure 14. ALU Zero-address Operations contain only the operation to be performed and no source or destination address fields. refer to the “MARC4 Programmer’s Guide".

register and fetches the return address from the return stack to the program counter. interrupt service routine is not yet finished). interrupt active register are all reset. cycles depending on the state of the core). Figure 15. Interrupt Handling

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Table 2. Interrupt Priority Table Table 3. Hardware Interrupts

ing reset by any external circuitry representing a resistor of less than 150 k/g87. Figure 16. Reset Configuration circuitry. For reset generation no external components are needed. stopped). In this power-down mode the brown-out detection is disabled.

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register description for BOT programming. Figure 17. Brown-out Detection exactly the same manner as a reset stimulus from any of the above sources. (VIM) is reset in the VMC-register. BOT = 1, low brown-out voltage threshold 1.7 V (is reset value). BOT = 0, high brown-out voltage threshold 2.0 V.

Figure 18. Voltage Monitor

101 N o t a l l o w e d

000 N o t a l l o w e d

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Figure 19. Internal Supply Voltage Supervisor Figure 20. External Input Voltage Supervisor types: two RC-oscillators, one 4-MHz crystal oscillator and one 32-kHz crystal oscillator. or an external input clock can be selected to generate the system clock (SYSCL). with a tolerance of/g32/g177/g3215% over the full operating temperature and voltage range. below 500 kHz for more than 1 ms.

Figure 21. Clock Module Table 4. Clock Modes oscillator 1. It operates without any external components and saves additional costs. O /g1873.8 MHz. The RC oscillator 1 is selected by default after power-on reset.

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Figure 22. RC-oscillator 1 the CM-register, the supervisory circuit generates a hardware reset. Figure 23. External Input Clock connecting a resistor Rext =3 6 0k/g87 (see Figure 16).

110 E n a b l e

111 D i s a b l e

Figure 24. RC-oscillator 2 tor circuitry is integrated, except the actual crystal, resonator, C3 and C4. Figure 25. Ceramic Resonator 32-kHz crystal oscillator can not be stopped while the power-down mode is in operation.

4 MHz

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Figure 26. 32-kHz Crystal Oscillator stage. Writing to this register triggers the synchronization cycle.

4552B–4BMCU–02/03 System Configuration Register (SC) Primary register address: "3"hex Power-down Modes The sleep mode is a shut-down condition wh ich is used to reduce the average system power consumption in applications where the microcontroller is not fully utilized. In this mode, the system clock is stopped. The sleep mode is entered via the SLEEP instruc- tion. This instruction sets the interrupt enabl e bit (I) in the condition code register to enable all interrupts and stops the core. During the sleep mode the peripheral modules remain active and are able to generate interrupts. The microcontroller exits the sleep mode by carrying out any interrupt or a reset. The sleep mode can only be kept when none of the interrupt pending or active register bits are set. The application of the $AUTOSLEEP routine ensures the correct function of the sleep mode. For standard applications use the $AUTOSLEEP routine to enter the power-down mode. Using the SLEEP instruction instead of the $AUTOSLEEP following an I/O instruction requires to insert 3 non-I/O instruction cycles (for example NOP NOP NOP) between the IN or OUT command and the SLEEP command. The total power consumption is directly proportional to the active time of the microcon- troller. For a rough estimation of the expected average system current consumption, the following formula should be used: I total (VDD,fsyscl) = ISleep + (IDD/g32/g180/g32tactive/ttotal) IDD depends on VDD and fsyscl B i t 3B i t 2B i t 1B i t 0 SC: write BOT – OS1 OS0 Reset value: 1x11b BOT B rown-Out Threshold BOT = 1, low brown-out voltage threshold (1.7 V) BOT = 0, high brown-out voltage threshold (2.0 V) OS1 O scillator Select 1 OS0 O scillator Select 0 Mode OS1 OS0 Input for SUBCL Selected Oscillators 111 C in/16 RC-oscillator 1 and external input clock

201 C in/16 RC-oscillator 1 and RC-oscillator 2

310 C in/16 RC-oscillator 1 and 4-MHz crystal

400 3 2 k H z RC-oscillator 1 and 32-kHz crystal oscillator Note: If bit CCS = 0 in the CM-register, the RC-oscillator 1 always stops.

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32-kHz oscillator is selected, power consumption is extremely low. Table 5. Power-down Modes

Figure 27. Example of I/O Addressing

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Table 6. Peripheral Addresses

1 P1DAT W/R 1xx1b Port 1 - data register/input data M3

2 P2DAT W/R 1111b Port 2 - data register/pin data M2

3 SC W 1x11b System configuration register M3

4 P4DAT W/R 1111b Port 4 - data register/pin data M2

5 P5DAT W/R 1111b Port 5 - data register/pin data M2

6 P6DAT W/R 1xx1b Port 6 - data register/pin data M2

7 T12SUB W – Data to Timer 1/2 subport M1

0 T2C W 0000b Timer 2 control register M1

1 T2M1 W 1111b Timer 2 mode register 1 M1

2 T2M2 W 1111b Timer 2 mode register 2 M1

3 T2CM W 0000b Timer 2 compare mode register M1

4 T2CO1 W 1111b Timer 2 compare register 1 M1

5 T2CO2 W 1111 1111b Timer 2 compare register 2 (byte) M1

8 T1C1 W 1111b Timer 1 control register 1 M1

9 T1C2 W x111b Timer 1 control register 2 M1

8 ASW W 1111b Auxiliary/switch register ASW

9 STB W xxxx xxxxb Serial transmit buffer (byte) M2

0 T3M W 1111b Timer 3 mode register M1

1 T3CS W 1111b Timer 3 clock select register M1

2 T3CM1 W 0000b Timer 3 compare mode register 1 M1

3 T3CM2 W 0000b Timer 3 compare mode register 2 M1

4 T3CO1 W 1111 1111b Timer 3 compare register 1 (byte) M1

4 T3CP R xxxx xxxxb Timer 3 capture register (byte) M1

5 T3CO2 W 1111 1111b Timer 3 compare register 2 (byte) M1

4552B–4BMCU–02/03 Bi-directional Ports With the exception of Port 1 and Port 6, all other ports (2, 4 and 5) are 4 bits wide. Port 1 and Port 6 have a data width of 2 bits (bit 0 and bit 3). All ports may be used for data input or output. All ports are equipped with Schmitt trigger inputs and a variety of mask options for open-drain, open-source, full-complementary outputs, pull-up and pull-down transistors. All Port Data Registers (PxDAT) are I/O mapped to the primary address reg- ister of the respective port address and the Port Control Register (PxCR), to the corresponding auxiliary register. There are five different directional ports available: Port 1 2-bit wide bi-directional port with automatic full bus width direction switching. Port 2 4-bit wide bitwise-programmable I/O port. Port 5 4-bit wide bitwise-programmable bi-directional port with optional strong pull-ups and programmable interrupt logic. Port 4 4-bit wide bitwise-programmable bi-directional port also provides the I/O interface to Timer 2, SSI, voltage monitor input and external interrupt input. Port 6 2-bit wide bitwise-programmable bi-directional port also provides the I/O interface to Timer 3 and external interrupt input. Bi-directional Port 1 In Port 1 the data direction register is not independently software programmable, the direction of the complete port being switched automatically when an I/O instruction occurs (see Figure 21). The port is switched to output mode via an OUT instruction and to input via an IN instruction. The data written to a port will be stored into the output data latches and appears immediately at the port pi n following the OUT instruction. After RESET all output latches are set to "1" and the port is switched to input mode. An IN instruction reads the condition of the associated pins. Note: Care must be taken when switching the bi-directional port from output to input. The capacitive pin loading at this port in conjunction with the high resistance pull-ups may cause the CPU to read the contents of the output data register rather than the external input state. To avoid this, one of the following programming techniques should be used: Use two IN-instructions and DROP the first data nibble. The first IN switches the port from output to input and the DROP removes the first invalid nibble. The second IN reads the valid pin state. Use an OUT -instruction followed by an IN-instruction. Via the OUT -instruction, the capac- itive load is charged or discharged depending on the optional pull-up/pull-down configuration. Write a "1" for pins with pull-up resistors and a "0" for pins with pull-down resistors.

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Figure 28. Bi-directional Port 1 output. It also opens up the possibility of reading the pin condition when in output mode. This is a useful feature for self testing and for serial bus applications. up/-down transistor mask option. nal test logic thus disabling the application firmware. switches off the pull-down transistors during reset. Figure 29. Bi-directional Port 2

4552B–4BMCU–02/03 Port 2 Data Register (P2DAT) Primary register address: "2"hex * Bit 3 -> MSB, Bit 0 -> LSB Port 2 Control Register (P2CR) Auxiliary register address: "2"hex Value: 1111b means all pins in input mode Bi-directional Port 5 As all other bi-directional ports, this port includes a bitwise programmable Control Reg- ister (P5CR), which allows the individual programming of each port bit as input or output. It also opens up the possibility of reading the pin condition when in output mode. This is a useful feature for self testing and for serial bus applications. The port pins can also be used as external interrupt inputs (see Figure 23 and Figure 24). The interrupts (INT1 and INT6) can be masked or independently configured to trig- ger on either edge. The interrupt configuration and port direction is controlled by the Port 5 Control Register (P5CR). An additional low resistance pull-up/-down transistor mask option provides an internal bus pull-up for serial bus applications. The Port 5 Data Register (P5DAT) is I/O mapped to the primary address register of address "5"h and the Port 5 Control Register (P5CR) to the corresponding auxiliary reg- ister. The P5CR is a byte-wide register and is configured by writing first the low nibble and then the high nibble (see section "Addressing Peripherals"). Bit 3 * Bit 2 Bit 1 Bit 0 P2DAT3 P2DAT2 P2DAT1 P2DAT0 Reset value: 1111b B i t 3B i t 2B i t 1B i t 0 P2CR3 P2CR2 P2CR1 P2CR0 Reset value: 1111b Code 3 2 1 0 Function x x x 1 BP20 in input mode x x x 0 BP20 in output mode x x 1 x BP21 in input mode x x 0 x BP21 in output mode x 1 x x BP22 in input mode x 0 x x BP22 in output mode 1 x x x BP23 in input mode 0 x x x BP23 in output mode

36 ATAR862-4

Figure 30. Bi-directional Port 5 Figure 31. Port 5 External Interrupts

Table 7. P5xM2, P5xM1 – Port 5x Interrupt Mode/Direction Code internal interfaces to bi-directional Port 4. Figure 32. Bi-directional Port 4 and Port 6

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4552B–4BMCU–02/03 Port 4 Data Register (P4DAT) Primary register address: "4"hex Port 4 Control Register (P4CR) Byte Write Auxiliary register address: "4"hex P4xM2, P4xM1 – Port 4x Interrupt mode/direction code Bi-directional Port 6 The bi-directional Port 6 is a bitwise configurable I/O port and provides the external pins for the Timer 3. As a normal port, it performs in exactly the same way as bi-directional Port 6 (see Figure ). Two additional multiplexes allow data and port direction control to be passed over to other internal module (Timer 3). The I/O-pin for T3I line has an addi- tional mode to generate a Timer 3-interrupt. All two Port 6 pins can be individually switched by the P6CR register . Figure shows the internal interfaces to bi-directional Port 6. Bit 3 Bit 2 Bit 1 Bit 0 P4DAT3 P4DAT2 P4DAT1 P4DAT0 Reset value: 1111b B i t 3B i t 2B i t 1B i t 0 First write cycle P41M2 P41M1 P40M2 P40M1 Reset value: 1111b B i t 7B i t 6B i t 5B i t 4 Second write cycle P43M2 P43M1 P42M2 P42M1 Reset value: 1111b Auxiliary Address: "4"hex First Write Cycle Second Write Cycle Code 3 2 1 0 Function Code 3 2 1 0 Function x x 1 1 BP40 in input mode x x 1 1 BP42 in input mode x x 1 0 BP40 in output mode x x 1 0 BP42 in output mode x x 0 1 BP40 enable alternate function (SC for SSI) x x 0 x BP42 enable alternate function (T2O for Timer 2) x x 0 0 BP40 enable alternate function (falling edge interrupt input for INT3) 1 1 x x BP43 in input mode 1 1 x x BP41 in input mode 1 0 x x BP43 in output mode 1 0 x x BP41 in output mode 0 1 x x BP43 enable alternate function (SD for SSI) 0 1 x x BP41 enable alternate function (VMI for voltage monitor input) 0 0 x x BP43 enable alternate function (falling edge interrupt input for INT3) 0 0 x x BP41 enable alternate function (T2I external clock input for Timer 2)

4552B–4BMCU–02/03 Port 6 Data Register (P6DAT) Primary register address: "6"hex Port 6 Control Register (P6CR) Auxiliary register address: "6"hex P6xM2, P6xM1 – Port 6x Interrupt mode/direction code Universal Timer/Counter/ Communication Module (UTCM) The Universal Timer/counter/Communication Module (UTCM) consists of three timers (Timer 1,Timer 2, Timer 3) and a Synchronous Serial Interface (SSI).

• Timer 1 is an interval timer that can be used to generate periodical interrupts and as prescaler for Timer 2, Timer 3, the serial interface and the watchdog function.
• Timer 2 is an 8/12-bit timer with an external clock input (T2I) and an output (T2O).
• Timer 3 is an 8-bit timer/counter with its own input (T3I) and output (T3O).
• The SSI operates as two wire serial interface or as shift register for modulation and demodulation. The modulator and demodulator units work together with the timers and shift the data bits into or out of the shift register. There is a multitude of modes in which the timers and the serial interface can work together. Bit 3 Bit 2 Bit 1 Bit 0 P6DAT3 – – P6DAT0 Reset value: 1xx1b Bit 3 Bit 2 Bit 1 Bit 0 P63M2 P63M1 P60M2 P60M0 Reset value: 1111b Auxiliary Address: "6"hex Write Cycle Code 3 2 1 0 Function Code 3 2 1 0 Function x x 1 1 BP60 in input mode 1 1 x x BP63 in input mode x x 1 0 BP60 in output mode 1 0 x x BP63 in output mode x x 0 x BP60 enable alternate port function (T3O for Timer 3) 0 x x x BP63 enable alternate port function (T3I for Timer 3)

40 ATAR862-4

Figure 33. UTCM Block Diagram as prescaler for Timer 2, Timer 3, the serial interface and the watchdog function. (CPU core -> sleep and OSC-Stop -> yes), the output T1OUT is stopped (T1OUT = 0). Timer 1 control register T1C1.

42 ATAR862-4

4552B–4BMCU–02/03 Timer 1 Control Register 1 (T1C1) Address: "7"hex - Subaddress: "8"hex * Bit 3 -> MSB, Bit 0 -> LSB The three bits T1C[2:0] select the divider for timer 1. The resulting time interval depends on this divider and the timer 1 input clock source. The timer input can be supplied by the system clock, the 32-kHz oscillator or via the clock management. If the clock manage- ment generates the SUBCL, the selected input clock from the RC oscillator, 4-MHz oscillator or an external clock is divided by 16. Bit 3 * Bit 2 Bit 1 Bit 0 T1RM T1C2 T1C1 T1C0 Reset value: 1111b T1RM T imer 1 Restart Mode T1RM = 0, write access without Timer 1 restart T1RM = 1, write access with Timer 1 restart Note: If WDL = 0, Timer 1 restart is impossible T1C2 T imer 1 Control bit 2 T1C1 T imer 1 Control bit 1 T1C0 T imer 1 Control bit 0 T1C2 T1C1 T1C0 Divider Time Interval with SUBCL Time Interval with SUBCL = 32 kHz Time Interval with SYSCL = 2/1 MHz 0 0 0 2 SUBCL/2 61 µs 1 µs/2 µs 0 0 1 4 SUBCL/4 122 µs 2 µs/4 µs 0 1 0 8 SUBCL/8 244 µs 4 µs/8 µs 0 1 1 16 SUBCL/16 488 µs 8 µs/16 µs 1 0 0 32 SUBCL/32 0.977 ms 16 µs/32 µs 1 0 1 256 SUBCL/256 7.812 ms 128 µs/256 µs 1 1 0 2048 SUBCL/2048 62.5 ms 1024 µs/2048 µs 1 1 1 16384 SUBCL/16384 500 ms 8192 µs/16384 µs

4552B–4BMCU–02/03 Timer 1 Control Register 2 (T1C2) Address: "7"hex - Subaddress: "9"hex * Bit 3 -> MSB, Bit 0 -> LSB Watchdog Control Register (WDC) Address: "7"hex - Subaddress: "A"hex * Bit 3 -> MSB, Bit 0 -> LSB Both these bits control the time interval for the watchdog reset. Bit 3 * Bit 2 Bit 1 Bit 0 – T1BP T1CS T1IM Reset value: x111b T1BP T imer 1 SUBCL ByPassed T1BP = 1, TIOUT = T1MUX T1BP = 0, T1OUT = SUBCL T1CS T imer 1 input Clock Select T1CS = 1, CL1 = SUBCL (see Figure 26) T1CS = 0, CL1 = SYSCL (see Figure 26) T1IM T imer 1 Interrupt Mask T1IM = 1, disables Timer 1 interrupt T1IM = 0, enables Timer 1 interrupt Bit 3 * Bit 2 Bit 1 Bit 0 WDL WDR WDT1 WDT0 Reset value: 1111b WDL W atchDog Lock mode WDL = 1, the watchdog can be enabled and disabled by using the WDR-bit WDL = 0, the watchdog is enabled and locked. In this mode the WDR-bit has no effect. After the WDL-bit is cleared, the watchdog is active until a system reset or power-on reset occurs. WDR W atchDog Run and stop mode WDR = 1, the watchdog is stopped/disabled WDR = 0, the watchdog is active/enabled WDT1 W atchDog Time 1 WDT0 W atchDog Time 0 WDT1 WDT0 Divider Delay Time to Reset with SUBCL = 32 kHz Delay Time to Reset with SYSCL = 2/1 MHz 0 0 512 15.625 ms 0.256 ms/0.512 ms 0 1 2048 62.5 ms 1.024 ms/2.048 ms 1 0 16384 0.5 s 8.2 ms/16.4 ms 1 1 131072 4 s 65.5 ms/131 ms

44 ATAR862-4

4552B–4BMCU–02/03 Timer 2 8-/12-bit Timer for:

• Interrupt, square-wave, pulse and duty cycle generation
• Baud-rate generation for the internal shift register
• Manchester and Biphase modulation together with the SSI
• Carrier frequency generation and modulation together with the SSI Timer 2 can be used as an interval timer for interrupt generation, as signal generator or as baud-rate generator and modulator for the serial interface. It consists of a 4-bit and an 8-bit up counter stage which both have compare registers. The 4-bit counter stages of Timer 2 are cascadable as a 12-bit timer or as an 8-bit timer with 4-bit prescaler. The timer can also be configured as an 8-bit timer and a separate 4-bit prescaler. The Timer 2 input can be supplied via the system clock, the external input clock (T2I), the Timer 1 output clock, the Timer 3 output clock or the shift clock of the serial inter- face. The external input clock T2I is not synchronized with SYSCL. Therefore, it is possible to use Timer 2 with a higher clock speed than SYSCL. Furthermore, with that input clock the Timer 2 operates in the power-down mode SLEEP (CPU core -> sleep and OSC-Stop -> yes) as well as in the POWER-DOWN (CPU core -> sleep and OSC- Stop -> no). All other clock sources supplied no clock signal in SLEEP. The 4-bit counter stages of Timer 2 have an additional clock output (POUT). Its output has a modulator stage that allows the generation of pulses as well as the gen- eration and modulation of carrier frequencies. The Timer 2 output can modulate with the shift register data output to generate Biphase- or Manchester code. If the serial interface is used to modulate a bitstream, the 4-bit stage of Timer 2 has a special task. The shift register can only handle bitstream lengths divisible by 8. For other lengths, the 4-bit counter stage can be used to stop the modulator after the right bitcount is shifted out. If the timer is used for carrier frequency modulation, the 4-bit stage works together with an additional 2-bit duty cycle generator like a 6-bit prescaler to generate carrier fre- quency and duty cycle. The 8-bit counter is used to enable and disable the modulator output for a programmable count of pulses. For programming the time interval, the timer has a 4-bit and an 8-bit compare register. For programming the timer function, it has four mode and control registers. The compar- ator output of stage 2 is controlled by a special compare mode register (T2CM). This register contains mask bits for the actions (counter reset, output toggle, timer interrupt) which can be triggered by a compare match ev ent or the counter overflow. This archi- tecture enables the timer function for various modes. The Timer 2 has a 4-bit compare register (T2CO1) and an 8-bit compare register (T2CO2). Both these compare registers are cascadable as a 12-bit compare register, or 8-bit compare register and 4-bit compare register. For 12-bit compare data value: m = x +1 0 /g163 x /g163 4095 For 8-bit compare data value: n = y +1 0 /g163 y /g163 255 For 4-bit compare data value: l = z +1 0 /g163 z /g163 15

46 ATAR862-4

4552B–4BMCU–02/03 The 4-bit stage is used as programmable prescaler for the 8-bit counter stage. In this mode, a duty cycle stage is also available. This stage can be used as an additional 2-bit prescaler or for generating duty cycles of 25%, 33% and 50%. The 4-bit compare output (CM1) supplies the clock output (POUT) with clocks. Mode 3/4: 8-bit Compare Counter and 4-bit Programmable Prescaler Figure 39. 4-/8-bit Compare Counter In these modes the 4-bit and the 8-bit c ounter stages work independently as a 4-bit prescaler and an 8-bit timer with an 2-bit prescaler or as a duty cycle generator. Only in the mode 3 and mode 4, can the 8-bit counter be supplied via the external clock input (T2I) which is selected via the P4CR register. The 4-bit prescaler is started via activating of mode 3 and stopped and reset in mode 4. Changing mode 3 and 4 has no effect for the 8-bit timer stage. The 4-bit stage can be used as prescaler for Timer 3, the SSI or to generate the stop signal for modulator 2 and modulator 3. Timer 2 Output Modes The signal at the timer output is generated via modulator 2. In the toggle mode, the com- pare match event toggles the output T2O. For high resolution duty cycle modulation 8 bits or 12 bits can be used to toggle the output. In the duty cycle burst modulator modes the DCG output is connected to T2O and switched on and off either by the toggle flipflop output or the serial data line of the SSI. Modulator 2 also has two modes to output the content of the serial interface as Biphase or Manchester code. The modulator output stage can be configured by the output control bits in the T2M2 register. The modulator is started with the start of the shift register (SIR = 0) and stopped either by carrying out a shift register stop (SIR = 1) or compare match event of stage 1 (CM1) of Timer 2. For this task, Timer 2 mode 3 must be used and the prescaler has to be supplied with the internal shift clock (SCL). 4-bit counter 4-bit compare RES 4-bit register 8-bit counter 8-bit compare 8-bit register OVF2 CM2 RES T2RM T2OTM Timer 2 output mode and T2OTM-bit T2IM T2CTM TOG2 INT4 CL2/2 DCG T2D1, 0 DCGO P41M2, 1P4CR CM1 POUT CL2/1 MUX TOG3 T1OUT SYSCL SCL T2CS1, 0 SYSCL T2I

48 ATAR862-4

Figure 43. Pulse Generator – the Timer Toggles with Timer Overflow and Compare Figure 44. Carrier Frequency Burst Modulation with Timer 2 Toggle Flip-flop Output Figure 45. Carrier Frequency Burst Modulation with the SSI Data Output

50 ATAR862-4

Figure 48. PWM Modulation the Timer 2 modes require an input at T2I/BP41 or an output at T2O/BP42.

4552B–4BMCU–02/03 Timer 2 Mode Register 1 (T2M1) Address: "7"hex - Subaddress: "1"hex Duty Cycle Generator The duty cycle generator generates duty cycles of 25%, 33% or 50%. The frequency at the duty cycle generator output depends on the duty cycle and the Timer 2 prescaler setting. The DCG-stage can also be used as additional programmable prescaler for Timer 2. B i t 3B i t 2B i t 1B i t 0 T2D1 T2D0 T2MS1 T2MS0 Reset value: 1111b T2D1 T imer 2 Duty cycle bit 1 T2D0 T imer 2 Duty cycle bit 0 T2D1 T2D0 Function of Duty Cycle Generator (DCG) Additional Divider Effect 1 1 Bypassed (DCGO0) /1 1 0 Duty cycle 1/1 (DCGO1) /2 0 1 Duty cycle 1/2 (DCGO2) /3 0 0 Duty cycle 1/3 (DCGO3) /4 T2MS1 T imer 2 Mode Select bit 1 T2MS0 T imer 2 Mode Select bit 0 Mode T2MS1 T2MS0 Clock Output (POUT) Timer 2 Modes 1 1 1 4-bit counter overflow (OVF1) 12-bit compare counter; the DCG has to be bypassed in this mode 2 1 0 4-bit compare output (CM1) 8-bit compare counter with 4- bit programmable prescaler and duty cycle generator 3 0 1 4-bit compare output (CM1) 8-bit compare counter clocked by SYSCL or the external clock input T2I, 4-bit prescaler run, the counter 2/1 starts after writing mode 3 4 0 0 4-bit compare output (CM1) 8-bit compare counter clocked by SYSCL or the external clock input T2I, 4-bit prescaler stop and resets

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Figure 49. DCG Output Signals This bit allows the programmer to preset the Timer 2 output T2O.

1111 T o g g l e m o d e : a T i m e r 2 c o m p a r e m a t c h t o g g l e s

2110 D u t y c y c l e b u r s t g e n e r a t o r 1 : t h e D C G o u t p u t

3101 D u t y c y c l e b u r s t g e n e r a t o r 2 : t h e D C G o u t p u t

4100 B i p h a s e m o d u l a t o r : T i m e r 2 m o d u l a t e s t h e S S I

5011 M a n c h e s t e r m o d u l a t o r : T i m e r 2 m o d u l a t e s t h e S S I

6010 S S I o u t p u t : T 2 O i s u s e d d i r e c t l y a s S S I i n t e r n a l

7001 P W M m o d e : a n 8 / 1 2 - b i t P W M m o d e

8000 N o t a l l o w e d

4552B–4BMCU–02/03 Timer 2 Compare and Compare Mode Registers Timer 2 has two separate compare registers, T2CO1 for the 4-bit stage and T2CO2 for the 8-bit stage of Timer 2. The timer compares the contents of the compare register cur- rent counter value and if it matches it generates an output signal. Dependent on the timer mode, this signal is used to generate a timer interrupt, to toggle the output flip-flop as SSI clock or as a clock for the next counter stage. In the 12-bit timer mode, T2CO1 contains bits 0 to 3 and T2CO2 bits 4 to 11 of the 12-bit compare value. In all other modes, the two compare registers work independently as a 4- and 8-bit compare register. When asigned to the compare register a compare event will be suppressed. Timer 2 Compare Mode Register (T2CM) Address: "7"hex - Subaddress: "3"hex Timer 2 COmpare Register 1 (T2CO1) Address: "7"hex - Subaddress: "4"hex In prescaler mode the clock is bypassed if the compare register T2CO1 contains 0. B i t 3B i t 2B i t 1B i t 0 T2OTM T2CTM T2RM T2IM Reset value: 0000b T2OTM T imer 2 Overflow Toggle Mask bit T2OTM = 0, disable overflow toggle T2OTM = 1, enable overflow toggle, a counter overflow (OVF2) toggles output flip-flop (TOG2). If the T2OTM-bit is set, only a counter overflow can generate an interrupt except on the Timer 2 output mode 7. T2CTM T imer 2 Compare Toggle Mask bit T2CTM = 0, disable compare toggle T2CTM = 1, enable compare toggle, a match of the counter with the compare register toggles output flip-flop (TOG2). In Timer 2 output mode 7 and when the T2CTM-bit is set, only a match of the counter with the compare register can generate an interrupt. T2RM T imer 2 Reset Mask bit T2RM = 0, disable counter reset T2RM = 1, enable counter reset, a match of the counter with the compare register resets the counter T2IM T imer 2 Interrupt Mask bit T2IM = 0, disable Timer 2 interrupt T2IM = 1, enable Timer 2 interrupt Timer 2 Output Mode T2OTM T2CTM Timer 2 Interrupt Source 1, 2, 3, 4, 5 and 6 0 x Compare match (CM2) 1, 2, 3, 4, 5 and 6 1 x Overflow (OVF2) 7 x 1 Compare match (CM2) Write cycle Bit 3 Bit 2 Bit 1 Bit 0 Reset value: 1111b

54 ATAR862-4

• Capture Register
• Edge Sensitive Input with Zero Cross Detection Capability
• Trigger and Single Action Modes
• Output Control Modes
• Automatically Modulation and Demodulation Modes
• FSK Modulation
• Pulse Width Modulation (PWM)
• Manchester Demodulation Together with SSI
• Biphase Demodulation Together with SSI
• Pulse-width Demodulation Together with SSI

Figure 50. Timer 3

4552B–4BMCU–02/03 Timer 3 consists of an 8-bit up-counter with two compare registers and one capture reg- ister. The timer can be used as event counter, timer and signal generator. Its output can be programmed as modulator and demodulator for the serial interface. The two com- pare registers enable various modes of signal generation, modulation and demodulation. The counter can be driven by internal and external clock sources. For external clock sources, it has a programmable edge-sensitive input which can be used as counter input, capture signal input or tri gger input. This timer input is synchronized with SYSCL. Therefore, in the power-down mode SLEEP (CPU core -> sleep and OSC- Stop -> yes), this timer input is stopped too. The counter is readable via its capture reg- ister while it is running. In capture mode, the counter value can be captured by a programmable capture event from the Timer 3 input or Timer 2 output. A special feature of this timer is the trigger- and single-action mode. In trigger mode, the counter starts counting triggered by the external signal at its input. In single-action mode, the counter counts only one time up to the programmed compare match event. These modes are very useful for modulation, demodulation, signal generation, signal measurement and phase controlling. For phase controlling, the timer input is protected against negative voltages and has zero-cross detection capability. Timer 3 has a modulator output stage and input functions for demodulation. As modula- tor it works together with Timer 2 or the serial interface. When the shift register is used for modulation the data shifted out of the register is encoded bitwise. In all demodulation modes, the decoded data bits are shifted automatically into the shift register. Timer/Counter Modes Timer 3 has 6 timer modes and 6 modulator/demodulator modes. The mode is set via the Timer 3 Mode Register T3M. In all these modes, the compare register and the compare-mode register belonging to it define the counter value for a compare match and the action of a compare match. A match of the current counter value with the content of one compare register triggers a counter reset, a Timer 3 interrupt or the toggling of the output flip-flop. The compare mode registers T3M1 and T3M2 contain the mask bits for enabling or disabling these actions. The counter can also be enabled to execute single actions with one or both compare registers. If this mode is set the corresponding compare match event is generated only once after the counter start. Most of the timer modes use their compare registers alternately. After the start has been activated, the first comparison is carried out via the compare register 1, the second is carried out via the compare register 2, the third is carried out again via the compare reg- ister 1 and so on. This makes it easy to generate signals with constant periods and variable duty cycle or to generate signals with variable pulse and space widths. If single-action mode is set for one compare register, the comparison is always carried out after the first cycle via the other compare register. The counter can be started and stopped via the control register T3C. This register also controls the initial level of the output before start. T3C contains the interrupt mask for a T3I input interrupt. Via the Timer 3 clock-select register, the internal or external clock source can be selected. This register selects also the active edge of the external input. An edge at the external input T3I can generate also an interrupt if the T3EIM-bit is set and the Timer 3 is stopped (T3R = 0) in the T3C-register.

56 ATAR862-4

Figure 51. Counter 3 Stage the interrupt source because all these events share only one timer interrupt. Timer 3 compares data values. can be ‘m’ for each of the Timer 3 compare registers. ware via the capture register.

58 ATAR862-4

Figure 55. Externally Triggered Counter Reset and Start Combined with Single-action ments or as event counter with time gate (see combination mode 10). Figure 56. Event Counter with Time Gate other clock source (see combination mode 11).

60 ATAR862-4

time-out error and handle it with an interrupt routine (see also combination mode 8). Figure 59. Manchester Demodulation shifts the toggle flip-flop output into shift register (see also combined mode 9). Figure 60. Biphase Demodulation

Figure 61. External Capture Mode and the prescaler must be supplied by the internal shift clock of the shift register. either by a shift register stop (SIR = 1) or compare match event of stage 1 of Timer 2. plied by the internal shift clock of the shift register. Figure 62. Modulator 3 Figure 63. Timer 3 Demodulator 3

6 MUX 1

7 MUX 2

9 MUX 3

62 ATAR862-4

4552B–4BMCU–02/03 Timer 3 Registers Timer 3 Mode Register (T3M) Address: "B"hex - Subaddress: "0"hex Note: 1. In this mode, the SSI can be used only as demodulator (8-bit NRZ rising edge). All other SSI modes are not allowed. B i t 3B i t 2B i t 1B i t 0 T3M3 T3M2 T3M1 T3M0 Reset value: 1111b T3M3 T imer 3 Mode select bit 3 T3M2 T imer 3 Mode select bit 2 T3M1 T imer 3 Mode select bit 1 T3M0 T imer 3 Mode select bit 0 Mode T3M3 T3M2 T3M1 T3M0 Timer 3 Modes

11111 T i m e r / c o u n t e r w i t h a r e a d a c c e s s

21110 T i m e r / c o u n t e r , e x t e r n a l c a p t u r e a n d e x t e r n a l

trigger restart mode (T3I)

31101 T i m e r / c o u n t e r , i n t e r n a l c a p t u r e a n d i n t e r n a l

trigger restart mode (TOG2)

41100 T i m e r / c o u n t e r m o d e 1 w i t h o u t o u t p u t ( T 2 O - >

T3O)

51011 T i m e r / c o u n t e r m o d e 2 w i t h o u t o u t p u t ( T 2 O - >

T3O)

61010 B u r s t m o d u l a t i o n w i t h T i m e r 2 ( M 2 )

71001 B u r s t m o d u l a t i o n w i t h s h i f t r e g i s t e r ( S O )

81000 F S K m o d u l a t i o n w i t h s h i f t r e g i s t e r ( S O )

90111 P u l s e - w i d t h m o d u l a t i o n w i t h s h i f t r e g i s t e r ( S O )

and Timer 2 (TOG2), internal trigger restart (SCO) -> counter reset 1 0 0110 M a n c h e s t e r d e m o d u l a t i o n / p u l s e - w i d t h demodulation (1) (T2O -> T3O) 1 1 0101 B i p h a s e d e m o d u l a t i o n ( T 2 O - > T 3 O ) 1 2 0100 T i m e r / c o u n t e r w i t h e x t e r n a l c a p t u r e m o d e ( T 3 I ) 1 3 0011 N o t a l l o w e d 1 4 0010 N o t a l l o w e d 1 5 0001 N o t a l l o w e d 1 6 0000 N o t a l l o w e d

4552B–4BMCU–02/03 Timer 3 Control Register 1 (T3C) Write Primary register address: "C"hex - Write Timer 3 Status Register 1 (T3ST) Read Primary register address: "C"hex - Read Note: The status bits T3C1, T3C2 and T3ED will be reset after a READ access to T3ST. Timer 3 Clock Select Register (T3CS) Address: "B"hex - Subaddress: "1"hex Bit 3 Bit 2 Bit 1 Bit 0 Write T3EIM T3TOP T3TS T3R Reset value: 0000b T3EIM T imer 3 Edge Interrupt Mask T3EIM = 0, disables the interrupt when an edge event for Timer 3 occurs (T3I) T3EIM = 1, enables the interrupt when an edge event for Timer 3 occurs (T3I) T3TOP T imer 3 Toggle Output Preset T3TOP = 0, sets toggle output (M3) to "0" T3TOP = 1, sets toggle output (M3) to "1" Note: If T3R = 1, no output preset is possible T3TS T imer 3 Toggle with Start T3TS = 0, Timer 3 output is not toggled during the start T3TS = 1, Timer 3 output is toggled if started with T3R T3R T imer 3 Run T3R = 0, Timer 3 stop and reset T3R = 1, Timer 3 run Bit 3 Bit 2 Bit 1 Bit 0 Read - - - T3ED T3C2 T3C1 Reset value: x000b T3ED T imer 3 Edge Detect This bit will be set by the edge-detect logic of Timer 3 input (T3I) T3C2 T imer 3 Compare 2 This bit will be set when a match occurs between Counter 3 and T3CO2 T3C1 T imer 3 Compare 1 This bit will be set when a match occurs between Counter 3 and T3CO1 Bit 3 Bit 2 Bit 1 Bit 0 T3CS T3E1 T3E0 T3CS1 T3CS0 Reset value: 1111b T3E1 T imer 3 Edge select bit 1 T3E1 T3E0 Timer 3 Input Edge Select (T3I) T3E0 T imer 3 Edge select bit 0 11 – 1 0 Positive edge at T3I pin 0 1 Negative edge at T3I pin 0 0 Each edge at T3I pin

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4552B–4BMCU–02/03 Timer 3 Compare- and Compare-mode Register Timer 3 has two separate compare registers T3CO1 and T3CO2 for the 8-bit stage of Timer 3. The timer compares the content of the compare register with the current counter value. If both match, it generates a signal. This signal can be used for the counter reset, to generate a timer interrupt, for toggling the output flip-flop, as SSI clock or as clock for the next counter stage. For each compare register, a compare-mode reg- ister exists. These registers contain mask bits to enable or disable the generation of an interrupt, a counter reset, or an output toggling with the occurrence of a compare match of the corresponding compare register. The mask bits for activating the single-action mode can also be located in the compare mode registers. When assigned to the com- pare register a compare event will be suppressed. Timer 3 Compare-Mode Register 1 (T3CM1) Address: "B"hex - Subaddress: "2"hex T3CM1 contains the mask bits for the match event of the Counter 3 compare register 1 T3CS1 T imer 3 Clock Source select bit 1 T3CS1 TCS0 Counter 3 Input Signal (CL3) T3CS0 T imer 3 Clock Source select bit 0 1 1 System clock (SYSCL) 1 0 Output signal of Timer 2 (POUT) 0 1 Output signal of Timer 1 (T1OUT) 0 0 External input signal from T3I edge detect B i t 3B i t 2B i t 1B i t 0 T3CM1 T3SM1 T3TM1 T3RM1 T3IM1 Reset value: 0000b T3SM1 T imer 3 Single action Mask bit 1 T3SM1 = 0, disables single-action compare mode T3SM1 = 1, enables single-compare mode. After this bit is set, the compare register (T3CO1) is used until the next compare match. T3TM1 T imer 3 compare Toggle action Mask bit 1 T3TM1 = 0, disables compare toggle T3TM1 = 1, enables compare toggle. A match of Counter 3 with the compare register (T3CO1) toggles the output flip-flop (TOG3). T3RM1 T imer 3 Reset Mask bit 1 T3RM1 = 0, disables counter reset T3RM1 = 1, enables counter reset. A match of Counter 3 with the compare register (T3CO1) resets the Counter 3. T3IM1 T imer 3 Interrupt Mask bit 1 T3RM1 = 0, disables Timer 3 interrupt for T3CO1 register. T3RM1 = 1, enables Timer 3 interrupt for T3CO1 register.

4552B–4BMCU–02/03 Timer 3 Compare Mode Register 2 (T3CM2) Address: "B"hex - Subaddress: "3"hex T3CM2 contains the mask bits for the match event of Counter 3 compare register 2 The compare registers and corresponding counter reset masks can be used to program the counter time intervals and the toggle masks can be used to program output signal. The single-action mask can also be used in this mode. It starts operating after the timer started with T3R. Timer 3 COmpare Register 1 (T3CO1) Byte Write Address: "B"hex - Subaddress: "4"hex Timer 3 COmpare Register 2 (T3CO2) Byte Write Address: "B"hex - Subaddress: "5"hex B i t 3B i t 2B i t 1B i t 0 T3CM2 T3SM2 T3TM2 T3RM2 T3IM2 Reset value: 0000b T3SM2 T imer 3 Single action Mask bit 2 T3SM2 = 0, disables single-action compare mode T3SM2 = 1, enables single-compare mode. After this bit is set, the compare register (T3CO2) is used until the next compare match. T3TM2 T imer 3 compare Toggle action Mask bit 2 T3TM2 = 0, disables compare toggle T3TM2 = 1, enables compare toggle. A match of Counter 3 with the compare register (T3CO2) toggles the output flip-flop (TOG3). T3RM2 T imer 3 Reset Mask bit 2 T3RM2 = 0, disables counter reset T3RM2 = 1, enables counter reset. A match of Counter 3 with the compare register (T3CO2) resets the Counter 3. T3IM2 T imer 3 Interrupt Mask bit 2 T3RM2 = 0, disables Timer 3 interrupt for T3CO2 register. T3RM2 = 1, enables Timer 3 interrupt for T3CO2 register. High Nibble Second write cycle Bit 7 Bit 6 Bit 5 Bit 4 Reset value: 1111b Low Nibble First write cycle Bit 3 Bit 2 Bit 15 Bit 0 Reset value: 1111b High Nibble Second write cycle Bit 7 Bit 6 Bit 5 Bit 4 Reset value: 1111b Low Nibble First write cycle Bit 3 Bit 2 Bit 15 Bit 0 Reset value: 1111b

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4552B–4BMCU–02/03 Timer 3 Capture Register The counter content can be read via the capture register. There are two ways to use the capture register. In modes 1 and 4, it is possible to read the current counter value directly out of the capture register. In the capture modes 2, 3, 5 and 12, a capture event like an edge at the Timer 3 input or a signal from Timer 2 stores the current counter value into the capture register. This counter value can be read from the capture register. Timer 3 CaPture Register (T3CP) Byte Read Address: "B"hex - Subaddress: "4"hex Synchronous Serial Interface (SSI) SSI Features – 2- and 3-wire NRZ – 2-wire multi-chip link mode (MCL), additional internal 2-wire link for multi- chip packaging solutions

• With Timer 2: – Biphase modulation – Manchester modulation – Pulse-width demodulation – Burst modulation
• With Timer 3: – Pulse-width modulation (PWM) – FSK modulation – Biphase demodulation – Manchester demodulation – Pulse-width demodulation – Pulse position Demodulation SSI Peripheral Configuration The synchronous serial interface (SSI) can be used either for serial communication with external devices such as EEPROMs, shift registers, display drivers, other microcontrol- lers, or as a means for generating and capturing on-chip serial streams of data. External data communication takes place via the Port 4 (BP4),a multi-functional port which can be software configured by writing the appropria te control word into the P4CR register. The SSI can be configured in any of the following ways: 1. 2-wire external interface for bi-directional data communication with one data ter- minal and one shift clock. The SSI uses the Port BP43 as a bi-directional serial data line (SD) and BP40 as shift clock line (SC). 2. 3-wire external interface for simultaneous input and output of serial data, with a serial input data terminal (SI), a serial output data terminal (SO) and a shift clock (SC). The SSI uses BP40 as shift clock (SC), while the serial data input (SI) is applied to BP43 (configured in P4CR as input!). Serial output data (SO) in this case is passed through to BP42 (configured in P4CR to T2O) via the Timer 2 output stage (T2M2 configured in mode 6). High Nibble First read cycle Bit 7 Bit 6 Bit 5 Bit 4 Reset value: xxxxb Low Nibble Second read cycle Bit 3 Bit 2 Bit 15 Bit 0 Reset value: xxxxb

1. Timer/SSI combined modes – the SSI used together with Timer 2 or Timer 3 is

can only be used as demodulator.

1. Internal Multi-Chip Link pads (MCL) – the SSI can also be used as an interchip

are available as conventional data ports. Figure 64. Block Diagram of the Synchronous Serial Interface fers or continuous bit streams can be supported. by the corresponding timer mode. transmission begins after a valid start condition and ends with a valid stop condition.

68 ATAR862-4

4552B–4BMCU–02/03 All directional control of the external data port used by the SSI is handled automatically and is dependent on the transmission direction set by the Serial Data Direction (SDD) control bit. This control bit defines whether the SSI is currently operating in Transmit (TX) mode or Receive (RX) mode. Serial data is organized in 8-bit telegrams which are shifted with the most significant bit first. In the 9-bit MCL mode, an additional acknowledge bit is appended to the end of the telegram for handshaking purposes (see MCL protocol). At the beginning of every telegram, the SSI control loads the transmit buffer into the shift register and proceeds immediately to shift data serially out. At the same time, incoming data is shifted into the shift register input. This incoming data is automatically loaded into the receive buffer when the complete telegram has been received. Thus, data can be simultaneously received and transmitted if required. Before data can be transferred, the SSI must first be activated. This is performed by means of the SSI reset control (SIR) bit. All further operation then depends on the data directional mode (TX/RX) and the present status of the SSI buffer registers shown by the Serial Interface Ready Status Flag (SRDY). This SRDY flag indicates the (empty/full) status of either the transmit buffer (in TX mode), or the receive buffer (in RX mode). The control logic ensures that data sh ifting is temporarily halted at any time, if the appropriate receive/transmit buffer is not ready (SRDY = 0). The SRDY status will then automatically be set back to ‘1’ and data shifting resumed as soon as the applica- tion software loads the new data into the transmit register (in TX mode) or frees the shift register by reading it into the receive buffer (in RX mode). A further activity status (ACT) bit indicates the present status of the serial communica- tion. The ACT bit remains high for the duration of the serial telegram or if MCL stop or start conditions are currently being generated. Both the current SRDY and ACT status can be read in the SSI status register. To deactivate the SSI, the SIR bit must be set high. 8-bit Synchronous Mode Figure 65. 8-bit Synchronous Mode In the 8-bit synchronous mode, the SSI can operate as either a 2- or 3-wire interface (see SSI peripheral configuration). The serial data (SD) is received or transmitted in NRZ format, synchronized to either the rising or falling edge of the shift clock (SC). The choice of clock edge is defined by the Serial Mode Control bits (SM0,SM1). It should be noted that the transmission edge refers to the SC clock edge with which the SD changes. To avoid clock skew problems, the incoming serial input data is shifted in with the opposite edge. When used together with one of the timer modulator or demodulator stages, the SSI must be set in the 8-bit synchronous mode 1. SC SC DATA SD/TO2 11 0 10100 Bit 7 Bit 0 11 0 10100 Bit 7 Bit 0 Data: 00110101 (Rising edge) (Falling edge)

contents will overwrite the receive buffer. Figure 66. Example of 8-bit Synchronous Transmit Operation

70 ATAR862-4

Figure 67. Example of 8-bit Synchronous Receive Operation to be returned to the device is predetermined by the SSI Status Register (RACK). using the SSI interrupt (IFN = 1) or by interrogating the ACT status. the current transfer and terminate the dialog with an MCL stop condition.

72 ATAR862-4

multiple bus control and bus contention will be omitted at this point. All data is packaged into 8-bit telegrams plus a trailing handshaking or acknowledge-bit. Figure 70. MCL Bus Protocol 1 Bus not busy (1) Both data and clock lines remain HIGH. is HIGH defines a STOP condition. duration of the HIGH period of the clock signal.

Figure 71. MCL Bus Protocol 2 nize the software control of the SSI and inform the controller of the present SSI status. of waking the controller out of sleep mode. ate control bits in P4CR register. 4 pins can be used as conventional bi-directional ports. vated (SIR = 0) and cease when deactivated (SIR = 1). all following data bits are blanked. ting the MCL-bit in the SISC-register.

74 ATAR862-4

Figure 72. Multi-chip Link Figure 73. SSI Output Masking Function

4552B–4BMCU–02/03

• In Transmit mode (SDD = 1) shifting starts only if the transmit buffer has been loaded (SRDY = 1).
• Setting SIR-bit loads the contents of the shift register into the receive buffer (synchronous 8-bit mode only).
• In MCL modes, writing a 0 to SIR generates a start condition and writing a 1 generates a stop condition. Serial Interface Control Register 2 (SIC2) Auxiliary register address: "A"hex Note: SDD controls port directional control and defines the reset function for the SRDY -flag B i t 3B i t 2B i t 1B i t 0 MSM SM1 SM0 SDD Reset value: 1111b MSM M odular Stop Mode MSM = 1, modulator stop mode disabled (output masking off) MSM = 0, modulator stop mode enabled (output masking on) - used in modulation modes for generating bit streams which are not sub–multiples of 8 bits. SM1 S erial Mode control bit 1 SM0 S erial Mode control bit 0 Mode SM1 SM0 SSI Mode 1 1 1 8-bit NRZ-Data changes with the rising edge of SC 2 1 0 8-bit NRZ-Data changes with the falling edge of SC 3 0 1 9-bit two-wire MCL mode 4 0 0 8-bit two-wire MCL mode (no acknowledge) SDD S erial Data Direction SDD = 1, transmit mode – SD line used as output (transmit data). SRDY is set by a transmit buffer write access. SDD = 0, receive mode – SD line used as input (receive data). SRDY is set by a receive buffer read access

76 ATAR862-4

4552B–4BMCU–02/03 Serial Interface Status and Control Register (SISC) Primary register address: "A"hex Serial Transmit Buffer (STB) – Byte Write Primary register address: "9"hex The STB is the transmit buffer of the SSI. The SSI transfers the transmit buffer into the shift regis- ter and starts shifting with the most significant bit. Serial Receive Buffer (SRB) – Byte Read Primary register address: "9"hex The SRB is the receive buffer of the SSI. The shift register clocks serial data in (most significant bit first) and loads content into the receive buffer when complete telegram has been received. Bit 3 Bit 2 Bit 1 Bit 0 Write MCL RACK SIM IFN Reset value: 1111b Read - - - TACK ACT SRDY Reset value: xxxxb MCL M ulti-Chip Link activation MCL = 1,multi-chip link disabled. This bit has to be set to "0" during transactions to/from EEPROM of the M44C892 MCL = 0, connects SC and SD additionally to the internal multi-chip link pads RACK R eceive ACKnowledge status/control bit for MCLmode RACK = 0, transmit acknowledge in next receive telegram RACK = 1, transmit no acknowledge in last receive telegram TACK T ransmit ACKnowledge status/control bit for MCL mode TACK = 0, acknowledge received in last transmit telegram TACK = 1, no acknowledge received in last transmit telegram SIM S erial Interrupt Mask SIM = 1, disable interrupts SIM = 0, enable serial interrupt. An interrupt is generated. IFN I nterrupt FuNction IFN = 1, the serial interrupt is generated at the end of telegram IFN = 0, the serial interrupt is generated when the SRDY goes low (i.e., buffer becomes empty/full in transmit/receive mode) SRDY S erial interface buffer ReaDY status flag SRDY = 1, in receive mode: receive buffer empty in transmit mode: transmit buffer full SRDY = 0, in receive mode: receive buffer full in transmit mode: transmit buffer empty ACT Transmission ACTive status flag ACT = 1, transmission is active, i.e., serial data transfer. Stop or start conditions are currently in progress. ACT = 0, transmission is inactive First write cycle Bit 3 Bit 2 Bit 1 Bit 0 Reset value: xxxxb Second write cycle Bit 7 Bit 6 Bit 5 Bit 4 Reset value: xxxxb First read cycle Bit 7 Bit 6 Bit 5 Bit 4 Reset value: xxxxb Second read cycle Bit 3 Bit 2 Bit 1 Bit 0 Reset value: xxxxb

a multitude of modes in which the timers and serial interface can work together. data bits into or out of the shift register. Figure 74. Combination Timer 2 and SSI

78 ATAR862-4

Figure 75. Carrier Frequency Burst Modulation with the SSI Internal Data Output Figure 76. Biphase Modulation 1

80 ATAR862-4

71 shows an example for a 13-bit Biphase telegram. Figure 79. Biphase Modulation

Figure 80. Combination Timer 3 and SSI an internal or external clock source.

82 ATAR862-4

Figure 81. FSK Modulation cycles. Timer 2 is used as baudrate generato r and for the triggered restart of Timer 3. internal or external clock source. Figure 82. Pulse-width Modulation error and handle it with an interrupt routine.

demodulator after an interval with the complete bitlength. match with the compare register 1 shifts the state at the input T3I into the shift register. The next positive edge at the input restarts the timer. Figure 83. Manchester Demodulation Biphase code timing consists of parts with the half bitlength and the complete bitlength.

84 ATAR862-4

Figure 84. Biphase Demodulation Figure 85. Combination Timer 3 and Timer 2

86 ATAR862-4

Figure 88. Burst Modulation 1

Figure 89. Combination Timer 2, Timer 3 and SSI

88 ATAR862-4

Figure 90. Burst Modulation 2 data output selects which compare register is used for the output frequency generation. is driven by an internal or external clock source.

90 ATAR862-4

Figure 93. Block Diagram EEPROM transfer and provides the clock for transmit and receive operations. into and out of the device. The following protocol is used for the data transfers. Serial Protocol • Data states on the SDA-line changing only while SCL is low.

• Changes on the SDA-line while SCL is high are interpreted as START or STOP condition.
• A START condition is defined as high to low transition on the SDA-line while the SCL-line is high.
• A STOP condition is defined as low to high transition on the SDA-line while the SCL- line is high.
• Each data transfer must be initialized with a START condition and terminated with a STOP condition. The START condition wakes the device from standby mode and the STOP condition returns the device to standby mode.
• A receiving device generates an acknowledge (A) after the reception of each byte. This requires an additional clock pulse, generated by the master. If the reception was successful the receiving master or slave device pulls down the SDA-line during that clock cycle. If an acknowledge is not detected (N) by the interface in transmit mode, it will terminate further data transmissions and go into receive mode. A master device must finish its read operation by a non-acknowledge and then send a stop condition to bring the device into a known state. 16-bit read/write buffer Address control 8-bit data register EEPROM 32 x 16 HV-generatorTiming control Mode control I/O control SCL V DD VSS SDA

Figure 94. MCL Protocol

• Before the START condition and after the STOP condition the device is in standby mode and the SDA line is switched as input with pull-up resistor.
• The control byte that follows the START condition determines the following operation. It consists of the 5-bit row address, 2 mode control bits and the READ/NWRITE bit that is used to control the direction of the following transfer. A "0" defines a write access and a "1" a read access. Control Byte Format EEPROM The EEPROM has a size of 512 bits and is organized as 32 x 16-bit matrix. To read and write data to and from the EEPROM the serial interface must be used. The interface supports one and two byte write accesses and one to n-byte read accesses to the EEPROM. EEPROM – Operating Modes The operating modes of the EEPROM are defined via the control byte. The control byte contains the row address, the mode control bits and the read/not-write bit that is used to control the direction of the following transfer. A "0" defines a write access and a "1" a read access. The five address bits select one of the 32 rows of the EEPROM memory to be accessed. For all accesses the complete 16-bit word of the selected row is loaded into a buffer. The buffer must be read or overwritten via the serial interface. The two mode control bits C1 and C2 define in which order the accesses to the buffer are per- formed: High byte – low byte or low by te – high byte. The EEPROM also supports autoincrement and autodecrement read operations. After sending the start address with the corresponding mode, consecutive memory cells can be read row by row without transmission of the row addresses. Two special control bytes enable the complete initialization of EEPROM with "0" or with "1". Start condition Data valid Data change Data/ acknowledge valid Stop condition SCL SDA Stand by Stand- by EEPROM Address Mode Control Bits Read/ NWrite S t a r tA 4A 3A 2A 1A 0C 1C 0 R / N W A c k n Start Control byte Ackn Data byte Ackn Data byte Ackn Stop

92 ATAR862-4

4552B–4BMCU–02/03 Write Operations The EEPROM permits 8-bit and 16-bit write operations. A write access starts with the START condition followed by a write control byte and one or two data bytes from the master. It is completed via the STOP condition from the master after the acknowledge cycle. The programming cycle consists of an erase cycle (write "zeros") and the write cycle (write "ones"). Both cycles together take about 10 ms. Acknowledge Polling If the EEPROM is busy with an internal write cycle, all inputs are disabled and the EEPROM will not acknowledge until the write cycle is finished. This can be used to detect the end of the write cycle. The master must perform acknowledge polling by sending a start condition followed by the control byte. If the device is still busy with the write cycle, it will not return an acknowledge and the master has to generate a stop con- dition or perform further acknowledge polling sequences. If the cycle is complete, it returns an acknowledge and the master can proceed with the next read or write cycle. Write One Data Byte Write Two Data Bytes Write Control Byte Only Write Control Bytes A -> acknowledge; HB -> high byte; LB -> low byte; R -> row address Read Operations The EEPROM allows byte-, word- and current address read operations. The read oper- ations are initiated in the same way as write operations. Every read access is initiated by sending the START condition followed by the control byte which contains the address and the read mode. When the device has received a read command, it returns an acknowledge, loads the addressed word into the read/write buffer and sends the selected data byte to the master. The master has to acknowledge the received byte if it wants to proceed the read operation. If two bytes are read out from the buffer the device increments respectively decrements the word address automatically and loads the buffer with the next word. The read mode bits determines if the low or high byte is read first from the buffer and if the word address is incremented or decremented for the next Start Control byte A Data byte 1 A Stop Start Control byte A Data byte 1 A Data byte 2 A Stop Start Control byte A Stop MSB LSB Write low byte first A4 A3 A2 A1 A0 C1 C0 R/NW Row address 0 1 0 Byte order LB(R) HB(R) MSB LSB Write high byte first A4 A3 A2 A1 A0 C1 C0 R/NW Row address 1 0 0 Byte order HB(R) LB(R)

4552B–4BMCU–02/03 read access. If the memory address limit is reached, the data word address will roll over and the sequential read will continue. The master can terminate the read operation after every byte by not responding with an acknowledge (N) and by issuing a stop condition. Read One Data Byte Read Two Data Bytes Read n Data Bytes Read Control Bytes A -> acknowledge, N -> no acknowledge; HB -> high byte; LB -> low byte, R -> row address Initialization After a Reset Condition The EEPROM with the serial interface has its own reset circuitry. In systems with micro- controllers that have their own reset circuitry for power-on reset, watchdog reset or brown-out reset, it may be necessary to bring the U505M into a known state indepen- dent of its internal reset. This is performed by writing: to the serial interface. If the U505M acknowledges this sequence it is in a defined state. Maybe it is necessary to perform this sequence twice. Start Control byte A Data byte 1 N Stop Start Control byte A Data byte 1 A Data byte 2 N Stop Start Control byte A Data byte 1 A Data byte 2 A – Data byte n N Stop MSB LSB Read low byte first, address increment A4 A3 A2 A1 A0 C1 C0 R/NW Row address 0 1 1 Byte order LB(R) HB(R) LB(R+1) HB(R+1) - - - LB(R+n) HB(R+n) MSB LSB Read high byte first, address decrement A4 A3 A2 A1 A0 C1 C0 R/NW Row address 1 0 1 Byte order HB(R) LB(R) HB(R-1) LB(R-1) - - - HB(R-n) LB(R-n) Start Control byte A Data byte 1 N Stop

94 ATAR862-4

4552B–4BMCU–02/03 Note: Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at any condition above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating condition for an extended period may affect device reliability. All inputs and outputs are protected against high electrostatic voltages or electric fields. However, precautions to minimize t he build-up of electrostatic charges during handling are recommended. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (e.g., V DD). Absolute Maximum Ratings Voltages are given relative to VSS Parameters Symbol Value Unit Supply voltage V DD -0.3 to +4.0 V Input voltage (on any pin) V IN VSS -0.3 /g163 VIN /g163 VDD +0.3 V Output short circuit duration t short Indefinite s Operating temperature range T amb -40 to +125 /g176C Storage temperature range T stg -40 to +130 /g176C Soldering temperature (t /g163 10 s) T sld 260 /g176C Thermal Resistance Parameter Symbol Value Unit Thermal resistance (SSO20) R thJA 140 K/W DC Operating Characteristics VSS = 0 V, Tamb = -40/g176C to +125/g176C unless otherwise specified. Parameters Test Conditions Symbol Min. Typ. Max. Unit Power Supply Operating voltage at VDD VDD VPOR 4.0 V Active current CPU active fSYSCL = 1 MHz VDD = 1.8 V VDD = 3.0 V IDD 200 300 450 µA µA Power down current (CPU sleep, RC oscillator active, 4-MHz quartz oscillator active) fSYSCL = 1 MHz VDD = 1.8 V VDD = 3.0 V IPD 40 70 180 µA µA Sleep current (CPU sleep, 32-kHz quartz oscillator active 4-MHz quartz oscillator inactive) VDD = 1.8 V VDD = 3.0 V ISleep 0.4 0.6 2.3 µA µA Sleep current (CPU sleep, 32-kHz quartz oscillator inactive 4-MHz quartz oscillator inactive) VDD = 1.8 V VDD = 3.0 V ISleep 0.1 0.3 1.5 µA µA Pin capacitance Any pin to V SS CL 71 0 p F

4552B–4BMCU–02/03 Note: The Pin BP20/NTE has a static pull-up resistor during the reset-phase of the microcontroller. Power-on Reset Threshold Voltage POR threshold voltage BOT = 1 V POR 1.6 1.7 1.8 V POR threshold voltage BOT = 0 V POR 1.85 2.0 2.15 V POR hysteresis V POR 50 mV Voltage Monitor Threshold Voltage VM high threshold voltage V DD > VM, VMS = 1 V MThh 2.75 3.0 3.25 V VM high threshold voltage V DD < VM, VMS = 0 V MThh 3.0 V VM middle threshold voltage V DD > VM, VMS = 1 V MThm 2.36 2.6 2.8 V VM middle threshold voltage V DD < VM, VMS = 0 V MThm 2.6 V VM low threshold voltage V DD > VM, VMS = 1 V MThl 1.97 2.2 2.4 V VM low threshold voltage V DD < VM, VMS = 0 V MThl 2.2 V External Input Voltage VMI V DD = 3 V, VMS = 1 V VMI 1.3 1.4 V VMI V DD = 3 V, VMS = 0 V VMI 1.2 1.3 V All Bi-directional Ports Input voltage LOW V DD = 1.8 to 6.5 V V IL VSS 0.2/g32/g180/g32 VDD V Input voltage HIGH V DD = 1.8 to 6.5 V V IH 0.8 /g180 VDD VDD V Input LOW current (switched pull-up) VDD = 2.0 V , VDD = 3.0 V, VIL= VSS IIL -1.4 -20 -12 -40 µA µA Input HIGH current (switched pull-down) VDD = 2.0 V , VDD = 3.0 V, VIH = VDD IIH 1.4 µA µA Input LOW current (static pull-up) VDD = 2.0 V VDD = 3.0 V , VIL= VSS IIL -14 -60 -50 -160 -100 -320 µA µA Input LOW current (static pull-down) V DD = 2.0 V VDD = 3.0 V , VIH= VDD IIH 14 160 100 320 µA µA Input leakage current V IL= VSS IIL 100 nA Input leakage current V IH= VDD IIH 100 nA Output LOW current V OL = 0.2 /g180VDD VDD = 2.0 V VDD = 3.0 V IOL 0.5 1.2 2.5 mA mA Output HIGH current V OH = 0.8 /g180VDD VDD = 2.0 V VDD = 3.0 V IOH -0.5 -1.2 -2.5 mA mA DC Operating Characteristics (Continued) VSS = 0 V, Tamb = -40/g176C to +125/g176C unless otherwise specified. Parameters Test Conditions Symbol Min. Typ. Max. Unit

96 ATAR862-4

4552B–4BMCU–02/03 AC Characteristics Supply Voltage VDD = 2.0 V to 4.0 V, VSS = 0 V, Tamb = 25/g176C unless otherwise specified. Parameters Test Conditions Symbol Min. Typ. Max. Unit Operation Cycle Time System clock cycle V DD = 2.0 V to 4.0 V Tamb = -40/g176C to +125/g176C tSYSCL 500 4000 ns VDD = 2.4 V to 4.0 V Tamb = -40/g176C to +125/g176C tSYSCL 250 4000 ns Timer 2 input Timing Pin T2I Timer 2 input clock f T2I 5M H z Timer 2 input LOW time Rise/fall time < 10 ns t T2IL 100 ns Timer 2 input HIGH time Rise/fall time < 10 ns t T2IH 100 ns Timer 3 Input Timing Pin T3I Timer 3 input clock f T3I SYSCL/2 MHz Timer 3 input LOW time Rise/fall time < 10 ns t T3IL 2t SYSCL ns Timer 3 input HIGH time Rise/fall time < 10 ns t T3IH 2t SYSCL ns Interrupt Request Input Timing Interrupt request LOW time Rise/fall time < 10 ns t IRL 100 ns Interrupt request HIGH time Rise/fall time < 10 ns t IRH 100 ns External System Clock EXSCL at OSC1, ECM = EN Rise/fall time < 10 ns f EXSCL 0.5 4 MHz EXSCL at OSC1, ECM = DI Rise/fall time < 10 ns f EXSCL 0.02 4 MHz Input HIGH time Rise/fall time < 10 ns t IH 0.1 µs Reset Timing Power-on reset time V DD > VPOR tPOR 1.5 5 ms RC Oscillator 1 Frequency f RcOut1 3.8 MHz Stability V DD = 2.0 V to 4.0 V Tamb = -40/g176C to +105/g176C /g68f/f ±50 % RC Oscillator 2 – External Resistor Frequency R ext = 170 k/g87 fRcOut2 4M H z Stability V DD = 2.0 V to 4.0 V Tamb = -40/g176C to +105/g176C /g68f/f ±15 % Stabilization time t S 10 µs 4-MHz Crystal Oscillator (Operating Range VDD = 2.2 V to 4.0 V) Frequency fX 4M H z Start-up time t SQ 5m s Stability /g68f/f -10 10 ppm Integrated input/output capacitances (mask programmable) CIN/COUT programmable in steps of 2p F CIN COUT pF pF

Figure 95. Crystal Equivalent Circuit Supply Voltage VDD = 2.0 V to 4.0 V, VSS = 0 V, Tamb = 25/g176C unless otherwise specified.

98 ATAR862-4

4552B–4BMCU–02/03

Ordering Information

Please select the option settings from the list below and insert ROM CRC. Output Input Output Input Port 1 Port 5 BP10 [ ] CMOS [ ] Switched pull-up BP50 [ ] CMOS [ ] Switched pull-up [ ] Open drain [N] [ ] Switched pull-down [ ] Open drain [N] [ ] Switched pull-down [ ] Open drain [P] [ ] Static pull-up [ ] Open drain [P] [ ] Static pull-up []S t a t i c p u l l - d o w n []S t a t i c p u l l - d o w n BP13 [ ] CMOS [ ] Switched pull-up BP51 [ ] CMOS [ ] Switched pull-up [ ] Open drain [N] [ ] Switched pull-down [ ] Open drain [N] [ ] Switched pull-down [ ] Open drain [P] [ ] Static pull-up [ ] Open drain [P] [ ] Static pull-up []S t a t i c p u l l - d o w n []S t a t i c p u l l - d o w n Port 2 BP52 [ ] CMOS [ ] Switched pull-up BP20 [ ] CMOS [ ] Switched pull-up [ ] Open drain [N] [ ] Switched pull-down [ ] Open drain [N] [ ] Switched pull-down [ ] Open drain [P] [ ] Static pull-up [ ] Open drain [P] [ ] Static pull-up [ ] Static pull-down BP53 [ ] CMOS [ ] Switched pull-up BP21 [ ] CMOS [ ] Switched pull-up [ ] Open drain [N] [ ] Switched pull-down [ ] Open drain [N] [ ] Switched pull-down [ ] Open drain [P] [ ] Static pull-up [ ] Open drain [P] [ ] Static pull-up [ ] Static pull-down [ ] Static pull-down Port 6 BP22 [ ] CMOS [ ] Switched pull-up BP60 [ ] CMOS [ ] Switched pull-up [ ] Open drain [N] [ ] Switched pull-down [ ] Open drain [N] [ ] Switched pull-down [ ] Open drain [P] [ ] Static pull-up [ ] Open drain [P] [ ] Static pull-up []S t a t i c p u l l - d o w n []S t a t i c p u l l - d o w n BP23 [ ] CMOS [ ] Switched pull-up BP63 [ ] CMOS [ ] Switched pull-up [ ] Open drain [N] [ ] Switched pull-down [ ] Open drain [N] [ ] Switched pull-down [ ] Open drain [P] [ ] Static pull-up [ ] Open drain [P] [ ] Static pull-up []S t a t i c p u l l - d o w n []S t a t i c p u l l - d o w n Port 4 BP40 [ ] CMOS [ ] Switched pull-up OSC1 [ ] Open drain [N] [ ] Switched pull-down [ ] No integrated capacitance [ ] Open drain [P] [ ] Static pull-up [ ] Internal capacitance (0 to 20 pF) [ _____pF] [ ] Static pull-down OSC2 BP41 [ ] CMOS [ ] Switched pull-up [ ] No integrated capacitance [ ] Open drain [N] [ ] Switched pull-down [ ] Internal capacitance (0 to 20 pF) [ _____pF] [ ] Open drain [P] [ ] Static pull-up [ ] Static pull-down Clock Used BP42 [ ] CMOS [ ] Switched pull-up [ ] External resistor [ ] Open drain [N] [ ] Switched pull-down [ ] External clock [ ] Open drain [P] [ ] Static pull-up [ ] 32-kHz crystal []S t a t i c p u l l - d o w n []4 - M H z c r y s t a l BP43 [ ] CMOS [ ] Switched pull-up [ ] Open drain [N] [ ] Switched pull-down ECM (External Clock Monitor) [ ] Open drain [P] [ ] Static pull-up [ ] Enable [ ] Static pull-down [ ] Disable

4552B–4BMCU–02/03

Package Information

Extended Type Number Package Remarks ATAR862M-xxxR4-TNQ SSO24 429 MHz to 439 MHz technical drawings according to DIN specifications Dimensions in mm 8.05 7.80 0.15 0.05 0.25 0.65 7.15 1.30 5.7 5.3 4.5 4.3 6.6 6.3 0.15 24 13 11 2

100 ATAR862-4

4552B–4BMCU–02/03

4552B–4BMCU–02/03

102 ATAR862-4

4552B–4BMCU–02/03

4552B–4BMCU–02/03 Timer 3 – Mode 2: Timer/Counter, External Trigger Restart and External Timer 3 – Mode 3: Timer/Counter, Internal Trigger Restart and Internal Timer 3 – Mode 5: Timer/Counter, External Trigger Restart and External Timer 3 – Mode 6: Carrier Frequency Burst Modulation Controlled by Timer 3 – Mode 7: Carrier Frequency Burst Modulation Controlled by Timer 3 – Mode 10: Manchester Demodulation/ Pulse-width Demodulation 60 Timer 3 Demodulator for Biphase, Manchester and Pulse-width-modulated

104 ATAR862-4

4552B–4BMCU–02/03 Combination Mode 8: Manchester Demodulation/Pulse-width Combination Mode 10: Frequency Measurement or Event Counter with

4552B–4BMCU–02/03

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