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Technical content
Features
/g1202.5 A maximum peak output current /g120Drive IGBTs up to IC = 150 A, VCE = 1200 V /g120Optically isolated, FAULT status feedback /g120SO-16 package /g120CMOS/TTL compatible /g120500 ns max. switching speeds /g120“Soft” IGBT turn-off /g120Integrated fail-safe IGBT protection – Desat (VCE) detection – Under Voltage Lock-Out protection (UVLO) with hysteresis /g120User configurable: inverting, noninverting, auto-reset, auto-shutdown /g120Wide operating V CC range: 15 to 30 Volts /g120-40°C to +105°C operating temperature range /g12015 kV//g80s min. Common Mode Rejection (CMR) at VCM = 1500 V /g120Qualified to AEC-Q100 Grade 2 Test Guidelines /g120Regulatory approvals (Pending): – UL1577, CSA – IEC/EN/DIN EN 60747-5-5
Applications
/g120 Automotive Isolated IGBT/MOSFET Inverter gate drive /g120 Automotive DC-DC Converter /g120 AC and brushless dc motor drives /g120 Industrial inverters for power supplies and motor controls /g120 Un-interruptible Power Supplies VLED2+SHIELD SHIELD D R I V E R VE DESAT VCC2 VOUT VEE VCC1 GND1 RESET VIN+ VIN 9, 12 DESAT UVLO LED1 LED2 11 VC FAULTFAULT 6 VLED1VLED1+
Typical Fault Protected IGBT Gate Drive Circuit The ACPL-36JV is an easy-to-use, intelligent gate driver which makes IGBT VCE fault protection compact, affordable, and easy-to-implement. Features such as user configurable inputs, integrated VCE detection, under voltage lockout (UVLO), “soft” IGBT turn-off and isolated fault feedback provide maximum design flexibility and circuit protection. Micro-Controller Boundary Isolation Boundary Isolation Boundary Isolation Boundary Isolation Boundary Isolation Boundary Isolation Boundary Isolation MDC-DC ConverterBattery MM BatteryBattery FAULT Typical Application Block Diagram of a motor control system.
Ordering Information
ACPL-36JV is UL Recognized with 3750 Vrms for 1 minute per UL1577. Part Number RoHS Compliant Package Surface Mount Tape & Reel Quantity ACPL-36JV -000E SO-16 X 45 per tube -500E X X 850 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example 1: ACPL-36JV-500E to order product of SO-16 Surface Mount RoHS compliant package in Tape and Reel packaging. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
Description of Operation during Fault Condition 1. DESAT terminal monitors the IGBT V CE voltage through DDESAT. 2. When the voltage on the DESAT terminal exceeds 7 volts, the IGBT gate voltage (VOUT) is slowly lowered. 3. FAULT output goes low, notifying the microcontroller of the fault condition. 4. Microcontroller takes appropriate action. VIN+ VIN- UVLO (VCC2 - VE) Desat Condition Detected on Pin 14 Pin 6 (FAULT) Output V OUT X X Low X X X Active X X X Yes X X Low X Low Low Low X High X X X Low High Low Not Active No High High Output Control The outputs (V OUT and FAULT) of the ACPL-36JV are con- trolled by the combination of V IN, UVLO and a detected IGBT Desat condition. As indicated in the below table, the ACPL-36JV can be configured as inverting or non- inverting using the V IN+ or VIN- inputs respectively. When an inverting configuration is desired, V IN+ must be held high and V IN- toggled. When a non-inverting configura- tion is desired, V IN- must be held low and V IN+ toggled. Once UVLO is not active (VCC2 - VE > VUVLO), VOUT is allowed to go high, and the DESAT (pin 14) detection feature of the ACPL-36JV will be the primary source of IGBT protec- tion. UVLO is needed to ensure DESAT is functional. Once V UVLO+ > 11.6 V, DESAT will remain functional until VUVLO- < 12.4 V. Thus, the DESAT detection and UVLO features of the ACPL-36JV work in conjunction to ensure constant IGBT protection. RG 100 /g58 CBLANK DDESAT VCE *RPULL-DOWN RF 0.1/g80F 0.1 /g80F 0.1/g80F 0.1/g80F VE VLED2+ DESAT VCC2 VEE VC VOUT VEE GND1 VCC1 VLED+ VLED VIN FAULT +_C + VF VIN+ RESET +_/g80C Typical de-saturation protected gate drive circuit, non-inverting.
Product Overview Description The ACPL-36JV (shown in Figure 1) is a highly integrated power control device that incorporates all the necessary components for a complete, isolated IGBT gate drive circuit with fault protection and feedback into one SO-16 package. TTL input logic levels allow direct interface with a microcontroller, and an optically isolated power output stage drives IGBTs with power ratings of up to 150 A and 1200 V. A high speed internal optical link minimizes the propagation delays between the microcontroller and the IGBT while allowing the two systems to operate at very large common mode voltage differences that are common in industrial motor drives and other power switching ap- plications. An output IC provides local protection for the IGBT to prevent damage during overcurrents, and a second optical link provides a fully isolated fault status feedback signal for the microcontroller. A built in “watchdog” circuit monitors the power stage supply voltage to prevent IGBT caused by insufficient gate drive voltages. This integrated IGBT gate driver is designed to increase the performance and reliability of a motor drive without the cost, size, and complexity of a discrete design. Two light emitting diodes and two integrated circuits housed in the same SO-16 package provide the input control circuitry, the output power stage, and two optical channels. The input Buffer IC is designed on a bipolar process, while the output Detector IC is designed manufactured on a high voltage BiCMOS/Power DMOS process. The forward optical signal path, as indicated by LED1, transmits the gate control signal. The return optical signal path, as indicated by LED2, transmits the fault status feedback signal. Both optical channels are com- pletely controlled by the input and output ICs respective- ly, making the internal isolation boundary transparent to the microcontroller. Under normal operation, the input gate control signal directly controls the IGBT gate through the isolated output detector IC. LED2 remains off and a fault latch in the input buffer IC is disabled. When an IGBT fault is detected, the output detector IC immediately begins a “soft” shutdown sequence, reducing the IGBT current to zero in a controlled manner to avoid potential IGBT damage from inductive over-voltages. Simultaneously, this fault status is transmit- ted back to the input buffer IC via LED2, where the fault latch disables the gate control input and the active low fault output alerts the microcontroller. During power-up, the Under Voltage Lockout (UVLO) feature prevents the application of insufficient gate voltage to the IGBT, by forcing the ACPL-36JV’s output low. Once the output is in the high state, the DESAT (V CE) detection feature of the ACPL-36JV provides IGBT protection. Thus, UVLO and DESAT work in conjunction to provide constant IGBT protection.
VIN VCC1 GND1 RESET FAULT V LED1+ VLED1 Package Pin Out Pin Descriptions Symbol Description Symbol Description VIN+ Noninverting gate drive voltage output (VOUT) control input. VE Common (IGBT emitter) output supply voltage. VIN- Inverting gate drive voltage output (VOUT) control input. VLED2+ LED 2 anode. This pin must be left unconnected for guaranteed data sheet performance. (For optical coupling testing only.) V CC1 Positive input supply voltage. (4.5 V to 5.5 V) DESAT Desaturation voltage input. When the voltage on DESAT exceeds an internal reference voltage of 7 V while the IGBT is on, FAULT output is changed from a high impedance state to a logic low state within 5 /g80s. See Note 25. GND1 Input Ground. V CC2 Positive output supply voltage. RESET FAULT reset input. A logic low input for at least 0.1 /g80s, asynchronously resets FAULT output high and enables VIN. Synchronous control of RESET relative to VIN is required. RESET is not affected by UVLO. Asserting RESET while VOUT is high does not affect VOUT. VC Collector of output pull-up triple-darlington transistor. It is connected to VCC2 directly or through a resistor to limit output turn-on current. FAULT Fault output. FAULT changes from a high impedance state to a logic low output within 5 /g80s of the voltage on the DESAT pin exceeding an internal reference voltage of 7 V. FAULT output remains low until RESET is brought low. FAULT output is an open collector which allows the FAULT outputs from all HCPL-316Js in a circuit to be connected together in a “wired OR” forming a single fault bus for interfacing directly to the micro-controller. V OUT Gate drive voltage output. VLED1+ LED 1 anode. This pin must be left unconnected for guaranteed data sheet performance. (For optical coupling testing only.) V EE Output supply voltage. VLED1- LED 1 cathode. This pin must be connected to ground.
0.295 ± 0.010 (7.493 ± 0.254) 10111213141516 87654321 0.018 (0.457) 0.138 ± 0.005 (3.505 ± 0.127) 0.406 ± 0.10 (10.312 ± 0.254) 0.408 ± 0.010 (10.363 ± 0.254) 0.025 MIN. 0.008 ± 0.003 (0.203 ± 0.076) STANDOFF 0.345 ± 0.010 (8.763 ± 0.254) 0–8° 0.018 (0.457) 0.050 (1.270) ALL LEADS TO BE COPLANAR ± 0.002 YYWW EE A 36JV TYPE NUMBER EXTENDED DATECODE FOR LOT TRACKING DATE CODE 0.458 (11.63) 0.085 (2.16) 0.025 (0.64) LAND PATTERN RECOMMENDATION Package Characteristics All specifications and figures are at the nominal (typical) operating conditions of VCC1 = 5 V, VCC2 - VEE = 30 V, VE - VEE = 0 V, and TA = +25°C. Parameter Symbol Min. Typ. Max. Units Test Conditions Note Input-Output Momentary Withstand Voltage V ISO 3750 V RMS RH < 50%, t = 1 min. TA = 25°C 1, 2, 3 Resistance (Input-Output) R I-O >109 /g58 VI-O = 500 Vdc 3 Capacitance (Input-Output) C I-O 1.3 pF f = 1 MHz Output IC-to-Pins 9 & 12 Thermal Resistance /g84O9-12 30 °C/W T A = 100°C Input IC-to-Pin 1 Thermal Resistance /g84I1 60 °C/W T A = 100°C IEC/EN/DIN EN 60747-5-5 Approved under: IEC 60747-5-5: Pending EN 60747-5-5: Pending DIN EN 60747-5-5: Pending UL Pending approval under UL 1577, component recognition program up to VISO = 3750 VRMS expected prior to product release. CSA Pending approval under CSA Component Acceptance Notice #5, File CA 88324. Recommended Pb-Free IR Profile Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used. The ACPL-36JV-000E is pending approval by the following organizations:
Figure 2. Dependence of safety limiting values on temperature.
- Isolation characteristics are guaranteed only within the safet y maximum ratings which must be ensured by protective circuits in application.
Surface Mount Classification is Class A in accordance with CECCOO802.
- Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulation s section, (IEC/EN/
DIN EN 60747-5-5) for a detailed description of Method a and Method b partial discharge test profiles.
- Refer to the following figure for dependence of P S and IS on ambient temperature.
Insulation and Safety Related Specifications Parameter Symbol Value Units Conditions Minimum External Air Gap (Clearance) L(101) 8.3 mm Measured from input terminals to output terminals, shortest distance through air. Minimum External Tracking (Creepage) L(102) 8.3 mm Measured from input terminals to output terminals, shortest distance path along body. Minimum Internal Plastic Gap (Internal Clearance) 0.5 mm Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. Tracking Resistance (Comparative Tracking Index) CTI >175 Volts DIN IEC 112/VDE 0303 Part 1 Isolation Group IIIa Material Group (DIN VDE 0110) Absolute Maximum Ratings Parameter Symbol Min. Max. Units Note Storage Temperature T S -55 150 °C Operating Temperature T A -40 105 °C Output IC Junction Temperature T J 140 °C 4 Peak Output Current |I O(peak)| 2.5 A 5 Fault Output Current I FAULT 8m A Positive Input Supply Voltage V CC1 -0.5 5.5V Volts Input Pin Voltages V IN+, VIN- and VRESET -0.5 V CC1 Volts Total Output Supply Voltage (V CC2 - VEE) -0.5 35 Volts Negative Output Supply Voltage (V E - VEE) -0.5 15 Volts 6 Positive Output Supply Voltage (V CC2 - VE) -0.5 35 - (V E - VEE) Volts Gate Drive Output Voltage V o(peak) -0.5 V CC2 Volts Collector Voltage V C VEE + 5 V V CC2 Volts DESAT Voltage V DESAT V E VE + 10 Volts Output IC Power Dissipation P O 600 mW 4 Input IC Power Dissipation P I 150 mW Solder Reflow Temperature Profile See Package Outline Drawings section Recommended Operating Conditions Parameter Symbol Min. Max. Units Notes Input Supply Voltage V CC1 4.5 5.5 Volts 28 Total Output Supply Voltage (V CC2 - VEE) 15 30 Volts 9 Negative Output Supply Voltage (V E - VEE) 0 15 Volts 6 Positive Output Supply Voltage (V CC2 - VE) 15 30 – (V E - VEE) Volts Collector Voltage V C V EE + 6 V CC2 Volts Operating Temperature T A -40 105 °C
Recommended operating conditions unless otherwise specified: T A = -40°C to +105°C, all typical values at T A = 25°C, VCC1 = 5 V, and VCC2 - VEE = 30 V, VE - VEE = 0 V; all Minimum/Maximum specifications are at Recommended Operating Conditions. Parameter Symbol Min. Typ.* Max. Units Test Conditions Fig. Note Logic Low Input Voltages V IN+L, VIN-L, VRESETL 0.8 V Logic High Input Voltages V IN+H, VIN-H, VRESETH 2.0 V Logic Low Input Currents I IN+L, IIN-L, IRESETL -0.5 -0.4 mA V IN = 0.4 V FAULT Logic Low Output Current IFAULTL 5.0 12 mA V FAULT = 0.4 V 29 FAULT Logic High Output Current IFAULTH -40 /g80A VFAULT = VCC1 30 High Level Output Current I OH -0.5 -2.0 -1.5 A V OUT = VCC2 - 4 V VOUT = VCC2 - 15 V 3, 8, Low Level Output Current I OL 0.5 2.0 2.3 A V OUT = VEE + 2.5 V VOUT = VEE + 15 V 4, 9, Low Level Output Current I OLF 90 160 230 mA V OUT - VEE = 14 V 5, 33 8 High Level Output Voltage V OH V C - 3.5 V C - 2.5 V C - 1.5 V I OUT = -100 mA 6, 8, 9, 10, 11 VC -2.9 V C - 2.0 V C - 1.2 V IOUT = -650 /g80A 34 VC VI OUT = 0 Low Level Output Voltage V OL 0.17 0.5 V I OUT = 100 mA 7, 9, 35 26 High Level Input Supply Current ICC1H 17 22 mA V IN+ = VCC1 = 5.5 V, VIN- = 0 V 10, 36 Low Level Input Supply Current ICCIL 6 11 mA V IN+ = VIN- = 0 V, VCC1 = 5.5 V, 10, 37 Output Supply Current I CC2 2.5 5 mA V OUT open 11, 12, 38, 39 Low Level Collector Current I CL 0.3 1.0 mA I OUT = 0 15, 58 27 High Level Collector Current I CH 0.3 1.3 mA I OUT = 0 15, 57 27 1.8 3.0 mA IOUT = -650 /g80A 15, 56 27 VE Low Level Supply Current I EL -0.7 -0.4 0 mA 14, 60 VE High Level Supply Current I EH -0.5 -0.14 0 mA 14, 59 25 Blanking Capacitor Charging Current ICHG -0.13 -0.18 -0.25 -0.25 -0.33 -0.33 mA mA VDESAT = 0 - 6 V VDESAT = 0 - 6 V, TA = 25°C - 105°C 13, 40 11, 12 Blanking Capacitor Discharge Current IDSCHG 10 50 mA V DESAT = 7 V 41 UVLO Threshold V UVLO+ VUVLO- 11.6 12.3 11.1 13.5 12.4 V V VOUT > 5 V VOUT < 5 V 42 9, 11, 13 9, 11, 14 UVLO Hysteresis (V UVLO+ VUVLO-) 0.4 1.2 V 42 DESAT Threshold V DESAT 6.5 7.0 7.5 V V CC2 - VE > VUVLO- 16, 43 11
Unless otherwise noted, all typical values at T A = 25°C, V CC1 = 5 V, and V CC2 - V EE = 30 V, V E - V EE = 0 V; all Minimum/ Maximum specifications are at Recommended Operating Conditions. Parameter Symbol Min. Typ.* Max. Units Test Conditions Fig. Note VIN to High Level Output Propagation Delay Time tPLH 0.10 0.30 0.50 /g80s Rg = 10 /g58 Cg = 10 nF f = 10 kHz Duty Cycle = 50% 17,18,19, 20,21,22, 44, 53, 54 V IN to Low Level Output Propagation Delay Time tPHL 0.10 0.32 0.5 /g80s Pulse Width Distortion PWD -0.30 0.02 0.30 /g80s 16,17 Propagation Delay Difference Between Any 2 Parts (tPHL-tPLH) PDD -0.35 0.35 /g80s 17,18 10% to 90% Rise Time t r 0.1 /g80s 44 90% to 10% Fall Time t f 0.1 /g80s 44 DESAT Sense to 90% VOUT Delay tDESAT(90%) 0.3 0.5 /g80s Rg = 10 /g58 Cg = 10 nF 23, 55 19 DESAT Sense to 10% VOUT Delay tDESAT(10%) 2.0 3.0 /g80s VCC2 - VEE = 30 V 24, 26, 27 45, 55 DESAT Sense to Low Level FAULT Signal Delay tDESAT(FAULT) 1.8 5 /g80s 25, 46, 55 20 DESAT Sense to DESAT Low Propagation Delay tDESAT(LOW) 0.25 /g80s 55 21 RESET to High Level FAULT Signal Delay tRESET(FAULT) 372 0 /g80s 28, 47, 55 22 RESET Signal Pulse Width PW RESET 0.1 /g80s UVLO to VOUT High Delay t UVLO ON 4.0 /g80s VCC2 = 1.0 ms ramp 48 13 UVLO to VOUT Low Delay t UVLO OFF 6.0 /g80s 14 Output High Level Common Mode Transient Immunity |CMH|1 5 3 0 kV//g80s TA = 25°C, VCM = 1500 V, VCC2 = 30 V 49, 50, 51, Output Low Level Common Mode Transient Immunity |CML|1 5 3 0 kV//g80s TA = 25°C, VCM = 1500 V, VCC2 = 30 V
Notes: 1. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥4500 Vrms for 1 second ( leakage detection current limit, II-O ≤ 5 /g80A). 2. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-outpu t continuous voltage rating. For the continuous voltage rating refer to your equipment level safety specification or IEC/EN/DIN EN 60747-5-5 Insulation Characteristics Table. 3. Device considered a two terminal device: pins 1 - 8 shorted together and pins 9 - 12 shorted together. 4. In order to achieve the absolute maximum power dissipation specified, pins 1, 9, and 12 require ground plane connections and may require airflow. See the Thermal Model section in the application notes at the end of this data sheet for details on how to estimate junction temperature and power dissipation. In most cases the absolute maximum output IC junction temperature is the limiting factor. The actual power dissipation achievable will depend on the application environment (PCB Layout, air flow, part placement, etc.). See the Recommended PCB Layo ut section in the application notes for layout considerations. Output IC po wer dissipation is derated linearly at 10 mW/°C above 90°C. Inp ut IC power dissipation does not require de-rating. 5. Maximum pulse width = 10 μs, maximum duty cycle = 0.2%. This value is intended to allow for component tolerances for designs with IO peak minimum = 2.0 A. See Applications section for additional details on I OH peak. De-rate linearly from 3.0 A at +25°C to 2.5 A at +105°C. This compensates for increased IOPEAK due to changes in VOL over temperature. 6. This supply is optional. Required only when negative gate drive is implemented. 7. Maximum pulse width = 50 /g80s, maximum duty cycle = 0.5%. 8. See the Slow IGBT Gate Discharge During Fault Condition section in the applications notes at the end of this data sheet for further details. 9. 15 V is the recommended minimum operating positive supply voltage (V CC2 - VE) to ensure adequate margin in excess of the maximum VUVLO+ threshold of 13.5 V. For High Level Output Voltage testing, V OH is measured with a dc load current. When driving capacitive loads, V OH will approach VCC as IOH approaches zero units. 10. Maximum pulse width = 1.0 ms, maximum duty cycle = 20%. 11. Once V OUT of the ACPL-36JV is allowed to go high (V CC2 - VE > VUVLO), the DESAT detection feature of the ACPL-36JV will be the primary source the DESAT detection and UVLO features of the ACPL-36JV work in conjunction to ensure constant IGBT protection. 12. See the Blanking Time Control section in the applications notes at the end of this data sheet for further details. 13. This is the “increasing” (i.e. turn-on or “positive going” direction) of V CC2 - VE. 14. This is the “decreasing” (i.e. turn-off or “negative going” direction) of V CC2 - VE. 15. This load condition approximates the gate load of a 1200 V/75A IGBT. 16. Pulse Width Distortion (PWD) is defined as |t PHL - tPLH| for any given unit. 17. As measured from V IN+, VIN- to VOUT. 18. The difference between t PHL and tPLH between any two ACPL-36JV parts under the same test conditions. 19. Supply Voltage Dependent. 20. This is the amount of time from when the DESAT threshold is exceeded, until the FAULT output goes low. 21. This is the amount of time the DESAT threshold must be exceeded before V OUT begins to go low, and the FAULT output to go low. 22. This is the amount of time from when RESET is asserted low, until FAULT output goes high. The minimum specification of 3 μs is the guaranteed minimum FAULT signal pulse width when the ACPL-36JV is configured for Auto-Reset. See the Auto-Reset section in the applications notes at the end of this data sheet for further details. 23. Common mode transient immunity in the high state is the maximum tolerable dV CM/dt of the common mode pulse, V CM, to assure that the output will remain in the high state (i.e., VO > 15 V or FAULT > 2 V). A 100 pF and a 3K/g58 pull-up resistor is needed in fault detection mode. 24. Common mode transient immunity in the low state is the maximum tolerable dV CM/dt of the common mode pulse, V CM, to assure that the 25. Does not include LED2 current during fault or blanking capacitor discharge current. 26. To clamp the output voltage at V CC - 3 VBE, a pull-down resistor between the output and V EE is recommended to sink a static current of 650 /g80A while the output is high. See the Output Pull-Down Resistor section in the application notes at the end of this data sheet if an output pull-down resistor is not used. 27. The recommended output pull-down resistor between V OUT and VEE does not contribute any output current when VOUT = VEE. 28. In most applications V CC1 will be powered up first (before VCC2) and powered down last (after VCC2). This is desirable for maintaining control of the IGBT gate. In applications where VCC2 is powered up first, it is important to ensure that Vin+ remains low until VCC1 reaches the proper operating voltage (minimum 4.5 V) to avoid any momentary instability at the output during VCC1 ramp-up or ramp-down.
14 IC (mA)
16 DELAY – /g80s
Figure 31. IOH pulsed test circuit. Figure 32. I OL pulsed test circuit. Figure 29. IFAULTL test circuit. Figure 30. IFAULTH test circuit.
Typical Application/Operation Introduction to Fault Detection and Protection The power stage of a typical three phase inverter is sus- ceptible to several types of failures, most of which are potentially destructive to the power IGBTs. These failure modes can be grouped into four basic categories: phase and/or rail supply short circuits due to user misconnect or bad wiring, control signal failures due to noise or compu- tational errors, overload conditions induced by the load, and component failures in the gate drive circuitry. Under any of these fault conditions, the current through the IGBTs can increase rapidly, causing excessive power dis- sipation and heating. The IGBTs become damaged when the current load approaches the saturation current of the device, and the collector to emitter voltage rises above the saturation voltage level. The drastically increased power dissipation very quickly overheats the power device and destroys it. To prevent damage to the drive, fault protec- tion must be implemented to reduce or turn--off the over---off the over--off the over- currents during a fault condition. A circuit providing fast local fault detection and shutdown is an ideal solution, but the number of required compo- nents, board space consumed, cost, and complexity have until now limited its use to high performance drives. The features which this circuit must have are high speed, low cost, low resolution, low power dissipation, and small size. Applications Information The ACPL-36JV satisfies these criteria by combining a high speed, high output current driver, high voltage optical isolation between the input and output, local IGBT de- saturation detection and shut down, and an optically isolated fault status feedback signal into a single 16-pin surface mount package. The fault detection method, which is adopted in the ACPL-36JV, is to monitor the saturation (collector) voltage of the IGBT and to trigger a local fault shutdown sequence if the collector voltage exceeds a predetermined threshold. A small gate discharge device slowly reduces the high short circuit IGBT current to prevent damaging voltage spikes. Before the dissipated energy can reach destructive levels, the IGBT is shut off. During the off state of the IGBT, the fault detect circuitry is simply disabled to prevent false ‘fault’ signals. The alternative protection scheme of measuring IGBT current to prevent desaturation is effective if the short circuit capability of the power device is known, but this method will fail if the gate drive voltage decreases enough to only partially turn on the IGBT. By directly measuring the collector voltage, the ACPL-36JV limits the power dissipation in the IGBT even with insufficient gate drive voltage. Another more subtle advantage of the desatu- ration detection method is that power dissipation in the IGBT is monitored, while the current sense method relies on a preset current threshold to predict the safe limit of operation. Therefore, an overly- conservative overcurrent threshold is not needed to protect the IGBT. Recommended Application Circuit The ACPL-36JV has both inverting and non-inverting gate control inputs, an active low reset input, and an open collector fault output suitable for wired ‘OR’ applications. The recommended application circuit shown in Figure 61 illustrates a typical gate drive implementation using the ACPL-36JV. The four supply bypass capacitors (0.1 /g80F) provide the large transient currents necessary during a switching transition. Because of the transient nature of the charging currents, a low current (5 mA) power supply suffices. The desat diode and 100pF capacitor are the necessary external components for the fault detection circuitry. The gate resistor (10 /g58) serves to limit gate charge current and indirectly control the IGBT collector voltage rise and fall times. The open collector fault output has a passive 3.3 k/g58 pull-up resistor and a 330 pF filtering capacitor. A clamping diode between V CC1 and RESET will prevent positive going voltage noises affecting the FAULT status. A 47 k /g58 pulldown resistor on V OUT provides a more predictable high level output voltage (V OH). In this appli- cation, the IGBT gate driver will shut down when a fault is detected and will not resume switching until the micro- controller applies a reset signal.
Slow IGBT Gate Discharge During Fault Condition When a desaturation fault is detected, a weak pull-down device in the ACPL-36JV output drive stage will turn on to ‘softly’ turn off the IGBT. This device slowly discharges the IGBT gate to prevent fast changes in drain current that could cause damaging voltage spikes due to lead and wire inductance. During the slow turn off, the large output pull-down device remains off until the output voltage falls below V EE + 2 Volts, at which time the large pull down device clamps the IGBT gate to VEE. DESAT Fault Detection Blanking Time The DESAT fault detection circuitry must remain disabled for a short time period following the turn-on of the IGBT to allow the collector voltage to fall below the DESAT theshold. This time period, called the DESAT blanking time, is controlled by the internal DESAT charge current, the DESAT voltage threshold, and the external DESAT capacitor. The nominal blanking time is calculated in terms of external capacitance (C BLANK), FAULT threshold voltage (VDESAT), and DESAT charge current (ICHG) as t BLANK = CBLANK x VDESAT / ICHG. The nominal blanking time with the recommended 100 pF capacitor is 100 pF * 7 V / 250 A = 2.8 /g80sec. The capacitance value can be scaled slightly to adjust the blanking time, though a value smaller than 100 pF is not recommended. This nominal blanking time also represents the longest time it will take for the ACPL-36JV to respond to a DESAT fault condition. If the IGBT is turned on while the collector and emitter are shorted to the supply rails (switching into a short), the soft shut-down sequence will begin after ap- proximately 3 /g80sec. If the IGBT collector and emitter are shorted to the supply rails after the IGBT is already on, the response time will be much quicker due to the parasitic parallel capacitance of the DESAT diode. The recommend- ed 100 pF capacitor should provide adequate blanking as well as fault response times for most applications. Under Voltage Lockout The ACPL-36JV Under Voltage Lockout (UVLO) feature is designed to prevent the application of insufficient gate voltage to the IGBT by forcing the ACPL-36JV output low during power-up. IGBTs typically require gate voltages of
15 V to achieve their rated V
CE(ON) voltage. At gate voltages below 13 V typically, their on-voltage increases dramatical- ly, especially at higher currents. At very low gate voltages (below 10 V), the IGBT may operate in the linear region and quickly overheat. The UVLO function causes the output to be clamped whenever insufficient operating supply (V CC2) is applied. Once V CC2 exceeds VUVLO+ (the positive-going UVLO threshold), the UVLO clamp is released to allow the device output to turn on in response to input signals. As V CC2 is increased from 0 V (at some level below V UVLO+), first the DESAT protection circuitry becomes active. As V CC2 is further increased (above V UVLO+), the UVLO clamp is released. Before the time the UVLO clamp is released, the DESAT protection is already active. Therefore, the UVLO and DESAT FAULT DETECTION features work together to provide seamless protection regardless of supply voltage (V CC2). Behavioral Circuit Schematic The functional behavior of the ACPL-36JV is represented by the logic diagram in Figure 63 which fully describes the interaction and sequence of internal and external signals in the ACPL-36JV. Input IC In the normal switching mode, no output fault has been detected, and the low state of the fault latch allows the input signals to control the signal LED. The fault output is in the open-collector state, and the state of the Reset pin does not affect the control of the IGBT gate. When a fault is detected, the FAULT output and signal input are both latched. The fault output changes to an active low state, and the signal LED is forced off (output LOW). The latched condition will persist until the Reset pin is pulled low. Output IC Three internal signals control the state of the driver output: the state of the signal LED, as well as the UVLO and Fault signals. If no fault on the IGBT collector is detected, and the supply voltage is above the UVLO threshold, the LED signal will control the driver output state. The driver stage logic includes an interlock to ensure that the pull-up and pull-down devices in the output stage are never on at the same time. If an undervoltage condition is detected, the output will be actively pulled low by the 50x DMOS device, regardless of the LED state. If an IGBT desaturation fault is detected while the signal LED is on, the Fault signal will latch in the high state. The triple darlington AND the 50x DMOS device are disabled, and a smaller 1x DMOS pull-down device is activated to slowly discharge the IGBT gate. When the output drops below two volts, the 50x DMOS device again turns on, clamping the IGBT gate firmly to Vee. The Fault signal remains latched in the high state until the signal LED turns off.
Other Recommended Components The application circuit in Figure 61 includes an output pull- down resistor, a DESAT pin protection resistor, a FAULT pin capacitor (330 pF), and a FAULT pin pull-up resistor. Output Pull-Down Resistor During the output high transition, the output voltage rapidly rises to within 3 diode drops of V CC2. If the output current then drops to zero due to a capacitive load, the output voltage will slowly rise from roughly V CC2-3(VBE) to VCC2 within a period of several microseconds. To limit the output voltage to V CC2-3(VBE), a pull-down resistor between the output and V EE is recommended to sink a static current of several 650 /g80A while the output is high. Pull-down resistor values are dependent on the amount of positive supply and can be adjusted according to the formula, R pull-down = [VCC2-3 * (VBE)] / 650 /g80A. DESAT Pin Protection The freewheeling of flyback diodes connected across the IGBTs can have large instantaneous forward voltage tran- sients which greatly exceed the nominal forward voltage of the diode. This may result in a large negative voltage spike on the DESAT pin which will draw substantial current out of the IC if protection is not used. To limit this current to levels that will not damage the IC, a 100 ohm resistor should be inserted in series with the DESAT diode. The added resistance will not alter the DESAT threshold or the DESAT blanking time. Pull-up Resistor on FAULT Pin The FAULT pin is an open-collector output and therefore requires a pull-up resistor to provide a high-level signal. Capacitor on FAULT Pin for High CMR Rapid common mode transients can affect the fault pin voltage while the fault output is in the high state. A 330 pF capacitor (Fig. 66) should be connected between the fault pin and ground to achieve adequate CMOS noise margins at the specified CMR value of 15 kV//g80s. The added capaci- tance does not increase the fault output delay when a de- saturation condition is detected. Protection on RESET Pin for High CMR Large voltage spike on RESET due to excessive switching noise coupling could trigger false FAULT output signal. In such cases connecting a 330pF filtering capacitor between RESET and GROUND or a clamping diode between RESET to V CC1 will eliminate the false FAULT signal. Driving with Standard CMOS/TTL for High CMR Capacitive coupling from the isolated high voltage circuitry to the input referred circuitry is the primary CMR limitation. This coupling must be accounted for to achieve high CMR performance. The input pins V IN+ and VIN- must have active drive signals to prevent unwanted switching of the output under extreme common mode transient conditions. Input drive circuits that use pull-up or pull- down resistors, such as open collector configurations, should be avoided. Standard CMOS or TTL drive circuits are recommended. User-Configuration of the ACPL-36JV Input Side The VIN+, VIN-, FAULT and RESET input pins make a wide variety of gate control and fault configurations possible, depending on the motor drive requirements. The ACPL-36JV has both inverting and nonninverting gate control inputs, an open collector fault output suitable for wired ‘OR’ applications and an active low reset input. Driving Input of ACPL-36JV in Non-Inverting/ Inverting Mode The Gate Drive Voltage Output of the ACPL-36JV can be configured as inverting or non-inverting using the V IN– and VIN+ inputs. As shown in Figure 67, when a non-inverting configuration is desired, VIN– is held low by connecting it to GND1 and VIN+ is toggled. As shown in Figure 68, when an inverting configuration is desired, V IN+ is held high by connecting it to VCC1 and VIN– is toggled. Local Shutdown, Local Reset As shown in Figure 69, the fault output of each ACPL-36JV gate driver is polled separately, and the individual reset lines are asserted low independently to reset the motor controller after a fault condition. Global-Shutdown, Global Reset As shown in Figure 70, when configured for inverting operation, the ACPL-36JV can be configured to shutdown automatically in the event of a fault condition by tying the FAULT output to V IN+. For high reliability drives, the open collector FAULT outputs of each ACPL-36JV can be wire ‘OR’ed together on a common fault bus, forming a single fault bus for interfacing directly to the micro-controller. When any of the six gate drivers detects a fault, the fault output signal will disable all six ACPL-36JV gate drivers simultaneously and thereby provide protection against further catastrophic failures.
maximum allowable power rating.
- Calculate the minimum desired R
- Calculate total power dissipation in the part referring
- Compare the input and output power dissipation
due to charging and discharging power device gate. SWITCH = average carrier signal frequency. Figure 75. Typical peak ION and IOFF currents vs. Rg (for ACPL-36JV output driving an IGBT rated at 600 V/100 A).