U9280M-H

U9280M-H ATMEL | Alldatasheet

Document overview

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Technical content

Features

• 4-bit HARVARD Architecture  4 k /g180/g328-bit Application ROM  256 /g180/g324-bit RAM  32 /g180/g3216-bit EEPROM  10 Bi-directional I/Os  4 External Interrupt Inputs (SSO20)  8 Interrupt Levels  2 /g180/g328-bit Multifunction Timer/Counter  Interval Timer with Watchdog  Two-Wire Interface (TWI)  Voltage Supervisor  On-chip RC Oscillator  On-chip Crystal Oscillator Benefits  Contactless Power Supply and Communication Interface  Power Management for Contactless and Battery Power Supply  Shift-register-supported Modulator and Demodulator Stages  Low Power Consumption  Active Mode < 300 µA at 2 V and 1 MHz System Clock Frequency (2 µs Instruction Cycle)  Power-down Mode < 1 µA  Supply Voltage 2.0 V to 6.5 V  High-level Language Programming in qFORTH  Operating Speed: 1 µs to 10 µs Instruction Cycle (2 µs at VDD = 2 V)

Description

The U9280M-H IC is a multi-chip module for remote control and contactless ID sys- tems. It consists of the ATAR092 microcontroller and U3280M transponder interface circuit with EEPROM. A coil connected to the transponder interface serves as a wire- less bi-directional communication interface as well as a power supply for the microcontroller and the interface. As a transponder, the device is supplied by a mag- netic RF field applied at the coil. For IR- or RF-transmitter applications, it can be supplied by a battery. The microcontroller supports, with its built-in timers, a wide range of IR- and RF-transmission modes such as burst-modulation modes, PWM-, NRZ-, Manchester- and Bi-phase coding. Microcontroller with Transponder Interface U9280M-H Preliminary Rev. 4591A–RFID–03/03

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Figure 1. Block Diagram Figure 2. Pinning SSO20

4591A–RFID–03/03 Pin Description Pin Symbol Function

1 COIL1 Coil input 1, Pin to connect an LC antenna for communication and field supply

2 COIL2 Coil input 2, Pin to connect an LC antenna for communication and field supply

3 VBATT Power-supply voltage input to connect a battery

Power-supply voltage for the microcontroller and EEPROM. At this pin a capacitor (0.5 µF to 10 µF) must be connected to buffer the voltage during field supply and to block the V DD of the microcontroller.

5 BP40/SC/INT3 I/O-port line/serial clock line/INT3 input (falling edge sensitive)

6 BP53/INT3 I/O-port line/INT3 interrupt input (falling or rising edge sensitive)

7 BP50/INT6 I/O-port line/INT6 interrupt input (falling or rising edge sensitive)

8 OSC1/ROSC Oscillator- or external system-clock input/input for RC-oscillator resistor

9 OSC2 Oscillator output

10 BP60/T3O Bi-directional I/O-line/Timer 3 output/modulator output

11 BP63/T3I/INT5 I/O-port line/INT5 interrupt input/Timer 3 input/demodulator input

12 BP20/NTE BP20-I/O-port line/test mode input. This input is used to control the test modes. During POR it must not be connected with a low impedance to V DD.

13 BP23 I/O-port line

14 BP41/VMI I/O-port line/Voltage monitor input/Timer 2 input

15 BP42/T2O I/O-port line/Timer 2 output/modulator output

16 BP43/SD/INT3 I/O-port line/serial data line/INT3 input (falling edge sensitive)

17 VSS Circuit ground

18 FC Field clock output of the clock extractor

19 MOD Modulation input - front end. Must be connected to the modulator output T2O. 20 NGAP Gap detect output - front end. Must be connected to the demodulator input T3I.

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4591A–RFID–03/03 Functional The U9280M-H multi-chip module contains a microcontroller and a transponder IC mounted in a single package. Everything necessary for remote control and wireless identifcation systems is integrated: Inputs to connect keys, outputs to control an IR- or RF transmitter and to drive indicator LEDs, an EEPROM to store key code and identifi- ers, and an interface for contactless communication and a power supply. The U3280M is a transponder interface consisting of an analog front end for contactless data communication and power supply, and a serial 512-bit EEPROM. In addition, it includes power management to switch the battery or magnetic-field power supply. For modulation and demodulation of the magnetic field, the device has input and output pins to connect the microcontroller. The MOD, NGAP and FC Pins can be connected exter- nally to the modulator, demodulator and timer I/O pins of the microcontroller. Access to the EEPROM is possible via a two-wire serial interface. The ATAR092 microcontrollers are equipped with compatible two-wire serial interface to communicate with the U3280M. In the U9280M-H the serial interfaces of the transponder interface and the microcontroller are linked internally. ATAR092 The ATAR092 microcontroller is a member of the Atmel’s 4-bit single-chip microcontrol- ler family. It is especially designed for remote-control applications. It consists of an advanced stack-based 4-bit CPU core with 4 K ROM, 256 nibble of RAM and on-chip peripherals. The CPU is based on the HARVARD architecture and contains an interrupt controller with 8 prioritized interrupt levels. The peripherals include parallel I/O ports, two 8-bit programmable multifunction timer/counters, a two-wire serial interface, an interval timer with watchdog function and a voltage supervisor. The serial interface supports, together with the timers, a modulator and demodulator stage for Manchester, Bi -phase and pulse-width modulation and demodulation. The integrated clock generator contains a RC-, a 32-kHz crystal, a 4-MHz crystal oscillator and a programmable input to use an external clock. Note: In the U9280M-H not all I/O pins of the ATAR092 are available (see “Pin Description”). The microcontroller is fully described in the MARC4 ATAR092 data sheet.

Figure 3. Block Diagram ATAR092 the coil and switches back to battery if the field is removed. to check if a field is applied at the coil. troller can read and write to the EEPROM if the supply voltage is in the operating range.

4 K x 8-bit

6 U9280M-H

4591A–RFID–03/03 The U3280M contains additional operating modes to support a wide range of applica- tions. These modes can be controlled via the serial interface. The power management can be switched off by software to disable the automatic switching between battery and field. This supports applications with battery supply only. There is an on-chip Bi-phase and Manchester modulator. It can be selected and con- trolled via the serial interface with a special mode control byte. If this modulator is used the external connection to the modulator input is not necessary. Modulation The transponder interface can modulate the m agnetic field by a modulator to transmit data to a base station. It modulates the coil voltage by varying the coil‘s load. The mod- ulator can be controlled via the MOD pin. A high level 1 increases the current into the coil inputs and damps the coil voltage. A low level 0 decreases the current and increases the coil voltage. The modulator generates a voltage stroke of about 2 V pp at the coil. A high level at the MOD input makes the maximum of the field energy available at V DD. During a reset a high level at the MOD input causes the optimum conditions for starting the device and charging the capacitor at VDD after the field is applied at the coil. Digital Input to Control the Damping Stage (MOD) Mod = 0: coil undamped Mod = 1: coil damped V CMS = VCID: modulation voltage stroke at coil inputs Note: If the automatic power management is disabled the internal front end V DD is limited at VDDC. In this case the value VDDC must be used in the formula above. Field Clock The field clock extractor of the interface makes the field clock available for the microcon- troller. It can be used to supply timer inputs to synchronize modulation and demodulation with the field clock. Gap Detect The transponder interface can also receive data. The base station modulates the data with short gaps in the field. The gap-detection circuit detects these gaps in the magnetic field and outputs the gap/field signal at the NGAP pin. A high level indicates that a field is applied at the coil and a low level indicates a gap or that the field is off. The microcon- troller must demodulate the incoming data stream at one of its inputs. Digital Output of the Gap Detection Stage (NGAP) NGAP = 0: gap detected/no field V COIL_peak = VFDOFF NGAP = 1: field detected VCOIL_peak = VFDON Note: No amplifier is used in the gap detection stage. A digital Schmitt trigger evaluates the rectified and smoothed coil voltage. VCOIL_peak VDD 2V CMS+/g180 VCU== VCOIL_peak VDD 2/g180 VCD==

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Figure 6. Switch Conditions for Power Management coil voltage becomes lower than the field-off-detection voltage (VFDOFF). will generate a reset of the microcontroller. power management-on and -off command must be transferred via the serial interface. capacitor depends on the length of the gaps and damping cycles. Table 1. Buffer Capacitor

following protocol is used for data transfers. Serial Protocol  Data states on the SDA line changing only while SCL is low. STOP condition returns the device to stand-by mode.  A receiving device generates an acknowledge (A) after the reception of each byte. condition to place the device into a known state. Figure 7. Serial Protocol

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4591A–RFID–03/03 Control Byte Format The control byte follows the start condition and consists of the 5-bit row address, 2 mode control bits and the read/not write- bit. Data Transfer Sequence  Before the START condition and after the STOP condition the device is in standby mode and the SDA-line is switched to input with a pull-up resistor.  The START condition follows a control byte that determines the following operation. Bit 0 of the control byte is used to control the following transfer direction. A 0 defines a write access and a 1 a read access. EEPROM The EEPROM has a size of 512 bi ts and is organized as a 32 /g180/g3216-bit matrix. To read and write data to and from the EEPROM the serial interface must be used. The interface supports one and two byte write accesses and one to n-byte read accesses to the EEPROM. Operating Modes The operating modes of the EEPROM are defined via the control byte. The control byte contains the row address, the mode control bits and the read/write bit that is used to control the direction of the following transfer. A 0 defines a write access and a 1 a read access. The five address bits select one of the 32 rows of the EEPROM memory to be accessed. For all accesses the complete 16-bit word of the selected row is loaded into a buffer. The buffer must be read or overwritten via the serial interface. The two mode control bits C1 and C2 define in which order the accesses to the buffer are performed: High byte – low byte or low byte – high byte. The EEPROM also supports autoincre- ment and autodecrement read operations. After sending the start address with the corresponding mode, consecutive memory ce lls can be read row by row without trans- mission of the row addresses. Two special control bytes enable the complete initialization of EEPROM with a 0 or with a 1. Write Operations The EEPROM allows 8-bit and 16-bit write operations. A write access starts with the START condition followed by a write control byte and one or two data bytes from the master. It is completed via the STOP condition from the master after the acknowledge cycle. If the EEPROM receives the control byte, it loads the content of the addressed memory cell into a 16-bit read/write buffer. After the first data byte has been received the EEPROM starts the internal programming cycle. It consists of an erase cycle (write “zeros”) and the write cycle (write “ones”). Each cycle takes about 10 ms. The write cycle is started after the stop condition and the complete buffer is stored back automati- cally to the EEPROM. That means for two-byte write operations, the second byte must be transferred within the erase cycle otherwise only the first byte will be stored in the EEPROM and the second byte will be ignored. EEPROM address Mode control bits Read/Write S t a r t A 4 A 3 A 2A 1A 0C 1C 0 R / W A c k n Start Control byte Ackn. Data byte Ackn. Data byte Ackn. Stop

4591A–RFID–03/03 Acknowledge Polling If the EEPROM is busy with an internal write cycle, all inputs are disabled and the EEPROM will not acknowledge until the write cycle is finished. This can be used to detect the end of the write cycle. The master must perform acknowledge polling by sending a start condition followed by the control byte. If the device is still busy with the write cycle, it will not return an acknowledge and the master has to generate a stop con- dition or perform further acknowledge polling sequences. If the cycle is complete, it returns an acknowledge and the master can proceed with the next read or write cycle. Note: A = acknowledge Write Control Bytes Note: HB: high byte; LB: low byte; R: row address Read Operations The EEPROM allows byte-, word- and current address read operations. The read oper- ations are initiated in the same way as write operations. Every read access is initiated by sending the START condition followed by the control byte which contains the address and the read mode. After the device receives a read command it returns an acknowl- edge, loads the addressed word into the read/write buffer and sends the selected data byte to the master. The master has to acknowledge the received byte if it wants to pro- ceed with the read operation. If two bytes are read out from the buffer the device increments respectively, decrements the word address automatically and loads the buffer with the next word. The read mode bits determines if the low or high byte is read first from the buffer and if the word address is incremented or decremented for the next read access. If the memory address limit is reached, the data word address will “roll over” and the sequential read will continue. The master can terminate the read operation after every byte by not responding with an acknowledge (N) and by issuing a stop condition. Write One Data Byte Start Control byte A Data byte 1 A Stop Write Two Data Bytes Start Control byte A Data byte 1 A Data byte 2 A Stop Write Control Byte Only Start Control byte A Stop MSB LSB Write low byte first A4 A3 A2 A1 A0 C1 C0 R/W Row address 0 1 0 Byte order LB(R) HB(R) MSB LSB Write high byte first A4 A3 A2 A1 A0 C1 C0 R/W Row address 1 0 0 Byte order HB(R) LB(R)

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and then generating a stop condition. continuous bit transfers, an acknowledge cycle after 8 bits must not be generated. Table 2. Special Modes

4591A–RFID–03/03 Data Transfer Sequence for Bi-phase and Manchester Modulation: Note: After a reset of the microcontroller, it is not known if the transponder interface has been reset, too. It could still be in a receive or transmit cycle. T o place the serial interface of the device into a known state, the miocrocontroller should read one byte from the device without acknowledge and generate a stop condition. Power-on Reset The analog front end starts working with the applied field. The EEPROM with the serial interface has its own reset circuitry. (The reset level of the front end is below the reset level of the ATAR092) The microcontroller has a power-on reset circuitry with a brown-out detection. One of two reset voltage levels [1.8 V/2.0 V] can be selected via the software (see the ATAR092 data sheet). If a fast instruction cycle (< 2 µs) is used the higher reset level should be selected. After a watchdog or brown-out detection reset, the serial interface and the EEPROM should be reset by reading one byte from the transponder interface device without acknowledgeing and generation of a STOP condition. That places the serial interface and EEPROM into a known state. Start Control byte Ackn Bit 1 Bit 2 Bit 3 ... Bit n Stop

14 U9280M-H

4591A–RFID–03/03 Electrical Characteristics – Common Features U9280M-H  Operating Temperature Range: -40/g176C to +85/g176C  Operating Voltage Range (VBatt): 2.0 V to 6.5 V  Low Power Consumption: – 600 µA at 6.5 V in Operating Mode ( with 2 µs Instruction Cycle) – 200 µA at 2.0 V in Operating Mode (with 2 µs Instruction Cycle) – 1 µA at 2.0 V in Stop Mode  Power Supply: Contactless (Coil 125 kHz) and Battery Supply Note: Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at any condition above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating condition for an extended period may affect device reliability. All inputs and outputs are protected against high electrostatic voltages or electric fields. However, precautions to minimize the build-up of electrostatic charges during handling are recommended. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (e.g., VDD). Absolute Maximum Ratings Voltages are given relative to VSS Parameters Symbol Value Unit Supply voltage V Batt,VDD 0 to +7 with reverse protection V Maximum current out of the VSS pin 15 mA Maximum current out of the VBatt pin 15 mA Input voltage (on any pin) V IN VSS- 0.6 < VIN < VDD + 0.6 V Input/output clamp current (VSS > Vi / Vo > VDD)I IK/IOK ±15 mA Minimum ESD protection (100 pF through 1.5 k/g87)± 2 k V Minimum ESD protection Coil 1 and Coil 2 inputs (100 pF through 1.5 k/g87) ±1 kV Operating temperature range T amb -40 to +85 /g176C Storage temperature range T stg -40 to +125 /g176C Soldering temperature (t /g16310 s) T sd 260 /g176C Thermal Resistance Parameters Symbol Value Unit Junction ambient SSO20 R thJA 140 K/W

4591A–RFID–03/03 Common DC Characteristics VSS = 0 V, Tamb = -40/g176C to +85/g176C unless otherwise specified Parameters Test Conditions/Pins Symbol Min. Typ. Max. Unit Power Supply Operating voltage at VBatt VBatt 2.0 6.5 V Operating voltage at VDD VDD VPOR 6.5 V Active current CPU active fSYSCL = 1 MHz VDD = 2.0 V I DD 200 250 µA VDD = 3.0 V 300 µA VDD = 6.5 V 600 800 µA Power down current (CPU sleep, RC oscillator active, 4-MHz quartz oscillator active) f SYSCL = 1 MHz 1.0 VDD = 2.0 V I PD 40 70 µA VDD = 3.0 V 100 µA VDD = 6.5 V 250 400 µA Sleep current (CPU sleep, 32-kHz quartz-oscillator inactive 4-MHz quartz-oscillator inactive) V DD = 6.5 V ISleep 1.0 2.0 µA Reset current V DD < VPOR IReset 150 µA DC Characteristics – Microcontroller ATAR092 VSS = 0 V, Tamb = -40/g176C to +85/g176C unless otherwise specified Parameters Test Conditions/Pins Symbol Min. Typ. Max. Unit Brown-out Protection Reset Threshold Voltage Reset threshold voltage BOT = 1 V POR 155 1.7 1.85 V Reset threshold voltage BOT = 0 V POR 1.85 2.0 2.2 V Reset hysteresis V POR 50 mV Voltage Monitor Threshold Voltage VM high threshold voltage V DD > VM, VMS = 1 V MThh 3.0 3.25 V VM high threshold voltage V DD < VM, VMS = 0 V MThh 2.8 3.0 V VM middle threshold voltage V DD > VM, VMS = 1 V MThm 2.6 2.8 V VM middle threshold voltage V DD < VM, VMS = 0 V MThm 2.4 2.6 V VM low threshold voltage V DD > VM, VMS = 1 V MThl 2.2 2.4 V VM low threshold voltage V DD < VM, VMS = 0 V MThl 2.0 2.2 V External Input Voltage VMI rising edge threshold VMS = 1, V DD = 3 V V VMI 1.3 1.4 V VMI falling edge threshold VMS = 0, V DD = 3 V V VMI 1.2 1.3 V

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4591A–RFID–03/03 Note: The BP20/NTE pin has a strong pull-up resistor during the reset-phase of the microcontroller. All Bi-directional Ports Input voltage LOW VDD = 1.8 V to 6.5 V VIL VSS 0.2 /g180 VDD V Input voltage HIGH VDD = 1.8 V to 6.5 V VIH 0.8 /g180 VDD VDD V Input LOW current (pull-up) VDD = 2.0 V , VDD = 3.0 V, VIL= VSS VDD = 6.5 V IIL -2.0 -50 -4.0 -20 -100 -12 -200 µA µA µA Input HIGH current (pull-down) VDD = 2.0 V , VDD = 3.0 V, VIH = VDD VDD = 6.5 V IIH 2.0 4.0 100 200 µA µA µA Input LOW current (strong pull-up) VDD = 2.0 V , VIL= VSS VDD = 6.5 V IIL -20 -300 -50 -600 -100 -1200 µA µA Input LOW current (strong pull-down) VDD = 2.0 V , VIH = VDD VDD = 6.5 V IIH 300 600 100 1200 µA µA Input leakage current V IL= VSS IIL 100 nA Input leakage current V IH= VDD IIH 100 nA Output LOW current VOL = 0.2 VDD VDD = 2.0 V VDD = 3.0 V, VDD = 6.5 V IOL 0.6 1.2 2.5 mA mA mA Output HIGH current V OH = 0.8 VDD VDD = 2.0 V VDD = 3.0 V, VDD = 6.5 V IOH -0.6 -1.2 -16 -2.5 -24 mA mA mA DC Characteristics – Microcontroller ATAR092 (Continued) VSS = 0 V, Tamb = -40/g176C to +85/g176C unless otherwise specified Parameters Test Conditions/Pins Symbol Min. Typ. Max. Unit

4591A–RFID–03/03 AC Characteristics – Operation Cycle Time Supply voltage VDD = 1.8 V to 6.5 V, VSS = 0 V, Tamb = -40/g176C to +85/g176C unless otherwise specified Parameters Test Conditions/Pins Symbol Min. Typ. Max. Unit System clock cycle VDD = 1.8 V to 6.5 V Tamb = -40/g176C to +85/g176C tSYSCL 500 2000 ns VDD = 2.4 V to 6.5 V Tamb = -40/g176C to +85/g176C tSYSCL 250 2000 ns Timer 2 Input Timing Pin T2I Timer 2 input clock f T2I 5M H z Timer 2 input LOW time t T2IL 100 ns Timer 2 input HIGH time t T2IH 100 ns Timer 3 Input Timing Pin T3I Timer 3 input clock f T3I SYSCL/2 Timer 3 input LOW time t T3IL 2 /g180/g32 tSYSCL ns Timer 3 input HIGH time t T3IH 2 /g180/g32 tSYSCL ns Interrupt Request Input Timing Interrupt request LOW time t IRL 100 ns Interrupt request HIGH time t IRH 100 ns External System Clock EXSCL at OSC1 ECM = EN Rise/fall time < 10 ns fEXSCL 0.5 4 MHz EXSCL at OSC1 ECM = DI Rise/fall time < 10 ns fEXSCL 0.02 4 MHz Input HIGH time Rise/fall time < 10 ns t IH 0.1 µs Reset Timing Power-on reset time V DD > VPOR tPOR 1.5 5 ms RC Oscillator 1 Frequency f RcOut1 3.8 MHz Stability V DD = 2.0 V to 6.5 V /g68f/f ±50 % Temperature coefficient /g68f/f//g176C0 . 1 5 % RC Oscillator 2 – External Resistor Frequency Rext = 170 k/g87 Rext = 720 k/g87 fRcOut2 fRcOut2

1 MHz

Stability V DD = 2.0 V to 6.5 V Df/f ±15 % Stabilization time t S 10 µs 4-MHz Crystal Oscillator (Operating Range 2.2 V to 6.5 V) Frequency f X 4M H z Start-up time t SQ 5m s Stability /g68f/f -10 +10 ppm Integrated input/output capacitances (mask programmable) CIN/COUT programmable in steps of 2p F CIN COUT pF pF

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Figure 8. Crystal and Equivalent Circuit

4591A–RFID–03/03 DC Characteristics –Transponder Interface U3280M Supply voltage VDD = 1.8 V to 6.5 V, VSS = 0 V, Tamb = -40/g176C to +85/g176C unless otherwise specified Parameters Test Conditions/Pins Symbol Min. Typ. Max. Unit Power Supply Operating voltage at VBatt VBatt 2.0 6.5 V Operating voltage at VDD during battery supply VDDB VBatt- VSD V VDD limiter voltage during coil supply V DDC 2.4 2.9 3.2 V Power Management Field on detection voltage V DD > 1.8 V V FDon 2.2 2.5 2.9 V Field off detection voltage V DD > 1.8 V V FDoff 0.8 V Voltage drop at power-supply switch I S = 1 mA, VBatt = 2 V V SD 300 mV Coil Input Coil 1, Coil 2 Coil input current I CI 20 mA Coil voltage stroke during modulation VCU > 5 V VCMS 1.8 4.0 V Input capacitance C IN 30 pF MOD Pin Input LOW voltage V IL VSS 0.2 /g180/g32 VDD V Input HIGH voltage V IH 0.8 /g180/g32 VDD VDD V Input leakage current I Ileak 10 nA NGAP/FC Pin Output LOW current VDD = 2.0 V VOL = 0.2 /g180/g32VDD IOL 0.08 0.2 0.3 mA Output HIGH current VDD = 2.0 V VOH = 0.8 /g180/g32VDD IOH -0.06 -0.15 -0.25 mA EEPROM Operating current during erase/write cycle VDD = 2 V IWR 450 µA

20 U9280M-H

4591A–RFID–03/03 AC Characteristics – Transponder Interface U3280M Supply voltage VDD = 1.8 V to 6.5 V, VSS = 0 V, Tamb = -40/g176C to +85/g176C unless otherwise specified Parameters Test Conditions Symbol Min. Typ. Max. Unit Serial Interface Timing (Internal) SCL clock frequency (intern) f SC 500 kHz Serial Timing (if SCL and SDA Available Extern) SCL clock frequency (extern) f SCL 01 0 0 k H z Clock low time t LOW 4.7 µs Clock high time t HIGH 4.0 µs SDA and SCL rise time t R 1000 ns SDA and SCL fall time t F 300 ns Start condition setup time t SUSTA 4.7 µs Start condition hold time t HDST A 4.0 µs Data input setup time t SUDA T 250 ns Data input hold time t HDDAT 0n s Stop condition setup time t SUSTO 4.7 µs Bus free time t BUF 4.7 µs Input filter time t I 100 ns Data output hold time t DH 300 1000 ns Coil Inputs Coil frequency f COIL 125 kHz Gap Detection Delay field off to gap = 0 V CoilGap < 0.7 VDC tFGAP0 10 50 µs Delay field on to gap = 1 V CoilField > 3 VDC tFGAP1 11 0 µ s Power Management Battery to field switch delay t BFS 160 650 µs Field to battery switch delay t FBS 10 60 ms EEPROM Endurance Erase/write-cycles ED 500,000 1,000,000 E/W- cycles Data erase/write cycle time for 16 bits access t DEW 91 2 m s Data erase time t DE 2 1/2 /g180/g32 tDEW ms Data retention time T amb = 25/g176C t DR 10 years Power-up to read operation tPUR 0.2 ms Power-up to write operation tPUW 0.2 ms

4591A–RFID–03/03

Ordering Information

Please select the option settings from the list below and insert in ROM CRC. Output Input Output Input Port 1 Port 5 B P 1 0[ X ] C M O S [ X ] P u l l - u p B P 5 0[]C M O S []P u l l - u p [ ] Open drain [N] [ ] Pull-down [ ] Open drain [N] [ ] Pull-down [ ] Open drain [P] [ ] Pull-up strong [ ] Open drain [P] [ ] Pull-up strong [ ] Pull-down strong [ ] Pull-down strong BP13 [X] CMOS [X] Pull-up BP51 [X] CMOS [X] Pull-up [ ] Open drain [N] [ ] Pull-down [ ] Open drain [N] [ ] Pull-down [ ] Open drain [P] [ ] Pull-up strong [ ] Open drain [P] [ ] Pull-up strong [ ] Pull-down strong [ ] Pull-down strong Port 2 BP52 [X] CMOS [X] Pull-up BP20 [ ] CMOS [ ] Pull-up [ ] Open drain [N] [ ] Pull-down [ ] Open drain [N] [ ] Pull-down [ ] Open drain [P] [ ] Pull-up strong [ ] Open drain [P] [ ] Pull-up strong [ ] Pull-down strong B P 5 3[]C M O S []P u l l - u p BP21 [X] CMOS [X] Pull-up [ ] Open drain [N] [ ] Pull-down [ ] Open drain [N] [ ] Pull-down [ ] Open drain [P] [ ] Pull-up strong [ ] Open drain [P] [ ] Pull-up strong [ ] Pull-down strong [ ] Pull-down strong Port 6 B P 2 2[ X ] C M O S [ X ] P u l l - u p B P 6 0[]C M O S []P u l l - u p [ ] Open drain [N] [ ] Pull-down [ ] Open drain [N] [ ] Pull-down [ ] Open drain [P] [ ] Pull-up strong [ ] Open drain [P] [ ] Pull-up strong [ ] Pull-down strong [ ] Pull-down strong B P 2 3[]C M O S []P u l l - u p B P 6 3[]C M O S []P u l l - u p [ ] Open drain [N] [ ] Pull-down [ ] Open drain [N] [ ] Pull-down [ ] Open drain [P] [ ] Pull-up strong [ ] Open drain [P] [ ] Pull-up strong [ ] Pull-down strong [ ] Pull-down strong Port 4 B P 4 0[]C M O S []P u l l - u p OSC1 [ ] Open drain [N] [ ] Pull-down [ ] No integrated capacitance [ ] Open drain [P] [ ] Pull-up strong [ ] Internal capacitance [ _____pF] [ ] Pull-down strong OSC2 BP41 [ ] CMOS [ ] Pull-up [ ] No integrated capacitance [ ] Open drain [N] [ ] Pull-down [ ] Internal capacitance [ _____pF] [ ] Open drain [P] [ ] Pull-up strong [ ] Pull-down strong ECM (External Clock Monitor) B P 4 2[]C M O S []P u l l - u p []E n a b l e [ ] Open drain [N] [ ] Pull-down [ ] Disable [ ] Open drain [P] [ ] Pull-up strong [ ] Pull-down strong B P 4 3[]C M O S []P u l l - u p [ ] Open drain [N] [ ] Pull-down [ ] Open drain [P] [ ] Pull-up strong [ ] Pull-down strong

22 U9280M-H

4591A–RFID–03/03 Customer ROM mask - To be defined by the customer - Lead time: 18 weeks after ROM mask programming and reception of the order Flash Version: As flash version of the U9280M-H the MARC4 ATAR892 is used (available from stock).

Package Information

Ordering Information (Continued) Extended Type Number Package Remarks U9280M-H-xxxz-FSG3 SSO20 > 200 kpcs annually taped and reeled technical drawings according to DIN specifications Dimensions in mm 6.75 6.50 0.25 0.65 5.85 1.30 0.15 0.05 5.7 5.3 4.5 4.3 6.6 6.3 0.15 20 11 11 0

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