U7006B ATMEL | Alldatasheet
Document overview
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Technical content
Features
Single 3-V Supply Voltage High Power-added Efficient Power Amplifier (Pout typically 26.5 dBm) Ramp-controlled Output Power Low-noise Preamplifier (NF typically 1.8 dB) Biasing for External PIN Diode T/R Switch Current-saving Standby Mode Few External Components Electrostatic sensitive device. Observe precautions for handling.
Description
The U7006B is a monolithic SiGe transmit/receive front end IC with power amplifier, 50- /g87 internal matching, low-noise amplifier and T/R switch driver. It is especially designed for operation in TDMA systems like DECT. Due to the ramp-control feature and a very low quiescent current, an external switch transistor for V S is not required. Figure 1. Block Diagram
2 U7006B
Figure 2. Pinning PSSO16
1 R_SWITCH Resistor to GND sets the PIN diode current
2 SWITCH_OUT Switched current output for PIN diode
4 LNA_IN Low-noise amplifier input
5 V1_PA Inductor to power supply for power amplifier
9 VS_PA Supply voltage for power amplifier
10 RAMP Power-ramping control input
11 P A_IN Power amplifier input
12 VS_LNA Supply-voltage input for low-noise amplifier
13 GND2 Ground
14 LNA_OUT Low-noise amplifier output
15 RX_ON RX active high
16 PU Power-up active high
4714A–DECT–07/03 Absolute Maximum Ratings All voltages refer to GND (Pins 3 and slug), ESD protection according to ESD-S5.2-1994, Class M1. Parameters Symbol Value Unit Supply voltage; pins 6, 10, 13 and 16 (no RF) V S 5V Junction temperature T j 150 /g176C Storage temperature T stg -40 to +125 /g176C Input power PA, Pin 11 P inPA +10 dBm Input power LNA, Pin 4 P inLNA -5 dBm Thermal Resistance Parameters Symbol Value Unit Junction ambient R thJA 30 K/W Operating Range All voltages refer to GND (Pins 3, 13 and slug). The following table represents the sum of all supply currents depending on the TX/RX mode. Power supply points are VS_LNA, VS_PA, V1_PA, V2_PA_OUT. Parameters Symbol Min. Typ. Max. Unit Supply voltage pins 5, 6, 7, 8 and 9 V S 2.7 3 4.6 V Supply voltage pin 12 V S 2.7 3.6 4.6 V Supply current TX RX IS IS 350 mA mA Standby current PU = 0 I S 10 µA Ambient temperature T amb -25 +25 +70 /g176C
Electrical Characteristics
Test conditions (unless otherwise specified): VS = 3 V, Tamb = 25°C, CW mode Parameters Test Conditions Symbol Min. Typ. Max. Unit Power Amplifier (1) Supply voltage Pins 5, 6, 7, 8 and 9 V S 2.7 3 4.6 V Supply current TX I S_TX 350 mA Supply current RX (PA off) I S_RX 10 µA Standby current Standby I S_standby 10 µA Frequency range TX f 1.88 1.94 GHz Power gain TX, pin 11 to pins 6, 7, 8 Gp 28 dB Gain-control range TX /g68Gp 48 dB Ramping voltage TX, power gain (max), pin 10 V RAMP max 2.1 V Ramping current TX, power gain (max), pin 10 I RAMP 0.5 2.0 mA Power-added efficiency TX PAE 40 % Notes: 1. Power amplifier shall be unconditionally stable, maximum duty cycle 50%, maximum load mismatch and duration: TBD 2. With external matching network (see Figure 13 ) 3. Low-noise amplifier shall be unconditionally stable
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4714A–DECT–07/03 Saturated output power TX, referred to pins 6, 7, 8 VS = 3.6 V Psat 26.5 dBm Input matching (2) TX, pin 11 VSWRin < 2:1 Output matching (2) TX, pins 6, 7, 8 VSWRout < 2:1 Harmonics at P 1dB TX, pins 6, 7, 8 2 fo 3 fo -30 dBc Maximum input power Pin 11 P inPA 10 dBm Stability (non harmonic emission) TX, pin 10 Pin = 2 dBm, VRAMP =2V VSWRout < 10:1 (all phases) -60 dBc T/R Switch Driver (Currently Programmed by External Resistor from R_SWITCH to GND) Switch-out current output Standby, pin 2 I S_O_standby 2µ A RX I S_O_RX 2µ A TX at 100 /g87 IS_O_100 1m A TX at 1.2 k/g87 IS_O_1k2 3m A TX at 33 k/g87 IS_O_33k 10 mA Low-noise Amplifier (3) Supply voltage All, pin 12 V S 2.7 3.6 4.6 V Supply current RX I S 8m A Supply current (LNA and control logic) TX (control logic active), pin 12 I S 300 µA Standby current Standby, pin 12 I S 11 0 µ A Frequency range RX f 1.88 1.94 GHz Power gain RX, pin 4 to pin 14 Gp 17 19 dB Noise figure RX NF 1.8 2.0 dB Gain compression RX, refer to pin 14 P1dB -7 dBm 3rd-order input interception point RX IIP3 -15 dBm Input matching RX VSWRin < 2:1 Output matching RX VSWRin < 2:1 Logic Input Levels (RX_ON, PU) High input level = 1, pins 5 and 16 V iH 2.4 V S V Low input level = 0 ViL 00 . 5 V High input current = 1 IiH 40 µA Low input current = 0 IiL 0µ A Electrical Characteristics (Continued) Test conditions (unless otherwise specified): VS = 3 V, Tamb = 25°C, CW mode Parameters Test Conditions Symbol Min. Typ. Max. Unit Notes: 1. Power amplifier shall be unconditionally stable, maximum duty cycle 50%, maximum load mismatch and duration: TBD 2. With external matching network (see Figure 13 ) 3. Low-noise amplifier shall be unconditionally stable
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Figure 5. Input Circuit RAMP/VS_PA Figure 6. Input Circuit V1_PA Figure 7. Input/Output Circuit V2_PA
8 U7006B
Figure 10. Input Circuit SWITCH_OUT/R_SWITCH Figure 11. Input Circuit RX_ON Figure 12. Input Circuit PU
Figure 13. Typical Schematic
10 U7006B
Figure 14. U7006B Application Board Schematic Figure 15. U7006B Application Board Layout
4714A–DECT–07/03
Package Information
Ordering Information
Extended Type Number Package Remarks U7006B-MLB PSSO16 Tube U7006B-MLBG3 PSSO16 Taped and reeled
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