U7004B-MFS

U7004B ATMEL | Alldatasheet

Document overview

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Technical content

Features

 Single 3-V Supply Voltage  High Power-added Efficient Power Amplifier (Pout typically 26.5 dBm)  Ramp-controlled Output Power  Low-noise Preamplifier (NF typically 1.8 dB)  Biasing for External PIN Diode T/R Switch  Current-saving Standby Mode  Few External Components Electrostatic sensitive device. Observe precautions for handling.

Description

The U7004B is a monolithic SiGe transmit/receive front end IC with power amplifier, 50- /g87 internal matching, low-noise amplifier and T/R switch driver. It is especially designed for operation in TDMA systems like DECT. Due to the ramp-control feature and a very low quiescent current, an external switch transistor for V S is not required. Figure 1. Block Diagram

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Figure 2. Pinning SSO20

1 R_SWITCH Resistor to GND sets the PIN diode current

2 SWITCH_OUT Switched current output for PIN diode

3 GND1 Ground

4 LNA_IN Low-noise amplifier input

5 GND2 Ground

6 V1_PA Inductor to power supply for power amplifier

7 GND3 Ground

8 GND4 Ground

9 GND5 Ground

10 V2_PA_OUT Inductor to power supply and matching network for power amplifier output

11 GND6 Ground

12 GND7 Ground

13 VS_PA Supply voltage for power amplifier

14 RAMP Power-ramping control input

15 PA_IN Power amplifier input

16 VS_LNA Supply-voltage input for low-noise amplifier

17 GND8 Ground

18 LNA_OUT Low-noise amplifier output

19 RX_ON RX active high

20 PU Power-up active high

4713A–DECT–07/03 Absolute Maximum Ratings All voltages refer to GND (pins 3, 5, 7, 8, 9, 11, 12 and 17), ESD protection according to ESD-S5.2-1994, Class M1. Parameters Symbol Value Unit Supply voltage pins 6, 10, 13 and 16 (no RF) V S 5V Duty cycle PA 50 % Burst duration PA 5m s Junction temperature T j 150 /g176C Storage temperature T stg -40 to +125 /g176C Input power PA pin 15 P inPA +10 dBm Input power LNA pin 4 P inLNA -5 dBm Thermal Resistance Parameters Symbol Value Unit Junction ambient R thJA 95 K/W Operating Range All voltages refer to GND (Pins 3, 5, 7, 8, 9, 11, 12 and 17). The following table represents the sum of all supply currents depending on the TX/RX mode. Power supply points are VS_LNA, VS_PA, V1_PA, V2_PA_OUT. Parameters Symbol Min. Typ. Max. Unit Supply voltage pins 6, 10 and 13 V S 2.7 3.6 4.6 V Supply voltage pin 16 V S 2.7 3.6 4.6 V Supply current TX RX IS IS 450 mA mA Standby current PU = 0 I S 10 µA Ambient temperature T amb -25 +25 +70 /g176C

Electrical Characteristics

Test conditions (unless otherwise specified): VS = 3.6 V, Tamb = 25°C, pulsed mode, duty cycle 4.17%, ton = 417 µs Parameters Test Conditions Symbol Min. Typ. Max. Unit Power Amplifier (1) Supply voltage Pins 6, 10 and 13 V S 2.7 3.6 4.6 V Supply current TX I S_TX 450 mA Supply current RX (PA off) I S_RX 10 µA Standby current Standby I S_standby 10 µA Frequency range TX f 1.88 1.94 GHz Power gain TX, pin 15 to pin 10 Gp 28 dB Gain-control range TX /g68Gp 48 dB Notes: 1. Power amplifier shall be unconditionally stable, maximum duty cycle 50%, maximum load mismatch and duration: load VSWR = 20:1 (all phases) 10 s, Z G = 50 /g87 2. With external matching network (see Figure 13 and Figure 14) 3. Low-noise amplifier shall be unconditionally stable

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4713A–DECT–07/03 Ramping voltage TX, power gain (max), pin 14 V RAMP max 2.1 V Ramping current TX, power gain (max), pin 14 I RAMP 0.5 2.0 mA Power-added efficiency TX PAE 30 % Saturated output power TX, refer to pin 10 P sat 26.5 dBm Input matching (2) TX, pin 15 VSWRin < 2:1 Output matching (2) TX, pin 10 VSWRout < 2:1 Harmonics at P 1dB TX, pin 10 2 fo 3 fo -30 dBc Maximum input power Pin 15 P inPA 10 dBm Stability (non harmonic emission) TX, pin 10 Pin = 2 dBm, VRAMP =2V VSWRout < 10:1 (all phases) -60 dBc T/R Switch Driver (Currently Programmed by External Resistor from R_SWITCH to GND) Switch-out current output Standby, pin 2 I S_O_standby 2µ A Switch-out current output RX I S_O_RX 2µ A Switch-out current output TX at 100 /g87 IS_O_100 1m A Switch-out current output TX at 1.2 k /g87 IS_O_1k2 3m A Switch-out current output TX at 33 k /g87 IS_O_33k 10 mA Low-noise Amplifier (3) Supply voltage All, pin 16 V S 2.7 3.6 4.6 V Supply current RX I S 8m A Supply current (LNA and control logic) TX (control logic active), pin 16 I S 300 µA Standby current Standby, pin 16 I S 11 0 µ A Frequency range RX f 1.88 1.94 GHz Power gain RX, pin 4 to pin 18 Gp 17 19 dB Noise figure RX NF 1.8 2.0 dB Gain compression RX, refer to pin 18 P1dB -7 dBm 3rd-order input interception point RX IIP3 -15 dBm Input matching RX VSWRin < 2:1 Output matching RX VSWRin < 2:1 Logic Input Levels (RX_ON, PU) High input level = 1, pins 19 and 20 V iH 2.4 V S V Low input level = 0 ViL 00 . 5 V High input current = 1 IiH 40 µA Low input current = 0 IiL 0µ A Electrical Characteristics (Continued) Test conditions (unless otherwise specified): VS = 3.6 V, Tamb = 25°C, pulsed mode, duty cycle 4.17%, ton = 417 µs Parameters Test Conditions Symbol Min. Typ. Max. Unit Notes: 1. Power amplifier shall be unconditionally stable, maximum duty cycle 50%, maximum load mismatch and duration: load VSWR = 20:1 (all phases) 10 s, ZG = 50 /g87 2. With external matching network (see Figure 13 and Figure 14) 3. Low-noise amplifier shall be unconditionally stable

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Figure 5. Input Circuit RAMP/VS_PA Figure 6. Input Circuit V1_PA Figure 7. Input/Output Circuit V2_PA

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Figure 10. Input Circuit SWITCH_OUT/R_SWITCH Figure 11. Input Circuit RX_ON Figure 12. Input Circuit PU

Figure 13. Typical Schematic

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Figure 14. U7004B Application Board Schematic Figure 15. U7004B Application Board Layout

4713A–DECT–07/03

Package Information

Ordering Information

Extended Type Number Package Remarks U7004B-MFS SSO20 Tube U7004B-MFSG3 SSO20 Taped and reeled technical drawings according to DIN specifications Dimensions in mm 6.75 6.50 0.25 0.65 5.85 1.30 0.15 0.05 5.7 5.3 4.5 4.3 6.6 6.3 0.15 20 11 11 0

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