U6820BM-FP

U6820BM ATMEL | Alldatasheet

Document overview

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Technical content

Features

• Four Short-circuit-protected High-side Drivers with a Maximum Current Capability of 50 mA Each  Four Short-circuit-protected Low-side Drivers with a Maximum Current Capability of 50 mA Each  ON Resistance High Side Ron < 10 Ω Versus Total Temperature Range  ON Resistance Low Side Ron < 7 Ω Versus Total Temperature Range  Short-circuit Detection of Each Driver Stage  Disabling of Driver Stages in the Case of Short-circuit and Overtemperature Detection  Independent Control of Each Driver Stage via an 8-bit Shift Register  Status Output Reports Short-circuit Condition  Status Output Reports when All Loads Are Switched Off  Timing of Status Output Reset Signalizes Failure Mode  Temperature Protection in Conjunction with Short-circuit Detection

Description

The U6820BM is a driver interface in BCDMOS technology with 8 independent driver stages having a maximum current capability of 50 mA each. Its partitioning into 4 high-side and 4 low-side driver stages allows an easy connection of either 4 half- bridges or 2 H-bridges on the pc board. The U6820BM communicates with a micro- controller via an 8-bit serial interface. Integrated protection against short circuit and overtemperature give added value. EMI protection and 2-kV ESD protection together with automotive qualification referring to conducted interference (ISO/TR 7637/1) make this IC ideal for both automotive and industrial applications. Figure 1. Block Diagram

2 U6820BM

Figure 2. Pinning SO16

1 HS1 Output high side 1

2 LS1 Output low side 1

3 VS Supply voltage 6 V to 18 V

4 GNDCC Digital ground

5 GNDS Power ground

6 VCC Supply voltage 5 V (external)

7 LS2 Output low side 2

8 HS2 Output high side 2

9 HS3 Output high side 3

10 LS3 Output low side 3

11 CS Set supply status (chip select)

12 CLK Clock line for 8-bit control shift register

13 DI Data line for 8-bit control shift register

14 STATUS Status output (H = fault, diagnostic “H” if all driver stages are switched off)

15 LS4 Output low side 4

16 HS4 Output high side 4

4527A–BCD–03/02 Description of the Control Interface to the Microcontroller The serial-parallel interface basically includes an 8-bit shift register (SR), an 8-bit com- mand register (CR) and a 4-bit counter. The data input takes place with commands at Pins DI (data input), CS (chip select) and CLK (clock). With a falling edge at CLK, the information at DI is transferred into the SR. The first information written into the SR is the least significant bit (LSB). The Pin STA- TUS is used for diagnostic purposes and reports any fault condition to the microcontroller. The input CS in accordance with the CR controls the serial interface. A high level at CS disables the SR. With a falling edge at CS, the SR is enabled. The CR control allows only the first 8 bits to be transferred into the SR, and further clocks at CLK are ineffec- tive. If a rising edge occurs at CS after 8 clocks precisely, the information from the SR is transferred into the CR. If the number of clock cycles during the low phase of CS was less or more than eight transitions, no transfer will take place. A new command switches the output stages on or off immediately. Each output stage is controlled by one specific bit of the CR. Low level means “supply off” or inactive, and high level means “supply on” or active. If all 8 bits are at a low level, the output stages will be set into standby mode. If one of the output stages detects a short circuit and additionally overtemperature con- dition, the corresponding control bit in the CR is set to low. This reset has priority over an external command to CR, thus, this does not affect the 1 st control bit. The priority pro- tects the IC against overtemperature by activating the temperature shut down immediately. The STATUS Output The STATUS output is at low level during normal operation. If one or more output stages detect short circuit or if overtemperature is indicated, the STATUS output changes to high level (OR-connection). For diagnostic purposes (self test of the status output), the status output can also be brought into high level during standby mode. Timing of the Status Output Reset Signalizes the Failure Mode The use of different reset conditions at the STATUS output simplifies the failure analysis during normal operation, and is also beneficial during testing. The storage content can be used for STATUS output. It is indicated and latched immedi- ately with the rising edge of CS at STATUS output if less than 8 clocks were received during the low phase of CS. The reset is initiated by the falling edge of the 8 th clock (bit 7) of the next data input. Also, the appearance of more than 8 clocks is latched and indicated at STATUS by the rising edge of the 9 th clock. The reset is initiated by the falling edge of the 2 nd clock (bit 1) of the next data input. The detection of overtemperature is latched internally. It is reset by the falling edge of the 4th clock (bit 3) of a data transfer if overtemperature is no longer present. Power-on Reset After switching on the supply voltage, all data latches are reset and the outputs are switched off. The typical power-on reset threshold is V CC = 3.7 V. The outputs are acti- vated after the first data transfer.

4 U6820BM

switched off selectively. It will be activated again after the first new data transfer. may exceed power dissipation. j = 155 °C typically is exceeded, the diagnostic Pin 14 (STATUS) is set “high”. external components (see Figure 5), all other pins are protected up to 2 kV (HBM). Table 1. Timing of the STATUS Output

0000000000000000 A l l o u t = O K o f f o f f o f f o f f o f f o f f o f f o f f H N e w C S

1111111111111111 A l l o n = O K o n o n o n o n o n o n o n o n L

0111111101111111 S h o r t a t L S 3 o f f o n o n o n o n o n o n o n H N o s h o r t

1111111111101111 T e m p & s h o r t a t H S 4 o n o n o n o f f o n o n o n o n H N e w C S 4

Figure 3. Data Transfer Timing Diagram Table 2. AC Characteristics for Testing

6 U6820BM

Figure 4. Block Diagram of the Control Interface

4527A–BCD–03/02 Absolute Maximum Ratings Parameters Pin Symbol Minimum Maximum Unit Supply voltage 3 V VS -0.3 +40 V Logic supply voltage 6 V VCC -0.3 +7 V Logic input voltage 11, 12 13 CS, CLK, DI -0.3 V VCC + 0.5 V Logic output voltage 14 STATUS -0.3 V VCC + 0.3 V Input current 3 I VS 0.2 mA 6I VCC 5m A Output current (internally limitted) 1-2, 8-11, 15-16 I 1H-4H and I 1L-4L 30 65 mA Junction temperature range T j -40 +150 °C Storage temperature range T stg -55 +150 °C Thermal Resistance Parameters Symbol Value Unit Junction ambient R thJA 110 K/W Junction case R thJC 26 K/W Operating Range Parameters Pin Symbol Value Unit Supply voltage 3 V VS 6 to 18 V Logic supply voltage 6 V VCC 4.5 to 5.5 V Logic input voltage low 11, 12, 13 CS, CLK, DI -0.2 to (0.2 x V VCC)V Logic input voltage high 11, 12, 13 CS, CLK, DI (0.7 x V VCC) to (VVCC + 0.3) V Logic output voltage (1 mA load) 14 STATUS 0.5 to (V VCC - 1) V Clock frequency f CLK 5M H z Junction temperature range T j -40 to +150 °C

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4527A–BCD–03/02

Electrical Characteristics

7V < VVS < 40 V; 4.5 V < VVCC > 5.5 V; -40°C < Tj < 150°C; unless otherwise specified No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*

1 Current Consumption

1.1 Supply current VS No external load 3 I VS 0.2 mA A

1.2 Supply current VCC No external load 6 I VCC 5m A A

1.3 Power-on reset threshold 6 V CC POR 3.4 3.7 4.0 V A

1.4 Power-on reset delay time After switching on V CC 6T d POR 60 95 130 µs D

2 Thermal Shutdown

2.1 Thermal shutdown set t j PW set 140 155 165 °CA

2.2 Thermal shutdown reset t j PW reset 130 135 155 °CA

2.3 Thermal hysteresis Dt 20 K A

3 Output Specifications (1L - 4L, 1H - 4H)

3.1 On-resistance low I out = 26 mA,

Tj = 125°C 2, 7, 10, 15 RDSONLOW 347 Ω A

3.2 On-resistance high I out = 26 mA,

Tj = 125°C 1, 8, 9, 16 RDSONHIGH 46 . 2 5 1 0 Ω A

3.3 Output leakage current

VLSIDE 1-4 = 17.5 V 2, 7, 10, 15 ILOWSIDE 5µ A A

3.4 Output leakage current

VHSIDE 1-4 = 0.5 V 1, 8, 9, 16 IHIGHSIDE -5 µA A

3.5 Output leakage steepness 1-2,

7-10, 15-16 dVOUT/ dt 50 200 400 mV/µs D

3.6 Over current limitation

1, 8, 9, 16 IHIGHSIDE 27 45 95 mA A

3.7 Over current limitation

2, 7, 10, 15 ILOWSIDE 27 45 80 mA A

4 Serial Interface – Inputs: CS, CLK and DATA

4.1 Input voltage low level

0.2× VVCC VA

4.2 Input voltage high level

0.7× VVCC VA

4.3 Hysteresis of input voltage 11-13 ∆Vi 300 mV A

4.4 Pull-down current (internal pull-up

resistor: 30 kΩ to 140 kΩ) 11-13 I i 300 µA A

5 Serial Interface – Output: STATUS

5.1 Output voltage low level I = 1 mA V OLOW 0.5 V A

5.2 Output voltage high level I = 1 mA V OHIGH VVCC-1 V VCC VA

*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Figure 5. Application Circuit

4 Hall-ICs for rotational speed detection

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4527A–BCD–03/02

Package Information

Ordering Information

Extended Type Number Package Remarks U6820BM-FP SO16 13036 technical drawings according to DIN specifications 10.0 9.85 8.89 0.4 1.27 1.4 0.25 0.10 5.2 4.8 3.7 3.8 6.15 5.85 0.2 16 9 Dimensions in mm

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