U6225B

U6225B TEMIC | Alldatasheet

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Technical content

Features

/C00682.9 GHz divide-by-16 prescaler integrated /C0068Universal bus: I2C-bus or 3-wire-bus I2C-bus software compatible to U6204B 3-wire-bus software compatible to U6358B (19 bit) /C0068I 2C-bus mode: 5 switching outputs (open collector) 4 addresses selectable at pin 10 for multituner application /C00683-wire-bus mode: 4 switching outputs (open collector) Locksignal output (open collector) /C0068Low power consumption (typical 5 V / 23 mA) /C0068Electrostatic protection according to MIL-STD 883 Benefits /C0068Only one device for 3-wire bus applications and I2C- bus applications necessary (universal bus) /C0068High input frequency of 2.9 GHz applicable for all TV-satellites

Ordering Information

Extended Type Number Package Remarks U6225B-FPG3 SO16 Taped and reeled

5 BIT LATCH SWITCHING

4 BIT LATCH8 BIT LATCH7 BIT LATCH

15 BIT LATCH

15 BIT COUNTER16RFi

Figure 1. Block diagram

TELEFUNKEN Semiconductors U6225B Rev. A1: 25.10.1995 3 (12) Pin Description SDA 95 10729 SCL SW7 SW6 SW5 PD RFi RFi V S SW1/ Lock AS/ ENA SW4 VD GND Figure 2. Pin Symbol Function

1 PD Charge pump output

2 Q1 Crystal

3 Q2 Crystal

4 SDA Data in/output

5 SCL Clock input

6 SW7 Switching output open collector

7 SW6 Switching output open collector

8 SW5 Switching output open collector

9 SW4 Switching output open collector

10 AS / ENA Address select / enable input

11 SW1 / Lock Switching / lock output open

12 Vs Supply voltage

13 RFi RF input

14 RFi RF input

15 GND Ground

16 VD Active filter output

All voltages are referred to GND (Pin 15) Parameters Symbol Value Unit Supply voltage Pin 12 Vs –0.3 to 6 V RF input voltage Pin 13, 14 RFi –0.3 to Vs+0.3 V Switching output current Open collectors Pin 6 – 9, 11 SW 1, 4-7 –1 to 15 mA Total current of switching outputs Open collectors Pin 6 – 9, 11 SW 1, 4-7 50 mA Switching output voltage Pin 6 – 9, 11 in off state: in on state: SW 1, 4-7 –0.3 to 14 –0.3 to 6 V V Bus input/output voltage Pin 4 Pin 5 VSDA VSCL –0.3 to 6 –0.3 to 6 V V SDA output current open collector Pin 4 ISDA –1 to 5 mA Address select voltage Pin 10 V AS / ENA –0.3 to Vs+0.3 V Charge pump output voltage Pin 1 PD –0.3 to Vs+0.3 V Active filter output voltage Pin 16 VD –0.3 to Vs+0.3 V Crystal oscillator voltage Pin 2 Q1 –0.3 to Vs+0.3 V Junction temperature Tj –40 to 125 °C Storage temperature Tstg –40 to 125 °C

TELEFUNKEN SemiconductorsU6225B Rev. A1: 25.10.19954 (12) Operating Range All voltages are referred to GND (Pin 15) Parameters Symbol Min. Typ. Max. Unit Supply voltage Pin 12 Vs 4.5 5.5 V Ambient temperature Tamb 0 70 °C Input frequency Pin 13, 14 R Fi 250 2900 MHz Progr. divider SF 256 32767 Thermal Resistance Parameters Symbol Value Unit Junction ambient R thJA 110 K/W

Electrical Characteristics

Test conditions: VS = 5 V , Tamb = 25°C, unless otherwise specified Parameters Test Conditions / Pins Symbol Min. Typ. Max. Unit Supply current SW 1, 4, 5, 6, 7 = 0 Pin 12 Is 18 23 28 mA Input sensitivity Input frequency fi = 250 MHz, Pin 13 fi = 750-2900 MHz, Pin 13 Vi 1) Vi 1) 100 300 300 mVrms mVrms Crystal oscillator Recommended crystal series resistance 10 200 /C0087 Crystal oscillator drive level Pin 2 50 mVrms Crystal oscillator source impedance Nominal spread ±15% Pin 2 –650 /C0087 External reference input frequency AC coupled sinewave Pin 2 2 8 MHz External reference input amplitude AC coupled sinewave Pin 2 70 200 mVrms Switching outputs (SW4–7,1), lock output, open collector Pin 6–9, 11 Leakage current VH = 13.5 V IL 10 /C0109A Saturation voltage IL = 10 mA VSL 2) 0.5 V Charge pump output (PD) Charge pump current ‘H’ 5I = H, VPD = 2V Pin 1 IPDH ±180 /C0109A Charge pump current ‘L’ 5I = L, VPD = 2V Pin 1 IPDL ±50 /C0109A Charge pump leakage current T0 = 0, VPD = 2V Pin 1 IPDTRI ±5 nA Charge pump amplifier gain Pin 1, 16 6400 Bus inputs (SDA, SCL) Input voltage Pin 4, 5 Pin 4, 5 Vi ‘H’ Vi ‘L’ 3 5.5 1.5 V V

TELEFUNKEN Semiconductors U6225B Rev. A1: 25.10.1995 5 (12) UnitMax.Typ.Min.SymbolTest Conditions / PinsParameters Input current VSCL ‘H’ = Vs Pin 4, 5 VSCL ‘L’ = 0 V Pin 4, 5 li ’H’ li ’L’ –10 10 /C0109A /C0109A Leakage current Vs = 0 V Pin 4, 5 IL 10 /C0109A Output voltage SDA (open collector) ISDA ‘L’ = 2 mA, Pin 4 VSDA ’L’ 0.4 V Address selection / Enable input (AS, ENA) Input current V AS ‘H’ = Vs Pin 10 V AS ‘L’ = 0 Pin 10 liAS ’H’ liAS ’L’ –100 10 /C0109A /C0109A 1) RMS-voltage calculated from the measured available power on 50 /C0087 2) Tested with one switch active, the collector voltage may not exceed 6 V

Description

The U6225B-B is a single chip PLL designed for SAT-TV receiver systems. It consists of a divide-by-16 prescaler with an integrated preamplifier, a 15 bit programmable divider, a crystal oscillator with a divide-by-512 refer- ence divider, a phase/frequency detector together with a charge-pump, which is driving the tuning amplifier. Only one external transistor is required for varactor line driv- ing. The device can be controlled via I 2C-bus format or the 3-wire-bus format. It detects automatically which bus format is received, therefore there is no need of a bus selection pin. In I2C-bus mode the device has 4 program- mable addresses, programmed by applying a specific input voltage to the address select input, enabling the use of up to four synthesizers in a system. The same pin serves in 3-wire-bus mode as the enable signal input. Five open collector outputs for switching functions are included, which are capable of sinking at least 10 mA. One of these open collector outputs serves as Locksignal output in the 3-wire-bus mode. Functional Description The U6225B-B is programmed via 2-wire I2C bus or 3-wire bus depending on the received data format. The three bus inputs pin 4, 5, 10 are used as SDA, SCL and ADDRESS SELECT inputs in I 2C-bus mode and as DATA, CLOCK and ENABLE inputs in 3-wire bus mode. The data includes the scaling factor SF (15 bit) and switching output information. In I 2C-bus mode there are some additional functions for testing of the device in- cluded. Oscillator Frequency Calculation fvco = 16 * SF * frefosc / 512 fvco: Locked frequency of voltage controlled oscillator SF: Scaling factor of programmable 15-bit-divider frefosc: Reference oscillator frequency: 3.2 / 4 MHz crystal or external reference frequency The input amplifier together with a divide-by-16 pres- caler gives an excellent sensitivity (see ‘Typical Prescaler Input Sensitivity’). The input impedance is shown in the diagram ‘Typical Input Impedance’. When a new divider ratio according to the requested fvco is entered, the phase detector and charge pump together with the tuning ampli- fier adjusts the control voltage of the VCO until the output signals of the programmable divider and the reference di- vider are in frequency and phase locked. The reference frequency may be provided by an external source capaci- tively coupled into pin 2, or by using an on-board crystal with an 18 pF capacitor in series. The crystal operates in the series resonance mode. The reference divider division ratio is fixed to 512. Therefore with a 4 MHz crystal the comparison frequency is 7.8125 kHz, which gives 125 kHz steps for the VCO, or with a 3.2 MHz crystal re- spectively 6.25 kHz comparison frequency and 100 kHz VCO step size. In addition there are switching outputs available for bandswitching and other purposes. Application A typical application is shown on page ?. All input / out- put interface circuits are shown on page ?. Some special features which are related to test- and alignment proce- dures for tuner production are explained together within the following bus mode description. I2C-Bus Description When the U6225B-B is controlled via 2-wire I2C-bus for- mat, then data and clock signals are fed into the SDA and SCL lines respectively. The table ’I 2C-BUS DATA FOR- MA T’ describes the format of the data and shows how to select the device address by applying a voltage at pin 10. When the correct address byte is received, the SDA line is pulled low by the device during the acknowledge pe-

TELEFUNKEN SemiconductorsU6225B Rev. A1: 25.10.19956 (12) riod, and then also during the acknowledge periods, when additional data bytes are programmed. After the address transmission (first byte), data bytes can be sent to the de- vice. There are four data bytes requested to fully program the device. The table ‘I 2C-Bus Pulse Diagram’ shows some possible data transfer examples. Programmable divider bytes PDB1 and PDB2 are stored in a 15 bit latch and are controlling the division ratio of the 15 bit programmable divider. The control Byte CB1 allows to control the following special functions: /C00685I-bit switches between low and high charge pump current /C0068T1-bit enables divider test mode when it is set to logic 1 /C0068T0-bit allows to disable the charge pump when it is set to logic 1 /C0068OS-bit disable the charge pump drive amplifier output when it is set to logic 1. Only in I 2C bus mode the charge pump current can be con- trolled. In 3-wire-bus mode there is always the high charge pump current active. The OS-bit function disables the complete PLL function. This allows the tuner align- ment by suppling the tuning voltage directly through the 30 V supply voltage of the tuner. The control byte CB2 programs the switching outputs SW 1, 4, 5, 6, 7; a logic 0 for high impedance output (off) and a logic 1 for low impedance output (on). Description I2C Bus Data Format MSB LSB Address byte 1 1 0 0 0 AS1 AS2 0 A Progr. divider byte 1 0 n14 n13 n12 n11 n10 n9 n8 A Progr. divider byte 2 n7 n6 n5 n4 n3 n2 n1 n0 A Control byte 1 1 5I T1 T0 X X X OS A Control byte 2 SW7 SW6 SW5 SW4 X X SW1 X A A = Acknowledge; X = not used; Unused bits of controlbyte 2 should be 0 for lowest power consumption T0, T1 Testmode selection T1 = 1: divider test mode on T1 = 0: divider test mode off T0 = 1: charge pump disable T0 = 0: charge pump enable SW1, 4, 5, 6, 7 Switching outputs SW1, SW4, SW5, SW6, SW7 = 1: open collector active 5I Charge pump current switch 5I = 1: high current 5I = 0: low current OS Output switch OS = 1: varicap driver disable OS = 0: varicap drive enable AS1, AS2 Address selection pin 10 AS1 AS2 Address Dec. Value V oltage at pin 0 1 1 194 open 0 0 2 192 0 to 10% Vs 1 0 3 196 40 to 60% Vs 1 1 4 198 90 to 100% Vs

TELEFUNKEN SemiconductorsU6225B Rev. A1: 25.10.19958 (12) 3-Wire-Bus Description When the U6225B-B is controlled via 3-wire bus format, then DATA, CLOCK and ENABLE signals are fed into the SDA, SCL and AS/ENA lines respectively. The dia- gram ’3-WIRE-BUS PULSE DIAGRAM’ shows the data format. The data consist of a single word, which contains the programmable divider and switch information. Only during the enable high period the data is clocked into the internal data shift register on the negative clock transi- tion. During enable low periods the clock input is disabled. New data words are only accepted by the inter- nal data latches from the shift register on a negative transition of the enable signal when during the high period of the enable exactly nineteen clock pulses were send. The data sequence and the timing is described in the fol- lowing diagrams. In 3-wire-bus mode pin 11 becomes automatically the Locksignal output. An improved lock detect circuit gen- erates a flag when the loop has attained lock. ’In lock’ is indicated by a low impedance state (on) of the open col- lector output. In 3-wire-bus mode there is always the high charge pump current active. Only in I 2C-bus mode the charge pump current can be controlled. The complete PLL function can be disabled by program- ming a normally not used division ratio of zero. This allows the tuner alignment by supplying the tuning volt- age directly through the 30 V supply voltage of the tuner. 3-Wire-Bus Pulse Diagram P5P7 Ports LSB SDA MSB

15 Bit scaling factor SF

4 Bit

Figure 5. 3-Wire-Bus Timing THTSTL TT LSB Clock Enable Data TSLTC 95 10734 Figure 6. Parameters Symbol Min. Typ. Unit Set up time TS 2 /C0109s Enable hold time TSL 2 /C0109s Clock width TC 2 /C0109s Enable set up time TL 10 /C0109s Enable between two transmissions TT 10 /C0109s Data hold time TH 2 /C0109s

TELEFUNKEN SemiconductorsU6225B Rev. A1: 25.10.199510 (12) Typical Prescaler Input Sensitivity Frequency (MHz) 100 1000 0 500 1000 1500 2000 2500 3000 3500 4000 Vi (mV RMS on 50 Ohm) 95 10741 OPERATING WINDOW Figure 13. Typical Input Impedance –0.2j –0.5j –2j –5j 0.2j 0.5j j ÁÁ ÁÁ 0.2 ÁÁ ÁÁ 0.5 Á Á ÁÁ ÁÁ ÁÁ ÁÁ 5 /C0049 95 9927

4.0 GHz

3.5 GHz

3.0 GHz

2.5 GHz

2.0 GHz

1 GHz

ÁÁÁ ÁÁÁ

500 MHz

ÁÁÁ ÁÁÁ

100 MHz

ÁÁÁ Z0 = 50 /C0087 Figure 14.

TELEFUNKEN Semiconductors U6225B Rev. A1: 25.10.1995 11 (12) Application Circuit

4 MHz 18 p

f f TUNER f RFi Vs GND AS / ENA 141323 119 SCL SDA from uC 30 V 12 V 22 k 22 k 22 k 39 k 22 k 22 n 1 n1 n 100 n IF VCOTV 76 8 SW6SW7 SW1 / Lock SW4SW5 95 10742 Figure 15. Dimensions in mm Package: SO-16 small 94 8875

TELEFUNKEN SemiconductorsU6225B Rev. A1: 25.10.199512 (12) Ozone Depleting Substances Policy Statement It is the policy of TEMIC TELEFUNKEN microelectronic GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs). The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. TEMIC TELEFUNKEN microelectronic GmbH semiconductor division has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency (EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively. TEMIC can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances. We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use TEMIC products for any unintended or unauthorized application, the buyer shall indemnify TEMIC against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. TEMIC TELEFUNKEN microelectronic GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 (0)7131 67 2831, Fax number: 49 (0)7131 67 2423