TSC51C1

TSC51C1 TEMIC | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 31

Technical content

Rev. D (14 Jan. 97) 1MA TRA MHS 1. Introduction The TSC8051C1 is a stand–alone high performance CMOS 8–bit embedded microcontroller and is designed for use in CRT monitors. It is also suitable for automotive and industrial applications. The TSC8051C1 includes the fully static 8–bit “80C51” CPU core with 256 bytes of RAM; 8 Kbytes of ROM; two 16–bit timers; 12 PWM Channels; a 6 sources and 2–level interrupt controller; a full duplex serial port; a full I 2C  * interface; a watchdog timer and on–chip oscillator. In addition, the TSC8051C1 has 2 software selectable modes of reduced activity for further reduction in power consumption. In the idle mode the CPU is frozen while the RAM, the timers, the serial ports, and the interrupt system continue to function. In the power down mode the RAM is saved and all other functions are inoperative. The TSC8051C1 enables the users reducing a lot of external discrete components while bringing the maximum of flexibility. 2. Features Boolean processor Fully static design 8K bytes of ROM 256 bytes of RAM 2 x 16–bit timer/counter Programmable serial port Programmable Multimaster I2C controller 6 interrupt sources: External interrupts (2) Timers interrupt (2) Serial port interrupt I2C interrupt Watchdog reset On chip oscillator for crystal or ceramic resonator 2 power saving control modes: Idle mode Power–down mode Controlled HSYNC & VSYNC outputs Up to 12 programmable PWM channels with 8–bit resolution Up to 32 programmable I/O lines depending on the package 40 pins DIP, 44 pins PQFP, 44 and 52 pins PLCC packages Commercial and industrial temperature ranges Operating Frequency: 12 MHz to 16 MHz 8-Bit Microcontroller for Digital Computer Monitors * I2C is a trademark of PHILIPS Corporation

2 MA TRA MHS

Figure 1. TSC8051C1 block diagram.

Figure 2. TSC8051C1 pin configurations.

Rev. D (14 Jan. 97)

4 MA TRA MHS

1. Pin Description VSS Circuit ground. VCC Power supply voltage. RST A high level on this pin for two machine cycles while the oscillator is running resets the device. An internal pulldown resistor permits power–on reset using only a capacitor connected to VCC. PORT 0 (P0.0–P0.7) Port 0 is an 8–bit open–drain bidirectional I/O port. Port 0 pins that have 1’s written to them float, and in that state can be used as high–impedance inputs. Port 0 is also the multiplexed low–order address and data bus during access to external Program and Data memory. In this application it uses strong internal pull–up when emitting 1’s. Port 0 can sink and source 8 LS TTL loads. PORT 1 (P1.0–P1.7) Port 1 is an 8–bit bidirectional I/O port with internal pullups. Port 1 pins that have 1’s written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL on the data–sheet) because of the internal pullups. Port 1 also serves 4 programmable PWM open drain outputs, as listed below: Port Pin Alternate Function P1.0 PWM8: Pulse Width Modulation output 8. P1.1 PWM9: Pulse Width Modulation output 9. P1.2 PWM10: Pulse Width Modulation output 10. P1.3 PWM11: Pulse Width Modulation output 11. Port 1 can sink and source 3 LS TTL loads. PORT 2 (P2.0–P2.7) Port 2 is an 8–bit bidirectional I/O port with internal pullups. Port 2 pins that have 1’s written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL on the data–sheet) because of the internal pullups. Port 2 emits the high–order 8–bit address during fetches from external Program Memory and during accesses to external Data Memory that use 16–bit addresses. In this application it uses strong internal pull–up when emitting 1’s. Port 2 can sink and source 3 LS TTL loads. PORT 3 (P3.0–P3.7) Port 3 is an 8–bit bidirectional I/O port with internal pullups. Port 3 pins that have 1’s written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL on the data–sheet) because of the internal pullups. Each line on this port has 2 or 3 functions either a general I/O or special control signal, as listed below: Port Pin Alternate Function P3.0 RXD: serial input port. P3.1 TXD: serial output port. P3.2 INT0 : external interrupt 0. VSYNC: vertical synchro input. P3.3 INT1 : external interrupt 1. VOUT: buffered V-SYNC output. P3.4 T0: Timer 0 external input. HSYNC: horizontal synchro input. P3.5 T1: Timer 1 external input. HOUT: buffered H–SYNC output. P3.6 WR : external data memory write strobe. SCL: serial port clock line I2C bus. P3.7 RD : external data memory read strobe. SDA: serial port data line I2C bus. Port 3 can sink and source 3 LS TTL loads. PWM0–7 These eight Pulse Width Modulation outputs are true open drain outputs and are floating after reset. ALE The Address Latch Enable output signal occurs twice each machine cycle except during external data memory access. The negative edge of ALE strobes the address into external data memory or program memory. ALE can sink and source 8 LS TTL loads. If desired, ALE operation can be disabled by setting bit 0 of SFR location AFh (MSCON). With the bit set, ALE is active only during MOVX instruction and external fetches. Otherwise the pin is pulled low.

Rev. D (14 Jan. 97) 5MA TRA MHS EA When the External Access input is held high, the CPU executes out of internal program memory (unless the Program Counter exceeds 1FFFh). When EA is held low the CPU executes only out of external program memory. must not be left floating. PSEN The Program Store Enable output signal remains high during internal program memory. An active low output occurs during an external program memory fetch. PSEN can sink and source 8 LS TTL loads. XTAL1 Input to the inverting oscillator amplifier and input to the external clock generator circuits. XTAL2 Output from the inverting oscillator amplifier. This pin should be non–connected when external clock is used.

6 MA TRA MHS

1. Basic Functional Description

operate while the clock to the CPU is gated off. Special Function Register, its hardware address is 87h. PCON is not bit addressable. Figure 3. Idle and Power Down Hardware. IDL PCON.0 Idle mode bit. Setting this bit activates idle mode operation. PD PCON.1 Power Down bit. Setting this bit activates power down operation. GF0 PCON.2 General–purpose flag bit. GF1 PCON.3 General–purpose flag bit. is being used in either modes 1, 2 or 3. If 1’s are written to PD and IDL at the same time, PD takes precedence. The reset value of PCON is 0XXX0000b. external pins during Idle mode. There are two ways to terminate the Idle mode. instruction that wrote 1 to PCON.0.

hardware reset is applied which frees the oscillator. the power down mode by the strong pullup transistor. Table 1. Status of the external pins during Idle and Power Down modes. consumption is the same as in the Power Down Mode. of port 1 and port 3 (see Pin Description section). Figure 4. shows a functional diagram of the generic bit actual pin logical level on the internal bus. and other instructions read the latch (SFR).

8 MA TRA MHS

• Internal pull–up not present on P3.6 and P3.7 when SIO1 is enabled.

Figure 4. Port Bit Latches and I/O buffers for noise rejection (see Figure 5. ). and PSEN pins as inputs (they are quasi–bidirectional).

Rev. D (14 Jan. 97)

10 MA TRA MHS

6.7. Memory organization The memory organisation of the TSC8051C1 is the same as in the 80C51, with the exception that the TSC8051C1 has 8k bytes ROM, 256 bytes RAM, and additional SFRs. Details of the differences are given in the following paragraphs. In the TSC8051C1, the lowest 8k of the 64k program memory address space is filled by internal ROM. Depending on the package used, external access is available or not. By tying the EA pin high, the processor fetches instructions from internal program ROM. Bus expansion for accessing program memory from 8k upward is automatic since external instruction fetches occur automatically when the program counter exceeds 1FFFh. If the EA pin is tied low, all program memory fetches are from external memory. The execution speed is the same regardless of whether fetches are from external or internal program memory. If all storage is on–chip, then byte location 1FFFh should be left vacant to prevent an undesired pre–fetch from external program memory address 2000h. Certain locations in program memory are reserved for specific purposes. Locations 0000h to 0002h are reserved for the initialisation program. Following reset, the CPU always begins execution at location 0000h. Locations 0003h to 0032h are reserved for the six interrupt request service routines. The internal data memory space is divided into a 256–bytes internal RAM address space and a 128 bytes special function register address space. The internal data RAM address space is 0 to FFh. Four 8–bit register banks occupy locations 0 to 1Fh. 128 bit locations of the internal data RAM are accessible through direct addressing. These bits reside in 16 bytes of internal RAM at location 20h to 2Fh. The stack can be located anywhere in the internal data RAM address space by loading the 8–bit stack pointer (SP SFR). The SFR address space is 100h to 1FFh. All registers except the program counter and the four 8–bit register banks reside in this address space. Memory mapping of the SFRs allows them to be accessed as easily as internal RAM, and as such, they can be operated on by most instructions.The mapping in the SFR address space of the 43 SFRs is shown in Table 2. The SFR names in italic are TSC8051C1 new SFRs and are described in Peripherals Functional Description section. The SFR names in bold are bit addressable.

Table 2. Mapping of Special Function Register

98 SCON SBUF

88 TCON TMOD TL0 TL1 TH0 TH1

80 P0 SP DPL DPH PCON

Rev. D (14 Jan. 97)

12 MA TRA MHS

IE: Interrupt Enable Register MSB SFR A8h LSB EA – ES1 ES0 ET1 EX1 ET0 EX0 Symbol Position Name and Function EX0 IE.0 Enable external interrupt 0. ET0 IE.1 Enable timer 0 interrupt. EX1 IE.2 Enable external interrupt 1. ET1 IE.3 Enable timer 1 interrupt. ES0 IE.4 Enable SIO0 (UART) interrupt. ES1 IE.5 Enable SIO1 (I2C) interrupt. – IE.6 (Reserved). EA IE.7 Enable all interrupts. 6.8.2. Interrupt Priority Structure: Each interrupt source can be assigned one of two priority levels. Interrupt priority levels are defined by the interrupt priority register (IP SFR). Setting a bit in the interrupt priority register selects a high priority interrupt, clearing it selects a low priority interrupt. IP: Interrupt Priority Register MSB SFR B8h LSB – – PS1 PS0 PT1 PX1 PT0 PX0 Symbol Position Name and Function PX0 IP.0 External interrupt 0 priority level. PT0 IP.1 Timer 0 interrupt priority level. PX1 IP.2 External interrupt 1 priority level. PT1 IP.3 Timer 1 interrupt priority level. PS0 IP.4 SIO0 (UART) interrupt priority level. PS1 IP.5 SIO1 (I2C) interrupt priority level. – IP.6 (Reserved). – IP.7 (Unused). A low priority interrupt service routine may be interrupted by a high priority interrupt. A high priority interrupt service routine cannot be interrupted by any other interrupt source. If two requests of different priority levels occur simultaneously, the high priority level request is serviced. If requests of same priority are received simultaneously, an internal polling sequence determines which request is serviced. Thus, within each priority level, there is a second priority structure determined by the polling sequence, as follows:

Rev. D (14 Jan. 97) 13MA TRA MHS Order Source Priority Within Level

1 INT0 (highest)

2 Timer 0 ↑

3 INT1

4 Timer 1

5 SIO0 ↓

6 SIO1 (lowest)

6.8.3. Interrupt Handling: The interrupt flags are sampled at S5P2 of every machine cycle. The samples are polled during the following machine cycle. If one of the flags was in a set condition at S5P2 of the previous machine cycle, the polling cycle will find it and the interrupt system will generate a LCALL to the appropriate service routine, provided this hardware–generated LCALL is not blocked by any of the following conditions: 1. An interrupt of higher or equal priority is already in progress. 2. The current (polling) cycle is not the final cycle in the execution of the instruction in progress. 3. The instruction in progress is RETI or any access to the IE or IP SFR. Any of these three conditions will block the generation of the LCALL to the interrupt service routine. Note that if an interrupt is active but not being responded to for one of the above conditions, if the flag is not still active when the blocking condition is removed, the denied interrupt will not be serviced. In other words, the facts that the interrupt flag was once active but not serviced is not memorized. Every polling cycle is new. The processor acknowledges an interrupt request by executing a hardware–generated LCALL to the appropriate service routine. In some cases it also clears the flag that generated the interrupt, and in other case it does not. It clears the timer 0, timer 1, and external interrupt flags. An external interrupt flag (IE0 or IE1) is cleared only if it was transition–activated. All other interrupt flags are not cleared by hardware and must be cleared by the software. The LCALL pushes the contents of the program counter onto the stack (but it does not save the PSW) and reloads the PC with an address that depends on the source of the interrupt being vectored to, as listed below: Source Vector Address IE0 0003h TF0 000Bh IE1 0013h TF1 001Bh RI + TI 0023h SI 002Bh Execution proceeds from the vector address until the RETI instruction is encountered. The RETI instruction clears the ‘priority level active’ flip–flop that was set when this interrupt was acknowledged. It then pops two bytes from the the top of the stack and reloads the program counter with them. Execution of the interrupted program continues from where it was interrupted.

14 MA TRA MHS

1. Peripherals Functional Description

Description and Programmer’s Guides. frequency (1MHz with a 12MHz oscillator). 2097.152ms in 16 possible steps (see Table 3. ). be generated which will reset the TSC8051C1. WT0 HWDR.0 Watchdog Timer Interval bit 0. WT1 HWDR.1 Watchdog Timer Interval bit 1. WT2 HWDR.2 Watchdog Timer Interval bit 2. WT3 HWDR.3 Watchdog Timer Interval bit 3. – HWDR.4 Reserved for test purpose, must remain to 0 for normal operation. WTE HWDR.7 Watchdog Timer Enable bit. Setting this bit activates watchdog operation. Table 3. Watchdog timer interval value format. cannot be disabled anymore, except by a system reset. which disables the watchdog operation. Figure 9. Watchdog timer block diagram

PWM registers when they are loaded with FEh or FFh. standard Port outputs with internal pullups. Function Registers addresses as detailed in Table 4. Table 4. PWM SFR register addresses used to enable or disable PWM outputs.

16 MA TRA MHS

PWMx output and activates the I/O pin (see Table 5). port with the value of P1 SFR. Function Register addresses, E7h and D7h respectively. Table 5. PWM alternate pin. PWMCON is used to control the PWM counter. is 00h which sets the PWM counter modulo to 256.

18 MA TRA MHS

8051 CORE

Figure 12. Buffered HSYNC and VSYNC block programmable INT0/VSYNC input block diagram.

1. Pulse duration shorter than 1 clock period is rejected;

positive pulses can be programmed. Figure 14. shows the programmable T0/HSYNC input T0/HSYNC pulses and rejects or lengthens them. I0L EICON.0 INT0 /VSYNC input Level bit. Setting this bit inverts INT0/VSYNC input signal. Clearing it allows standard use of INT0/VSYNC input. allows standard use of T0/HSYNC input. allows negative pulse capture. which allows standard INT0 and T0 inputs feature. Figure 13. INT0/VSYNC input block diagram Figure 14. T0/HSYNC input block diagram reflects the status of SIO1 and the I2C bus.

20 MA TRA MHS

Table 6. Serial Clock Rates machine cycle after SI has been reset by software. Table 7. to Table 9. give the status for the operating modes and miscellaneous states. SC0 S1STA.3 Status Code bit 0. SC1 S1STA.4 Status Code bit 1. SC2 S1STA.5 Status Code bit 2. SC3 S1STA.6 Status Code bit 3. SC4 S1STA.7 Status Code bit 4.

Table 7. Status for master transmitter mode. 08h A START condition has been transmitted. 38h Arbitration lost in SLA+R/W or data bytes. Table 8. Status for master receiver mode 08h A START condition has been transmitted. Table 9. Status for miscellaneous states F8h No relevant state information available. last byte present on the bus. SD0 S1DAT.0 Address bit 0 (R/W) or Data bit 0. SDX S1DAT.X Address bit X or Data bit X. avoid low level asserting on SCL or SDA lines.

Rev. D (14 Jan. 97)

22 MA TRA MHS

1. Electrical Characteristics Absolute Maximum Ratings(1) Operating Temperature: Notice: 1. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. This value is based on the maximum allowable die temperate and the thermal resistance of the package. 8.1. DC Characteristics TA = 0°C to +70°C; VSS = 0V; VCC = 5V ± 10%; F = 0 to 16MHz. TA = –40°C to +85°C; VSS = 0V; VCC = 5V ± 10%; F = 0 to 16MHz. Symbol Parameter Min Typ Max Unit Test Conditions Inputs VIL Input Low V oltage, except SCL, SDA –0.5 0.2 Vcc – 0.1 V VIL1 Input Low V oltage, SCL, SDA(5) –0.5 0.3 Vcc V VIH Input High V oltage except XTAL1, RST, SCL, SDA 0.2 Vcc + 0.9 Vcc + 0.5 V VIH1 Input High V oltage, XTAL1, RST 0.7 Vcc Vcc + 0.5 V VIH2 Input High V oltage, SCL, SDA(5) 0.7 Vcc Vcc + 0.5 V IIL Logical 0 Input Current ports 1, 2 and 3 –50 µA Vin = 0.45V ILI Input Leakage Current ±10 µA 0.45 < Vin < Vcc ITL Logical 1 to 0 Transition Current, ports 1, 2, 3 –650 µA Vin = 2.0V Outputs VOL Output Low V oltage, ports 1, 2, 3, SCL, SDA, PWM0–7 (7) 0.3 0.45 1.0 V V V IOL = 100µA (4) IOL = 1.6mA(4) IOL = 3.5mA(4) VOL1 Output Low V oltage, port 0, ALE, PSEN (7) 0.3 0.45 1.0 V V V IOL = 200µA (4) IOL = 3.2mA(4) IOL = 7.0mA(4) VOH Output High V oltage, ports 1, 2, 3, SCL, SDAVcc – 0.3 Vcc – 0.7 Vcc – 1.5 V V V IOH = –10µA IOH = –30µA IOH = –60µA Vcc = 5V ± 10% VOH1 Output High V oltage, port 0, ALE, PSEN Vcc – 0.3 Vcc – 0.7 Vcc – 1.5 V V V IOH =–200µA IOH = –3.2mA IOH = –7.0mA Vcc = 5V ± 10% RRST RST Pulldown Resistor 50 90 (6) 200 kΩ

24 MA TRA MHS

Figure 20. Clock Signal Waveform for ICC Tests in Active and Idle Modes. is a list of all the characters and what they stand for. TA VLL = Time for Address Valid to ALE low. TLLPL = Time for ALE low to PSEN low. H: Logic level HIGH. V: Valid. I: Instruction (Program memory contents). W: WRITE signal. L: Logic level LOW, or ALE. X: No longer a valid logic level.

Rev. D (14 Jan. 97) 25MA TRA MHS Units 0 to 12MHz ParameterSymbol Units MaxMin ParameterSymbol TPXIZ Input Instruction Float After PSEN TCLCL – 25 ns TPXA V PSEN to Address Valid TCLCL – 8 ns TA VIV Address to Valid Instruction In 5TCLCL – 105 ns TPLAZ PSEN Low to Address Float 10 ns 8.5. External Program Memory Read Cycle TPLIV TPLAZ ALE PSEN PORT 0 PORT 2 A0–A7A0–A7 INSTR ININSTR IN INSTR IN ADDRESS OR SFR–P2 ADDRESS A8–A15ADDRESS A8–A15

12 TCLCL

8.6. External Data Memory Characteristics Symbol Parameter 0 to 12MHz UnitsSym bol Parame ter Min Max U nits TRLRH RD Pulse Width 6TCLCL–100 ns TWLWH WR Pulse Width 6TCLCL–100 ns TRLDV RD to Valid Data In 5TCLCL–165 ns TRHDX Data Hold After RD 0 ns TRHDZ Data Float After RD 2TCLCL–60 ns TLLDV ALE to Valid Data In 8TCLCL–150 ns TA VDV Address to Valid Data In 9TCLCL–165 ns TLLWL ALE to WR or RD 3TCLCL–50 3TCLCL+50 ns TA VWL Address to WR or RD 4TCLCL–130 ns TQVWX Data Valid to WR Transition TCLCL–50 ns TQVWH Data set–up to WR High 7TCLCL–150 ns TWHQX Data Hold After WR TCLCL–50 ns TRLAZ RD Low to Address Float 0 ns TWHLH RD or WR High to ALE high TCLCL–40 TCLCL+40 ns

Rev. D (14 Jan. 97)

26 MA TRA MHS

8.7. External Data Memory Write Cycle TQVWHTLLAX ALE PSEN WR PORT 0 PORT 2 A0–A7 DATA OUT ADDRESS OR SFR–P2 TA VWL TLLWL TQVWX ADDRESS A8–A15 OR SFR P2 TWHQX TWHLH TWLWH 8.8. External Data Memory Read Cycle ALE PSEN RD PORT 0 PORT 2 A0–A7 DATA IN ADDRESS OR SFR–P2 TA VWL TLLWL TRLAZ ADDRESS A8–A15 OR SFR P2 TRHDZ TWHLH TRLRH TLLDV TRHDX TA VDV TLLAX 8.9. Serial Port Timing–Shift Register Mode Symbol Parameter 0 to 12MHz UnitsSym bol Parame ter Min Max U nits TXLXL Serial port clock cycle time 12TCLCL ns TQVHX Output data set–up to clock rising edge 10TCLCL–133 ns TXHQX Output data hold after clock rising edge 2TCLCL–117 ns TXHDX Input data hold after clock rising edge 0 ns TXHDV Clock rising edge to input data valid 10TCLCL–133 ns

Rev. D (14 Jan. 97) 27MA TRA MHS 8.10. Shift Register Timing Waveforms V ALIDV ALIDINPUT DATA V ALIDV ALID 0123456 8 7 ALE CLOCK OUTPUT DATA WRITE to SBUF CLEAR RI TXLXL TQVXH TXHQX TXHDV TXHDX SET TI SET RI INSTRUCTION 01234567 V ALID V ALID V ALID V ALID 8.11. SIO1 (I2C) Interface Timing Symbol Parameter Input Output THD; STA Start condition hold time ≥ 14 TCLCL > 4.0µs (1) TLOW SCL low time ≥ 16 TCLCL > 4.7µs (1) THIGH SCL high time ≥ 14 TCLCL > 4.0µs (1) TRC SCL rise time ≤ 1µs – (2) TFC SCL fall time ≤ 0.3µs < 0.3µs (3) TSU; DAT1 Data set–up time ≥ 250ns > 20 TCLCL – TRD TSU; DAT2 SDA set–up time (before repeated START condition) ≥ 250ns > 1µs (1) TSU; DAT3 SDA set–up time (before STOP condition) ≥ 250ns > 8 TCLCL THD; DAT Data hold time ≥ 0ns > 8 TCLCL – TFC TSU; STA Repeated START set–up time ≥ 14 TCLCL > 4.7µs (1) TSU; STO STOP condition set–up time ≥ 14 TCLCL > 4.0µs (1) TBUF Bus free time ≥ 14 TCLCL > 4.7µs (1) TRD SDA rise time ≤ 1µs – (2) TFD SDA fall time ≤ 0.3µs < 0.3µs (3) Notes: 1. At 100 kbit/s. At other bit–rates this value is inversely proportional to the bit–rate of 100 kbit/s. 2. Determined by the external bus–line capacitance and the external bus–line pull–up resistor, this must be < 1µs. 3. Spikes on the SDA and SCL lines with a duration of less than 3 TCLCL will be filtered out. Maximum capacitance on bus–lines SDA and SCL = 400pF.

Rev. D (14 Jan. 97)

28 MA TRA MHS

8.12. SIO1 (I2C) Timing Waveforms TRD ;STOTSU ;STASTOP condition ;DAT1 ;DAT;STA START or repeated START condition SDA (INPUT/OUTPUT) SCL (INPUT/OUTPUT)

0.7 VCC

0.3 VCC

;DAT3 ;DAT2 Repeated START condition Repeated START condition THD TLOW THIGH TSU THD TSU TSU TBUF TSU TFD TRC TFC 8.13. External Clock Drive Characteristics (XTAL1) Symbol Parameter Min Max Units TCLCL Oscillator Period 83.3 ns TCHCX High Time 5 ns TCLCX Low Time 5 ns TCLCH Rise Time 5 ns TCHCL Fall Time 5 ns 8.14. External Clock Drive Waveforms Vcc–0.5V 0.45V 0.7Vcc 0.2Vcc–0.1 TCHCL TCLCX TCLCL TCLCH TCHCX 8.15. AC Testing Input/Output Waveforms INPUT/OUTPUT 0.2 Vcc + 0.9 0.2 Vcc – 0.1 Vcc –0.5 V 0.45 V AC inputs during testing are driven at Vcc – 0.5 for a logic “1” and 0.45V for a logic “0”. Timing measurement are made at VIH min for a logic “1” and VIL max for a logic “0”.

Rev. D (14 Jan. 97) 29MA TRA MHS 8.16. Float Waveforms FLOA TFLOA T VOH – 0.1 V VOL + 0.1 V VLOAD VLOAD + 0.1 V VLOAD – 0.1 V For timing purposes as port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs. IOL/IOH ≥ ± 20mA.

Rev. D (14 Jan. 97)

30 MA TRA MHS

8.17. Clock Waveform DATA PCL OUT DATA PCL OUT DATA PCL OUT SAMPLED SAMPLED SAMPLED STATE4 STATE5 STATE6 STATE1 STATE2 STATE3 STATE4 STATE5 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 FLOA T FLOA T FLOA T THESE SIGNALS ARE NOT ACTIV ATED DURING THE EXECUTION OF A MOVX INSTRUCTION INDICA TES ADDRESS TRANSITIONS EXTERNAL PROGRAM MEMORY FETCH FLOA T DATA SAMPLED 00H IS EMITTED DURING THIS PERIOD DPL OR Rt OUT INDICA TES DPH OR P2 SFR TO PCH TRANSITION PCL OUT (IF PROGRAM MEMORY IS EXTERNAL) PCL OUT (EVEN IF PROGRAM MEMORY IS INTERNAL) PCL OUT (IF PROGRAM MEMORY IS EXTERNAL) OLD DATA NEW DATA P0 PINS SAMPLED P1, P2, P3 PINS SAMPLED P1, P2, P3 PINS SAMPLED P0 PINS SAMPLED RXD SAMPLED INTERNAL CLOCK XTAL2 ALE PSEN P2 (EXT) READ CYCLE WRITE CYCLE RD WR PORT OPERATION MOV PORT SRC MOV DEST P0 MOV DEST PORT (P1. P2. P3) (INCLUDES INTO. INT1. TO T1) SERIAL PORT SHIFT CLOCK TXD (MODE 0) DATA OUT DPL OR Rt OUT INDICA TES DPH OR P2 SFR TO PCH TRANSITION RXD SAMPLED This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins, however, ranges from 25 to 125ns. This propagation delay is dependent on variables such as temperature and pin loading. Propagation also varies from output to output and component. Typically though A =25/C0095C fully loaded) RD and WR propagation delays are approximately 50ns. The other signals are typically 85ns. Propagation delays are incorporated in the AC specifications.

Rev. D (14 Jan. 97) 31MA TRA MHS 9. Ordering Information TSC 51C1 XXX Part Number 8051C1: Romless version 51C1: 8Kx8 Mask ROM TEMIC Semiconductor Microcontroller Product Line C Temperature Range C : Commercial 0° to 70°C I : Industrial –40° to 85°C –12 : 12 MHz version –16 : 16 MHz version Packaging A : PDIL 40 B : PLCC 44 C : PQFP 44 D : SSOP 44 E : PLCC 52 G : CDIL 40 H : LCC 44 I : CQPJ 44 B Customer Rom Code Conditioning R : Tape & Reel D : Dry Pack B : Tape & Reel and Dry Pack R–A Bounding Option –none : 12 PWM –A : 4 PWM & P2x Examples Part Number Description TSC51C1XXX–12CA Mask ROM XXX, 12 MHz, PDIL 40, 0 to 70°C TSC8051C1–16CER ROMless, 16 MHz, PLCC 52, 0 to 70°C, Tape and Reel Development Tools Reference Description synchronization signals using TSC8051C1/C2 Microcontroller” IM–80C51–RB–400–40 Emulator Base PC–TSC8051C1–RB–16 Probe card for TSC8051C1. These products are released by Metalink. Please consult the local tools distributor or your sales office. Product Marking : TEMIC Customer P/N Temic P/N  Intel 80, 82 YYWW Lot Number