U6083B_05 ATMEL | Alldatasheet
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- Pulse-width Modulation up to 2 kHz Clock Frequency Protection Against Short-circuit, Load Dump Overvoltage and Reverse VS Duty Cycle 18% to 100% Continuously Internally Reduced Pulse Slope of Lamp’s Voltage Interference and Damage Protection According to VDE 0839 and ISO/TR 7637/1 Charge-pump Noise Suppression Ground-wire Breakage Protection 1. Description The U6083B is a PWM IC in bipolar technology for the control of an N-channel power MOSFET used as a high-side switch. The IC is ideal for use in brightness control sys- tems (dimming) of lamps, for example, in dashboard applications. PWM Power Control IC with Interference Suppression U6083B Rev. 4770B–AUTO–09/05
4770B–AUTO–09/05 U6083B Figure 1-1. Block Diagram with External Circuit Current monitoring + short circuit detection Output Charge pumpRC oscillator Duty cycle range 18 to 100% Duty cycle reduction Control input Voltage monitoring Slew rate control PWM Logic 47 kΩ 47 nF VBatt 150 Ω GND Ground Rsh VS
4770B–AUTO–09/05 U6083B 2. Pin Configuration Figure 2-1. Pinning DIP8 4 5 8VS GND VI OSC OUTPUT SENSE 2 VS DELAY Table 2-1. Pin Description Pin Symbol Function
1 VS Supply voltage V S
2 GND IC ground
3 VI Control input (duty cycle)
4 OSC Oscillator
5 DELAY Short-circuit protection delay
6 SENSE Current sensing
8 OUTPUT Output
4770B–AUTO–09/05 U6083B 3. Functional Description
3.1 Pin 1, Supply Voltage, V S or VBatt
3.1.1 Overvoltage Detection
3.1.1.1 Stage 1
If overvoltages of V Batt > 20V (typically) occur, the ext ernal transistor is switched off, and switched on again at VBatt < 18.5V (hysteresis).
3.1.1.2 Stage 2
If VBatt > 28.5V (typically), the voltage limitation of the IC is reduced from V S = 26V to 20V. The gate of the external transistor remains at the potential of the IC ground, thus producing voltage sharing between FET and lamps in the event of overvoltage pulses (e.g., load dump). The short- circuit protection is not in operation. At V Batt approximately < 23V, the overvoltage detection stage 2 is switched off. Thus, during overvoltage detection stage 2, the lamp voltage Vlamp is cal- culated as follows: VLamp = VBatt – VS – VGS VS = supply voltage of the IC at overvoltage detection stage 2 VGS = gate - source voltage of the FET
3.1.2 Undervoltage Detection
In the event of voltages of approximately V Batt < 5.0V, the external FET is switched off and the latch for short-circuit detection is reset. A hysteresis ensures that the FET is switched on again at approximately VBatt ≥ 5.4V.
3.2 Pin 2, GND
3.2.1 Ground-wire Breakage
To protect the FET in the case of ground-wire breakage, a 1 M Ω resistor between gate and source is recommended to provide proper switch-off conditions.
3.3 Pin 3, Control Input
The pulse width is controlled by means of an external potentiometer (47 k Ω). The characteristic (angle of rotation/duty cycle) is linear. The duty cycle can be varied from 18 to 100%. It is possi- ble to further restrict the duty cycle with the resistors R 1 and R2 (see Figure 7-1 on page 11). In order to reduce the power dissipation of the FET and to increase the lifetime of the lamps, the IC automatically reduces the maximum duty cycle at pin 8 if the supply voltage exceeds V 2 = 13V. Pin 3 is protected against short-circuit to VBatt and ground (VBatt ≤ 16.5V).
4770B–AUTO–09/05 U6083B
3.4 Pin 4, Oscillator
The oscillator determines the frequ ency of the output voltage. This is defined by an external capacitor, C 2. It is charged with a constant current, I, until the upper switching threshold is reached. A second current source is then activated which taps a double current, 2 × I, from the charging current. The capacitor, C2, is thus discharged at the current, I, until the lower switching threshold is reached. The second source is then switched off again and the procedure starts once more.
3.4.1 Example for Oscillator Frequency Calculation
VT100 = High switching threshold (100% duty cycle) VT100 = V S × α 1 = (VBatt – IS × R3) × α 1 VT<100 = High switching threshold (< 100% duty cycle) VT<100 = V S × α 2 = (VBatt – IS × R3) × α 2 VTL = Low switching threshold VTL = V S × α 3 = (VBatt – IS × R3) × α 3 where α1, α2 and α3 are fixed values
3.4.2 Calculation Example
The above mentioned threshold voltages are calculated for the following values given in the data sheet. VBatt = 12V, I S = 4 mA, R3 = 150Ω, α1 = 0.7, α2 = 0.67 and α3 = 0.28 VT100 = (12V – 4 mA × 150Ω) × 0.7 ≈ 8V VT<100 = 11.4V × 0.67 = 7.6V VTL = 11.4V × 0.28 = 3.2V
3.4.3 Oscillator Frequency
3 cases have to be distinguished 1. f 1 for duty cycle = 100%, no slope reduction with capacitor C4 (see Figure 7-1 on page 11) , where C2 = 68 nF, IOSC = 45 µA f1 = ... = 75 Hz 2. f 2 for duty cycle < 100%, no slope reduction with capacitor C4 For a duty cycle of less than 100%, the oscillator frequency, f, is as follows: , where C2 = 68 nF, IOSC = 45 µA f2 = ... = 69 Hz IOSC IOSC
4770B–AUTO–09/05 U6083B 3. f 3 with duty cycle < 100% with slope reduction capacitor C4 (see “Output Slope Control” on page 6) where C2 = 68 nF, IOSC = 45 µA, C4 = 1.8 nF f3 = ... = 70 Hz By selecting different values of C2 and C4, it is possible to have a range of oscillator frequencies from 10 to 2000 Hz as shown in the data sheet.
3.5 Output Slope Control
The slope of the lamp voltage is internally limited to reduce radio interference by limitation of the voltage gain of the PWM comparator. Thus, the voltage rise on the lamp is proportional to the oscillator voltage increase at the switchover time according to the equation. dV8/dt = α4 × dV4/dt = 2 × α 4 × f × (α2 – α3) × (VBatt – IS × R3) when f = 75 Hz, V TX = VT < 100 and α4 = 63 then dV8/dt = 2 × 63 × 75 Hz × (0.67 – 0.28) × (12V – 4 mA × 15Ω) = 42 V/ms Via an external capacitor, C4, the slope can be further reduced as follows: dV8/dt = IOSC/(C4 + C2/α4) when I OSC = 45 µA, C4 = 1.8 nF, C2 = 68 nF and α4 = 63 then dV8/dt = 45 µA/(1.8 nF + 68 nF/63) = 15.6 V/ms To damp oscillation tendencie s, a resistance of 100 Ω in series with capacitance C 4 is recommended. Iosc
4770B–AUTO–09/05 U6083B
3.6 Interference Suppression
“On-board” radio reception according to VDE 0879 part 3/4.81 Test conditions referring to Figure 3-1 Application circuit according to Figure 1-1 on page 2 or Figure 7-1 on page 11 Load: nine 4W lamps in parallel Duty cycle = 18% V Batt = 12V f Osc = 100 Hz Figure 3-1. Voltage Spectrum of On-board Radio Reception
3.7 Pins 5 and Pin 6, Short-circui t Protection and Current Sensing
3.7.1 Short-circuit Detection and Time Delay, t d
The lamp current is monitored by means of an external shunt resistor. If the lamp current exceeds the threshold for the sh ort-circuit detection circuit (V T2 ≈ 90 mV), the duty cycle is switched over to 100% and the capacitor C 5 is charged by a current source of I ch – Idis. The external FET again is switched off after the cut-off threshold (V T5) is reached. Switching on the FET again is possible after a power-on reset only. The current source, I dis, ensures that the capacitor C5 is not charged by parasitic currents. The time delay, td, is calculated as follows: td = C5 × VT5/(Ich – Idis) With C5 = 100 nF and VT5 = 10.4V, Ich =13 µA, Idis = 3 µA, the time delay is as follows: td = 100 nF × 10.4V/(13 µA – 3 µA) td = 104 ms
4770B–AUTO–09/05 U6083B
3.7.2 Current Limitation
The lamp current is limited by a control amplifier to protect the external power transistor. The voltage drop across the external shunt resistor acts as the measured variable. Current limitation takes place for a voltage drop of V T1 ≈ 100 mV. Owing to the difference V T1 – VT2 ≈ 10 mV, it ensures that current limitation occurs only when the short-circuit detection circuit has responded. After a power-on reset, the output is inactive for half an oscillator cycle. During this time, the sup- ply voltage capacitor can be charged so that current limitation is guaranteed in the event of a short-circuit when the IC is switched on for the first time.
3.8 Pins 7 and 8, Charge Pump and Output
Pin 8 (output) is suitable for controlling a pow er MOSFET. During the active integration phase, the supply current of the operational amplifier is mainly supplied by the capacitor C 3 (bootstrap- ping). In addition, a trickle charge is generated by an integrated oscillator (f 7 ≈ 400 kHz) and a voltage doubler circuit. This permits a gate voltage supply at a duty cycle of 100%.
4770B–AUTO–09/05 U6083B 4. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Symbol Value Unit Junction temperature T j 150 °C Ambient temperature range T amb –40 to +110 °C Storage temperature range T stg –55 to +125 °C 5. Thermal Resistance Parameters Symbol Value Unit Junction ambient R thJA 120 K/W 6. Electrical Characteristics Tamb = –40°C to +110°C, VBatt = 9V to 16.5V, (basic function is guaranteed between 6.0V to 9.0V) reference point ground, unless otherwise specified (see Figure 1-1 on page 2). All other values refer to pin GND (pin 2). Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Current consumption 1 I S 7.9 mA Supply voltage Overvoltage detection, stage 1 V Batt 25 V Stabilized voltage I S = 10 mA 1 V s 24.5 27.0 V Battery undervoltage detection on off VBatt 4.4 4.8 5.0 5.4 5.6 6.0 V Battery Overvoltage Detection Stage 1: on off V Batt 18.3 16.7 20.0 18.5 21.7 20.3 V V Stage 2: Detection stage 2 on off VBatt 25.5 19.5 28.5 23.0 32.5 26.5 V V Stabilized voltage I S = 30 mA 1 V s 18.5 20.0 21.5 V Short-circuit Protection 6 Short-circuit current limitation V T1 = VS – V6 VT1 85 100 120 mV Short-circuit detection VT2 = VS – V6 VT2 75 90 105 mV VT2 = VS – V6 VT1 – VT2 31 0 3 0 m V Delay Timer Short-circuit Detection, VBatt = 12V 5 Switched off threshold V T5 = VS – V5 VT5 10.2 10.4 10.6 V Charge current I ch 13 µA Discharge current I dis 3µ A Capacitance current I 5 = Ich – Idis I5 51 0 1 5 m A Note: 1. Reference point is battery ground
4770B–AUTO–09/05 U6083B Voltage Doubler 7 Voltage Duty cycle 100% V 7 2 VS Oscillator frequency f 7 280 400 520 kHz Internal voltage limitation I 7 = 5 mA (whichever is lower) V7 26 27.5 30.0 V V7 VS+14 VS+15 VS+16 V Edge steepness dv8/dt = α4 dV4/dt dV8/dtmax α4 53 63 72
130 V/ms
Low level V 8 0.35 0.70 0.95 V VBatt = 16.5V Tamb = 110°C, R3 = 150Ω V8 1.5(1) V High level, duty cycle 100% V 8 V7 V Current V8 = Low level I 8 1.0 mA V8 = High level, I7 > ⏐ I8 ⏐ I8 –1.0 mA Duty cycle Min: C2 = 68 nF Max: VBatt ≤ 12.4V VBatt = 16.5V, C2 = 68 nF tp/T 100 Oscillator Frequency 4 f 10 2000 Hz Threshold cycle Upper Lower α 0.68 0.65 0.26 0.7 0.67 0.28 0.72 0.69 0.3 Oscillator current V Batt = 12V ±I OSC 34 45 54 µA Frequency C4 open, C2 = 68 nF duty cycle = 50% f5 6 7 5 9 0 H z 6. Electrical Characteristics (Continued) Tamb = –40°C to +110°C, VBatt = 9V to 16.5V, (basic function is guaranteed between 6.0V to 9.0V) reference point ground, unless otherwise specified (see Figure 1-1 on page 2). All other values refer to pin GND (pin 2). Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Note: 1. Reference point is battery ground V8 High, α1 VT100 VS V8 Low, α2 VT<100 VS VTL VS
4770B–AUTO–09/05 U6083B 7. Application Figure 7-1. Application Circuit - + - + + - Reset Reset Switch-on delay 2 I I Oscillator Overvoltage m onitoring stage 1 Low voltage m onitoring Reset 2Overvoltage m onitoring stage 2 Voltage doubler + - 90 m V 10 m V Current lim iting 47 nF 1 M Ω 150 Ω Ground 47 kΩ 47 µF Load R L 63 x R R GND 1.8 nF 100 nF 68 nF C C R sh V Batt V S V S V S R V S C V S Ich Idis V S V S V S V S V S R R C C
4770B–AUTO–09/05 U6083B 9. Package Information 8. Ordering Information Extended Type Number Package Remarks U6083B-MY DIP8 Pb-free 9.8 9.5 Di mensi ons i n mm 1.64 1.44 4.8 max 0.5 min 3.3 0.58 0.48 7.62 2.54 6.4 max 0.36 max 9.8 8.2 7.77 7.47 technical drawings according to DIN specifications
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