U6083B

U6083B ATMEL | Alldatasheet

Document overview

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Technical content

Features

 Pulse-width Modulation up to 2 kHz Clock Frequency  Protection Against Short-circuit, Load Dump Overvoltage and Reverse VS  Duty Cycle 18 to 100% Continuously  Internally Reduced Pulse Slope of Lamp's Voltage  Interference and Damage Protection According to VDE 0839 and ISO/TR 7637/1  Charge-pump Noise Suppression  Ground-wire Breakage Protection

Description

The U6083B is a PWM IC in bipolar technology for the control of an N-channel power MOSFET used as a high-side switch. The IC is ideal for use in brightness control sys- tems (dimming) of lamps, for example, in dashboard applications. PWM Power Control IC with Interference Suppression U6083B

2 U6083B

Figure 1. Block Diagram with External Circuit

Figure 2. Pinning DIP8

1 VS Supply voltage V S

2 GND IC ground

3 VI Control input (duty cycle)

5 DELAY Short-circuit protection delay

6 SENSE Current sensing

8 OUTPUT Output

4 U6083B

4770A–AUTO–11/03 Functional Description Pin 1, Supply Voltage, VS or VBatt Overvoltage Detection Stage 1 If overvoltages of V Batt > 20 V (typically) occur, the external transistor is switched off, and switched on again at VBatt < 18.5 V (hysteresis). Stage 2 If VBatt > 28.5 V (typically), the voltage limitation of the IC is reduced from V S = 26 V to 20 V. The gate of the external transistor remains at the potential of the IC ground, thus producing voltage sharing between FET and lamp s in the event of overvoltage pulses (e.g., load dump). The short-circuit protection is not in operation. At V Batt approximately < 23 V, the overvoltage detection stage 2 is switched off. Thus, dur- ing overvoltage detection stage 2, the lamp voltage Vlamp is calculated as follows: VLamp = VBatt - VS - VGS VS = supply voltage of the IC at overvoltage detection stage 2 VGS = gate - source voltage of the FET Undervoltage Detection In the event of voltages of approximately V Batt < 5.0 V, the external FET is switched off and the latch for short-circuit detection is reset. A hysteresis ensures that the FET is switched on again at approximately VBatt /g179 5.4 V. Pin 2, GND Ground-wire Breakage To protect the FET in the case of ground-wire breakage, a 1 M /g87 resistor between gate and source is recommended to provide proper switch-off conditions. Pin 3, Control Input The pulse width is controlled by means of an external potentiometer (47 k /g87). The char- acteristic (angle of rotation/duty cycle) is linear. The duty cycle can be varied from 18 to 100%. It is possible to further restrict the duty cycle with the resistors R 1 and R2 (see Figure 4 on page 10). In order to reduce the power dissipation of the FET and to increase the lifetime of the lamps, the IC automatically reduces the maximum duty cycle at pin 8 if the supply volt- age exceeds V 2 = 13 V. Pin 3 is protected against short-circuit to V Batt and ground (VBatt /g16316.5 V). Pin 4, Oscillator The oscillator determines the frequency of the output voltage. This is defined by an external capacitor, C 2. It is charged with a constant current, I, until the upper switching threshold is reached. A second current source is then activated which taps a double cur- rent, 2 /g180/g32I, from the charging current. The capacitor, C 2, is thus discharged at the current, I, until the lower switching threshold is reached. The second source is then switched off again and the procedure starts once more.

4770A–AUTO–11/03 Example for Oscillator Frequency Calculation Switching thresholds VT100 = High switching threshold (100% duty cycle) VT100 = V S /g180/g32/g971 = (VBatt - IS /g180/g32R3) /g180/g32/g971 VT<100 = High switching threshold (< 100% duty cycle) VT<100 = V S /g180/g32/g972 = (VBatt - IS /g180 R3) /g180/g32/g972 VTL = Low switching threshold VTL = V S /g180/g32/g973 = (VBatt - IS /g180 R3) /g180/g32/g973 where /g971, /g972 and /g973 are fixed values Calculation Example The above mentioned threshold voltages are calculated for the following values given in the data sheet. VBatt = 12 V, I S = 4 mA, R3 = 150 /g87, /g971 = 0.7, /g972 = 0.67 and /g973 = 0.28 VT100 = (12 V - 4 mA /g180 150 /g87) /g180/g320.7 /g187 8 V VT<100 = 11.4 V /g180/g320.67 = 7.6 V VTL = 11.4 V /g180/g320.28 = 3.2 V Oscillator Frequency 3 cases have to be distinguished 1. f 1 for duty cycle = 100%, no slope reduction with capacitor C4 (see Figure 4 on page 10) , where C2 = 68 nF, IOSC = 45 µA f1 = ... = 75 Hz 2. f 2 for duty cycle < 100%, no slope reduction with capacitor C4 For a duty cycle of less than 100%, the oscillator frequency, f, is as follows: , where C2 = 68 nF, IOSC = 45 µA f2 = ... = 69 Hz 3. f 3 with duty cycle < 100% with slope reduction capacitor C 4 (see “Output Slope Control” on page 6) where C2 = 68 nF, IOSC = 45 µA, C4 = 1.8 nF f3 = ... = 70 Hz By selecting different values of C2 and C4, it is possible to have a range of oscillator fre- quencies from 10 to 2000 Hz as shown in the data sheet. IOSC IOSC Iosc

6 U6083B

tion of the voltage gain of the PWM comparator. switchover time according to the equation. Figure 3. Voltage Spectrum of On-board Radio Reception

4770A–AUTO–11/03 Pins 5 and Pin 6, Short-circuit Protection and Current Sensing Short-circuit Detection and Time Delay, td The lamp current is monitored by means of an external shunt resistor. If the lamp current exceeds the threshold for the short-circuit detection circuit (V T2 /g187 90 mV), the duty cycle is switched over to 100% and the capacitor C5 is charged by a current source of Ich -I dis. The external FET again is switched off after the cut-off threshold (V T5) is reached. Switching on the FET again is possible after a power-on reset only. The current source, I dis, ensures that the capacitor C5 is not charged by parasitic currents. The time delay, td, is calculated as follows: td = C5 /g180/g32VT5/(Ich - Idis) With C5 = 100 nF and VT5 = 10.4 V, Ich =13 µA, Idis = 3 µA, the time delay is as follows: td = 100 nF /g180/g3210.4 V/(13 µA - 3 µA) td = 104 ms Current Limitation The lamp current is limited by a control amplifier to protect the external power transistor. The voltage drop across the external shunt resistor acts as the measured variable. Cur- rent limitation takes place for a voltage drop of V T1 /g187 100 mV. Owing to the difference VT1 - VT2 /g187 10 mV, it ensures that current limitation occurs only when the short-circuit detection circuit has responded. After a power-on reset, the output is inactive for half an oscillator cycle. During this time, the supply voltage capacitor can be charged so that current limitation is guaranteed in the event of a short-circuit when the IC is switched on for the first time. Pins 7 and 8, Charge Pump and Output Pin 8 (output) is suitable for controlling a power MOSFET. During the active integration phase, the supply current of the operational amplifier is mainly supplied by the capacitor C3 (bootstrapping). In addition, a trickle charge is generated by an integrated oscillator (f7 /g187 400 kHz) and a voltage doubler circuit. This permits a gate voltage supply at a duty cycle of 100%. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Symbol Value Unit Junction temperature T j 150 /g176C Ambient temperature range T amb -40 to +110 /g176C Storage temperature range T stg -55 to +125 /g176C Thermal Resistance Parameters Symbol Value Unit Junction ambient R thJA 120 K/W

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4770A–AUTO–11/03

Electrical Characteristics

Tamb = -40/g176C to +110/g176C, VBatt = 9 to 16.5 V, (basic function is guaranteed between 6.0 V to 9.0 V) reference point ground, unless otherwise specified (see Figure 1 on page 2). All other values refer to pin GND (pin 2). Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Current consumption 1 I S 7.9 mA Supply voltage Overvoltage detection, stage 1 V Batt 25 V Stabilized voltage I S =1 0m A 1 V s 24.5 27.0 V Battery undervoltage detection on off VBatt 4.4 4.8 5.0 5.4 5.6 6.0 V Battery Overvoltage Detection Stage 1: on off V Batt 18.3 16.7 20.0 18.5 21.7 20.3 V V Stage 2: Detection stage 2 on off VBatt 25.5 19.5 28.5 23.0 32.5 26.5 V V Stabilized voltage I S = 30 mA 1 V s 18.5 20.0 21.5 V Short-circuit Protection 6 Short-circuit current limitation V T1 = VS -V 6 VT1 85 100 120 mV Short-circuit detection VT2 = VS -V 6 VT2 75 90 105 mV VT2 = VS -V 6 VT1 -V T2 31 0 3 0 m V Delay Timer Short-ciruit Detection, VBatt = 12 V 5 Switched off threshold V T5 = VS - V5 VT5 10.2 10.4 10.6 V Charge current I ch 13 µA Discharge current I dis 3µ A Capacitance current I 5 = Ich - Idis I5 51 0 1 5 m A Voltage Doubler 7 Voltage Duty cycle 100% V 7 2V S Oscillator frequency f 7 280 400 520 kHz Internal voltage limitation I 7 = 5 mA (whichever is lower) V7 26 27.5 30.0 V V7 VS+14 VS+15 VS+16 V Edge steepness dv8/dt = /g974 dV4/dt dV8/dtmax /g974 53 63 72

130 V/ms

Low level V 8 0.35 0.70 0.95 V VBatt = 16.5 V Tamb =1 1 0/g176C, R3 =1 5 0/g87 V8 1.5(1) V High level, duty cycle 100% V 8 V7 V Current V8 = Low level I 8 1.0 mA V8 = High level, I7 > /g189 I8 /g189 I8 -1.0 mA Duty cycle Min: C2 = 68 nF Max: VBatt /g163 12.4 V VBatt = 16.5 V, C2 = 68 nF tp/T 100 Note: 1. Reference point is battery ground

4770A–AUTO–11/03 Oscillator Frequency 4 f 10 2000 Hz Threshold cycle Upper Lower /g97 /g972 /g973 0.68 0.65 0.26 0.7 0.67 0.28 0.72 0.69 0.3 Oscillator current V Batt = 12 V ±I OSC 34 45 54 µA Frequency C4 open, C2 = 68 nF duty cycle = 50% f5 6 7 5 9 0 H z Electrical Characteristics (Continued) Tamb = -40/g176C to +110/g176C, VBatt = 9 to 16.5 V, (basic function is guaranteed between 6.0 V to 9.0 V) reference point ground, unless otherwise specified (see Figure 1 on page 2). All other values refer to pin GND (pin 2). Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Note: 1. Reference point is battery ground V8 High, /g971 VT100 VS V8 Low, /g972 VT<100 VS /g973 VTL VS

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Figure 4. Application Circuit

4770A–AUTO–11/03

Package Information

Ordering Information

Extended Type Number Package Remarks U6083B DIP8 – 9.8 9.5 Dimensions in mm 1.64 1.44 4.8 max 0.5 min 3.3 0.58 0.48 7.62 2.54 6.4 max 0.36 max 9.8 8.2 7.77 7.47 technical drawings according to DIN specifications

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