U6057B TEMIC | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 9
Technical content
Features
Only a single data line is necessary Quadruple comparison of the data signal for high transmission safety Minimum of peripherals Master/slave operation Wide supply-voltage range According to VDE 0839 Load-dump protected
Ordering Information
U6057B–FL SO20 VS 13273 Synchronization Stabilization POR Clock output Oscillator Operating mode Frequency divider Start pulse detection Data decoding Data end detection Overflow store 8 bit Buffer 8 bit Sequence control detection Safety condition 4-stage counter Comparison Output memory 8-bit shift register 1. or 2. byte Parallel P Serial S 14 V 14 V VS CO OSC PP DI P/S DIN CLK VStab SYN GND DOUT VS Figure 1. Block diagram
Rev. A1, 03-Dec-97 Preliminary Information 2 (9) Pin Configuration Table 1. Pin description Figure 2. Pinning of U6057B in the event of voltage dips at VS. All timing in the circuit is derived from an RC-oscillator. minimum value of ROSC should not be less than 68 k. Table 2. Times derived from the transmitted frequency
Description
9.688 ms Transmission cycle 15 ms Minimum reaction time 60 ms Data word master – slave 10 ms + 312 s start bit Data pause master – slave 4.688 ms
Rev. A1, 03-Dec-97 3 (9) Supply Voltage 5 V The receivers can be supplied from one stabilized, noise- free voltage source. In this case, the series resistor and the filter capacitor are not required. Pin VStab is also supplied by the 5-V supply (see figure 4). Structure of the Data Word A switch information unit consists of four parts: 1. One bit for receiver synchronization 2. Information bit with ”High” = switch open ”Low” = switch closed 3. Zero bit 4. Zero bit The data word consists of two start bits and eight information units. For a transmitter frequency of 6.4 kHz, the data word length is 5 ms plus the start pulse followed by a 10-ms-long data interval. The data interval has high potential. When the supply voltage is applied, data transmission is constantly repeated in accordance with this pattern. Data Decoding If a negative edge appears at the data input, the receiver checks whether a start pulse or a fault is present by measuring the duration of the pulse (a minimum time must be observed). If there is a fault, the receiver waits for the next negative edge. If it recognizes a start pulse, it checks whether an information unit with 8 bits is following and stores this in an 8-bit overflow store. The arriving data are ignored if there is no 8-bit string owing to a fault or a synchronism. The receiver is synchronized by each one bit. Scanning of the information takes place in the middle of the information bit. In order to make scanning sufficiently precise, the oscillator frequency of the receiver was selected to be four times as large as that of the transmitter. The deviation of the receiver frequency to the four-fold transmitter frequency may be up to 15% while still guaranteeing reliable data cognition. Data Check The data read into the 8-bit overflow store is compared with the content of the buffer. If this is identical, a 4-stage counter is incremented by one stage. If this is not identical, the counter is reset. The new data combination is transferred to the buffer after each comparison irrespective of the result. After double or quadruple coincidence has been estab- lished, the content of the buffer is always transferred to the output memory. Since the period of data transmission is 15 ms this results in a minimum delay time of 60 ms or 30 ms for detection of a change of the data word. Faults on the data line and switch bouncing may lead to an extension of the delay time. Precondition to transfer the data word into the output memory: Input P/S must be in high potential. Synchronization Proper data transfer requires a synchronization between the internal data processing and the microcontroller’s read-out frequency. The U6057B provides a synchronization pulse (Pin SYN) of t = 161/fOSC which triggers the microcontroller to read-out data in the following time window of typically 215 ms or 415 ms. The synchronization is derived from the positive edge of the internal transfer pulse. This pulse causes the data transfer to the output shift register after double/quadruple data word comparison. The microcontroller reads the output shift register after each synchronization pulse. In practise, the time delay for data recognition varies depending on the event of data signal change on the data line and the status of the internal 4-stage (or 2-stage) counter. This counter is 0 after each synchronization pulse. With a programmed quadruple comparison the data recognition time ranges from 4 15 ms to 715 ms whereas it may range from 2 15 ms to 315 ms in the case of the programmed double comparison. If the system is operated with multiple change of the data- word during the comparison time (415 ms or 2 15 ms), the data recognition time may last longer than mentioned above. Note: In master – slave operation, each IC produces its own synchronization pulse. Cascading (Master – Slave Operation) Determination of master or slave is defined by the con- necting of the Pin PP: Master/ alone: PP open or PP to VS Slave: PP to GND In master mode, the oscillator is connected with ROSC and COSC, and the clock output is active. In slave mode, the oscillator is blocked and must be activated by the clock output of the master. The master recognizes the start-bit and decodes the first eight information bits. The slave also
Rev. A1, 03-Dec-97 Preliminary Information 6 (9) Absolute Maximum Ratings Receiver with recommended circuitry Parameters Symbol Value Unit Supply voltage (static) VS V Power dissipation Tamb = 85°C Ptot 920 mW Junction temperature Tj 150 Storage temperature range Tstg –55 to +125 Ambient temperature range Tamb –40 to +85 Thermal Resistance Parameters Symbol Value Unit Junction ambient SO20 RthJA K/W
Electrical Characteristics
VBatt = 13.5 V, Tamb = 25°C, reference point = GND Receiver with recommended circuitry Parameters Test Conditions / Pins Symbol Min. Typ. Max. Unit Supply voltage VBatt V 5-V supply (without RV and CV) VS 4.75 5.0 V Stabilized voltage VStab 5.2 V Supply current IS 1.5 3.0 mA Internal clamping VZ 14.3 V POR threshold VPOR 2.5 3.4 4.0 V Protection resistor RV 510 Protection capacitor CV 100 F Input data DIN Threshold voltage VDIN–TH 1.6 1.8 2.3 V Input current VDIN = 0 V –IDIN–IN 2.0 A Internal pull-down resistor RDIN–IN 100 k Input clock CLK Threshold voltage VCLK–TH 1.6 1.8 2.3 V Input current VCLK = 0 V –ICLK–IN 2.0 A Internal pull-down resistor RCLK–IN 100 k Clock frequency fCLK 1.0 24.8 kHz Delay time CLK – DOUT tDEL s Clock pulse length tCPL s Waiting time P/S – CLK tWT s Input parallel/serial P/S Threshold voltage VP/S–TH 1.6 1.8 2.3 V Input current VP/S = 0 V –IP/S–IN 2.0 A Internal pull-down resistor RP/S–IN 100 k Input data 2/4 Threshold voltage V2/4–TH 1.6 1.8 2.3 V Input current V2/4 = 0 V –I2/4–IN 2.0 A Internal pull-down resistor R2/4–IN 100 k
Rev. A1, 03-Dec-97 7 (9) Unit Max. Typ. Min. Symbol Test Conditions / Pins Parameters Serial data output DOUT ( open collector ) Saturation voltage 1 mA VDOUT 0.2 V Current capability IDOUT 1.0 mA Leakage current ILDOUT 5.0 A Rise time RDOUT = 51 k to Vstab trOUT s Fall time RDOUT = 51 k to Vstab tfOUT 200 ns Oscillator input OSC Internal discharge resistor RDIS 1.6 2.0 2.4 k Lower threshold Vstab0.214 VOSC–THL 1.1 V Upper threshold Vstab0.615 VOSC–THH 3.3 V Input current VOSC = 0 V –IOSC 1.0 A Frequency fOSC 1.0 24.8 40.0 kHz Data input DI Threshold voltage VDI VS0.5 V Input current –IDI 1.0 A Internal pull-down resistor RDI 100 k Internal clamping VZDI 14.3 V External protection RDI–EXT 0.1 k Program Pin PP Lower threshold VPPtl VS0.24 V Upper threshold VPPth VS0.50 V Pin PP open VPPO VS0.37 V Input current VPP = 0 V VPP = VS –IPP IPP A A Clock output CO Output current VCO = 0 V –ICO 110 300 A Output open VCO–open Vstab0.8 V Output current VCO = 1 V ICO 1.0 mA Saturation voltage low VCO = 1 V VCO 1.2 V Internal pull-down resistor RCO 200 k Synchronization output SYN (open collector) Saturation voltage 1 mA VSYN 0.2 V Current capability ISYN 1.0 mA Leakage current ILSYN 5.0 A Rise time RSYN = 51 k to Vstab trSYN s Fall time RSYN = 51 k to Vstab tfSYN 200 ns
Rev. A1, 03-Dec-97 Preliminary Information 8 (9)
Package Information
9.15 8.65 11.43 12.95 12.70 2.35 0.25 0.10 0.4 1.27 7.5 7.3 0.25 10.50 10.20
Rev. A1, 03-Dec-97 9 (9) Ozone Depleting Substances Policy Statement It is the policy of TEMIC TELEFUNKEN microelectronic GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs). The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. TEMIC TELEFUNKEN microelectronic GmbH semiconductor division has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency (EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively. TEMIC can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances. We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use TEMIC products for any unintended or unauthorized application, the buyer shall indemnify TEMIC against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. TEMIC TELEFUNKEN microelectronic GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 (0)7131 67 2831, Fax number: 49 (0)7131 67 2423