U5021M ATMEL | Alldatasheet
Document overview
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Technical content
Features
Low Current Consumption: IDD < 100 µA RC Oscillator Internal Reset During Power-up and Supply Voltage Drops (POR) “Short” Trigger Window for Active Mode, “Long” Trigger Window for Sleep Mode Cyclical Wake-up of the Microcontroller in Sleep Mode Trigger Input Single Wake-up Input Reset Output Enable Output
Description
The digital window watchdog timer, U5021M, is a CMOS integrated circuit. In applica- tions where safety is critical, it is especia lly important to monitor the microcontroller. Normal microcontroller operation is indicated by a cyclically transmitted trigger signal, which is received by a window watchdog timer within a defined time window. A missing or a wrong trigger signal causes the watchdog timer to reset the microcon- troller. The IC is tailored for microcontrollers which can work in both full-power and sleep mode. With an additional voltage monitoring (power-on reset and supply voltage drop reset), the U5021M offers a complete monitoring solution for microsystems in automotive and industrial applications. Digital Window Watchdog Timer U5021M
2 U5021M
Figure 1. Block Diagram with External Ciruit Figure 2. Pinning SO8
4756C–AUTO–09/04 Functional Supply Voltage, Pin 6 The U5021M requires a stabilized supply voltage VDD = 5 V ±5% to comply with its elec- trical characteristics. An external buffer capacitor of C = 10 nF may be connected between pin 6 and GND. RC Oscillator, Pin 8 The clock frequency, f, can be adjusted by the components R 1 and C1 according to the formula: where t = 1.35 + 1.57 R1 (C1 + 0.01) R1 in kΩ, C1 in nF and t in µs The clock frequency determines all time periods of the logic part as shown in the table “Electrical Characteristics” under the subheading “Timing” on page 9. With an appropri- ate component selection, the clock frequency, f, is nearly independent of the supply voltage as shown in Figure 3 on page 4. Frequency tolerance ∆f max = 10% with R1 ±1%, C1 = ±5% Pin Description Pin Symbol Function
1 WAKE-UP
Wake-up input (pull-down resistor) There is one digitally debounced wake-up input. During the long watchdog window, each signal slope at the input initiates a reset pulse at pin 5. 2T R I G Trigger input (pull-up resistor) It is connected to the microprocessor’s trigger signal. 3M O D E Mode input (pull-up resistor) The processor’s mode signal initiates the switchover between the long and the short watchdog time. 4E N A Enable output (push-pull) It is used for the control of peripheral components. It is activated after the processor triggers three times correctly.
5 RESET
Reset output (open drain) Resets the processor in the case of a trigger error or if a wake-up pulse occurs during the long watchdog period.
6 VDD Supply voltage
7 GND Ground, reference voltage
8 OSC RC oscillator
t---=
4 U5021M
Figure 3. Period t versus R1, at C1 = 500 pF Figure 4. Power-on Reset and Switch-over Mode its defined reset status (see Figure 4). Pin 5 has an open-drain output.
- If the low signal does not occur within t1 (see Figure
6 U5021M
Figure 6. Pulse Diagram of a Correct Trigger Sequence During the Short Watchdog Time signal during the enable time, t5, activates a reset pulse, t6. low potential at the mode pin (pin 3). Figure 7. Pulse Diagram of the Long Watchdog Time
internal timer. The numbers for the time-outs are the same as on the pulse diagrams. Figure 8. State Diagram
8 U5021M
4756C–AUTO–09/04 Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Symbol Value Unit Supply voltage V DD 6.5 V Output current I OUT ±2 mA Input voltage V IN -0.4 V to VDD +0.4 V V Ambient temperature range T amb -40 to +125 ° C Storage temperature range T stg -55 to +150 ° C Thermal Resistance Parameters Symbol Value Unit Junction ambient R thJA 180 K/W
Electrical Characteristics
VDD = 5 V; Tamb = -40°C to +85°C; reference point is pin 7, unless otherwise specified Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Supply voltage 6 V DD 4.5 5.5 V Current consumption R 1 = 66 kΩ 6I DD 60 µA Power-on reset Release reset state with rising voltage 6V POR1 3.9 4.5 V Get reset state with falling voltage 6V POR2 3.8 4.4 V Power-on reset hysteresis V POR_hys 40 200 mV Reset level for low VDD VDD = 1 V to VPOR1 IRST = -300 µA VRST 0.1 V DD Inputs 1, 2, 3 Logical “high” V IH 3.4 V Logical “low” V IL 1.6 V Hysteresis V IN_hys 0.6 1.4 V Input voltage range V IN -0.3 VDD + 0.3 V Input current 2, 3 I IN1 52 0 µ A Input current 1 I IN2 -20 -5 µA Outputs Maximum output current 4, 5 I OUT -2 2 mA Logical output “low” I OUT = -1 mA 4, 5 V OL 0.2 V Logical output “high” I OUT = -1 mA 4 V OH VDD - 0.2 V Leakage current V OUT = 5 V 5 I leak 2µ A
4756C–AUTO–09/04
Package Information
Frequency deviation(1) R1 = 66 kΩ, C1 = 470 pF , VDD = 4.5 V to 5.5 V ∆f5 % Debounce time 2, 3 3 4 Cycle Debounce time 1 96 128 Cycle Maximum trigger pulse length t trgmax 45 Cycle Power-up reset time t o 201 Cycle Switch over mode time t 1 1,112 Cycle Disable time Short watchdog window t 2 130 Cycle Enable time Short watchdog window t 3 124 Cycle Disable time Long watchdog window t 4 71,970 Cycle Enable time Long watchdog window t 5 30,002 Cycle Reset-out time t 6 40 Cycle Note: 1. Frequency deviation also depends on the tolerances of the external components Electrical Characteristics (Continued) VDD = 5 V; Tamb = -40°C to +85°C; reference point is pin 7, unless otherwise specified Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit
Ordering Information
Extended Type Number Package Remarks U5021M-NFP SO8 – technical drawings according to DIN specifications Dimensions in mm 5.00 4.85 0.4 1.27 3.81 1.4 0.25 0.10 5.2 4.8 3.7 3.8 6.15 5.85 0.2
10 U5021M
4756C–AUTO–09/04 Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Changes from Rev. 4756A-AUTO-11/03 to Rev. 4756B-AUTO-07/04 1. Electrical Characteristics Table, page 8, row “Reset capability” added Changes from Rev. 4756B-AUTO-07/04 to Rev. 4756C-AUTO-09/04 1. Electrical Characteristics Table, page 8, row “Reset capability” changed in “Reset level for low VDD“
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