U4256BM-R

U4256BM-R ATMEL | Alldatasheet

Document overview

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Technical content

Features

• Reference Oscillator up to 15 MHz (Tuned)  Oscillator Buffer Output (for AM Up/Down Conversion)  Two Programmable 16-bit Dividers  Fine-tuning Steps Possible  Fast Response Time due to Integrated Loop Push-pull Stage  3-wire Bus (Enable, Clock and Data; 3 V and 5 V Microcontrollers Acceptable)  Four Programmable Switching Outputs (Open Drain)  Three DACs for Software Controlled Tuner Alignment  Low-power Consumption  High S/N Ratio  Integrated Band Gap – only One Supply Voltage Necessary

Description

The U4256BM-R is a synthesizer IC for FM receivers and an AM up-convertion system in BICMOS technology. Together with the AM/FM IC T4258 or U4255BM, it performs a complete AM/FM car radio front-end, which is recommended also for RDS (Radio Data System) applications. It is controlled by a 3-wire bus and also contains switches and Digital to Analog Converters (DACs) for software-controlled alignment of the AM/FM tuner. The U4256BM-R is the pin-compatible succesor IC of U4256BM-N. Pin Configuration Figure 1. Pinning SSO20 1

2 U4256BM-R

Figure 2. Block Diagram

1 PDO Phase detector output

2 PD Pulsed current output

3 DAC1 Digital-to-analog converter 1

4 DAC2 Digital-to-analog converter 2

5 DAC3 Digital-to-analog converter 3

6 VS Supply voltage analog part

7 SWO1 Switching output 1

8 SWO2 Switching output 2

9 SWO3 Switching output 3

10 SWO4 Switching output 4

11 GND Ground, digital part

12 OSCOUT Reference oscillator output

13 OSCIN Reference oscillator input

14 V5 Capacitor band gap

15 MX2LO Oscillator buffer output

16 DATA Data input

17 CLK Clock

18 EN Enable

19 FMOSCIN FM-oscillator input

20 GNDan Ground, analog part

4562C–AUDR–08/04 Functional For a tuned FM-broadcast receiver, the following parts are needed:  Voltage-Controlled Oscillator (VCO)  Antenna Amplifier Tuned Circuit  RF Amplifier Tuned Circuit Typical modern receivers with electronic tuning are tuned to the desired FM frequency by the frequency synthesizer IC U4256BM-R. The special design allows the user to build software-controlled tuner alignment systems. Two programmable DACs (Digital-to- Analog Converter) support the computer-controlled alignment. The output of the PLL is a tuning voltage which is connected to the VCO of the receiver IC. The output of the VCO is equal to the desired station frequency plus the IF (10.7 MHz). The RF and the oscillator signal (VCO) are both input to the mixer that translates the desired FM chan- nel signal to the fixed IF signal. For FM, the double-conversion system of the receiver requires exactly 10.7 MHz for the first IF frequency, which determines the center fre- quency of the software-controlled integrated second IF filter. If this oscillator tuning feature is not used, the internal capacities have to be switched off and the oscillator has to be operated with high-quality external capacities to ensure that the operational frequency is exactly 10.250 MHz. When dimensioning the oscillator circuit, it is important that the additional capacities enable the oscillator to operate through its complete tracking range. The oscillating abil- ity depends very strongly on the used crystal oscillator. Initializing the oscillator should be established without switching any additional capacities to guarantee that the oscilla- tor starts to operate properly. Due to the lower quality of the integrated capacities compared to discrete capacities, the amount of the switched integrated capacities should always be minimized. (If necessary reduce tracking range or use another crystal oscillator.) The U4256BM-R has a very fast response time of maximum 800 µs (at 2 mA, f Step = 50 kHz, measured on MPX signal). It performs a high signal to noise ratio. Only one supply voltage is necessary, due to a integrated band gap. Input/Output Interface Circuits PDO (Pin 1) PDO is the buffer amplifier output of the PLL. The bipolar output stage is a rail-to-rail amplifier. PD (Pin 2) PD is the current charge pump output of the PLL. The current can be controlled by setting the Bits. The loop filter has to be designed corresponding to the choosen pump current and the internal reference frequency. A recommendation can be found in the application circuit. The charge-pump current can be choosen by setting the Bits 71 and 70 as following: IPD (µA) B71 B70 25 0 0 100 0 1 500 1 0 2000 1 1

4 U4256BM-R

Figure 3. Internal Components at PDO Connection FMOSCIN (Pin 19) FMOSCIN is the preamplifier input for the FM oscillator signal. Figure 4. Internal Components at FMOSCIN ence frequency for U4255BM or T4258. Figure 5. Internal Components at MX2LO

6 U4256BM-R

4562C–AUDR–08/04 DAC 1, 2 in FM Mode (Pin 3 and Pin 4) The gains of DAC1 and DAC2 have a range of 0.69 × V(PDO) to 2.16 × V(PDO). V(PDO) is the PLL tuning voltage output. This range is divided into 256 steps. So one step is approximately (2.16 - 0.46) × V (PDO) / 255 = 0.005764 × V(PDO). The gain of DAC1 can be controlled by the Bits 36 to 43 (G-20 to G-27) and the gain of DAC2 by the Bits 0 to 7 (G- 20 to G-27) as following: Offset = 31 (intermediate position) The offset of DAC1 and DAC2 has a range of 0.56 V to -0.59 V. This range is divided into 64 steps. So one step is approximately 1.15 V/ 63 = 18.25 mV. The offset DAC1 can be controlled by the Bits 44 to 49 (O-2 0 to O-25) and the offset of DAC2 by the Bits 8 to 13 (O-20 to O-25) as following: Gain = 53 (intermediate position) Gain DAC1 Approximately B43 B42 B41 B40 B39 B38 B37 B36 Decimal Gain Gain DAC2 A p p r o x i m a t e l yB 7B 6B 5B 4B 3B 2B 1B 0 Decimal Gain 0.69 × V(PDO) 00000000 0 0.69576 × V(PDO) 00000001 1 0.70153 × V(PDO) 00000010 2 0.70729 × V(PDO) 00000011 3 0.99549 × V(PDO) 00110101 5 3 2.14847 × V(PDO) 11111101 2 5 3 2.15424 × V(PDO) 11111110 2 5 4 2.16 × V(PDO) 11111111 2 5 5 Offset DAC1 Approximately B49 B48 B47 B46 B45 B44 Decimal Gain Offset DAC2 Approximately B13 B12 B11 B10 B9 B8 Decimal Gain 0 . 5 6 V 000000 0 0 . 5 4 1 7 V000001 1 0 . 5 2 3 5 V000010 2 0 . 5 0 5 2 V000011 3 +0.0059 V 0 1 1 1 1 1 31 0 . 5 5 3 5 V111101 6 1 - 0 . 5 7 1 7 V 111110 6 2 - 0 . 5 9 V 111111 6 3

4562C–AUDR–08/04 DAC 1, 2 in AM Mode (Pin 3 and Pin 4) In AM mode the DAC input voltage V (PDO) is internal connected to 3 V. The gains of DAC1 and DAC2 have a range of 0.46 × 3V t o 3 . 0 3× 3V . V(PDO) is the PLL tuning volt- age output. This range is divided into 256 steps. So one step is approximately (3.03 - 0.46) × 3 V/255 = 0.01007 × 3 V. The gain of DAC1 can be controlled by the Bits 36 to 43 (G-2 0 to G-2 7) and the gain of DAC2 by the Bits 0 to 7 (G-2 0 to G-2 7) as following: Offset = 31 (intermediate position) Remark: V(PDO) is 3 V in AM mode. The offset of DAC1 and DAC2 has a range of +1.46 V to -1.49 V. This range is divided into 64 steps. So one step is approximately 2.95 V/ 63 = 46.8 mV. The offset DAC1 can be controlled by the Bits 44 to 49 (O-2 0 to O-25) and the offset of DAC2 by the Bits 8 to 13 (O-20 to O-25) as following: Gain = 53 (intermediate position) Gain DAC1 Approximately B43 B42 B41 B40 B39 B38 B37 B36 Decimal Gain Gain DAC2 A p p r o x i m a t e l y B 7B 6B 5B 4B 3B 2B 1B 0 Decimal Gain 0.4607 × 3 V 00000000 0 0.4710 × 3 V 00000001 1 0.4812 × 3 V 00000010 2 0.4915 × 3 V 00000011 3 1.0029 × 3 V 00110101 5 3 3.0097 × 3 V 11111101 2 5 3 3.0196 × 3 V 11111110 2 5 4 3.0296 × 3 V 11111111 2 5 5 Offset DAC1 Approximately B49 B48 B47 B46 B45 B44 Decimal Gain Offset DAC2 Approximately B13 B12 B11 B10 B9 B8 Decimal Gain 1 . 4 6 0 6 V000000 0 1 . 4 1 3 8 V000001 1 1 . 3 6 6 5 V000010 2 1 . 3 1 9 6 V000011 3 - 0 . 0 0 7 9 V 011111 3 1 - 1 . 3 9 7 5 V 111101 6 1 - 1 . 4 4 4 7 V 111110 6 2 - 1 . 4 9 1 7 V 111111 6 3

8 U4256BM-R

Figure 8. Internal Components at DAC3 CLOCK. The bus is designed for microcontrollers which operate with 3 V supply voltage. Details of the data transfer protocol are shown in the table ‘3-wire Bus Description’. Figure 9. Internal Components at EN, DATA, CLK

0.55 V 0 0 0

1.25 V 0 0 1

1.90 V 0 1 0

2.60 V 0 1 1

3.30 V 1 0 0

4.10 V 1 0 1

4.80 V 1 1 0

5.45 V 1 1 1

All switching outputs are ‘open drain’ and can be set and reset by software control. Details are described in the data transfer protocol. Figure 10. Internal Components at SWO1, 2, 3 and 4 tion circuit is shown in Figure 15. If a reference is available, it can be applied at OSCIN. The minimum voltage should be 100 mVrms. In this case, Pin OSCOUT has to be open.

10 U4256BM-R

Figure 11. Internal Components at OSCIN and OSCOUT Figure 12. Internal Connection of Tuning Capacity for Crystal Oscillator

4562C–AUDR–08/04

Application Information

Figure 13. FMOSCIN Sensitivity The register settings of U4256BM-R are programmed by a 3-wire bus protocol. The bus protocol consists of separate commands. A defined number of bits is transmitted sequentially during each command. One command is used to program all the bits of one register. The different registers available (see table Data Transfer) are addressed by the length of the command (num- ber of transmitted bits) and by two address bits, that are unique to each register of a given length. 16-bit registers are programmed by 16-bit commands and 24-bit registers are programmed by 24-bit commands. Each bus command starts with a rising edge on the enable line (EN) and ends with a falling edge on EN. EN has to be kept HIGH during the bus command. The sequence of transmitted bits during one command starts with the LSB of the first byte and ends with the MSB of the last byte of the register addressed. To transmit one bit (0/1) DATA has to be set to the appropriate value (LOW/HIGH) and a LOW to HIGH transition has to be performed on the clock line (CLK) while DATA is valid. The DATA is evaluated at the rising edges of CLK. The number of LOW to HIGH transitions on CLK during the HIGH period of EN is used to determine the length of the command. The bus protocol and the register addressing of U4256BM-R are compatible to the addressing used in U4255BM and T4258. That means U4256BM-R and U4255BM (or T4258) can be operated on the same 3-wire bus as shown in the application circuit. 100 150 0 20 40 60 80 100 120 140 160 Frequency (MHz) Vi (mVrms on 50 Ω)

12 U4256BM-R

Figure 14. 3-wire Bus Timing Diagram Figure 15. 3-wire Pulse Diagram

13 IPD

Table 1. Control Registers

00 I P D

00 O - 2 5 O-24 O-23 O-22 O-21 O-20 G-27 G-26 G-27 G-25 G-24 G-23 G-22 G-20

01 O - 2 5 O-24 O-23 O-22 O-21 O-20 G-27 G-26 G-27 G-25 G-24 G-23 G-22 G-20

14 U4256BM-R

4562C–AUDR–08/04 Thermal Resistance Parameters Symbol Value Unit Junction ambient, when soldering to PCB R thJA 140 K/W Operating Range All voltages are referred to GND (Pin 11) Parameters Symbol Min. Typ. Max. Unit Supply voltage range Pin 6 V S 88 . 5 1 2V Ambient temperature T amb -40 +85 °C Input frequency FMOSCIN Pin 19 f in 70 160 MHz Programmable N, R divider SF 2 65535 Crystal reference oscillator Pins 12 and 13 fXTAL 0.1 15 MHz

Electrical Characteristics

Test Conditions (unless otherwise specified): VS = 8.5 V , Tamb = 25°C. No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*

1 Supply Voltage

1.1 Analog supply voltage 6 V S 88 . 5 1 2VA

2 Supply Current

2.1 Analog supply current 6 I S 51 0 2 5 m A A

3.1 Input voltage f = 0.1 to 15 MHz 13 OSC 100 mV rms B

4 OSC Buffer (MX2LO)

4.1 Output AC voltage At Pin15: 47 pF and

1k Ω 15 v MX2LO 80 120 200 mV pp B 4.2 Output DC voltage 15 V MX2LO 1.8 2.0 2.2 V A 5F M O S C I N

5.1 Input voltage f = 70 to 120 MHz

f = 120 to 160 MHz 19 FMOSC FMOSC 150 mVrms mVrms B

6 Pulsed Current Output PD

6.1 Output current Bit 71,

70 = ‘00’ PD = 2.5 V 2 ± IPD 20 25 30 µA A

6.2 Output current Bit 71,

70 = ‘01’ PD = 2.5 V 2 ± IPD 80 100 120 µA A

6.3 Output current Bit 71,

70 = ‘10’ PD = 2.5 V 2 ± IPD 400 500 600 µA A

6.4 Output current Bit 71,

70 = ‘11’ PD = 2.5 V 2 ± IPD 1500 2000 2400 µA A 6.5 Leakage current PD = 2.5 V 2 ± IPDL 20 nA A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

4562C–AUDR–08/04 7P D O

7.1 Saturation voltage

HIGH 3, 4 8.0 8.5 V A

7.2 Saturation voltage

LOW 3, 4 0 0.4 V A

8 SWO1, SWO2, SWO3, SWO4 (Open Drain)

8.1 Output leakage current

Pin 7,8,9,10 over R against 8.5 V 7, 8, 9, 10 ISWOH 100 nA A

8.2 Output voltage LOW I = 1 mA 7, 8,

9, 10 VSWOL 100 400 mV A

9 DAC1, DAC2

9.1 Output current 3, 4 I DAC1, 2 ± 1m AC

9.2 Output voltage 3, 4 V DAC1, 2 0.3 V S-0.6 V A

9.3 Maximum offset range

(FM) offset = 0, gain = 53 3, 4 0.45 0.56 0.65 V A

9.4 Minimum offset range

(FM) offset = 63, gain = 53 3, 4 -0.45 -0.57 -0.65 V A

9.5 Maximum gain range

(FM) gain = 255, offset = 31 3, 4 0.63 0.69 0.75 A

9.6 Minimum gain range

(FM) gain = 0, offset = 31 3, 4 2.1 2.16 2.23 A

10 DAC3

10.1 Output current 5 I DAC3 ±1m A C

10.2 Output voltage Bit 68-66: 000 5 V DAC3 0.4 0.55 0.7 V A 10.3 Output voltage Bit 68-66: 001 5 V DAC3 1.1 1.25 1.4 V A 10.4 Output voltage Bit 68-66: 010 5 V DAC3 1.8 1.90 2.1 V A 10.5 Output voltage Bit 68-66: 011 5 V DAC3 2.4 2.60 2.8 V A 10.6 Output voltage Bit 68-66: 100 5 V DAC3 3.2 3.30 3.5 V A 10.7 Output voltage Bit 68-66: 101 5 V DAC3 3.8 4.10 4.3 V A 10.8 Output voltage Bit 68-66: 110 5 V DAC3 4.5 4.80 5.0 V A 10.9 Output voltage Bit 68-66: 111 5 V DAC3 5.2 5.45 5.7 V A 11 3-wire Bus, ENABLE, DATA, CLOCK

11.1 Input voltage HIGH

2.7 -0.3 5.3 0.8 V V A 11.2 Clock frequency 17 1.0 MHz A

11.3 Period of CLK HIGH

11.4 Rise time EN, DAT A,

11.5 Fall time EN, DAT A,

Electrical Characteristics (Continued) Test Conditions (unless otherwise specified): VS = 8.5 V , Tamb = 25°C. No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

16 U4256BM-R

Figure 16. Application Circuit

11.6 Set-up time 16-18 t s 100 ns D

11.7 Hold time EN 18 t HEN 250 ns D

11.8 Hold time DATA 16 t HDA 0n s D

Test Conditions (unless otherwise specified): VS = 8.5 V , Tamb = 25°C.

10.25 MHz

Figure 17. Application Board Schematic

18 U4256BM-R

4562C–AUDR–08/04

Package Information

Ordering Information

Extended Type Number Package Remarks U4256BM-RFS SSO20 Tube U4256BM-RSG3 SSO20 Taped and reeled technical drawings according to DIN specifications Dimensions in mm 6.75 6.50 0.25 0.65 5.85 1.30 0.15 0.05 5.7 5.3 4.5 4.3 6.6 6.3 0.15 20 11 11 0

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