U3770M TEMIC | Alldatasheet

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Technical content

Features

/C0068Programmable 0.8/1.6 MHz quadrature modulated carrier generation /C0068More than 26 dB LO and sideband suppression /C006818.432 MHz CMOS level clock generation /C0068Supply voltage range 2.7 to 3.3 V /C0068Low power consumption, typical 12 mW /C0068SO16 package or die form Block Diagram Phase comparator DIV / 36 VCO 512 kHz

3.2 MHz

512 kHz 18.432 MHz 95 9881R Ref in 12.8 MHz VDD DGND AGND Q in QB in Iin IBin DNC 1, 15, 16

6.4 MHz

Amp. LF

14 CLK out

9 MOD out

Figure 1. Block diagram

0.8 MHz or 1.6 MHz by the PROG control pin. The typical supply voltage is 3 V @ 4 mA. is needed in the complete CT2 device. control voltage (LF pin) controls the VCO frequency. Figure 2. Pinning

3 VDD Supply voltage

4 DGND Digital ground

5 QB in Analog switches input

6 Q in Analog switches input

7 IBin Analog switches input

8 Iin Analog switches input

9 MOD out Modulator output signal

10 TST Test input, must be connected to

11 LF PLL loop filter

13 AGND Analog ground

14 CLK out Digital CMOS clock output

18.432 MHz

Rev. A2, 03-Dec-97 3 (5) Absolute Maximum Ratings Stresses at or above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in this data sheet is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Symbol Value Unit Supply voltage V DD 6 V Modulator input voltages I IB Q QB –0.5 to VDD V Reference frequency input FRef in –0.5 to VDD V Ambient temperature Tamb –40 to +85 °C Storage temperature Tstg –65 to +150 °C Junction temperature Tj Tj < Tamb +10 °C Operating Range Parameters Symbol Value Unit Supply voltage V DD 3 /C0034 10% V Ambient temperature Tamb –5 to +70 °C Junction temperature Tj Tj < Tamb +5 °C Storage temperature Tstg –40 to +125 °C

Electrical Characteristics

Test conditions (unless otherwise specified) related to test circuit V S = 3 V , VBIi, V BIi and VBQi , VBQ i = 1 VPP single ended, oscillator frequency FRef in = 12.8 MHz, Tamb = –5 to +70°C Parameters Test Conditions / PinsSymbol Min. Typ. Max. Unit Supply voltage range Pin 3 V DD 2.7 3 3.3 V Supply current Pin 3 IDD 4 mA FRef in Pin 2 Input voltage V F Ref in 150 mV PP Input impedance ZF Ref in 100 k/C0087 I, Q inputs Pins 5, 6, 7 and 8 Input voltage Single ended V Iin, Qin 1 V PP Input impedance Single ended ZIin, Qin 20 k/C0087 Input frequency FIin, Qin 18 kHz External bias voltage V IB, QB 1.5 V MOD out Pin 9 Output level 1) Unloaded V Mod out 70 mVRMS LO and sideband suppres- sion LO sub SB sub –26 dBc Output impedance ZMod out 5 k/C0087 CLK out Pin 14 Output frequency FCLK out 18.432 MHz Output voltage swing @ load = 20 pF V CLK out 1.8 V Note 1) The output signal contains some harmonics, to be filtered by an external low-pass filter

12.8 MHz

Figure 3. Test circuit

Rev. A2, 03-Dec-97 5 (5)

Package Information

We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use TEMIC products for any unintended or unauthorized application, the buyer shall indemnify TEMIC against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. TEMIC TELEFUNKEN microelectronic GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 (0)7131 67 2831, Fax number: 49 (0)7131 67 2423