U3741BM

U3741BM ATMEL | Alldatasheet

Document overview

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Technical content

Features

• Minimal External Circuitry Requirements, No RF Components on the PC Board Except Matching to the Receiver Antenna  High Sensitivity, Especially at Low Data Rates  Sensitivity Reduction Possible Even While Receiving  Fully Integrated VCO  Low Power Consumption Due to Configurable Self Polling with a Programmable Time Frame Check  Supply Voltage 4.5 V to 5.5 V  Operating Temperature Range -40°C to 105°C  Single-ended RF Input for Easy Adaptation to λ/4 Antenna or Printed Antenna on PCB  Low-cost Solution Due to High Integration Level  ESD Protection According to MIL-STD 883 (4KV HBM) Except Pin POUT (2KV HBM)  High Image Frequency Suppression due to 1 MHz IF in Conjunction with a SAW Front-end Filter – Up to 40 dB is Thereby Achievable with Newer SAWs.  Programmable Output Port for Sensitivity Selection or for Controlling External Periphery  Communication to the Microcontroller Possible via a Single, Bi-directional Data Line  Power Management (Polling) is also Possible by Means of a Separate Pin via the Microcontroller  2 Different IF Bandwidth Versions are Available (300 kHz and 600 kHz)

Description

The U3741BM is a multi-chip PLL receiver device supplied in an SO20 package. It has been specially developed for the demands of RF low-cost data transmission systems with low data rates from 1 kBaud to 10 kBaud (1 kBaud to 3.2 kBaud for FSK) in Manchester or Bi-phase code. The receiver is well suited to operate with Atmel's PLL RF transmitter U2741B. Its main applications are in the areas of telemetering, security technology and keyless-entry systems. It can be used in the frequency receiving range of f 0 = 300 MHz to 450 MHz for ASK or FSK data transmission. All the state- ments made below refer to 433.92-MHz and 315-MHz applications. UHF ASK Receiver IC U3741BM Rev. 4662B–RKE–10/04

2 U3741BM

4662B–RKE–10/04 System Block Diagram Block Diagram Demod Control U3741BM 1...3 U2741B Antenna Antenna UHF ASK/FSK Remote control transmitter UHF ASK/FSK Remote control receiver

1 Li cell

µC PLL XTO VCOLNA PLL VCOXTO Encoder ATARx9x Power amp. FSK/ASK- Demodulator and data filter IF Amp IF Amp 4th Order LPF

3 MHz

DEMOD_OUT Limiter outRSSI Sensitivity reduction Standby logic Polling circuit and control logic FE CLK VCO XTO ÷ 64 f 50 kΩ VS FSK/ASK CDEM AVCC SENS AGND DGND MIXVCC LNAGND LNA_IN DATA ENABLE TEST POUT MODE LFGND LFVCC XTO LF DVCC LNA

4662B–RKE–10/04 Pin Configuration Figure 1. Pinning SO20 SENS FSK/ASK CDEM AVCC AGND DGND MIXVCC LNAGND LNA_IN NC DATA ENABLE TEST POUT MODE DVCC XTO LFGND LF LFVCC Pin Description Pin Symbol Function

1 SENS Sensitivity-control resistor

2 FSK/ASK Selecting FSK/ASK. Low: FSK, High: ASK

3 CDEM Lower cut-off frequency data filter

4 AVCC Analog power supply

5 AGND Analog ground

6 DGND Digital ground

7 MIXVCC Power supply mixer

8 LNAGND High-frequency ground LNA and mixer

9L N A _ I N R F i n p u t

10 NC Not connected

11 LFVCC Power supply VCO

12 LF Loop filter

13 LFGND Ground VCO

14 XTO Crystal oscillator

15 DVCC Digital power supply

17 POUT Programmable output port

18 TEST Test pin, during operation at GND

19 ENABLE

Low: polling mode off (sleep mode) H: polling mode on (active mode)

20 DATA Data output/configuration input

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an LNA (low noise amplifier), LO (local oscillator), a mixer and RF amplifier. tal. According to Figure 2, the crystal should be connected to GND via a capacitor CL. of the crystal and XTO must be considered. Figure 2. PLL Peripherals

not equal to 1 MHz. f IF is then dependent on the logical level at pin MODE and on f RF. Table 1 summarizes the different conditions. works for the parameters given in the “Electrical Characteristics”. Table 1. Calculation of LO and IF Frequency

300 MHz < fRF < 365 MHz, MODE = 0

365 MHz < fRF < 450 MHz, MODE = 1

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Figure 3. Input Matching Network with SAW Filter Figure 4. Input Matching Network without SAW Filter value is not critical but must be large enough not to detune the series resonance circuit. improves the sensitivity of the receiver by about 1 dB to 2 dB.

U2741B is used. The receiver U3741BM-M3 employs an IF bandwidth of BIF = 600 kHz. signal is about 60 dB higher compared to the RF input signal at full sensitivity. In FSK mode, the S/N ratio is not affected by the dynamic range of the RSSI amplifier. strength at the output of the RSSI amplifier. ing to Figure 5 is issued at pin DATA to indicate that the receiver is still active. Figure 5. Steady L State Limited DATA Output Pattern

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4662B–RKE–10/04 FSK/ASK Demodulator and Data Filter The signal coming from the RSSI amplifier is converted into the raw data signal by the ASK/FSK demodulator. The operating mode of the demodulator is set via pin ASK/FSK. Logic 'L' sets the demodulator to FSK, Logic 'H' sets it into ASK mode. In ASK mode an automatic threshold control circuit (ATC) is employed to set the detec- tion reference voltage to a value where a good signal-to-noise ratio is achieved. This circuit also implies the effective suppression of any kind of in-band noise signals or com- peting transmitters. If the S/N ratio exceeds 10 dB, the data signal can be detected properly. The FSK demodulator is intended to be used for an FSK deviation of ∆f ≥ 20 kHz. Lower values may be used but the sensitivity of the receiver is reduced in that condition. The minimum usable deviation is dependent on the selected baud rate. In FSK mode, only BR_Range0 and BR_Range1 are available. In FSK mode, the data signal can be detected if the S/N Ratio exceeds 2 dB. The output signal of the demodulator is filtered by the data filter before it is fed into the digital signal processing circuit. The data f ilter improves the S/N ratio as its bandpass can be adopted to the characteristics of the dat a signal. The data filter consists of a 1st-order high-pass and a 1st-order low-pass filter. The high-pass filter cut-off frequency is defin ed by an external capacitor connected to pin CDEM. The cut-off frequency of the high-pass filter is defined by the following for- mula: In self-polling mode, the data filter must settle very rapidly to achieve a low current con- sumption. Therefore, CDEM cannot be increased to very high values if self polling is used. On the other hand, CDEM must be large enough to meet the data filter require- ments according to the data signal. Recommended values for CDEM are given in the “Electrical Characteristics” on page 23. T he values are slightly different for ASK and FSK mode. The cut-off frequency of the low-pass filter is defined by the selected baud rate range (BR_Range). BR_Range is defined in the OPMODE register (refer to section “Configu- ration of the Receiver” on page 17). BR_Range must be set in accordance to the used baud rate. The U3741BM is designed to operate with data coding where the DC level of the data signal is 50%. This is valid for Mancheste r and Bi-phase coding. If other modulation schemes are used, the DC level should always remain within the range of VDC_min = 33% and VDC_max = 66%. The sensitivity may be reduced by up to 1.5 dB in that condition. Each BR_Range is also defined by a minimum and a maximum edge-to-edge time (tee_sig). These limits are defined in the “Electrical Characteristics” on page 23. They should not be exceeded to maintain full sensitivity of the receiver. fcu_DF

a SAW filter is used, an insertion loss of about 4 dB must be considered. ASK mode but not in FSK mode. Figure 6. Receiving Frequency Response

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is disabled during that time. consumption, system response time, data rate etc. nected microcontroller, it can be operated by up to three uni-directional ports. operating frequency of the local oscillator (fLO). Figure 7. Generation of the Basic Clock Cycle

4662B–RKE–10/04  USA Applications (fXTO = 4.90625 MHz, MODE = L, TClk = 2.0383 µs)  Europe Applications (fXTO = 6.76438 MHz, MODE = H, TClk = 2.0697 µs)  Other applications (TClk is dependent on fXTO and on the logical state of pin MODE. The electrical characteristic is given as a function of TClk). The clock cycle of some function blocks depends on the selected baud rate range (BR_Range) which is defined in the OPMODE register. This clock cycle T XClk is defined by the following formulas for further reference: Polling Mode According to Figure 3 on page 6, the receiv er stays in polling mode in a continuous cycle of three different modes. In sleep mode, the signal processing circuitry is disabled for the time period T Sleep while consuming a low current of I S = ISoff. During the start-up period, TStartup, all signal processing circuits are enabled and settled. In the following bit check mode, the incoming data stream is analyzed bit by bit against a valid transmitter signal. If no valid signal is present, the receiver is set back to sleep mode after the period T Bitcheck. This period varies check by check as it is a statistical process. An aver- age value for T Bitcheck is given in “Electrical Characteristics” on page 23. During T Startup and TBitcheck the current consumption is I S = ISon. The average current consumption in polling mode is dependent on the duty cycle of the active mode and can be calculated as: During TSleep and TStartup, the receiver is not sensitive to a transmitter signal. To guaran- tee the reception of a transmitted command, the transmitter must start the telegram with an adequate preburst. The required length of the preburst is dependent on the polling parameters T Sleep, TStartup, TBitcheck and the startup time of a connected microcontroller (TStart,µC). TBitcheck thus depends on the actual bit rate and the number of bits (NBitcheck) to be tested. The following formula indicates how to calculate the preburst length. T Preburst ≥ TSleep + TStartup + TBitcheck + TStart_µC Sleep Mode The length of period T Sleep is defined by the 5-bit word Sleep of the OPMODE register, the extension factor XSleep, according to Figure 10 on page 13, and the basic clock cycle TClk. It is calculated to be: In US and European applications, the maximum value of TSleep is about 60 ms if XSleep is set to 1. The time resolution is about 2 ms in that case. The sleep time can be extended to almost half a second by setting X Sleep to 8. XSleep can be set to 8 by bit X SleepStd or by bit XSleepTemp resulting in a different mode of action as described below: BR_Range = BR_Range0: T XClk = 8 × TClk BR_Range1: TXClk = 4 × TClk BR_Range2: TXClk = 2 × TClk BR_Range3: TXClk = 1 × TClk ISpoll ISoff TSleep ISon TStartup TBitcheck+()×+× TSleep Sleep X Sleep× 1024× TClk×=

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XSleepStd = 1 implies the standard extension factor. The sleep time is always extended. several devices share a single data line. Figure 8. Polling Mode Flow Chart The incomming data stream is analyzed. mode. Otherwise it is set to Sleep mode. Bit-check: Depends on the result of the bit check. (NBit-checked) and on the utilized data rate. Baud1 in the OPMODE register.

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Lim_min and Lim_max are defined by a 5-bit word each within the LIMIT register. should be set to Lim_min ≥ 10. The maximum value of the upper limit is Lim_max = 63. check also fails if CV_Lim reaches Lim_max. This is illustrated in Figure 13 on page 15. Figure 11. Timing Diagram During Bit Check Figure 12. Timing Diagram for Failed Bit Check (Condition: CV_Lim < Lim_min)

Figure 13. Timing Diagram for Failed Bit Check (Condition: CV_Lim ≥ Lim_max) relevant stable time period. the receiver has switched to receiving mode.

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Figure 14. Synchronization of the Demodulator Output Figure 15. Debouncing of the Demodulator Output Figure 16. Steady L State Limited DATA Output Pattern after Transmission noise pulses is equal to or slightly higher than TDATA_min. The receiver can be set back to polling mode via pin DATA or via pin ENABLE. tor may not be exceeded to ensure proper operation.

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default configuration is highlighted for each word. is used to define the bit check limits TLim_min and TLim_max as shown in Table 4. Table 2. Effect of Bit 1 and Bit 2 in Programming the Registers Table 3. Effect of the Configuration Words within the Registers Table 4. Effect of the Configuration Word BR_Range

Table 5. Effect of the Configuration Word NBitcheck Table 6. Effect of the Configuration Bit VPOUT Table 7. Effect of the Configuration Word Sleep Table 8. Effect of the Configuration Word XSleep

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provide a mechanism to preserve the RAM register information. the supply voltage of the receiver is turned on. Table 9. Effect of the Configuration Word Lim_min Table 10. Effect of the Configuration Word Lim_max

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4662B–RKE–10/04 To start programming, the serial data line DATA is pulled to ‘L’ for the time period t1 by the microcontroller. When DATA has been released, the receiver becomes the master device. When the programming delay period t2 has elapsed, it emits 14 subsequent synchronization pulses with the pulse length t3. After each of these pulses, a program- ming window occurs. The delay until the program window starts is determined by t4, the duration is defined by t5. Within the programming window, the individual bits are set. If the microcontroller pulls down pin DATA for the time period t7 during t5, the according bit is set to ‘0’. If no programming pulse t7 is issued, this bit is set to ‘1’. All 14 bits are subsequently programmed in this way. The time frame to program a bit is defined by t6. Bit 14 is followed by the equivalent time wi ndow t9. During this window, the equivalent acknowledge pulse t8 (E_Ack) occurs if the mode word just programmed is equivalent to the mode word that was already stored in that register. E_Ack should be used to verify that the mode word was correctly transferred to the register. The register must be pro- grammed twice in that case. Programming of a register is possible both during sleep and active mode of the receiver. During programming, the LNA, LO, low-pass filter, IF-amplifier and the demodulator are disabled. The programming start pulse t1 initiates the programming of the configuration registers. If bit 1 is set to ‘1’, it represents the OFF command to set the receiver back to polling mode at the same time. For the length of the programming start pulse t1, the following convention should be considered:  t1(min) < t1 < 1535 × TClk: [t1(min) is the minimum specified value for the relevant BR_Range] Programming (respectively OFF command) is initiated if the receiver is not in reset mode. If the receiver is in reset mode, programming (respectively Off command) is not initiated, and the reset marker RM is still present at pin DATA. This period is generally used to switch the receiver to polling mode. In a reset condition, RM is not canceled by accident.  t1 > 5632 × TClk Programming (respectively OFF command) is initiated in any case. RM is cancelled if present. This period is used if the connected microcontroller detected RM. If a configura- tion register is programmed, this time period for t1 can generally be used. Note that the capacitive load at pin DATA is limited. The resulting time constant t together with an optional external pull-up resistor may not be exceeded to ensure proper operation.

4662B–RKE–10/04 Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Symbol Min. Max. Unit Supply voltage V S 6V Power dissipation P tot 450 mW Junction temperature T j 150 °C Storage temperature T stg -55 +125 °C Ambient temperature T amb -40 +105 °C Maximum input level, input matched to 50 W P in_max 10 dBm Thermal Resistance Parameters Symbol Value Unit Junction ambient R thJA 100 K/W

Electrical Characteristics

All parameters refer to GND, Tamb = -40°C to +105°C, VS = 4.5 V to 5.5 V , f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (VS = 5 V , Tamb = 25°C) Parameter Test Condition Symbol 6.76438-Mhz Osc. (Mode 1) 4.90625-Mhz Osc. (Mode 0) Variable Oscillator Basic Clock Cycle of the Digital Circuitry Basic clock cycle MODE = 0 (USA) MODE = 1 (Europe) TClk 2.0697 2.0383 1/(fXTO/10) 1/(fXTO/14) µs µs Extended basic clock cycle BR_Range0 BR_Range1 BR_Range2 BR_Range3 TXClk 16.6 8.3 4.1 2.1 16.3 8.2 4.1 2.0 × TClk 4 × TClk 2 × TClk 1 × TClk µs µs µs µs Polling Mode Sleep time Sleep and X Sleep are defined in the OPMODE register TSleep Sleep × XSleep × 1024 × 2.0697 Sleep × XSleep × 1024 × 2.0383 Sleep × XSleep × 1024 × TClk ms Start-up time BR_Range0 BR_Range1 BR_Range2 BR_Range3 TStartup 1855 1061 1061 663 1827 1045 1045 653 896.5 512.5 512.5 320.5 × TClk µs µs µs µs Time for Bit Check Average bit check time while polling BR_Range0 BR_Range1 BR_Range2 BR_Range3 T Bitcheck 0.45 0.24 0.14 0.14 0.47 0.26 0.16 0.15 ms ms ms ms Bit check time for a valid input signal f Sig NBitcheck = 0 NBitcheck = 3 NBitcheck = 6 NBitcheck = 9 TBitcheck 3/fSig 6/fSig 9/fSig 3.5/fSig 6.5/fSig 9.5/fSig 3/fSig 6/fSig 9/fSig 3.5/fSig 6.5/fSig 9.5/fSig TXClk 3.5/fSig 6.5/fSig 9.5/fSig ms ms ms ms

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4662B–RKE–10/04 Receiving Mode Intermediate frequency MODE=0 (USA) MODE=1 (Europe) fIF 1.0 1.0 fXTO × 64/314 fXTO × 64/432.92 MHz MHz Baud rate range BR_Range0 BR_Range1 BR_Range2 BR_Range3 BR_Range 1.0 1.8 3.2 5.6 1.8 3.2 5.6 10.0 1.0 1.8 3.2 5.6 1.8 3.2 5.6 10.0 BR_Range0 × 2 µs/T Clk BR_Range1 × 2 µs/TClk BR_Range2 × 2 µs/TClk BR_Range3 × 2 µs/TClk kBaud kBaud kBaud kBaud Minimum time period between edges at pin DATA (Figure 15) BR_Range0 BR_Range1 BR_Range2 BR_Range3 T DATA_min tmin1 tmin2 tmin1 tmin2 tmin1 tmin2 tmin1 tmin2 149 182 37.3 45.5 18.6 22.8 147 179 36.7 44.8 18.3 22.4 9 × T XClk 11 × TXCl 9 × TXClk 11 × TXClk 9 × TXClk 11 × TXClk 9 × TXClk 11 × TXClk µs µs µs µs µs µs µs µs Maximum low period at DATA (Figure 16) BR_Range0 BR_Range1 BR_Range2 BR_Range3 T DATA_L_max 2169 1085 542 271 2136 1068 534 267 131 × TXClk 131 × TXClk 131 × TXClk 131 × TXClk µs µs µs µs OFF command at pin ENABLE (Figure 18) t Doze 3.1 3.05 1.5 ¥ TClk µs Configuration of the Receiver Frequency of the reset marker (Figure 19) fRM 117.9 119.8 Hz Programming start pulse (Figure 17, Figure 20) BR_Range0 BR_Range1 BR_Range2 BR_Range3 after POR 2188 1104 561 290 11656 3176 3176 3176 3176 2155 1087 553 286 11479 3128 3128 3128 3128 1057 × T Clk 533 × TClk 271 × TClk 140 × TClk 5632 × TClk 1535 × TClk 1535 × TClk 1535 × TClk 1535 × TClk µs Programming delay period (Figure 17, Figure 20) t2 795 798 783 786 384.5 × TClk 385.5 × TClk µs Synchroni- zation pulse (Figure 17, Figure 20) t3 265 261 128 × T Clk µs Electrical Characteristics (Continued) All parameters refer to GND, Tamb = -40°C to +105°C, VS = 4.5 V to 5.5 V , f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (VS = 5 V , Tamb = 25°C) Parameter Test Condition Symbol 6.76438-Mhz Osc. (Mode 1) 4.90625-Mhz Osc. (Mode 0) Variable Oscillator

26 U3741BM

4662B–RKE–10/04 Maximum input level Input matched according to Figure 4, BER ≤ 10-3, ASK mode Pin_max -28 -20 dBm dBm Local Oscillator Operating frequency range VCO fVCO 299 449 MHz Phase noise VCO/LO fosc = 432.92 MHz at 1 MHz at 10 MHz L (fm) -93 -113 -90 -110 dBC/Hz dBC/Hz Spurious of the VCO at ±fXTO -55 -47 dBC VCO gain KVCO 190 MHz/V Loop bandwidth of the PLL For best LO noise (design parameter) R1 = 820 Ω C9 = 4.7 nF C10 = 1 nF BLoop 100 kHz Capacitive load at pin LF The capacitive load at pin LF is limited if bit check is used. The limitation therefore also applies to self polling. CLF_tot 10 nF XTO operating frequency XTO crystal frequency, appropriate load capacitance must be connected to XTAL

6.764375 MHz

4.90625 MHz

fXTO 6.764375 -30 ppm 4.90625 -30 ppm 6.764375 4.90625 6.764375 +30 ppm 4.90625 +30 ppm MHz MHz Series resonance resistor of the crystal fXTO = 6.764 MHz

4.906 MHz RS

Ω Ω Static capacitance of the crystal Cxto 6.5 pF Analog Signal Processing Input sensitivity ASK 300-kHz IF filter Input matched according to Figure 4 ASK (level of carrier) BER ≤ 10-3, B = 300 kHz fin = 433.92 MHz/315 MHz T = 25°C, VS = 5 V fIF = 1 MHz PRef_ASK Input sensitivity ASK 300-kHz IF filter BR_Range0 -109 -111 -113 dBm Input sensitivity ASK 300-kHz IF filter BR_Range1 -107 -109 -111 dBm Input sensitivity ASK 300-kHz IF filter BR_Range2 -106 -108 -110 dBm Input sensitivity ASK 300-kHz IF filter BR_Range3 -104 -106 -108 dBm Input sensitivity ASK 600 kHz IF filter Input matched according to Figure 4 ASK (level of carrier) BER ≤ 10-3, B = 600 kHz fin = 433.92 MHz/315 MHz T = 25°C, VS = 5 V fIF = 1 MHz PRef_ASK Electrical Characteristics (Continued) All parameters refer to GND, Tamb = -40°C to +105°C, VS = 4.5 V to 5.5 V , f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (VS = 5 V , Tamb = 25°C) Parameters Test Conditions Symbol Min. Typ. Max. Unit

4662B–RKE–10/04 Input sensitivity ASK 600 kHz IF filter BR_Range0 -108 -110 -112 dBm Input sensitivity ASK 600 kHz IF filter BR_Range1 -106.5 -108.5 -110.5 dBm Input sensitivity ASK 600 kHz IF filter BR_Range2 -106 -108 -110 dBm Input sensitivity ASK 600 kHz IF filter BR_Range3 -104 -106 -108 dBm Sensitivity variation ASK for the full operating range compared to Tamb = 25°C, VS = 5 V 300-kHz and 600-kHz version fin = 433.92 MHz/315 MHz fIF = 1 MHz PASK = PRef_ASK + ∆PRef ∆PRef +2.5 -1.5 dB Sensitivity variation ASK for full operating range including IF filter compared to T amb = 25°C, VS = 5 V 300-kHz version fin = 433.92 MHz/315 MHz fIF = 0.88 MHz to 1.12 MHz fIF = 0.85 MHz to 1.15 MHz PASK = PRef_ASK + ∆PRef ∆PRef +5.5 +7.5 -1.5 -1.5 dB dB Sensitivity variation ASK for full operating range including IF filter compared to T amb = 25°C, VS = 5 V 600-kHz version fin = 433.92 MHz/315 MHz fIF = 0.79 MHz to 1.21 MHz fIF = 0.73 MHz to 1.27 MHz PASK = PRef_ASK + ∆PRef ∆PRef +5.5 +7.5 -1.5 -1.5 dB dB Input sensitivity FSK 600 kHz IF filter Input matched according to Figure 4, BER ≤ 10-3, B = 600 kHz fin = 433.92 MHz/315 MHz T = 25°C, VS = 5 V fIF = 1 MHz PRef_FSK Input sensitivity FSK 600 kHz IF filter BR_Range0 df ≥ ±20 kHz df ≥ ±30 kHz -95.5 -96.5 -97.5 -98.5 -99.5 -100.5 dBm dBm Input sensitivity FSK 600 kHz IF filter BR_Range1 df ≥ ±20 kHz df ≥ ±30 kHz -94.5 -95.5 -96.5 -97.5 -98.5 -99.5 dBm dBm Sensitivity variation FSK for the full operating range compared to T amb = 25°C, VS = 5 V 600-kHz version fin = 433.92 MHz/315 MHz fIF = 1 MHz PFSK = PRef_FSK + ∆PRef ∆PRef +2.5 -1.5 dB Sensitivity variation FSK for full operating range including IF filter compared to T amb = 25°C, VS = 5 V 600-kHz version fin = 433.92 MHz/315 MHz fIF = 0.86 MHz to 1.14 MHz fIF = 0.82 MHz to 1.18 MHz PFSK = PRef_FSK + ∆PRef ∆PRef +5.5 +7.5 -1.5 -1.5 dB dB FSK frequency deviation The sensitivity of the receiver is higher for higher values of ∆f FSK BR_Range0 BR_Range1 BR_Range2 and BR_Range3 are not suitable for FSK operation ∆fFSK kHz kHz S/N ratio to suppress inband noise signals ASK mode FSK mode SNRASK SNRFSK dB dB Dynamic range RSSI ampl. ∆RRSSI 60 dB Electrical Characteristics (Continued) All parameters refer to GND, Tamb = -40°C to +105°C, VS = 4.5 V to 5.5 V , f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (VS = 5 V , Tamb = 25°C) Parameters Test Conditions Symbol Min. Typ. Max. Unit

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4662B–RKE–10/04 Lower cut-off frequency of the data filter fcu_DF 0.11 0.16 0.20 kHz Recommended CDEM for best performance ASK mode BR_Range0 (Default) BR_Range1 BR_Range2 BR_Range3 CDEM 8.2 nF nF nF nF Recommended CDEM for best performance FSK mode BR_Range0 (Default) BR_Range1 BR_Range2 and BR_Range3 are not suitable for FSK operation CDEM 27 nF nF Maximum edge-to-edge time period of the input data signal for full sensitivity BR_Range0 (Default) BR_Range1 BR_Range2 BR_Range3 tee_sig 1000 560 320 180 µs µs µs µs Upper cut-off frequency data filter Upper cut-off frequency programmable in 4 ranges via a serial mode word BR_Range0 (Default) BR_Range1 BR_Range2 BR_Range3 fu 2.5 4.3 7.6 13.6 3.1 5.4 9.5 17.0 3.7 6.5 11.4 20.4 kHz kHz kHz kHz Minimum edge-to-edge time period of the input data signal for full sensitivity BR_Range0 (Default) BR_Range1 BR_Range2 BR_Range3 tee_sig 270 156 µs µs µs µs Reduced sensitivity RSense connected from pin Sens to VS, input matched according to Figure 4 PRef_Red dBm (peak level) Reduced sensitivity RSense = 56 kΩ, fin = 433.92 MHz, (VS = 5 V, Tamb = 25°C) at B = 300 kHz at B = 600 kHz -71 -67 -76 -72 -81 -77 dBm dBm Reduced sensitivity RSense = 100 kΩ, fin = 433.92 MHz at B = 300 kHz at B = 600 kHz -80 -76 -85 -81 -90 -86 dBm dBm Reduced sensitivity RSense = 56 kΩ, fin = 315 MHz at B = 300 kHz at B = 600 kHz -72 -68 -77 -73 -82 -78 dBm dBm Reduced sensitivity RSense = 100 kΩ, fin = 315 MHz at B = 300 kHz at B = 600 kHz -81 -77 -86 -82 -91 -87 dBm dBm Reduced sensitivity variation over full operating range RSense = 56 kΩ RSense = 100 kΩ PRed = PRef_Red + DPRed ∆PRed dB dB Electrical Characteristics (Continued) All parameters refer to GND, Tamb = -40°C to +105°C, VS = 4.5 V to 5.5 V , f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (VS = 5 V , Tamb = 25°C) Parameters Test Conditions Symbol Min. Typ. Max. Unit fcu_DF

4662B–RKE–10/04 Reduced sensitivity variation for different values of RSense Values relative to RSense = 56 kΩ R Sense = 56 kΩ RSense = 68 kΩ RSense = 82 kΩ RSense = 100 kΩ RSense = 120 kΩ RSense = 150 kΩ PRed = PRef_Red + ∆PRed ∆PRed -3.5 -6.0 -9.0 -11.0 -13.5 dB dB dB dB dB dB Threshold voltage for reset VThRESET 1.95 2.8 3.75 V Digital Ports Data output - Saturation voltage LOW - Internal pull-up resistor - Maximum time constant - Maximum capacitive load Iol = 1 mA t = CL (Rpup//RExt) without ext. pull-up resistor Rext = 5 kΩ VOI RPup τ CL CL 0.08 0.3 2.5 540 V kΩ µs pF pF POUT output - Saturation voltage LOW - Saturation voltage HIGH IPOUT = 1 mA IPOUT = -1 mA VOl VOh VS - 0.3 V 0.08 VS - 0.14V 0.3 V V FSK/ASK input - Low-level input voltage - High-level input voltage FSK selected ASK selected VIl VIh 0.8 × VS 0.2 × VS V V ENABLE input - Low-level input voltage - High-level input voltage Idle mode Active mode VIl VIh 0.8 × VS 0.2 × VS V V MODE input - Low-level input voltage - High-level input voltage Division factor = 10 Division factor = 14 VIl VIh 0.8 × VS 0.2 × VS V V TEST input - Low-level input voltage Test input must always be set to LOW VIl 0.2 × VS V Electrical Characteristics (Continued) All parameters refer to GND, Tamb = -40°C to +105°C, VS = 4.5 V to 5.5 V , f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (VS = 5 V , Tamb = 25°C) Parameters Test Conditions Symbol Min. Typ. Max. Unit

30 U3741BM

4662B–RKE–10/04

Package Information

Ordering Information

Extended Type Number Package Remarks U3741BM-P2FL SO20 2: IF bandwidth of 300 kHz, tube U3741BM-P2FLG3 SO20 2: IF bandwidth of 300 kHz, taped and reeled U3741BM-P3FL SO20 3: IF bandwidth of 600 kHz, tube U3741BM-P3FLG3 SO20 3: IF bandwidth of 600 kHz, taped and reeled technical drawings according to DIN specifications Dimensions in mm 9.15 8.65 11.43 12.95 12.70 2.35 0.25 0.10 0.4 1.27 7.5 7.3 0.25 10.50 10.20 20 11 11 0

4662B–RKE–10/04 Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Changes from Rev. 4662A - 06/03 to Rev. 4662B - 10/04 1. Put datasheet in a new template. 2. Heading rows at Table “Absolute Maximum Ratings” added. 3. Table “Ordering Information” on page 30 changed.

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