U2794B ATMEL | Alldatasheet
Document overview
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Technical content
Features
- Supply Voltage 5 V Very Low Power Consumption 125 mW Very Good Image Rejection By Means of Phase Control Loop for Precise 90° Phase Shifting Duty-cycle Regeneration for Single-ended LO Input Signal Low LO Input Level -10 dBm LO Frequency from 70 MHz to 1 GHz Power-down Mode 25 dB Gain Control Very Low I/Q Output DC Offset Voltage Typically < 5 mV Benefits Low Current Consumption Easy to Implement Perfect Performance for Large Variety of Wireless Applications Electrostatic sensitive device. Observe precautions for handling.
Description
The silicon monolithic integrated circui t U2794B is a quadrature demodulator manu- factured using Atmel’s advanced UHF technology. This demodulator features a frequency range from 70 MHz to 1000 MHz, low current consumption, selectable gain, power-down mode and adjustment-free handling. The IC is suitable for direct conver- sion and image rejection applications in digital radio systems up to 1 GHz such as cellular radios, cordless telephones, cable TV and satellite TV systems. 1000-MHz Quadrature Demodulator U2794B Rev. 4653C–CELL–06/03
2 U2794B
Figure 1. Block Diagram Figure 2. Pinning SSO20
4653C–CELL–06/03 Pin Description Pin Symbol Function
1 IX IX output
2 I I output
3 II II lowpass filter I
4 IIX IIX lowpass filter I
9 QQ QQ lowpass filter Q
10 QQX QQX lowpass filter Q
11 GC GC gain control
12 PCX PCX phase control
13 PC PC phase control
14 PU PU power up
15 LOX
16 GND Ground
18 GND Ground
19 Q Q output
20 QX QX output
4 U2794B
4653C–CELL–06/03 Absolute Maximum Ratings Parameters Symbol Value Unit Supply voltage V S 6V Input voltage V i 0 to VS V Junction temperature T j +125 /g176C Storage-temperature range T stg -40 to +125 /g176C Thermal Resistance Parameters Symbol Value Unit Junction ambient SSO20 R thJA 140 K/W Operating Range Parameters Symbol Value Unit Supply-voltage range V S 4.75 to 5.25 V Ambient-temperature range T amb -40 to +85 /g176C
Electrical Characteristics
Test conditions (unless otherwise specified); VS = 5 V, Tamb = 25°C, referred to test circuit System impedance ZO = 50 /g87, fiLO = 950 MHz, PiLO = -10 dBm No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* 1.1 Supply-voltage range 5, 6 V S 4.75 5.25 V A
1.2 Supply current 5, 6 I S 22 30 35 mA A
2 Power-down Mode
2.1 “OFF” mode supply current V PU /g163 0.5 V VPU = 1.0 V (1) 14, 5 ISPU /g163 1 µA µA B D 3S w i t c h V o l t a g e 3.1 “Power ON” 14 V PON 4V D *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. During power-down status a load circuitry with DC-isolation to GND is assumed, otherwise a current of I /g187/g32(VS -0.8 V)/RI has to be added to the above power-down current for each output I, IX, Q, QX. 2. The required LO-Level is a function of the LO frequency (see Figure 8). 3. Measured with input matching. For 950 MHz, the optional transmission line T3 at the RF input may be used for this pur- pose. Noise figure measurements without using the differential output signal result in a worse noise figure. 4. Using Pins 7 and 8 as a symmetric RF input, the second-order IIP can be improved. 5. Due to test board parasitics, this bandwidth may be reduced and not be equal for I, IX, Q, QX. If symmetry and full band- width is required, the lowpass Pins 3, 4 and 9, 10 should be isolated from the board. the bandwidth of the I/Q outputs can be increased further by using a resistor between Pins 3, 4, 9 and 10. These resistors shunt the internal loads of RI ~ 5.4 k/g87. The decrease in gain here has to be considered. 6. The internal current of the output emitter followers is 0.6 mA. This reduces the undistorted output voltage swing at a 50 /g87 load to approsimately 30 mV. For low signal distortion the load impedance should be RI /g179 5 k/g87. 7. Referred to the level of the output vector 8. The low-gain status is achieved with an open or high-ohmic Pin 11. A recommended application circuit for switching between high and low gain status is hown in Figure 3. I2 Q2+
4653C–CELL–06/03 3.2 “Power DOWN” 14 V POFF 1V D
4 LO Input, LO in
4.1 Frequency range 17 f iLO 70 1000 MHz D
4.2 Input level (2) 17 P iLO -12 -10 -5 dBm D
4.3 Input impedance See Figure 12 17 Z iLO 50 /g87 D
4.4 Voltage standing
See Figure 5 17 VSWR LO 1.2 2 D 4.5 Duty-cycle range 17 DCR LO 0.4 0.6 D
5 RF Input, RF in
5.1 Noise figure (DSB)
at 950 MHz (3) at 100 MHz 7, 8 NF 12 dB D
5.2 Frequency range f iRF = FiLO ±/g32BWYQ 7, 8 f iRF 40 1030 MHz D
5.3 -1 dB input compression point High gain Low gain 7, 8 P 1dBHG P1dBLG +3.5 dBm D
5.4 Second order IIP (4) 7, 8 IIP 2HG 35 dBm D
5.5 Third order IIP High gain
7, 8 IIP 3HG IIP3LG +13 dBm D
5.6 LO leakage Symmetric input
7, 8 L OL /g163 -60 /g163 -55 dBm D 5.7 Input impedance see Figure 12 7, 8 Z iRF 500II0.8 /g87IIpF D 6 I/Q Outputs (I, IX, Q, QX) Emitter Follower I = 0.6 mA 6.1 3–dB bandwidth w/o external C 1, 2, 19, BWI/Q /g179 30 MHz D
6.2 I/Q amplitude error 1, 2, 19,
Ae -0.5 /g163 /g1770.2 +0.5 dB B
6.3 I/Q phase error 1, 2, 19,
Pe -3 /g163 /g1771.5 +3 Deg B Electrical Characteristics (Continued) Test conditions (unless otherwise specified); VS = 5 V, Tamb = 25°C, referred to test circuit System impedance ZO = 50 /g87, fiLO = 950 MHz, PiLO = -10 dBm No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. During power-down status a load circuitry with DC-isolation to GND is assumed, otherwise a current of I /g187/g32(VS -0.8 V)/RI has to be added to the above power-down current for each output I, IX, Q, QX. 2. The required LO-Level is a function of the LO frequency (see Figure 8). 3. Measured with input matching. For 950 MHz, the optional transmission line T3 at the RF input may be used for this pur- pose. Noise figure measurements without using the differential output signal result in a worse noise figure. 4. Using Pins 7 and 8 as a symmetric RF input, the second-order IIP can be improved. 5. Due to test board parasitics, this bandwidth may be reduced and not be equal for I, IX, Q, QX. If symmetry and full band- width is required, the lowpass Pins 3, 4 and 9, 10 should be isolated from the board. the bandwidth of the I/Q outputs can be increased further by using a resistor between Pins 3, 4, 9 and 10. These resistors shunt the internal loads of RI ~ 5.4 k/g87. The decrease in gain here has to be considered. 6. The internal current of the output emitter followers is 0.6 mA. This reduces the undistorted output voltage swing at a 50 /g87 load to approsimately 30 mV. For low signal distortion the load impedance should be RI /g179 5 k/g87. 7. Referred to the level of the output vector 8. The low-gain status is achieved with an open or high-ohmic Pin 11. A recommended application circuit for switching between high and low gain status is hown in Figure 3. I2 Q2+
6 U2794B
4653C–CELL–06/03
6.4 I/Q maximum output
Symm. output RL > 5 k/g87 1, 2, 19, VPP 2D
6.5 DC output voltage 1, 2, 19,
VOUT 2.5 2.8 3.1 V A
6.6 DC output offset
(6) 1, 2, 19, Voffset < 5 mV Test Spec.
6.7 Output impedance see Figure 12 1, 2, 19,
7 Gain Control, GC
7.1 Control range power
(7) 11 GCR GH GL dB dBm dBm D B D
7.2 Switch Voltage
7.3 “Gain high” 11 1 V 7.4 “Gain low” (8) 11 < open
7.5 Settling Time, ST
7.6 Power “OFF” - “ON” T SON < 4 µs D
7.7 Power “ON” - “OFF” T SOFF < 4 µs D
Electrical Characteristics (Continued) Test conditions (unless otherwise specified); VS = 5 V, Tamb = 25°C, referred to test circuit System impedance ZO = 50 /g87, fiLO = 950 MHz, PiLO = -10 dBm No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. During power-down status a load circuitry with DC-isolation to GND is assumed, otherwise a current of I /g187/g32(VS -0.8 V)/RI has to be added to the above power-down current for each output I, IX, Q, QX. 2. The required LO-Level is a function of the LO frequency (see Figure 8). 3. Measured with input matching. For 950 MHz, the optional transmission line T3 at the RF input may be used for this pur- pose. Noise figure measurements without using the differential output signal result in a worse noise figure. 4. Using Pins 7 and 8 as a symmetric RF input, the second-order IIP can be improved. 5. Due to test board parasitics, this bandwidth may be reduced and not be equal for I, IX, Q, QX. If symmetry and full band- width is required, the lowpass Pins 3, 4 and 9, 10 should be isolated from the board. the bandwidth of the I/Q outputs can be increased further by using a resistor between Pins 3, 4, 9 and 10. These resistors shunt the internal loads of RI ~ 5.4 k/g87. The decrease in gain here has to be considered. 6. The internal current of the output emitter followers is 0.6 mA. This reduces the undistorted output voltage swing at a 50 /g87 load to approsimately 30 mV. For low signal distortion the load impedance should be RI /g179 5 k/g87. 7. Referred to the level of the output vector 8. The low-gain status is achieved with an open or high-ohmic Pin 11. A recommended application circuit for switching between high and low gain status is hown in Figure 3. I2 Q2+
8 U2794B
Figure 5. Typical VSWR Frequency Response of the LO Input Figure 6. Noise Figure versus LO Frequency; o: Value at 950 MHz with RF Input Figure 7. Typical Suitable LO Power Range versus Frequency
10 U2794B
Figure 11. Typical Output Voltage (single ended) versus PRF at Tamb = 25°C and Figure 12. Typical S11 Frequency Response
12 U2794B
4653C–CELL–06/03 External Components Calibration Part Conversion to Single Ended Output (see data sheet of AD620) CUCC 100 nF CRFX 1 nF CLO 100 pF CNLO 1 nF CRF 100 pF CII, CQQ optional external lowpass filters T3 transmission line for RF-input matching, to connect optionally CI, CIX optional for AC-coupling at CQ, CQX baseband outputs CPDN 100 pF not connected CGC 100 pF CPC 100 pF not connected CNPC 100 pF not connected GSW gain switch CO, CS, CL 100 pF RL 50 /g87 OP1, OP2 AD620 RG1, RG2 prog. gain, see datasheet, for 5.6 k /g87 a gain of 1 at 50 /g87 is achieved together with RD1 and RD2. RD1, RD2 450 /g87 CS1, CS2 100 nF CS3, CS4 100 nF
4653C–CELL–06/03 Description of the Evaluation Board Board material: epoxy; /g101r = 4.8, thickness = 0.5 mm, transmission lines: ZO = 50 /g87 The board offers the following functions: Test circuit for the U2794B: – The supply voltage and the control inputs GC, PC and PU are connected via a plug strip. The control input voltages can be generated via external potentiometers; then the inputs should be AC-grounded (time requirements in burst mode for power up have to be considered). – The outputs I, IX, Q, QX are DC coupled via an plug strip or can be AC- connected via SMB plugs for high frequency tests e.g. noise figure or s- parameter measurement. The Pins II, IIX, QQ, QQX allow user-definable filtering with 2 external capacitors CII, CQQ. – The offsets of both channels can be adjusted with two potentimeters or resistors. – The LO- and the RF-inputs are AC-coupled and connected via SMB plugs. If transmission line T3 is connected to the RF-input and AC-grounded at the other end, gain and noise performance can be improved (input matching to /g87). – The complementary RF-input is AC-coupled to GND (CRFX = 1 nF), the same appears to the complementary LO input (CNLO = 1 nF). A calibration part which allows to calibrate an s-parameter analyzer directly to the in- and output- signal ports of the U2794B. For single-ended measurements at the demodulator outputs, two OPs (e.g., AD620 or other) can be con-figured with programmable gain; together with an output- divider network RD = 450 /g87 to RL = 50 /g87, direct measurements with 50 /g87 load impedances are possible at frequencies t < 100 kHz.
14 U2794B
4653C–CELL–06/03
Package Information
Ordering Information
Extended Type Number Package Remarks U2794B-MFS SSO20 Tube, MOQ 830 pcs U2794B-MFSG3 SSO20 Taped and reeled, MOQ 4000 pcs technical drawings according to DIN specifications Dimensions in mm 6.75 6.50 0.25 0.65 5.85 1.30 0.15 0.05 5.7 5.3 4.5 4.3 6.6 6.3 0.15 20 11 11 0
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