U2739M-B ATMEL | Alldatasheet
Document overview
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Technical content
Rev. A1, 22-May-01 1 (69) DAB One-Chip Channel- and Source Decoder
Description
The U2739M-B is an integrated circuit in advanced CMOS technology for demodulation and decoding of a DAB signal according to ETS 300 401. The channel decoder part includes the main features OFDM demodulation & decoding and time & frequency synchro- nization algorithms, using the embedded OAK DSP core. The source decoder consists of an audio and a data decoder part. The audio source decoder supports ISO MPEG 1,2 layer 2 and the data decoder offers 2 independent packet mode decoders. Several standard interfaces, like I 2C/L3, I2S, SPDIF or RDI are implemented to offer a flexible utilization. Moreover the U2739M-B includes a mechanism to replace respectively extend certain software modules by using a special boot mode (so-called USE). For example, the time & frequency synchronization modules can be replaced by down-loading the corresponding user software algorithms to the OAK DSP core. Electrostatic sensitive device. Observe precautions for handling. Block Diagram Channel decoder Audio decoder Data decoder RDI interface ADC ROM Tuner DAC I2S SPDIF V24/RS232 MC interface MCU SFCO RDI RAM U2739M–A HSSO SLI, WAGC Figure 1. Block diagram
Ordering Information
Extended Type Number Package Remarks U2739M-BFT T–PQFP–G100 Tray U2739M-BFC CQFP144 Tray
Rev. A1, 22-May-012 (69) Table of Contents
Rev. A1, 22-May-01 3 (69) Table of Contents (continued)
Rev. A1, 22-May-014 (69) Table of Contents (continued)
Rev. A1, 22-May-01 5 (69)
1 Features
1.1 General
/C0068Support of mode I, II, III and IV acc. to ETS 300 401 /C0068Time & frequency synchronization with a wide-range parameter set /C0068Optional implementation of user-defined synchro- nization strategy by using USE boot mode /C0068Flexible software configuration: set 1 – (temic kernel), set 2 – (user extension) concept /C0068Automatic mode detection (AMD) /C0068FIC on-chip memory, access via MC interface /C0068Generation of receiver status information /C0068Generation of tuner control signals /C0068Generation of pulse width modulated VCXO control signal /C0068Power supply 3.3 V , master clock 24.576 MHz /C0068Plastic TQFP100 package or /C0068Ceramic QFP144 package for software development
1.2 Channel Decoder
/C0068Demodulation and decoding of up to 64 UEP/EEP sub-channels /C0068Support of dynamic multiplex reconfiguration (DMR) without mute state /C0068Digital Null-Symbol detection (FSYNCH generation) /C0068Channel filtering (48 dB) /C0068Optional SAW filter equalization /C0068Digital AFC (freq. tolerance < 0.5 Hz for mode I) /C0068Digital AGC with a wide gain control range /C0068Off-chip de-interleaver memory for full 1.8 Mbit/s decoding data rate /C0068Time & frequency synchronization on DSP OAK core /C0068Support of TII decoding and corresponding RDI insertion (set 2)
1.3 Audio Source Decoder
/C0068Supports MPEG1 layer II streams according to ISO/ IEC 11172/3 /C0068Supports MPEG2 layer II (half sampling rate) streams according to ISO/IEC 13818–3 /C0068Supports all bit rates defined in the ETS 300 401 standard /C0068I2S and SPDIF output interfaces /C0068Programmable fader /C0068Programmable DRC /C0068PAD extraction
1.4 Data Decoder
/C00682 independent packet mode decoder /C0068Flexible configuration via MC commands /C0068Data group length limited to ~1 kbyte each /C0068Output via HSSO or V24 /C0068DD1 option: FIDC decoder /C0068Support of AIC decoding (set 2)
1.5 Interfaces
2 Functional Block Diagram
Figure 2. Functional block diagram
Rev. A1, 22-May-01 7 (69)
3 Pin Description
QFP144 QFP100 Pin Name Signal Description Pad Type Dir. 5 V Tol. 1 1 ADC_CLK ADC sampling clock output 8.192 MHz PDO04T out
2 TIN0 Test input 0 (pull down) PDDZ in x
3 TIN1 Test input 1 (pull down) PDDZ in x
4 2 ADC_DA TA9 ADC data input, bit 9 (MSB) PDIZ in x 5 3 ADC_DA TA8 ADC data input, bit 8 PDIZ in x 6 4 ADC_DA TA7 ADC data input, bit 7 PDIZ in x 7 5 ADC_DA TA6 ADC data input, bit 6 PDIZ in x
8 TIN2 Test input 2 (pull down) PDDZ in x
9 DVSSE Ground PVSS1Z, PVSS2Z gnd x
10 6 ADC_DA TA5 ADC data input, bit 5 PDIZ in x 11 7 ADC_DA TA4 ADC data input, bit 4 PDIZ in x 12 8 ADC_DA TA3 ADC data input, bit 3 PDIZ in x 13 9 ADC_DA TA2 ADC data input, bit 2 PDIZ in x
14 TIN3 Test input 3 (pull down) PDDZ in x
15 TIN4 Test input 4 (pull down) PDDZ in x
16 10 ADC_DA TA1 ADC data input, bit 1 PDIZ in x 17 11 ADC_DA TA0 ADC data input, bit 0 (LSB) PDIZ in x 18 12 DVSS1 Digital ground PVSS1Z, PVSS2Z gnd x 19 13 A VSS1 Analog ground PVSS3Z gnd x 20 14 XIN Oscillator input PDX02 osc 21 15 XOUT Oscillator output (PDX02) osc 22 16 A VDD1 Analog power supply PVDD3Z pwr 23 /C_DR C-bus data read enable PRO04T out 24 17 /RS Low active reset PDIZ in x 25 18 PWM Pulse width modulated control outputPRO04T out 26 /C_DW C-bus data write enable PRO04T out 27 19 W_AGC Window AGC PRO04T out 28 20 SLI Synchronization lock indicator PRO04T out 29 /C_PR C-bus program read enable PRO04T out 30 21 HSSO_WIN HSSO window signal PRO04T out 31 /C_PW C-bus program write enable PRO04T out 32 22 HSSO _CLK HSSO clock signal PRO04T out 33 /ABORT Low active ABORT signal (pull up) PDUZ in x 34 23 HSSO _DA T HSSO data signal PRO04T out 35 24 C_ADD0 C-bus address bit 0 (LSB) PRO04T out 36 25 C_ADD1 C-bus address bit 1 PRO04T out 37 26 /BOOT_RE BOOT read enable PRO04T out 38 27 C_ADD2 C-bus address bit 2 PRO04T out 39 28 C_ADD3 C-bus address bit 3 PRO04T out 40 29 C_ADD4 C-bus address bit 4 PRO04T out 41 30 C_ADD5 C-bus address bit 5 PRO04T out 42 31 C_ADD6 C-bus address bit 6 PRO04T out
43 TOUT0 Test output bit 0 PRO02T out
44 32 C_ADD7 C-bus address bit 7 PRO04T out
Rev. A1, 22-May-018 (69) QFP144 QFP100 Pin Name Signal Description Pad Type Dir. 5 V Tol. 45 33 C_ADD8 C-bus address bit 8 PRO04T out 46 34 C_ADD9 C-bus address bit 9 PRO04T out 47 35 C_ADD10 C-bus address bit 10 PRO04T out 48 36 C_ADD11 C-bus address bit 11 PRO04T out 49 37 C_ADD12 C-bus address bit 12 PRO04T out 50 38 DVDD1 Digital power supply PVDD1Z, PVDD2Z pwr x 51 39 C_ADD13 C-bus address bit 13 PRO04T out
52 C_ADD14 C-bus address bit 14 PRO04T out
53 C_ADD15 C-bus address bit 15 PRO04T out
54 40 C_DA TA0/DBG C-bus data bit 0 (pull down) PRD04TZ inout x 55 41 C_DA TA1/BOOT C-bus data bit 1 (pull down) PRD04TZ inout x
56 C_DA TA8 C-bus data bit 8 (pull down) PRD04TZ inout x
57 C_DA TA9 C-bus data bit 9 (pull down) PRD04TZ inout x
58 42 DVSS2 Digital ground PVSS1Z, PVSS2Z gnd x 59 43 C_DA TA2/URST C-bus data bit 2 (pull down) PRD04TZ inout x 60 44 C_DA TA3/XUSE C-bus data bit 3 (pull down) PRD04TZ inout x
61 C_DA TA10 C-bus data bit 10 (pull down) PRD04TZ inout x
62 C_DA TA11 C-bus data bit 11 (pull down) PRD04TZ inout x
63 45 C_DA TA4/PSPC C-bus data bit 4 (pull down) PRD04TZ inout x 64 46 C_DA TA5/RDI_VBIT C-bus data bit 5 (pull down) PRD04TZ inout x
65 C_DA TA12 C-bus data bit 12 (pull down) PRD04TZ inout x
66 C_DA TA13 C-bus data bit 13 (pull down) PRD04TZ inout x
67 47 C_DA TA6/XO12 C-bus data bit 6 (pull down) PRD04TZ inout x 68 48 C_DA TA7/ADE C-bus data bit 7 (pull down) PRD04TZ inout x
69 C_DA TA14 C-bus data bit 14 (pull down) PRD04TZ inout x
70 C_DA TA15 C-bus data bit 15 (pull down) PRD04TZ inout x
71 49 TEST_MODE/BYPP Test mode selection (pull down) PDDZ in x 72 50 MCM_TRIGGER MCM trigger signal PRO04T out 73 51 MC_MODE Microcontroller mode signal PDIZ in x 74 52 MC_CLK Microcontroller clock signal PDIZ in x 75 53 MC_DA T Microcontroller data signal PRB04TZ inout x
76 DVDDE Digital power supply PVDD1Z, PVDD2Z pwr x
77 54 SPDIF SPDIF output PRO04T out 78 55 RS232 RS232 output PRO04T out 79 56 I2S_CLK I2S clock output PRO04T out 80 57 I2S_DA T I2S data output PRO04T out
81 TOUT1 Test output bit 1 PRO02T out
82 58 I2S_WIN I2S win output PRO04T out
83 TOUT2 Test output bit 2 PRO02T out
84 59 TOUT3 Test output bit 3 PRO02T out 85 60 RDI_RX RDI receive data PDIZ in x 86 61 RDI_TX RDI transmit data PRO04T out 87 62 DVSS3 Digital ground PVSS1Z, PVSS2Z gnd x
88 TOUT4 Test output bit 4 PRO02T out
Rev. A1, 22-May-01 9 (69) QFP144 QFP100 Pin Name Signal Description Pad Type Dir. 5 V Tol.
89 TOUT5 Test output bit 5 PRO02T out
90 63 SFCO_SID SFCO sub-channel ID PRO04T out 91 64 SFCO_ERR SFCO errorflag PRO04T out 92 65 SFCO_DA T SFCO data PRO04T out
93 TOUT6 Test output bit 6 PRO02T out
94 66 SFCO_CLK SFCO clock PRO04T out 95 67 SFCO_WIN SFCO window PRO04T out
96 TOUT7 Test output bit 7 PRO02T out
97 68 DVDD2 Digital power supply PVDD1Z, PVDD2Z pwr x 98 69 TOUT8 Test output bit 8 PRO02T out
99 TOUT9 Test output bit 9 PRO02T out
100 70 SRAM_D7 SRAM data bit 7 PRB04TZ inout x 101 71 SRAM_D6 SRAM data bit 6 PRB04TZ inout x
102 TOUT10 Test output bit 10 PRO02T out
103 72 SRAM_D5 SRAM data bit 5 PRB04TZ inout x 104 73 SRAM_D4 SRAM data bit 4 PRB04TZ inout x
105 TOUT11 Test output bit 11 PRO02T out
106 74 SRAM_D3 SRAM data bit 3 PRB04TZ inout x 107 75 SRAM_D2 SRAM data bit 2 PRB04TZ inout x
108 TOUT12 Test output bit 12 PRO02T out
109 76 SRAM_D1 SRAM data bit 1 PRB04TZ inout x 110 77 SRAM_D0 SRAM data bit 0 PRB04TZ inout x
111 TIN5 Test input 5 (pull down) PDDZ in x
112 78 SRAM_WR SRAM write signal PRO04T out 113 79 SRAM_OE SRAM output enable PRO04T out 114 80 SRAM_A18 SRAM address bit 18 PRO04T out
115 TIN6 Test input 6 (pull down) PDDZ in x
116 81 SRAM_A17 SRAM address bit 17 PRO04T out 117 82 SRAM_A16 SRAM address bit 16 PRO04T out
118 TOUT13 Test output bit 13 PRO02T out
119 83 SRAM_A15 SRAM address bit 15 PRO04T out 120 84 SRAM_A14 SRAM address bit 14 PRO04T out 121 85 DVSS4 Digital ground PVSS1Z, PVSS2Z gnd x
122 TIN7 Test input 7 (pull down) PDDZ in x
123 86 SRAM_A13 SRAM address bit 13 PRO04T out 124 87 SRAM_A12 SRAM address bit 12 PRO04T out
125 TOUT14 Test output bit 14 PRO02T out
126 88 SRAM_A11 SRAM address bit 11 PRO04T out 127 89 SRAM_A10 SRAM address bit 10 PRO04T out
128 TOUT15 Test output bit 15 PRO02T out
129 90 SRAM_A9 SRAM address bit 9 PRO04T out 130 91 SRAM_A8 SRAM address bit 8 PRO04T out
Rev. A1, 22-May-0110 (69) QFP144 QFP100 Pin Name Signal Description Pad Type Dir. 5 V Tol.
131 TOUT16 Test output bit 16 PRO02T out
132 92 SRAM_A7 SRAM address bit 7 PRO04T out 133 93 SRAM_A6 SRAM address bit 6 PRO04T out 134 94 DVDD3 Digital power supply PVDD1Z, PVDD2Z pwr
135 TOUT17 Test output bit 17 PRO02T out
136 95 SRAM_A5 SRAM address bit 5 PRO04T out 137 96 SRAM_A4 SRAM address bit 4 PRO04T out
138 TMUX0 Test mux in bit 0 (LSB) (pull down) PDDZ in x
139 97 SRAM_A3 SRAM address bit 3 PRO04T out 140 98 SRAM_A2 SRAM address bit 2 PRO04T out
141 TMUX1 Test mix in bit 1 (pull down) PDDZ in x
142 99 SRAM_A1 SRAM address bit 1 PRO04T out 143 100 SRAM_A0 SRAM address bit 0 PRO04T out
144 TMUX2 Test mux in bit 2 (pull down) PDDZ in x
4 Strap Pins
QFP144 QFP100 Pin Name Signal Description Pad Type Dir Comment 16 10 ADC_DA TA1 ADC data input, bit 1PDIZ in Strap pin OCSEL 1 17 11 ADC_DA TA0 ADC data input, bit 0PDIZ in Strap pin OCSEL 0 54 40 C_DA TA0/DBG C-bus data bit 0 PRD04TZ inout Strap pin C_DA TA0/DBG 55 41 C_DA TA1/BOOT C-bus data bit 1 PRD04TZ inout Strap pin C_DA TA1/BOOT 59 43 C_DA TA2/URST C-bus data bit 2 PRD04TZ inout Strap pin C_DA TA2/URST 60 44 C_DA TA3/XUSE C-bus data bit 3 PRD04TZ inout Strap pin C_DA TA3/XUSE 63 45 C_DA TA4/PSPC C-bus data bit 4 PRD04TZ inout Strap pin C_DA TA4/PSPC 64 46 C_DA TA5/ RDI_VBIT C-bus data bit 5 PRD04TZ inout Strap pin C_DA TA5/RDI_VBIT 0 RDI spec.: validity bit 1 1 IEC958 spec.: validity bit 0 67 47 C_DA TA6/XO12 C-bus data bit 6 PRD04TZ inout Strap pin C_DA TA6/XO12 0 external oscillator 24.576 MHz 1 external oscillator 12.288 MHz 68 48 C_DA TA7/ADE C-bus data bit 7 ADC_DA TA strap pin function enable PRD04TZ inout Strap pin C_DA TA7/ADE
0 ADC_DA TA strap pin function disabled
1 ADC_DA TA strap pin function enabled
71 49 TEST_MODE/BYPP Test mode selection PDDZ in Strap pin TEST_MODE/BYPP
0 PLL activated
1 PLL bypassed
73 51 MC_MODE Microcontroller mode signal PDIZ in Strap pin I2C/L3
0 I2C
5 Pin Configuration
Figure 3. Production version QFP100
Figure 4. Software development version QFP144
Figure 5. Version QFP144 used as production version
6 Interface Description
6.1 Overview
offer a flexible usage of the U2739M-B. Figure 6. Functional block diagram
6.2 ADC Interface
6.2.1 ADC Interface Signal Description
QFP144 QFP100 Pin Name Signal Description Pad Type Dir. 5 V Tol.
6.2.2 ADC Interface Description
(parameter IFM) are given by the formula. “U2739M_MC_Command_set_vxxx.pdf ”]. derived inside U2739M-B. It has to be 8.192 MHz.
6.2.3 ADC Interface Timing Diagram
Figure 7. ADC interface timing diagram
6.2.4 ADC Interface Timing Parameters
Rev. A1, 22-May-0116 (69)
6.3 Tuner Interface
6.3.1 Tuner Interface Signal Description
QFP144 QFP100 Pin Name Signal Description Pad Type Dir. 5 V Tol. 27 19 W_AGC Window AGC 0 during COFDM symbols 1 during the NULL symbol PRO04T out 28 20 SLI Synchronization lock indicator 0 receiver synchronization not locked 1 receiver synchronization locked PRO04T out
6.3.2 Tuner Interface Description
In order to implement a flexible AGC concept of a DAB receiver the signals W_AGC and SLI can be used to control the tuner IC U2731B. The influence of W_AGC and SLI to the RF AGC voltage generation block is described in the U2731B preliminary datasheet. The W AGC signal must be controlled by the MC by using the set W AGC configuration MC command. The W AGC signal does not follow the moving FFT window. The rising and falling edge can be adjusted by the MC. The MC can use the differential dT, which correspond to the FFT window shift, from the read synchronization status command to adjust the W AGC rising and falling edge.
6.4 MC Interface
6.4.1 MC Interface Signal Description
QFP144 QFP100 Pin Name Signal Description Pad Type Dir. 5 V Tol. 72 50 MCM_TRIGGER MCM trigger signal PRO04T out 73 51 MC_MODE Microcontroller mode signal
0 I2C bus protocol
1 L3 bus protocol
74 52 MC_CLK Microcontroller clock signal PDIZ in x 75 53 MC_DAT Microcontroller data signal PRB04TZ inout x
6.4.2 MC Interface Description
The MC interface is used for data transmission between the U2739M-B (slave) and an external microcontroller (master). It can be configured for L3- or I2C protocol depending on the status of the MC_MODE line during reset (/RS = LOW): MC_MODE = HIGH /C0086L3 bus selected MC_MODE = LOW /C0086I2C bus selected The MCM_TRIGGER line indicates the status of the internal interface controller. The external MCU is able to communicate with the U2739M-B during LOW phases of MCM_TRIGGER only ! Further the MCM trigger signal indicates the synchro- nization status. If the MCM trigger has period of 8 ms, then the U2739M-B is not locked. In the synchronized (‘locked’) state the MCM trigger period correspond to the CIF frame, which is provided every 24 ms. The complete FIC is processed at the beginning of the transmission frame.
6.4.3 L3 Bus Interface Timing Diagram
1 Address mode
2 Data mode
3 Halt mode
Figure 8. MC L3 bus interface timing diagram
6.4.4 L3 Bus Timing Parameter
6.4.5 I2C Bus Interface Timing Diagram
Figure 9. MC I2C bus timing diagram
6.4.6 I2C Bus Timing Parameter
Rev. A1, 22-May-01 19 (69)
6.5 C-Bus / BOOT Bus Interface
6.5.1 C-Bus Signal Description
QFP144 QFP100 Pin Name Signal Description Pad Type Dir. 5 V Tol. 23 /C_DR C-bus data read enable PRO04T out 26 /C_DW C-bus data write enable PRO04T out 29 /C_PR C-bus program read enable PRO04T out 31 /C_PW C-bus program write enable PRO04T out 35 24 C_ADD0 C-bus address bit 0 (LSB) PRO04T out 36 25 C_ADD1 C-bus address bit 1 PRO04T out 37 26 /BOOT_RE BOOT read enable PRO04T out 38 27 C_ADD2 C-bus address bit 2 PRO04T out 39 28 C_ADD3 C-bus address bit 3 PRO04T out 40 29 C_ADD4 C-bus address bit 4 PRO04T out 41 30 C_ADD5 C-bus address bit 5 PRO04T out 42 31 C_ADD6 C-bus address bit 6 PRO04T out 44 32 C_ADD7 C-bus address bit 7 PRO04T out 45 33 C_ADD8 C-bus address bit 8 PRO04T out 46 34 C_ADD9 C-bus address bit 9 PRO04T out 47 35 C_ADD10 C-bus address bit 10 PRO04T out 48 36 C_ADD11 C-bus address bit 11 PRO04T out 49 37 C_ADD12 C-bus address bit 12 PRO04T out 51 39 C_ADD13 C-bus address bit 13 PRO04T out 54 40 C_DATA0/DBG C-bus data bit 0 (pull down) PRD04TZ inout x 55 41 C_DATA1/BOOT C-bus data bit 1 (pull down) PRD04TZ inout x
56 C_DATA8 C-bus data bit 8 (pull down) PRD04TZ inout x
57 C_DATA9 C-bus data bit 9 (pull down) PRD04TZ inout x
59 43 C_DATA2/URST C-bus data bit 2 (pull down) PRD04TZ inout x 60 44 C_DATA3/XUSE C-bus data bit 3 (pull down) PRD04TZ inout x
61 C_DATA10 C-bus data bit 10 (pull down)PRD04TZ inout x
62 C_DATA11 C-bus data bit 11 (pull down)PRD04TZ inout x
63 45 C_DATA4/PSPC C-bus data bit 4 (pull down) PRD04TZ inout x 64 46 C_DATA5/RDI_VBIT C-bus data bit 5 (pull down) PRD04TZ inout x
65 C_DATA12 C-bus data bit 12 (pull down)PRD04TZ inout x
66 C_DATA13 C-bus data bit 13 (pull down)PRD04TZ inout x
67 47 C_DATA6/XO12 C-bus data bit 6 (pull down) PRD04TZ inout x 68 48 C_DATA7/BYPP C-bus data bit 7 (pull down) PRD04TZ inout x
69 C_DATA14 C-bus data bit 14 (pull down)PRD04TZ inout x
70 C_DATA15 C –-bus data bit 15 (pull down)PRD04TZ inout x
6.5.2 C-Bus / BOOT Bus Interface Description
clock) to support slow devices. timing diagram refers to the BOOT bus signals only.
6.5.3 BOOT Bus Timing Diagram
Figure 10. C-bus interface timing diagram
6.5.4 BOOT Bus Timing Parameter
Rev. A1, 22-May-01 21 (69)
6.6 SRAM Interface
6.6.1 SRAM Interface Signal Description
QFP144 QFP100 Pin Name Signal Description Pad Type Dir. 5 V Tol. 100 70 SRAM_D7 SRAM data bit 7 PRB04TZ inout x 101 71 SRAM_D6 SRAM data bit 6 PRB04TZ inout x 103 72 SRAM_D5 SRAM data bit 5 PRB04TZ inout x 104 73 SRAM_D4 SRAM data bit 4 PRB04TZ inout x 106 74 SRAM_D3 SRAM data bit 3 PRB04TZ inout x 107 75 SRAM_D2 SRAM data bit 2 PRB04TZ inout x 109 76 SRAM_D1 SRAM data bit 1 PRB04TZ inout x 110 77 SRAM_D0 SRAM data bit 0 PRB04TZ inout x 112 78 SRAM_WR SRAM write signal PRO04T out 113 79 SRAM_OE SRAM output enable PRO04T out 114 80 SRAM_A18 SRAM address bit 18 PRO04T out 116 81 SRAM_A17 SRAM address bit 17 PRO04T out 117 82 SRAM_A16 SRAM address bit 16 PRO04T out 119 83 SRAM_A15 SRAM address bit 15 PRO04T out 120 84 SRAM_A14 SRAM address bit 14 PRO04T out 123 86 SRAM_A13 SRAM address bit 13 PRO04T out 124 87 SRAM_A12 SRAM address bit 12 PRO04T out 126 88 SRAM_A11 SRAM address bit 11 PRO04T out 127 89 SRAM_A10 SRAM address bit 10 PRO04T out 129 90 SRAM_A9 SRAM address bit 9 PRO04T out 130 91 SRAM_A8 SRAM address bit 8 PRO04T out 132 92 SRAM_A7 SRAM address bit 7 PRO04T out 133 93 SRAM_A6 SRAM address bit 6 PRO04T out 136 95 SRAM_A5 SRAM address bit 5 PRO04T out 137 96 SRAM_A4 SRAM address bit 4 PRO04T out 139 97 SRAM_A3 SRAM address bit 3 PRO04T out 140 98 SRAM_A2 SRAM address bit 2 PRO04T out 142 99 SRAM_A1 SRAM address bit 1 PRO04T out 143 100 SRAM_A0 SRAM address bit 0 PRO04T out
6.6.2 SRAM Interface Descriptions
For time de-interleaving and further task an external static random access memory of 4 MB is necessary. The organization of the SRAM is 512 k × 8 bit. Due to the high data rates a fast SRAM with a access time of 18 ns or below is necessary.
6.6.3 SRAM Interface Timing Diagram
Figure 11. SRAM interface timing diagram
6.6.4 SRAM Interface Timing Parameter
6.7 VCXO Interface
6.7.1 VCXO Interface Signal Description
QFP144 QFP100 Pin Name Signal Description Pad Type Dir. 5 V Tol.
6.7.2 VCXO Interface Description
49.192 MHz
Figure 12. VCXO application circuit lated output signal PWM of the U2739M-B can be used to control the VCXO frequency of 24.576 MHz.
6.8 Audio Interfaces
6.8.1 I2S Interface Signal Description
QFP144 QFP100 Pin Name Signal Description Pad Type Dir. 5 V Tol.
6.8.2 I2S Interface Description
6.8.3 I2S Interface Timing Diagram
Figure 13. I2S interface timing diagram
6.8.4 I2S Interface Timing Parameter
6.8.5 SP-DIF Interface Signal Description
QFP144 QFP100 Pin Name Signal Description Pad Type Dir. 5 V Tol.
6.8.6 SP-DIF Interface Description
audio sampling rate (48 resp. 24 kHz).
6.8.7 SP-DIF Interface Timing
Digital Audio Interface Standard].
6.8.8 SP-DIF Interface Timing Diagram
Figure 14. SP-DIF interface timing diagram
6.9 RDI Interface
6.9.1 RDI Interface Signal Description
QFP144 QFP100 Pin Name Signal Description Pad Type Dir. 5 V Tol.
6.9.2 RDI Interface Description
DAB Command Set for Receiver (DCSR)].
6.9.3 RDI Interface Timing Diagram
Figure 15. RDI interface timing diagram
Rev. A1, 22-May-0126 (69)
6.9.4 RDI Interface Timing Parameter
The RDI interface is realized according to the digital audio interface IEC958 specification [CEI/ISO 958 Digital Audio Interface Standard]. Parameter Symbol Min. Typ. Max. Unit Data high period TH 160 ns Data low period TL 160 ns
6.10 SFCO Interface
6.10.1 SFCO Interface Signal Description
QFP144 QFP100 Pin Name Signal Description Pad Type Dir. 5 V Tol. 90 63 SFCO_SID SFCO sub-channel ID PRO04T out 91 64 SFCO_ERR SFCO error flag PRO04T out 92 65 SFCO_DA T SFCO data PRO04T out 94 66 SFCO_CLK SFCO clock PRO04T out 95 67 SFCO_WIN SFCO window PRO04T out
6.10.2 SFCO Interface Description
The simple full capacity output interface (SFCO) is a 3.072 MHz burst mode interface. It consists of a window, data, errorflag and clock line. Furthermore, a serial sub- channel identifier information is provided. The interface carries fast information channel (FIC) and main service information (MSC) at the output of the COFDM channel decoder. The window line can be used to distinguish between FIC and MSC data. Via the MC interface the provided sub-channel can be selected. Only these selected sub-channels are processed by the channel decoder.
6.10.3 SFCO Interface Timing Diagram
Figure 16. SFCO interface timing diagram
6.10.4 Detailed SFCO Interface Timing Diagram
Figure 17. Detailed SFCO interface timing diagram
6.10.5 SFCO Interface Timing Parameter
6.11 RS232 Interface
6.11.1 RS232 Interface Signal Description
QFP144 QFP100 Pin Name Signal Description Pad Type Dir. 5 V Tol.
6.11.2 RS232 Interface Description
mitted followed by the low byte (LSB first both).
6.11.3 RS232 Interface Timing Diagram
Figure 18. RS232 interface timing diagram
6.11.4 RS232 Interface Timing Parameter
The RS232 timing is related to the defined baud rate of the interface.
6.12 HSSO Interface
6.12.1 HSSO Interface Signal Description
QFP144 QFP100 Pin Name Signal Description Pad Type Dir. 5 V Tol.
6.12.2 HSSO Interface Description
(as indicated in the header).
6.12.3 HSSO Interface Timing Diagram
Figure 19. HSSO interface timing diagram
6.12.4 HSSO Interface Timing Parameters
Rev. A1, 22-May-01 31 (69)
7 Electrical Characteristics
7.1 Absolute Maximum Ratings
Parameter Symbol Min. Max. Unit Supply voltage VDD –0.5 VDD + 0.5 V Input / output voltage Vin/Vout –0.5 VDD + 0.5 V Storage temperature Tstg –65 125 °C
7.2 Operating Range
Parameter Symbol Min. Typ. Max. Unit Supply voltage VDD 3.0 3.3 3.6 V Input / output voltage Vin/Vout 0 VDD V Ambient temperature Tamb –40 +85 °C Power dissipation Pstat 20 mW Power dissipation Pdyn 860 mW
7.3 DC Characteristics
Parameter Test Conditions Pad Type Symbol Min. Typ. Max. Unit Input HIGH voltage VIH 2.0 V Input LOW voltage VIL 0.8 V Threshold VT 1.4 V Output HIGH voltage IOH= –2 mA VOH Pxx02x 2.4 VDD V IOH= –4 mA Pxx04x 2.4 VDD V Output LOW voltage IOL= 2 mA VOL Pxx02x 0.2 0.4 V IOL= 4 mA Pxx04x 0.2 0.4 V
Rev. A1, 22-May-0132 (69)
8 MC Command Set
8.1 ’Set System’ Commands
8.1.1 Set DAB System Mode
Command Settings Overview: /C0068Set system mode /C0068Set FSLI control loops Command sequence: Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 0 DAB U2739M-B Write Command $6E Data Mode 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 $00 Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 0 DAB U2739M-B Write Command $6C Data Mode 7 6 5 4 3 2 1 0 SMODE NSM 0 0 0 0 0 $XX Command Parameters: Parameter Meaning Description SMODE(1..0) New DAB system mode 00: DAB system mode 4 01: DAB system mode 1 10: DAB system mode 2 11: DAB system mode 3 NSM New system mode valid 0: SMODE not valid 1: SMODE indicates new system mode
Rev. A1, 22-May-01 33 (69)
8.1.2 Set ASD
Command Settings Overview: /C0068Set ASD on/off /C0068Set ASD mute state /C0068Set ASD sub–channel ID /C0068Set ASD dynamic range control on/off /C0068Set ASD dynamic range control fixed value /C0068Set ASD ScF–CRC on/off /C0068Set ASD dual channel configuration /C0068Set ASD fader value Command sequence: Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 0 DAB U2739M-B Write Command $6E Data Mode 7 6 5 4 3 2 1 0 0 0 0 1 0 0 0 0 $10 Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 0 DAB U2739M-B Write Command $6C Data Mode 7 6 5 4 3 2 1 0 ASDE MUTE IDV DCCV FADV DRCON DRCFIX SCFON $XX FADD SBCHID $XX DCC DRCFV $XX
Rev. A1, 22-May-0134 (69) Command Parameters: Parameter Meaning Description ASDE ASD enable 0: ASD disabled 1: ASD enabled MUTE ASD mute state 0: ASD output active 1: ASD output muted IDV ASD SBCHID valid 0: Last set ASD SBCHID remains valid 1: Following ASD SBCHID valid DCCV DCC setting valid 0: Last set DCC remains valid 1: Following DCC valid FADV Fader setting valid 0: Last set FAD remains valid 1: Following FAD valid DRCON DRC on/off switch 0: DRC off 1: DRC on DRCFIX DRC additional fixed gain value valid 0: DRC additional fixed gain + 6 dB (default) 1: DRC additional fixed gain according to DRCFV SCFON ScF–CRC on/off switch 0: ScF –CRC off 1: ScF –CRC on FAD Fader value 00: Fade In / Fade out over 0 frames each 01: Fade In / Fade out over 30 frames each 10: Fade In / Fade out over 60 frames each 11: Fade In / Fade out over 90 frames each SBCHID(5..0) Sub–channel identifier n: ASD sub –channel ID DCC(1..0) Dual channel configuration 00/10: Left channel on both ASD output channels 01: Right channel on both ASD output channels 11: Both channels on ASD output DRCFV(5..0) DRC additional fixed gain value 000000: Fixed gain 0 dB 000001: Fixed gain + 0.25 dB ... (continuous steps of +0.25 dB) 111111: fixed gain + 15.75 dB
Rev. A1, 22-May-01 35 (69)
8.1.3 Set DD1
DD configuration for transmission in packet mode Command Settings Overview: /C0068Set DD1 on/off /C0068Set DD1 sub–channel ID /C0068Set DD1 packet address Command sequence: Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 0 DAB U2739M-B Write Command $6E Data Mode 7 6 5 4 3 2 1 0 0 0 0 1 0 0 0 1 $11 Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 0 DAB U2739M-B Write Command $6C Data Mode 7 6 5 4 3 2 1 0 DD1E FIDC PA1V ID1V 0 PA(9/8) $XX PA(7..0) $XX
0 SBCHID $XX
Command Parameters: Parameter Meaning Description DD1E DD1 enable 0: DD1 disabled 1: DD1 enabled FIDC FIDC decoding switch 0: DD1 decodes MSC 1: DD1 decodes FIDC PA1V PA valid 0: Last set DD1 PA remains valid 1: Following DD1 PA valid ID1V DD1 SBCHID valid 0: Last set DD1 SBCHID remains valid 1: Following DD1 SBCHID valid PA(9..0) Packet address n: DD1 packet address SBCHID(5..0) Sub–channel identifier n: DD1 sub –channel ID 1) in this case PA and SBCHID parameters are ignored (regardless of whether PA1V/ID1V have been set or not)
Rev. A1, 22-May-0136 (69)
8.1.4 Set DD2
DD configuration for transmission in packet mode Command Settings Overview: /C0068Set DD2 on/off /C0068Set DD2 AIC on/off /C0068Set DD2 sub–channel ID /C0068Set DD2 packet address Command sequence: Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 0 DAB U2739M-B Write Command $6E Data Mode 7 6 5 4 3 2 1 0 0 0 0 1 0 0 1 0 $12 Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 0 DAB U2739M-B Write Command $6C Data Mode 7 6 5 4 3 2 1 0 DD2E AIC PA2V ID2V 0 PA(9/8) $0X PA(7..0) $XX Command Parameters: Parameter Meaning Description DD2E DD2 enable 0: DD2 disabled 1: DD2 enabled AIC AIC decoding switch 0: DD2 decodes MSC 1: DD2 decodes AIC PA2V DD2 PA valid 0: Last set DD2 PA remains valid 1: Following DD2 PA valid ID2V DD2 SBCHID valid 0: Last set DD2 SBCHID remains valid 1: Following DD2 SBCHID valid PA(9..0) Packet address n: DD2 packet address SBCHID(5..0) Sub–channel identifier n: DD2 sub –channel ID 1) in this case PA and SBCHID parameters are ignored (regardless of whether PA2V/ID2V have been set or not) and the default values for AIC decoding (PA = 1023, SBCHID = 63) are used instead
Rev. A1, 22-May-01 37 (69)
8.1.5 Set CIF Counter and Occurrence Change
Command Settings Overview: /C0068Set channel decoder CIF counter /C0068Set channel decoder occurrence change Command sequence: Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 0 DAB U2739M-B Write Command $6E Data Mode 7 6 5 4 3 2 1 0 0 0 0 1 0 0 1 1 $13 Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 0 DAB U2739M-B Write Command $6C Data Mode 7 6 5 4 3 2 1 0 CF AF CIFCH(4..0) $XX CIFCL(7..0) $XX OC(7..0) $XX Command Parameters: Parameter Meaning Description CF(1..0) Change flags 00: No change 01: Sub –channel organization change 10: Service organization change 11: Sub –channel & service organization change AF Alarm flag 0: Alarm messages not accessible 1: Alarm messages accessible CIFCH(4..0) CIF counter (higher part)n: CIF counter higher part (modulo 20) CIFCL(7..0) CIF counter (lower part)n: CIF counter lower part (modulo 250) OC(7..0) Occurrence change n: V alue for CIFCL, from which the new configuration is valid
Rev. A1, 22-May-0138 (69)
8.1.6 Set Current SBCHID Long Form
Command Settings Overview: /C0068Set current sub–channel parameters (long form) Command sequence: Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 0 DAB U2739M-B Write Command $6E Data Mode 7 6 5 4 3 2 1 0 0 0 0 1 0 1 0 0 $14 Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 0 DAB U2739M-B Write Command $6C Data Mode 7 6 5 4 3 2 1 0 ON SCEFC SBCHID $XX SCU(9..2) $XX SCU(1..0) EP EPPAR CU(9..8) $XX CU(7..0) $XX
Rev. A1, 22-May-01 39 (69) Command Parameters: Parameter Meaning Description ON Sub–channel on/off switch0: Switch sub –channel off 1: Switch sub –channel on SCEFC Single sub–channel for EFC 0: Single sub –channel for EFC remains unchanged 1: Set SBCHID as single sub–channel for EFC SBCHID(5..0) sub–channel identifier n: Sub –channel ID SCU(9..0) Start CU for SBCHID n: Start CU address (0..863) EP Error Protection 0: UEP 1: EEP EPPAR(2..0) Error Protection parameters If EP = 0 (UEP): 000: Protection level P 1 001: Protection level P 2 010: Protection level P 3 011: Protection level P 4 100: Protection level P 5 If EP = 1 (EEP): 0xx: EEP long form option 0 (protection level xx–A) 00: Protection level 1–A (code rate 2/8) 01: Protection level 2–A (code rate 3/8) 10: Protection level 3–A (code rate 4/8) 11: Protection level 4–A (code rate 6/8) 1xx: EEP long form option 1 (protection level xx–B) 00: Protection level 1–B (code rate 4/9) 01: Protection level 2–B (code rate 4/7) 10: Protection level 3–B (code rate 4/6) 11: Protection level 4–B (code rate 4/5) CU(9..0) Sub–channel size (number of CU’s) n: Sub –channel size in CU’s (4..864)
Rev. A1, 22-May-0140 (69)
8.1.7 Set Next SBCHID Long Form
Command Settings Overview: /C0068Set next sub–channel parameters Command sequence: Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 0 DAB U2739M-B Write Command $6E Data Mode 7 6 5 4 3 2 1 0 0 0 0 1 0 1 0 1 $15 Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 0 DAB U2739M-B Write Command $6C Data Mode 7 6 5 4 3 2 1 0 ON SCEFC SBCHID $XX SCU(9..2) $XX SCU(1..0) EP EPPAR CU(9..8) $XX CU(7..0) $XX
Rev. A1, 22-May-01 41 (69) Command Parameters: Parameter Meaning Description ON Sub–channel on/off switch0: Switch sub –channel off 1: Switch sub –channel on SCEFC Single sub–channel for EFC 0: Single sub –channel for EFC remains unchanged 1: Set SBCHID as single sub–channel for EFC SBCHID(5..0) Sub–channel identifier n: Sub –channel ID SCU(9..0) Start CU for SBCHID n: Start CU address (0..863) EP Error Protection 0: UEP 1: EEP EPPAR(2..0) Error Protection parameters If EP = 0 (UEP): 000: Protection level P 1 001: Protection level P 2 010: Protection level P 3 011: Protection level P 4 100: Protection level P 5 If EP = 1 (EEP): 0xx: EEP long form option 0 (protection level xx–A) 00: Protection level 1–A (code rate 2/8) 01: Protection level 2–A (code rate 3/8) 10: Protection level 3–A (code rate 4/8) 11: Protection level 4–A (code rate 6/8) 1xx: EEP long form option 1 (protection level xx–B) 00: Protection level 1–B (code rate 4/9) 01: Protection level 2–B (code rate 4/7) 10: Protection level 3–B (code rate 4/6) 11: Protection level 4–B (code rate 4/5) CU(9..0) Sub–channel size (number of CU’s) n: Sub –channel size in CU’s (4..864)
Rev. A1, 22-May-0142 (69)
8.1.8 Set Current SBCHID Short Form
Command Settings Overview: /C0068Set current sub–channel parameters (short form) Command sequence: Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 0 DAB U2739M-B Write Command $6E Data Mode 7 6 5 4 3 2 1 0 0 0 0 1 0 1 1 0 $16 Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 0 DAB U2739M-B Write Command $6C Data Mode 7 6 5 4 3 2 1 0 ON SCEFC SBCHID $XX Command Parameters: Parameter Meaning Description ON Sub–channel on/off switch0: Switch sub –channel off 1: Switch sub –channel on SCEFC Single sub–channel for EFC 0: Single sub –channel for EFC remains unchanged 1: Set SBCHID as single sub–channel for EFC SBCHID(5..0) Sub–channel identifier n: Sub –channel ID
Rev. A1, 22-May-01 43 (69) 8.2 ’Set Configuration’ Commands
8.2.1 Set Global Configuration
Command Settings Overview: /C0068Set channel decoder AGC values /C0068Set channel decoder global parameters Command sequence: Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 0 DAB U2739M-B Write Command $6G Data Mode 7 6 5 4 3 2 1 0 0 0 1 0 0 0 0 0 $00 Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 0 DAB U2739M-B Write Command $6C Data Mode 7 6 5 4 3 2 1 0 AGCV 0 dB3 DSC PSC(10..8) $XX PSC(7..0) $XX CDPV IFM FSYS SAW ADCF 0 $XX Command Parameters: Parameter Meaning Description D efaults AGCV AGC values valid 0: Following DSC/PSC values ignored 1: Following DSC/PSC values valid DSC(1..0) Input data scale n: Scale value PSC(10..0) Programmable (I)FFT scale n: Scale value CDPV Channel decoder parameters valid0: Following global parameters ignored 1: Following global parameters valid IFM IF input signal mode 0: Common IF representation 1: Reverse IF representation FSYS Frame synchronization sensitivity level 00: V ery high 01: High 10: Low 11: V ery low SAW SAW filter equalization switch 0: Equalization off 1: Equalization on ADCF ADC format 0: Binary ADC input format 1: 2 ’s complement ADC input format
Rev. A1, 22-May-0144 (69)
8.2.2 Set TS Configuration
Command Settings Overview: /C0068Set TS post processing parameters Command sequence: Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 0 DAB U2739M-B Write Command $6E Data Mode 7 6 5 4 3 2 1 0 0 0 1 0 0 0 0 1 $21 Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 0 DAB U2739M-B Write Command $6C Data Mode 7 6 5 4 3 2 1 0 PARV COV PKS ISPCnt $XX TMIN $XX CIRTH $XX NSTH $XX GFCH $XX GFCL $XX
Rev. A1, 22-May-01 45 (69) Command Parameters: Parameter Meaning Description D e- faults PARV CIR post processing parameters valid (PKS / A VG / CIRTH / NSTH / TMIN) 0: Parameters not valid 1: Following parameters valid COV CIR post processing filter coefficients valid 0: Coefficients not valid 1: following coefficients valid PKS Number of peaks required for ’CIR correct’ indication 2n: Required peaks 0 ISPCnt CIR post processing average n: CIR output average over n+1 values 0 TMIN(7..0) CIR minimum dT output n: Minimum dT output after CIR post processing (* 488 ns) CIRTH(7..0) CIR threshold n.n: – Threshold value for CIR peak detection (format: 4.4 bit) – Will be multiplied by ? (standard deviation) 3.0 NSTH(7..0) Noise threshold n: – Noise threshold value (8 bit unsigned) – Will be multiplied by 32 B0(15..0) IIR filter coefficients Coefficients for 1st order IIR filter used for CIR post processing (Q15 format required) 0.5 0.5
Rev. A1, 22-May-0146 (69)
8.2.3 Set FS Configuration
Command Settings Overview: /C0068Set FS post processing parameters Command sequence: Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 0 DAB U2739M-B Write Command $6E Data Mode 7 6 5 4 3 2 1 0 0 0 1 0 0 0 1 0 $22 Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 0 DAB U2739M-B Write Command $6C Data Mode 7 6 5 4 3 2 1 0 GA $XX THA $XX GB $XX THB $XX GC $XX F2FT $XX Command Parameters: Parameter Meaning Description D efaults GA(7..0) Area A gradient n: Fractional part 0.03125 THA(7..0) Area A threshold n: Fractional part 0.03125 GB(7..0) Area B gradient n: Fractional part 0.125 THB(7..0) Area B threshold n: Fractional part 0.25 GC(7..0) Area C gradient n: Fractional part 0.5 F2FT(7..0) Max. frame–to–frame tolerancen: Maximum frequency shift in carriers (format: 3.5 bit) 1.0
Rev. A1, 22-May-01 47 (69)
8.2.4 Set XO Configuration
Command Settings Overview: /C0068Set XO control parameters Command sequence: Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 0 DAB U2739M-B Write Command $6E Data Mode 7 6 5 4 3 2 1 0 0 0 1 0 0 0 1 1 $23 Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 0 DAB U2739M-B Write Command $6C Data Mode 7 6 5 4 3 2 1 0 XO_Rough line $XX XO_Fine line $XX XOA VG 0 $XX Command Parameters: Parameter Meaning Description D efaults XO_B0(15..0) XO_B1(15..0) XO_B2(15..0) XO_A1(15..0) XO_A2(15..0) IIR filter coefficientsCoefficients for 2nd order IIR filter used for XO control 0.25 0.5 0.25 XOA VG(4..0) XO control average n: XO control average over n+1 values 0
Rev. A1, 22-May-0148 (69)
8.2.5 Set HSSO / RS232 Configuration
Command Settings Overview: /C0068Set HSSO parameters /C0068Set RS232 parameters Command sequence: Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 0 DAB U2739M-B Write Command $6E Data Mode 7 6 5 4 3 2 1 0 0 0 1 0 0 1 0 0 $00 Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 0 DAB U2739M-B Write Command $6C Data Mode 7 6 5 4 3 2 1 0 HCLK HCIRL HPAD HDD2 HDD1 HCIR $XX RSBAUD 0 RSSEL $XX Command Parameters: Parameter Meaning Description HCLK(1..0) HSSO bit clock 00: 0.768 MHz 10: 3.072 MHz 01: 1.536 MHz 11: 6.144 MHz HCIRL(1..0) HSSO CIR output length 00: N values (DAB system mode dependent) 01: N/2 1x: N/4 HPAD HSSO PAD output switch 0: No PAD output via HSSO 1: PAD output HDD2 HSSO DD2 output switch 0: No DD2 output via HSSO 1: DD2 output HDD1 HSSO DD1 output switch 0: No DD1 output via HSSO 1: DD1 output HCIR HSSO CIR output switch 0: No CIR output via HSSO 1: CIR output RSBAUD(1..0) RS232 baud rate 00: 19200 baud 10: 57600 baud 01: 38400 baud 11: 115200 baud RSSEL(1..0) RS232 output selection 00: no output 01: DD1 10: DD2 11: PAD
Rev. A1, 22-May-01 49 (69) Command Parameters: Parameter Meaning Description UFS USE FS module 0: Internal set2 XTFPR module used 1: External USE module used UFSP USE FS post processing module 0: Internal set2 module used 1: External USE module used UTSP USE TS post processing module 0: Internal set2 module used 1: External USE module used UXOC USE XO control module 0: Internal set2 module used 1: External USE module used UDD1 USE DD1 module 0: Internal set2 module used 1: External USE module used UDD2 USE DD2 module 0: Internal set2 module used 1: External USE module used UPAD USE PAD extraction module 0: Internal set2 module used 1: External USE module used UTII USE TII module 0: Internal set2 module used 1: External USE module used UAMD ... UNMI Reserved
Rev. A1, 22-May-0150 (69)
8.2.6 Set W AGC Configuration
Command Settings Overview: /C0068Set W AGC rising edge / falling edge parameters Command sequence: Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 0 DAB U2739M-B Write Command $6E Data Mode 7 6 5 4 3 2 1 0 0 0 1 0 0 1 1 0 $26 Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 0 DAB U2739M-B Write Command $6C Data Mode 7 6 5 4 3 2 1 0 WRISE(3..0) WS 0 WV $XX WRISE(11..4) $XX WFALL(1..0) WRISE(17..12) $XX WFALL(9..2) $XX WFALL(17..10) $XX Command Parameters: Parameter Meaning Description WV WAGC values valid 0: use default W AGC values 1: use following W AGC values WRISE(17..0) WAGC rising edge time marker n: value for W AGC rising edge WFALL(17..0) WAGC falling edge time marker n: value for W AGC falling edge
Rev. A1, 22-May-01 51 (69)
8.2.7 Set RCC Slot Configuration
Command Settings Overview: /C0068Set RCC slot data Command sequence: Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 0 DAB U2739M-B Write Command $6E Data Mode 7 6 5 4 3 2 1 0 0 0 1 0 0 1 1 1 $27 Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 0 DAB U2739M-B Write Command $6C Data Mode 7 6 5 4 3 2 1 0 RCC(7..0) $XX RCC(15..8) $XX RCC(23..16) $XX RCC(31..24) $XX RCC(39..32) $XX RCC(47..40) $XX RCC(55..48) $XX RCC(63..56) $XX Command Parameters: Parameter Meaning Description RCC(63..0) RCC slot data
Rev. A1, 22-May-0152 (69)
8.2.8 Set RFU
Command Settings Overview: /C0068Set RFU parameters Command sequence: Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 0 DAB U2739M-B Write Command $6E Data Mode 7 6 5 4 3 2 1 0 0 0 1 1 0 0 0 0 $30 Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 0 DAB U2739M-B Write Command $6C Data Mode 7 6 5 4 3 2 1 0 (reserved) $XX (reserved) $XX (reserved) $XX (reserved) $XX RFU4 $XX RFU5 $XX RFU6 $XX ... $XX ... $XX RFU42 $XX RFU43 $XX RFU44 $XX Command Parameters: Parameter Meaning Description (reserved) Reserved for internal use (Atmel Wireless & Microcontrollers will deliver default values, if necessary) RFU4..44 Reserved for future use
Rev. A1, 22-May-01 53 (69) 8.3 ’Read Status’ Commands
8.3.1 Read Global Status
Command Overview: /C0068Get DAB system mode /C0068Get OAK core operating mode /C0068Get synchronization status /C0068Get AGC information Command sequence: Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 1 DAB U2739M-B Write Command $6F Data Mode 7 6 5 4 3 2 1 0 0 1 0 0 0 0 0 0 $40 Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 1 DAB U2739M-B Write Command $6D Data Mode 7 6 5 4 3 2 1 0 DABMODE OAKMODE MV FSLI SLI WDSP $XX
0 CIRS CCIR CAFC $XX
0 PSLI IDSL P(8) $XX
P(7..0) $XX
Rev. A1, 22-May-0154 (69) Command Parameters: Parameter Meaning Description DABMODE(1..0) DAB system mode 00: DAB system mode 4 01: DAB system mode 1 10: DAB system mode 2 11: DAB system mode 3 OAKMODE(1..0) OAK operating mode 00: Normal stand –alone 01: USE boot mode 10: XUSE boot mode 11: HOST boot mode MV MODE_VALID line status FSLI FSLI line status SLI SLI line status CIRS CIR status 0: No CIR detected 1: CIR correct CCIR(1..0) Coded CIR status 00: |average| ? N/64 01: N/64 < |average| ? N/8 10: |average| > N/4 11: rfu. CAFC(1..0) Coded AFC status 00: |dF FRAME | ? TA 01: TA < |dFFRAME | ? TB 10: TB < |dFFRAME |< 16 kHz 11: |dF FRAME | ? 16 kHz PSLI(3..0) Precise signal level infor- mation 0000: V ery weak signal ... 1111: Very strong signal IDSL(1..0) Input data signal level 00: Weak input signal 01: Typical input signal 10: Strong input signal 11: rfu. P(8..0) Calculated in–band power WDSP Watchdog DSP Toggels every 24 ms from 0 to 1
Rev. A1, 22-May-01 55 (69)
8.3.2 Read Synchronization Status
Command Overview: /C0068Get TS control value /C0068Get FS control value Command sequence: Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 1 DAB U2739M-B Write Command $6F Data Mode 7 6 5 4 3 2 1 0 0 1 0 0 0 0 0 1 $41 Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 1 DAB U2739M-B Write Command $6D Data Mode 7 6 5 4 3 2 1 0 DT(9..2) $XX DF(15..8) $XX DF(7..0) $XX Command Parameters: Parameter Meaning Description DT(9..0) Detected time deviation n: Cycle count (signed, @2.048 MHz) 1) DF(19..0) Detected channel frequency deviation n: Deviation in carriers (signed, Q11 format) 1) Signed values refers to virtual zero at Tguard/2
Rev. A1, 22-May-0156 (69)
8.3.3 Read CIR Status
Command Overview: /C0068Get CIR post processing results 1) Command sequence: Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 1 DAB U2739M-B Write Command $6F Data Mode 7 6 5 4 3 2 1 0 0 1 0 0 0 0 1 0 $42 Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 1 DAB U2739M-B Write Command $6D Data Mode 7 6 5 4 3 2 1 0 P_FIRST(15..8) $XX P_FIRST(7..0) $XX P_AGV(15..8) $XX P_AGV(7..0) $XX P_LAST(15..8) $XX P_LAST(7..0) $XX Command Parameters: Parameter Meaning Description P_FIRST(15..0) Index of 1st CIR peak above CIR thresholdn: Cycle count (signed, @2.048 MHz) 2) P_A VG(15..0) Index of CIR average value n: Cycle count (signed, @2.048 MHz) P_LAST(15..0) Index of last CIR peak above CIR thresholdn: Cycle count (signed, @2.048 MHz) 1) If time synchronization has lost all values are set to $8000 ! 2) Signed values refers to zero at Tguard/2
Rev. A1, 22-May-01 57 (69) 8.4 ’Read Data’ Commands
8.4.1 Read ASD Header Data
Command Overview: /C0068Get MPEG audio header Command sequence: Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 1 DAB U2739M-B Write Command $6F Data Mode 7 6 5 4 3 2 1 0 0 1 0 1 0 0 0 0 $50 Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 1 DAB U2739M-B Write Command $6D Data Mode 7 6 5 4 3 2 1 0 MPG_HW1(15..8) $XX MPG_HW1(7..0) $XX MPG_HW2(15..8) $XX MPG_HW2(7..0) $XX Command Parameters: Parameter Meaning Description MPG_HW1(15..0) 1st MPEG header word Sync. word ($FFFx) expected MPG_HW2(15..0) 2nd MPEG header word MPEG stream signature
Rev. A1, 22-May-0158 (69)
8.4.2 Read X –PAD
Command Overview: /C0068Get MPEG ancillary data (X–PAD) Command sequence: Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 1 DAB U2739M-B Write Command $6F Data Mode 7 6 5 4 3 2 1 0 0 1 0 1 0 XPNUM $5X Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 1 DAB U2739M-B Write Command $6D Data Mode 7 6 5 4 3 2 1 0 X –PAD0 $XX ... X –PAD31 $XX Command Parameters: Parameter Meaning Description XPNUM X –PAD block number n (n from 1..5) The maximum X –PAD capacity supported by the U2739M-B is 64kbit/s. The access is splitted into 6 blocks (numbered 1..5) of 32 bytes. The blocks are time aligned, that means block 1 is the first block in an MPEG frame after audio samples. X –PADm X –PAD byte m Byte 0 is the first byte of block n, byte 31 the last one. It is followed by the first one of block n+1. Read RFU Use MC command “RFU ” to read block 6
Rev. A1, 22-May-01 59 (69)
8.4.3 Read F –PAD
Command Overview: /C0068Get MPEG ancillary data (F–PAD) Command sequence: Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 1 DAB U2739M-B Write Command $6F Data Mode 7 6 5 4 3 2 1 0 0 1 0 1 1 0 0 0 $58 Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 1 DAB U2739M-B Write Command $6D Data Mode 7 6 5 4 3 2 1 0 F–PAD0 $XX F–PAD1 $XX Command Parameters: Parameter Meaning Description F–PAD0 F–PAD byte 0 F–PAD1 F–PAD byte 1
Rev. A1, 22-May-0160 (69)
8.4.4 Read AIC Data
Command Overview: /C0068Get AIC data Command sequence: Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 1 DAB U2739M-B Write Command $6F Data Mode 7 6 5 4 3 2 1 0 0 1 1 0 AICNUM $6X Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 1 DAB U2739M-B Write Command $6D Data Mode 7 6 5 4 3 2 1 0 AIC0 $XX ... AIC31 $XX Command Parameters: Parameter Meaning Description AICNUM AIC block number n The maximum AIC capacity is 512 bytes. The access is splitted into 16 blocks (numbered 0..15) of 32 bytes. The blocks are time aligned, that means block 0 is the first filled block. AICm AIC byte m Byte 0 is the first byte of block n, byte 31 the last one. It is followed by the first one of block n+1.
Rev. A1, 22-May-01 61 (69)
8.4.5 Read TII Data
Command Overview: /C0068Get TII data Command sequence: Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 1 DAB U2739M-B Write Command $6F Data Mode 7 6 5 4 3 2 1 0 0 1 1 1 0 0 TIINUM $7X Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 1 DAB U2739M-B Write Command $6D Data Mode 7 6 5 4 3 2 1 0 TII0 $XX ... TII31 $XX Command Parameters: Parameter Meaning Description TIINUM TII block number n The maximum TII capacity is 128 bytes. The access is splitted into 4 blocks (numbered 0..3) of 32 bytes. The blocks are time aligned, that means block 0 is the first filled block. TIIm TII byte m Byte 0 is the first byte of block n, byte 31 the last one. It is followed by the first one of block n+1.
Rev. A1, 22-May-0162 (69)
8.4.6 Read EFC Data
Command Overview: /C0068Get EFC data Command sequence: Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 1 DAB U2739M-B Write Command $6F Data Mode 7 6 5 4 3 2 1 0 1 0 0 0 0 0 EFCSEL $8X Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 1 DAB U2739M-B Write Command $6D Data Mode 7 6 5 4 3 2 1 0 EFC(7..0) $XX EFC(15..8) $XX Command Parameters: Parameter Meaning Description EFCSEL EFC selection 00: EFC of FIC 01: EFC of all MSC applications EFC(15..0) EFC value for chosen application n: EFC value summarized over... ... 12 FIB’s (DAB mode 1) ... 3 FIB’s (DAB mode 2) ... 4 FIB’s (DAB mode 3) ... 6 FIB’s (DAB mode 4)
Rev. A1, 22-May-01 63 (69)
8.4.7 Read FIC Data
Command Overview: /C0068Get FIB bytes Command sequence: Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 1 DAB U2739M-B Write Command $6F Data Mode 7 6 5 4 3 2 1 0 1 0 0 1 FIBNUM $9X Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 1 DAB U2739M-B Write Command $6D Data Mode 7 6 5 4 3 2 1 0 FIB0 $XX ... FIB31 $XX Command Parameters: Parameter Meaning Description FIBNUM FIB number n Possible FIB numbers DAB mode dependent: 0..11 (DAB mode 1) 0..2 (DAB mode 2) 0..3 (DAB mode 3) 0..5 (DAB mode 4) FIBm FIB byte m Each FIB consists of 32 bytes. The order of the FIB bytes and bits corresponds to the serial FIC processing. That means: (1) Byte order: The first 8 output bits after FIC processing represent FIB byte 0 of FIB num- ber 0, the next ones FIB byte 1 of FIB number 0 and so on. (2) Bit order: The FIB bytes are given out MSB first. The first outgoing bit represents bit 7 of the corresponding byte, the next one bit 6 and so on. The FIB bits are num- bered from bit 0 (MSB of FIB0) up to bit 255 (LSB of FIB31). NOTE: The last 2 bytes of an FIB represent the result of the U2739M internal CRC check. That means, if these bytes are $00 both, the internal CRC check was successful and the FIB data bytes are correct.
Rev. A1, 22-May-0164 (69)
8.4.8 Read RCC Slot
Command Overview: /C0068Get RCC slot data Command sequence: Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 1 DAB U2739M-B Write Command $6F Data Mode 7 6 5 4 3 2 1 0 1 0 1 0 0 0 0 0 $A0 Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 1 DAB U2739M-B Write Command $6D Data Mode 7 6 5 4 3 2 1 0 RCC(7..0) $XX RCC(15..8) $XX RCC(23..16) $XX RCC(31..24) $XX RCC(39..32) $XX RCC(47..40) $XX RCC(55..48) $XX RCC(3..56) $XX Command Parameters: Parameter Meaning Description RCC(63..0) RCC slot data
Rev. A1, 22-May-01 65 (69)
8.4.9 Read Slot Pointer
Command Overview: /C0068Get RCC RX/TX slot pointer Command sequence: Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 1 DAB U2739M-B Write Command $6F Data Mode 7 6 5 4 3 2 1 0 1 0 1 0 0 0 0 1 $A1 Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 1 DAB U2739M-B Write Command $6D Data Mode 7 6 5 4 3 2 1 0 TXPTR RXPTR $XX Command Parameters: Parameter Meaning Description RXPTR(3..0) RCC RX slot pointer TXPTR(3..0) RCC TX slot pointer
Rev. A1, 22-May-0166 (69)
8.4.10 Read RFU
Command Overview: /C0068Get RFU data Command sequence: Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 1 DAB U2739M-B Write Command $6F Data Mode 7 6 5 4 3 2 1 0 1 0 1 1 0 0 0 0 $9X Address Mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 1 DAB U2739M-B Write Command $6D Data Mode 7 6 5 4 3 2 1 0 RFU0 $XX ... RFU43 $XX Command Parameters: Parameter Meaning Description XPAD0..31 XPAD block 6 See: read XPAD command RFU0..11 Reserved for future use
Rev. A1, 22-May-01 67 (69)
9 Package Information
Rev. A1, 22-May-0168 (69)
Rev. A1, 22-May-01 69 (69) Ozone Depleting Substances Policy Statement It is the policy of Atmel Germany GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs). The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. V arious national and international initiatives are pressing for an earlier ban on these substances. Atmel Germany GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency (EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively. Atmel Germany GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances. We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use Atmel Wireless & Microcontrollers products for any unintended or unauthorized application, the buyer shall indemnify Atmel Wireless & Microcontrollers against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. Data sheets can also be retrieved from the Internet: http://www.atmel–wm.com Atmel Germany GmbH, P .O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 (0)7131 67 2594, Fax number: 49 (0)7131 67 2423