U2731B-NFN

U2731B ATMEL | Alldatasheet

Document overview

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Technical content

Features

 8.5 V Supply Voltage  Voltage Regulator for Stable Operating Conditions  Microprocessor-controlled Via a Simple Two-wire Bus  Two Addresses Selectable  Gain-controlled RF Amplifier with Two Inputs, Selectable Via a Simple Two-wire Bus Control  Balanced RF Amplifier Inputs  Gain-controlled RF Mixer  Four-pin Voltage-controlled Oscillator  SAW Filter Driver with Differential Low-impedance Output  AGC Voltage Generation for RF Section, Available at Charge-pump Output (Can Also Be Used to Control a PIN Diode Attenuator)  Gain-controlled IF Amplifier  Balanced IF Amplifier Inputs  Selectable Gain-controlled IF Mixer  Single-ended IF Output  AGC Voltage Generation for IF Section, Available at Charge-pump Output  Separate Differential Input for the IF AGC Block  All AGC Time Constants Adjustable  AGC Thresholds Programmable Via a Simple Two-wire Bus  Three AGC Charge Pump Currents Selectable (Zero, Low, High)  Reference Oscillator  Programmable 9-bit Reference Divider  Programmable 15-bit Counter 1:2048 to 1:32767 Effectively  Tristate Phase Detector with Programmable Charge Pump  Superior Phase-noise Performance  Deactivation of Tuning Output Programmable  Three Switching Outputs (Open Collector)  Three D/A Converters (Resolution: 8 Bits)  Lock Status Indication (Open Collector) Electrostatic sensitive device. Observe precautions for handling.

Description

The U2731B is a monolithically integrat ed Digital Audio Broadcasting one-chip front end circuit manufactured using Atmel’s advanced UHF5S technology. Its functionality covers a gain-controlled RF amplifier with two selectable RF inputs, a gain-controlled RF mixer, a VCO which provides the LO signal for the RF mixers, either directly or after passing a frequency divider, a SAW filter driver, an AGC block for the RF section, a gain-controlled IF amplifier, an IF mixer which can also be bypassed, an AGC block for the IF section and a fractional-N frequency synthesizer. The frequency synthesizer controls the VCO to synthesize frequencies in the range of 70 MHz to 500 MHz in a 16-kHz raster; within certain limits the reference divider factor is fully programmable. The lock status of the phase detector is indicated at a special output pin; three switch- ing outputs can be addressed. A reference signal which is generated by an on-chip reference oscillator is available at an output pin. This reference signal is also used to generate the LO signal for the IF mixer, ei ther by doubling the frequency or by using the reference frequency itself. Three D/A converters at a resolution of 8 bits provide a digitally controllable output voltage. The thresholds inside the AGC blocks can be digi- tally controlled by means of on-chip 4-bit D/A converters. All functions of this IC are controlled via a simple two-wire bus. DAB One-chip Front End U2731B

2 U2731B

Figure 1. Block Diagram

Figure 2. Pinning

4 U2731B

4671C–DAB–06/04 Pin Description Pin Symbol Function

1 SCL Clock (simple two-wire bus)

2 SDA Data (simple two-wire bus)

3 SWA Switching output (open collector)

4 SWB Switching output (open collector)

5 FREF Reference frequency output (for U2731B)

6 SWC Switching output (open collector)

7 CAO Output of D/A converter A

8 CCO Output of D/A converter B

9 CBO Output of D/A converter C

10 GND Ground

11 GND Ground

12 RFA1 Input 1 of RF amplifier A (differential)

13 RFA2 Input 2 of RF amplifier A (differential)

14 RFB1 Input 1 of RF amplifier B (differential)

15 RFB2 Input 2 of RF amplifier B (differential)

16 CPRF Charge-pump output (RF AGC block)

17 GND Ground

18 SAW1 SAW driver output 1 (differential)

19 SAW2 SAW driver output 2 (differential)

20 VS Supply voltage RF part

21 SLI AGC mode selection (charge-pump current high)

22 WAGC AGC mode selection (charge-pump current off)

23 IFIN2 Input 2 of IF amplifier (differential)

24 IFIN1 Input 1 of IF amplifier (differential)

25 VS Supply voltage IF part

26 IFAGCIN2 Input 2 of IF AGC block (differential)

27 IFAGCIN1 Input 1 of IF AGC block (differential)

28 CPIF Charge-pump output (IF AGC block)

29 IFOUT IF output (single ended)

30 GND Ground

31 GND Ground

32 C1VC Collector 1 of VCO

33 B2VCO Base 2 of VCO

34 B1VCO Base 1 of VCO

35 C2VC Collector 2 of VCO

36 GND Ground

37 GND Ground

38 VS Supply voltage PLL

39 PD Tri-state charge pump output

40 VD Active filter output

4671C–DAB–06/04 Functional Description The U2731B represents a monolithically integrated front end IC designed for applica- tions in DAB receivers. It covers RF and IF signal processing, the PLL section and also supporting functions such as D/A converters or switching outputs. Two RF input ports offer the possibility of handling various input signals such as a down- converted L-band signal or band II and band III RF signals. The high dynamic range of the RF inputs and the use of a gain-controlled amplifier and a gain-controlled mixer in the RF section offer the possibility of handling even strong RF input signals. The LO signal of the first mixer stage is derived from an on-chip VCO. The VCO frequency is either divided by two or directly fed to the mixer. In this way band II and band III can be covered easily. In the IF section, it can be selected if the first IF signal is down-converted to a second, lower IF or if it is simply amplified to appear at the IF output. If the down-conversion option is chosen, it can be selected if the LO signal of the IF mixer is directly derived from the reference signal of the PLL, or if it is generated by doubling its frequency. The amplifiers in the IF section are gain-controlled in similar fashion to the RF section. The RF and the IF part also contain AGC functional blocks which generate the AGC control voltages. The AGC thresholds can be defined by means of three on-chip 4-bit D/A converters. The frequency of the VCO is locked to a reference frequency by an on-chip fractional-N PLL circuit which guarantees a superior phase-noise performance. The reference frequency is generated by an on-chip crystal oscillator which can also be overdriven by an external signal. Starting from a minimum value, the reference scaling factor is freely programmable. Three switching outputs can be used for various switching tasks on the front end board. Three 8-bit D/A converters providing an output voltage between 0 and 8.5 V are used to improve the tuning voltages of the tuned preselectors which are derived from the tuning voltage of the VCO.

41 PLCK Lock-indicating output (open collector)

42 OSCI Input of reference oscillator/buffer

43 OSCO Output of reference oscillator/buffer

44 ADR Address selection (simple two-wire bus)

Pin Description (Continued) Pin Symbol Function

6 U2731B

ponents stronger than -40 dBc. generation block (which is described in the following section) and an output buffer stage. M0 and M1 as indicated in the section “Simple Two-wire Bus Functions” on page 11. frequency in the range between 200 MHz to 300 MHz. is fixed by the two-wire bus bits TBi (i =1, 2, 3, 4). Table 1. Current of Charge Pump The function can be seen in Figure 11 on page 22.

to the gain-controlled IF amplifier generated by an internal gain-control circuit. the application circuit in Figure 8 on page 20. Table 2. Current of Charge Pump The function can be seen in Figure 12 on page 23.

8 U2731B

weighting function is shown in Figure 3. Figure 3. Phase-noise-weighting Function noise in the positions of such zeros is patent protected. reference signal has to be applied to the pin OSCI and the pin OSCO must be left open.

4671C–DAB–06/04 If, for example, a frequency raster of 16 kHz is requested, the scaling factor of the refer- ence divider has to be specified in such a way that the division process results in an output frequency which is four times higher than the desired frequency raster, i.e., the comparison frequency of the phase detector equals four times the frequency raster. By changing the division ratio of the main divider from N to N+1 in an appropriate way (fractional-N technique), this frequency raster is interpolated to deliver a frequency spacing of 16 kHz. So effectively a reference scaling divide factor is achieved. By setting, the two-wire bus bit T, a test signal representing the divided input signal can be monitored at the switching output SWA. Main Divider The main divider consists of a fully programmable 13-bit divider which defines a division ratio N. The applied division ratio is either N or N+1 according to the control of a special control unit. On average, the scaling factors SF = N + k/4 can be selected where k = 0, 1, 2 or 3. In this way, VCO frequencies f VCO = 4 × (N+k/4) × fref/(4 × SFref) can be synthesized starting from a reference frequency fref. If we define SF eff = 4 × N + k and SFref,eff =4 × SFref (previous section), then f VCO = SF eff × fref/SFref,eff , where SF eff is defined by 15 bits. In the following, this circuit is described in terms of SFeff and SFref,eff. SFeff has to be pro- grammed via the two-wire bus interface. An effective scaling factor from 2048 to 32767 can be selected by means of the two-wire bus bits ni (i = 0, ..., 14) according to By setting the two-wire bus bit T, a test signal representing the divided input signal can be monitored at the switching output SWC. When the supply voltage is switched on, both the reference divider and the programma- ble divider are kept in RESET state until a complete scaling factor is written onto the chip. Changes in the setting of the programmable divider become active when the corre- sponding two-wire bus transmission is co mpleted. An internal synchronization procedure ensures that such changes do not become active while the charge pump is sourcing or sinking current at its output pin. This behavior allows a smooth tuning of the output frequency without restricting the controlled VCO's frequency spectrum. Phase Comparator and Charge Pump The tri-state phase detector causes the charge pump to source or to sink current at the output Pin PD depending on the phase relation of its input signals which are provided by the reference and the main divider respectively. Four different values of this current can be selected by means of the two-wire bus bits I50 and I100. By use of this option, changes of the loop characteristics due to the variation of the VCO gain as a function of the tuning voltage can be reduced. The charge-pump current can be switched off using the two-wire bus bit TRI. A change in the setting of the charge pump current becomes active when the corresponding two-wire bus transmission is completed. As described for the setting of the scaling factor of the programmable divider, an internal synchronization procedure ensures that such changes do not become active while the charge pump is sourcing or sinking current at its output pin. This behavior allows a change in the charge pump current without restricting the controlled VCO's frequency spectrum. SFref,eff 4r i∑× 2i×= SFeff ni∑ 2i×=

10 U2731B

4671C–DAB–06/04 A high-gain amplifier (output pin: VD), which is implemented in order to construct a loop filter, as shown in the application circuit, c an be switched off by means of the two-wire bus bit OS. An internal lock detector checks if the phase difference of the input signals of the phase detector is smaller than approximately 250 ns in seven subsequent comparisons. If phase lock is detected, the open collector output pin PLCK is set to H (logical value). It should be noted that the output current of this pin must be limited by external circuitry as it is not limited internally. If the two-wire bus bit TRI is set to H, the lock detector function is deactivated and the logical value of the PLCK output is undefined. Switching Outputs Three switching outputs controlled by the two-wire bus bits SWA, SWB, SWC can be used for any switching task on the front-end board. The currents of these outputs are not limited internally. They have to be limited by an external circuit. D/A Converters Three D/A converters, A, B and C, offer the possibility of generating three output volt- ages at a resolution of 8 bits. These voltages appear at the output pins CAO, CBO and CCO. The converters are controlled via the two-wire bus interface by means of the con- section “Two-wire Bus Instruction Codes”. The output voltages are defined as where VM = 4.25 V nominally. Due to the rail-to-rail outputs of these converters, almost the full voltage range from 0 to 8.5 V can be used. A common application of these converters is the digital synthesis of cont rol signals for the tuning of preselectors. The output pins CAU, CBO and CCO must be blocked externally with capacitors (100 nF) as shown in the application circuit (see Figure 8 on page 20). VCAO VM j = 0 ∑ 2j××= VCBO VM j = 0 ∑ 2j××= VCCO VM j = 0 ∑ 2j××=

Via its two-wire bus interface, various functions can be controlled by a microprocessor. are explained, Figure 7 on page 20 shows a typical two-wire bus pulse diagram. Table 3. Simple Two-wire Bus Instruction Codes SWA (reference divider) and SWC (programmable divider).

12 U2731B

Table 4. Current of Charge Pump Table 5. Mode Selection before the current triplet is finished. START - ADR - ACK - DB1 - ACK - CB1 -ACK - STOP is not allowed.

14 U2731B

4671C–DAB–06/04 Absolute Maximum Ratings Parameters Symbol Min. Max. Unit Supply voltage V S -0.3 +9.5 V Junction temperature T j 150 ° C Storage temperature T stg -40 +150 ° C Differential input RF amplifier, pins 12 and 13 V RFA1,2 500 mV rms Pins 14 and 15 V RFB1,2 500 mV rms Externally applied voltage at RF charge pump output, pin 16 V CPRF 0.5 6.75 V Pin 28 V CPIF 0.5 6.25 V WAGC input voltage, pin 22 V WAGC -0.3 5.5 V SLI input voltage, pin 21 V SLI -0.3 5.5 V Differential base input VCO, pins 33 and 34 V BiVC 500 mV rms Differential input IF amplifier, pins 23 and 24 V IFIN 500 mV rms Differential input IF AGC block, pins 26 and 27 V IFAGCIN 500 mV rms Reference input voltage (AC), pin 42 V OSCI 1V pp Two-wire bus input/output voltage, pins 1 and 2 SCL, SDA -0.3 5.5 V SDA output current, pin 2 SDA 5 mA Address select voltage, pin 44 ADR -0.3 5.5 V Switch output voltage; pins 3, 4 and 6 SW α -0.3 9.5 V Switch output current SW α 4m A PLCK output voltage, pin 41 PLCK -0.3 5.5 V PLCK output current, pin 41 PLCK 0.5 mA Thermal Resistance Parameters Symbol Value Unit Junction ambient (soldered on application board) R thJA 40 K/W Operating Range Parameters Symbol Value Unit Supply voltage V S 8.0 to 9.35 V Ambient temperature range T amb -40 to +85 ° C

4671C–DAB–06/04

Electrical Characteristics

Test conditions (unless otherwise specified): VS = 8.5 V, Tamb = 25°C No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*

1 Overall Characteristics 20, 25, 38

1.1 Supply voltage VS 8.0 8.5 9.35 V

1.2 Minimum supply current

V(CPRF) = V(CPIF) < 0.8 V M3 = M2 = HIGH M1 = M0 = LOW TAi = TCi = 0000; TBi = 1000 SWA = SWB = SWC = LOW TRI = LOW; PLCK = LOW I100 = I50 = LOW; V(ADR) = open SLI = LOW; WAGC = HIGH IS,min 74 mA B

1.3 Maximum supply

3 . 4V<V ( C P R F )=V ( C P I F ) <3 . 6V ; M 3=M 2=H I G H M1 = M0 = LOW TAi = TCi = 0000; TBi = 1000 SWA = LOW; SWB = LOW SWC = LOW; TRI = LOW PLCK = LOW; I100 = I50 = LOW V(ADR) = open; SLI = LOW WAGC = HIGH IS,max 79 mA B

2 RF Part

2.1 Voltage gain

RFA1, RFA2; RFB1, RFB2) → SAW1, SAW2 (see Figure 9 on page 21) 12 (14) → 18, 19 GV, RF 20 24 26 dB A

2.2 AGC range RF 23 27 29 dB A

2.3 Noise figure

(double side band) RFA1, (RFB1) → SAW1, SAW2; RFA2, RFB2 blocked 12 (14) → 19 NFDSB,RF 12 dB D

2.4 Maximum input power

Differential, 3rd order intermodulation distance ≥ 40 dBc, Pout = -19 dBm, TAi = 0000, RL (SAW1, SAW2) = 200 Ω 12, 13 (14, 15) Pin,max,MIX -10 dBm A

2.5 Input frequency range 12, 13

(14, 15) fin,RF 70 260 MHz B 2.6 Input impedance Single ended 12 (14) Zin,RF 1.3 kΩ D 2.7 Output frequency range for AGC-voltage generation 18, 19 fout,SAW 38,912 ±5 MHz D

2.8 Maximum output power

Output power, differential; RL (SAW1, SAW2) > 200 Ω, TAi = 0000 18, 19 -7 dBm D 2.9 AGC threshold (th1) TAi = ‘1000’ TAi = ‘1111’ TAi = ‘0000’ Output power, differential controlled by two-wire bus bits T Ai; RL (SAW1, SAW2) = 200 Ω 18, 19 pTH,RF 50 90 160 120 mVrms A B B *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. The phase detector’s phase-noise contribution to the VCO’s frequency spectrum is determined by the operating frequency of the phase detector divided by 4 according to the fractional-N technique (regularly: 16 kHz).

16 U2731B

4671C–DAB–06/04 2.10 AGC threshold (th2) (internal AGC) upper limit (TBi = 1111) lower limit (TBi = 0000) Controlled by two-wire bus bits TBi; PIN,MAX = -25 dBm 16 Vint AGC,RF 1.0 5.1 1.5 1.8 V V B A

2.11 Output impedance Single ended; f(SAW1) = 39 MHz 18 (19) Zout,SAW 30 Ω

3 VCO

3.1 Phase noise ∆f = 10 kHz L(f) -88 dBc/Hz D

3.2 Phase noise fLO 100 400 MHz D

4 IF Part

4.1 Voltage gain

(see Figure 9 on page 21) f LO,IFMIX = fref or FLO,IFMIX = 2 × fref 24 → 29 GV,tot 42 44 48 dB A

4.2 Voltage gain

(see Figure 9 on page 21) IF mixer switched off 24 → 29 GV,tot 45 47 51 dB A

4.3 AGC range IF 42 44 48 dB A

4.4 Noise figure

(double side band) IFIN2 blocked 24 → 29 NFDSB 11 dB D

4.5 Maximum input power

IFIN2 blocked, 3rd order intermodulation distance ≥ 40 dBc; RL(IFOUT) = 1 k; TCi = 0000; R 10 = 4.7 k, R11 = 1.8 k

24 Pin,max -20 dBm C

4.6 Input frequency range 23, 24 fin,IFIN 10 60 MHz D

4.7 Input impedance IFIN2 blocked, fIF ,IFIN = 38.912 MHz 23, 24 Zin,IFIN 600 - j1000 Ω D

4.8 Output frequency range Single ended 29 fout,IFO 1 45 MHz D

4.9 Output impedance

fout,IFO (3 MHz) fout,IFO (20 MHz) fout,IFO (38.9 MHz)

29 Zout,IFOUT

Ω Ω Ω D

5 RF AGC Unit

5.1 Positive charge pump

current, fast mode VWAGC = LOW VSLI = HIGH 16 ICPRFPOS,FM 145 180 220 µA A

5.2 Negative charge pump

current, fast mode V WAGC = LOW VSLI = HIGH 16 ICPRFNEG,FM -220 -180 -145 µA A

5.3 Positive charge pump

current, slow mode VWAGC = LOW VSLI = LOW 16 ICPRFPOS,SM 30 40 52 µA A

5.4 Negative charge pump

current, fast mode VWAGC = LOW VSLI = LOW 16 ICPRFNEG,FM -52 -40 -30 µA A

5.5 Minimum gain control

VAGCmin 0.75 V C Electrical Characteristics (Continued) Test conditions (unless otherwise specified): VS = 8.5 V, Tamb = 25°C No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. The phase detector’s phase-noise contribution to the VCO’s frequency spectrum is determined by the operating frequency of the phase detector divided by 4 according to the fractional-N technique (regularly: 16 kHz).

4671C–DAB–06/04

5.6 Maximum gain control

voltage VAGCmax 6.6 V C

6 IF AGC Unit

6.1 Positive charge pump

current, fast mode VWAGC = LOW VSLI = HIGH 28 ICPIFPOS,FM 145 180 220 µA A

6.2 Negative charge pump

current, fast mode VWAGC = LOW VSLI = HIGH 28 ICPIFNEG, FM -220 -180 -145 µA A

6.3 Positive charge pump

current, slow mode VWAGC = LOW VSLI = LOW 28 ICPIFPOS, SM 30 40 52 µA A

6.4 Negative charge pump

current, slow mode VWAGC = LOW VSLI = LOW 28 ICPIFNEG, SM -52 -40 -30 µA A

6.5 Window AGC mode

charge pump current VWAGC = HIGH 28 ICPIFWAGC -4 0 +4 µA A

6.6 Minimum gain control

voltage 28 VAGCIFmin 0.75 V C

6.7 Maximum gain control

28 VAGCIFmax 5.9 V C

6.8 Control voltage for

activated WAGC WAGC = HIGH 22 VWAGCHigh 2.0 V A

6.9 Control voltage for

deactivated WAGC WAGC = LOW 22 VWAGCLow 0.7 V A

6.10 Control voltage for

SLI = HIGH 21 VSLIHigh 2.0 V A

6.11 Control voltage for

SLI = LOW 21 VSLILow 0.7 A

7 PLL Part

7.1 Effective scaling factor of programmable divider SFeff 2048 32766 D

7.2 Effective scaling factor

SFref,eff 144 2047 D

7.3 Tuning step 16 kHz D

8 REF Input 42

8.1 Input frequency range Internal oscillator overdriven fref 5 30 MHz B

8.2 Input sensitivity Internal oscillator overdriven vref,min 50 mVrms A

8.3 Maximum input signal Internal oscillator overdriven vref,max 300 mVrms D

8.4 Input impedance Single ended Zref 2 || 2.5 kΩ/pF D

9 REF Output 5

9.1 Output voltage 1.5 kΩ || 2.5 pF load vout,ref 65 100 mVrms A Electrical Characteristics (Continued) Test conditions (unless otherwise specified): VS = 8.5 V, Tamb = 25°C No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. The phase detector’s phase-noise contribution to the VCO’s frequency spectrum is determined by the operating frequency of the phase detector divided by 4 according to the fractional-N technique (regularly: 16 kHz).

18 U2731B

4671C–DAB–06/04

10 Phase Detector 39

10.1 Charge-pump current I100 = HIGH, I50 = HIGH 160 200 240 µA A

10.2 I100 = HIGH, I50 = LOW 120 150 180 µA A

10.3 I100 = LOW, I50 = HIGH 80 100 120 µA A

10.4 I100 = LOW, I50 = LOW 35 50 65 µA A

10.5 High impedance mode TRI = HIGH IPD,tri -100 100 nA A

10.6 Effective phase noise(1) IPD = 203 mA LPD -159 dBc/

11 Lock Indication 41

11.1 Leakage current V PLCK = 5.5 V IPLCK,L 10 µA A 11.2 Saturation voltage I PLCK = 0.25 mA VPLCK,sat 0.5 V A

12 Switches 3, 4, 6

12.1 Leakage current ISW,L 10 µA A

12.2 Saturation voltage I SW = 0.25 mA VSW,sat 0.5 V A

13 Address Selection 44

13.1 AS1 = 0 0 0.1 VS C 13.2 AS1 = 1 0.4 VS

0.6 VS C

14 D/A Converters 7, 8, 9

14.1 Output voltage

Cα7 = HIGH Cα0 to Cα6 = LOW α = A, B, C VM 4.05 4.25 4.45 V A 14.2 Variation of VM VS = 8.00 to 9.35 V ∆VM,VS -50 50 mV A

14.3 Variation of VM Tamb = -40 to +85° C ∆VM,temp ±20 mV C

14.4 Accuracy VCαn-n VM/128

n = 24 ... 232, α = A, B, C ∆VCαn -70 70 mV A

14.5 Maximum output

20 µA C

15 Simple Two-wire Bus 1, 2

15.1 Input voltage SCL/SDA HIGH 3 5.5 V D 15.2 Input voltage SCL/SDA LOW 1.5 V D

15.3 Output voltage SDA

(open collector) ISDA = 2 mA, SDA = LOW 0.4 V D 15.4 SCL clock frequency 0.1 100 kHz D

15.5 Rise time (SCL, SDA) tr 1 µs D

15.6 Fall time (SCL; SDA) tf 300 µs D

15.7 Time before new

tbuf 4.7 µs D Electrical Characteristics (Continued) Test conditions (unless otherwise specified): VS = 8.5 V, Tamb = 25°C No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. The phase detector’s phase-noise contribution to the VCO’s frequency spectrum is determined by the operating frequency of the phase detector divided by 4 according to the fractional-N technique (regularly: 16 kHz). IPD4 IPD3 IPD2 IPD1

Figure 6. Application Circuit

15.8 SCL HIGH period thigh 4 µs D

15.10 Hold time ST ART thdsta 4 µs D

15.13 Hold time DAT A thddat 0 µs D

15.14 Setup time DATA tsudat 250 ns D

of the phase detector divided by 4 according to the fractional-N technique (regularly: 16 kHz).

16.384 MHz

20 U2731B

Figure 7. Oscillator Operation Figure 8. Oscillator Overdriven

Figure 9. Measurement Circuit for Electrical Characteristics

22 U2731B

Figure 10. RFAGC Voltage-generation Block Circuit Figure 11. IFAGC Voltage-generation Block Circuit

24 U2731B

4671C–DAB–06/04

Package Information

Ordering Information

Extended Type Number Package Remarks U2731B–NFN SSO44 Tube U2731B–NFNG1 SSO44 Taped and reeled technical drawings according to DIN specifications Dimensions in mm 0.25 0.10 0.3 0.8 18.05 17.80 16.8 2.35 9.15 8.65 7.50 7.30 10.50 10.20 0.25 44 23 1 22

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