U2730B-N ATMEL | Alldatasheet
Document overview
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Technical content
Features
Supply Voltage: 8.5 V RF Frequency Range: 1400 MHz to 1550 MHz IF Frequency Range: 150 MHz to 250 MHz Enhanced IM3 Rejection Overall Gain Control Range: 30 dB Typically DSB Noise Figure: 10 dB Gain-controlled Amplifier and L-band Mixer Power-down Function for the Analog Part On-chip Gain-control Circuitry On-chip VCO, Typical Frequency 1261.568 MHz Internal VCO Can Be Overdriven by an External LO On-chip Frequency Synthesizer – Fixed LO Divider Factor: 2464 – Nine Selectable Reference Divider Factors : 32, 33, 35, 36, 48, 49, 63, 64, 65 – A Reference Oscillator (Can Be Overdriven by an External Reference Signal) – Tristate Phase Detector with Programmable Charge Pump – Programmable Deactivation of Tuning Output – Lock-status Indication – Test Interface Electrostatic sensitive device. Observe precautions for handling.
Description
The U2730B-N is a monolithically integrated L-band down-converter circuit fabricated with Atmel’s advanced UHF5S technology. This IC covers all functions of an L-band down-converter in a DAB receiver. The device includes a gain-controlled amplifier, a gain-controlled mixer, an output buffer, a gain control block, a power save function for the analog part, an L-band oscillator and a complete frequency syntheziser unit. The frequency syntheziser block consists of a reference oscillator/buffer, a reference divider, an RF divider, a tri-state phase detector, a loop filter amplifier, a lock detector, a programmable charge pump, a test interface and a control interface. L-band Down-converter for DAB Receivers U2730B-N Preliminary
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Figure 1. Block Diagram
Figure 2. Pinning SSO28
13 OSCE
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4719A–DAB–05/03 Pin Description Pin Symbol Function
1 PSM Power save mode
2 SI2 Control input
3 VCC1 Supply voltage VCO
4 VREF Reference pin of VCO
5 TANK Tank pin of VCO
6, 7, 8, 21, 22, 23, 24 GND Ground
9 VCC2 Supply voltage PLL
10 CI Control input
11 TI Test interface
12 CD Active filter output
13 PD Tristate charge pump output
14 PLCK Lock-indication output (open collector)
15 OSCB Input of internal oscillator/buffer
16 OSCE Output of internal oscillator/buffer
17 TH Threshold voltage of comparator
18 AGC Charge-pump output of comparator, AGC input for amplifier and mixer
19 IF Intermediate frequency output
20 VCC3 Supply voltage
25 NRF RF input (inverted)
26 RF RF input
27 SI1 Control input
28 VCC4 Supply voltage
4719A–DAB–05/03 Functional Description The U2730B-N is an L-band down-converter circuit covering a gain-controlled amplifier, a gain-controlled mixer, an output buffer, a gain control circuitry, an L-band oscillator and a frequency synthesizer block. Designed for applications in a DAB receiver, the cir- cuit down-converts incoming L-band signals in the frequency range of 1452 MHz to
1492 MHz to an IF frequency in a range of 190 MHz to 230 MHz which can be handled
by a subsequent DAB tuner. A block diagram of this circuit is shown in Figure 1. Gain-controlled Amplifier RF signals applied to the 'RF' input pin are amplified by a gain-controlled amplifier. The complementary pin NRF is not internally blocked, it is recommended to block this pin carefully by an external capacitor. The gain-control voltage is generated by an internal gain-control circuitry. The output signal of this amplifier is fed to a gain-controlled mixer. Gain-controlled Mixer and Output Buffer The purpose of this mixer is to down-convert the L-band signal in the frequency range of 1452 MHz to 1492 MHz to an IF frequency in the range of about 190 MHz to 230 MHz. Like the amplifier, the gain of the mixer is controlled by the gain-control circuitry. The IF signal is buffered and filtered by a one-pole low-pass filter at a 3 dB frequency of about 500 MHz, and then it is fed to the single-ended output pin IF. Gain-control Circuitry The gain-control circuitry measures the signal power, compares it with a certain power level and generates control voltages for the gain-controlled amplifier and mixer. An equivalent circuit of this functional block is shown in Figure 6. In order to meet this functionality, the output signal of the buffer amplifier is weakly band-pass filtered (transition range of about 60 MHz to 550 MHz), rectified, low-pass fil- tered and fed to a comparator whose threshold can be defined by an external resistor, RTH, at pin TH. By varying the value of this resistor, a power threshold of about -33 dBm to -20 dBm can be selected. In order to achieve a good intermodulation ratio, it is recom- mended to keep the power threshold below -25 dBm. An appropriate application is shown in Figure 3. Depending on the selection made by the comparator, a charge pump charges or discharges a capacitor which is applied to the AGC pin. By varying this capacitor, different time constants of the AGC loop can be realized. The voltage arising at the AGC pin is used to control the gain setting of the gain-controlled amplifier and mixer. The voltage at pin AGC is in the range of 5.75 V for maximum gain and 0.3 V for minimum gain. This voltage can be use to control a dual-gate GaAs-FET in front of the U2730B-N to achieve an extended AGC range. By applying an external voltage to the AGC pin, the internal AGC loop can be overdriven. Voltage-controlled Oscillator A voltage-controlled oscillator supplies a LO signal to the mixer. An equivalent circuit of this oscillator is shown in Figure 7. In the application circuits Figure 8 and Figure 9, a ceramic coaxial resonator is applied to the oscillator's TANK and VREF pins. It should be noted that V ref has to be blocked carefully. Figure 9 shows a different application where the oscillator is overdriven by an external oscillator. In any case, a DC path at a low impedance must be established between the TANK and VREF pins. The output sig- nal of the oscillator is fed to the LO divider block of the frequency synthesizer unit which locks the VCO's frequency on the frequency of a reference oscillator. Figure 5 shows the typical phase-noise performance of the oscillator in locked state.
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The overall gain of this circuit amounts to 24 dB, the gain-control range is about 30 dB. modulation distances (DIM3) at higher IF output power levels. PLL is not influenced by the power-down mode. the reference and the LO divider. Table 1. Scaling Factors of the Reference Frequency
reference divider factors result in reference oscillator frequencies shown in Table 1. be 1261.568 MHz in locked state and the output frequency of the RF divider is 512 kHz. pleted by connecting the pins PD and CD by an appropriate RC network. logical value of the PLCK output is undefined. tors the output frequency of the reference divider appears at the output pin TI. Table 2. Control Interface (CI) Settings
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4719A–DAB–05/03 Absolute Maximum Ratings Parameters Pins Symbol Value Unit Supply voltage 3, 9, 20 and 28 VCC -0.3 to +9.5 V RF input voltage 25 and 26 VRF 750 mVpp Voltage at pin AGC 18 VAGC 0.5 to 6 V Voltage at pin TH 17 VTH -0.3 to +4.0 V Input voltage at pin T ANK (internal oscillator overdriven) 5 VTANK 1 Vpp Current at IF output 19 IIF 4.0 mA Reference input voltage (diff.) 15 OSCB 1 Vpp Control input voltage 1, 2, 10 and 27 CI, SI1, SI2, PD -0.3 to +9.5 V PLCK output current 14 IPLCK 0.5 mA PLCK output voltage 14 VPLCK -0.3 to +5.5 V Junction temperature Tj 125 /g176C Storage temperature Tstg -40 to +125 /g176C Operating Range Parameters Pins Symbol Value Unit Supply voltage 3, 9, 20 and 28 V CC 8 to 9.35 V Ambient Temperature T amb -40 to +85 /g176C Thermal Resistance Parameters Symbol Value Unit Junction ambient SSO28 (mod.) R thJA 50 K/W
Electrical Characteristics
Operating conditions: VCC = 8.5 V, Tamb = 25/g176C, see application circuit (Figure 8), unless otherwise specified No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* Supply current (max. gain) pRF = -60 dBm VPSM < 0.5 V IS,MAX 40 48 mA A Supply current (min. gain) pRF = -10 dBm VPSM < 0.5 V IS,MIN 41 50 mA B Supply current (power save mode) pRF = -10 dBm VPSM > 2 V IS,PD 20 24 mA A Amplifier Mixer Pin 26 26 /g174 19 Maximum conversion gain p RF = -60 dBm g c,max 20 24 dB A Minimum conversion gain p RF = -15 dBm g c,min -8 dB B AGC range /g68gc 28 32 dB A Third order 2 tone intermodulation ratio pRF1 + pRF2 = -10 dBm pRF1 + pRF2 = -15 dBm dim3 30 dB dB B A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
4719A–DAB–05/03 DSB noise figure (50-/g87 system) Maximum gain Minimum gain NF 10 dB dB D RF Input 26 Frequency range f in,RF 1400 1550 MHz C Maximum input power dim3 /g179 20 dB p in,max,RF -6 dBm C Input impedance Z in,RF 200 ||/g321 /g87 || pF D IF Output 19 Frequency range f out,IF 150 250 MHz C Output impedance Z out,IF 50 /g87 D Voltage standing wave ratio VSWR IF 2.0 D Gain Control Threshold adjustment External resistor 17 R TH 100 k /g87 D Charge pump current pRF = -10 dBm VAGC = 3.5 V 18 I CP ,P 75 100 125 µA A pRF = -60 dBm VAGC = 3.5 V ICP ,N -125 -100 -75 µA A Minimum gain control voltage pRF = -10 dBm 18 V AGCmin 0.1 0.6 V A Maximum gain control voltage pRF = -60 dBm 18 V AGCmax 5.5 5.75 V A VCO 5 Frequency f LO 1000 1261.568 1500 MHz Phase noise 1 kHz distance L 1kHz -75 dBc/Hz C Minimum input power VCO over-driven, see “Application Circuit” (Figure 8) pLO,MIN -11 dBm C Maximum input power p LO,MAX -5 dBm C Frequency Synthesizer RF divide factor SF 2464 A Reference divide factor SI1 = GND, SI2 = GND SI1 = GND, SI2 = VCC SI1 = GND, SI2 = open SI1 = VCC, SI2 = GND SI1 = VCC, SI2 = VCC SI1 = VCC, SI2 = open SI1 = open, SI2 = GND SI1 = open, SI2 = VCC SI1 = open, SI2 = open SF ref A Input frequency range f ref 55 0 M H z C Input sensitivity 15 V refs 30 mV rms C Maximum input signal 15 V refmax 300 mV rms C Input impedance Single-ended Z ref 2.7k || 2.5 k /g87 || pF D Electrical Characteristics (Continued) Operating conditions: VCC = 8.5 V, Tamb = 25/g176C, see application circuit (Figure 8), unless otherwise specified No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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4719A–DAB–05/03 Example: reference divider factor = 35, fREF = 17.92 MHz, charge-pump current = 200 µA Phase Detector Charge-pump current Pin CI connected to GND 13 I PD2 160 200 240 µA A Pin CI connected to VCC I PD1 240 300 360 µA A Pin CI connected to VCC/2 I PD1,tri 100 nA A Output voltage PD Pin CI open, Pin 13 V PD 0.3 V A Internal reference frequency f PD 512 kHz B Typical tuning voltage range 12 V tune 0.3 5 V C Lock Indication PLCK 14 Leakage current V PLCK = 5.5 V I PLCK 10 µA A Saturation voltage I PLCK = 0.25 mA V PLCK,sat 0.5 V A Control Inputs SI 2 and 27 Input voltage Pin connected to GND V L 00 . 1 V CC A Pin open V M open A Pin connected to VCC VH 0.9 1 V CC A Control Input CI 10 Input voltage Pin connected to GND V L 00 . 1 V CC A Pin connected to VCC/2 V M 0.5 V CC A Pin open V open open A Pin connected to VCC VH 0.9 1 V CC A Test Interface TI 11 Reference test frequency Pin CI open f test,ref 512 kHz B LO test frequency Pin CI = VCC/2 f test,LO 512 kHz B Voltage swing Rload /g179 1M /g87, Cload /g163 15 pF , Pin CI open or VCC/2 Vsw 400 mV pp C Power-save Mode PSM 1 PSM not active VPSM 0.6 V A PSM active VPSM 2.0 V A Electrical Characteristics (Continued) Operating conditions: VCC = 8.5 V, Tamb = 25/g176C, see application circuit (Figure 8), unless otherwise specified No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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A low phase-noise signal generator (Marconi 2042) was taken as PLL reference. Figure 5. Phase-noise Performance operating Conditions: fREF = 17.92 MHz, -10 dB, IPD = 200 µA
Figure 7. VCO Circuit
60 MHz
550 MHz
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Figure 8. Application Circuit
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4719A–DAB–05/03
Package Information
Ordering Information
Extended Type Number Package Remarks U2730B-NFS SSO28 Tube U2730B-NFSG1 SSO28 Taped and reeled according to IEC 286-3 technical drawings according to DIN specifications Dimensions in mm 9.10 9.01 0.15 0.05 0.25 0.65 8.45 1.30 5.7 5.3 4.5 4.3 6.6 6.3 0.15 28 15 11 4
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