U2730B-B

U2730B-B TEMIC | Alldatasheet

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Technical content

Features

/C0068Supply voltage: 8.5 V /C0068RF frequency range: 1400 MHz to 1550 MHz /C0068IF frequency range: 150 MHz to 250 MHz /C0068Overall IM3 rejection: > 40 dB /C0068Overall gain control range: typ. 30 dB /C0068DSB noise figure: 9.5 dB /C0068Gain-controlled amplifier /C0068Gain-controlled L-band mixer /C0068On-chip gain-control circuitry /C0068On-chip VCO, typical frequency 1261.568 MHz /C0068Internal VCO can be overdriven by an external LO /C0068On-chip frequency synthesizer – Fixed LO divider factor: 2464 – Four reference divider factors selectable: 32, 35, 36, 48 – Tristate phase detector with programmable charge pump – De-activation of tuning output programmable – Lock-status indication – Test interface Block Diagram 14749 ΔU VCO RF 26 25NRF Tristate phase detector Reference counter 32/35/36/48 RF counter 2464 Test interface 10 11 Programmable charge pump (50µA / 200µA) Control interface Lock detector V oltage stabilizer 9 6, 7, 8, 21, 22, 23, 24 internal supply voltage for frequency synthesizer TH IF TMD TRD VCC1 VCC3 VCC4 VCC2 GND PLCK PD CD 4 5 15 16 2 27 VREF TANK REF NREF C S 20k AGC Figure 1. Block diagram

Rev. A1, 22-Jul-98 Preliminary Information 2 (12)

Ordering Information

Extended Type Number Package Remarks U2730B-BFS SSO28 U2730B-BFSG1 SSO28 Taped and reeled according to IEC 286–3 Pin Description GND GND VCC2 TMD TRD CD PD PLCK 1712 GND GND GND VCC3 IF AGC NRF GND TH RF S VCC4 1514 14828 NREF REF n.c. C VCC1 VREF TANK GND Figure 2. Pinning

2 C Control input

3 VCC1 Supply voltage

4 VREF Reference pin of VCO

5 TANK Tank pin of VCO

9 VCC2 Supply voltage

10 TMD Test output of main divider

11 TRD Test output of reference divider

12 CD Active filter output

13 PD Three-state charge pump output

14 PLCK Lock-indication output

15 REF Reference divider input

16 NREF Reference divider input

17 TH Threshold voltage of comparator

18 AGC Charge-pump output of

19 IF Intermediate frequency output

20 VCC3 Supply voltage

25 NRF RF input (inverted)

26 RF RF input

27 S Control input

28 VCC4 Supply voltage

Rev. A1, 22-Jul-98 3 (12) Functional Description The U2730B-B is an L-band down-converter circuit covering a gain-controlled amplifier, a gain-controlled mixer, an output buffer, a gain-control circuitry, an L-band oscillator and a frequency synthesizer block. Designed for applications in an DAB receiver, the purpose of this circuit is to down-convert incoming L-band signals in the frequency range of 1452 MHz to

1492 MHz to an IF frequency in the range of about

190 MHz to 230 MHz which can be handled by a

subsequent DAB tuner. A block diagram of this circuit is shown in figure 1. Gain-Controlled Amplifier RF signals applied to the input Pin RF are amplified by a gain-controlled amplifier. Although the complementary Pin NRF is internally blocked, it is recommended to block this pin additionally by an external capacitor. The gain-control voltage is generated by an internal gain- control circuitry. The output signal of this amplifier is fed to a gain-controlled mixer. Gain-Controlled Mixer and Output Buffer The purpose of this mixer is to down-convert the L-band signal in the frequency range of 1452 MHz to 1492 MHz to an IF frequency in the range of about 190 MHz to 230 MHz. Like the amplifier, the gain of the mixer is controlled by the gain-control circuitry. The IF signal is buffered and filtered by a one-pole lowpass filter at a 3-dB frequency of about 500 MHz and then it is fed to the single-ended output Pin IF. Gain-Control Circuitry The purpose of the gain-control circuitry is to measure the signal power, to compare it with a certain power level and to generate control voltages for the gain-controlled amplifier and mixer. An equivalent circuit of this functional block is shown in figure 4. In order to meet this functionality, the output signal of the buffer amplifier is weakly bandpass filtered (transition range about 60 MHz to 550 MHz), rectified, lowpass filtered and fed to a comparator whose threshold can be defined by an external resistor, R TH , at Pin TH. By varying the value of this resistor, a power threshold of about –35 dBm to –25 dBm can be selected. In order to achieve a good intermodulation ratio, it is recommended to keep the power threshold below –30 dBm. An appropriate application is shown in figure 3. Depending on the selection made by the comparator, a charge pump charges or discharges a capacitor which is applied to the Pin AGC. By varying this capacitor, different time constants of the AGC loop can be realized. The voltage arising at the Pin AGC is used to control the gain setting of the gain-controlled amplifier and mixer. By applying an external voltage to the Pin AGC the internal AGC loop can be overdriven. Voltage-Controlled Oscillator A voltage-controlled oscillator supplies an LO signal to the mixer. An equivalent circuit of this oscillator is shown in figure 5. In the application circuits figures 3 and 5, a ceramic coaxial resonator is applied to the oscillator’s Pins TANK and REF. It should be noted that the Pin REF has to be blocked carefully. Figure 6 shows a different application where the oscillator is overdriven by an external oscillator. In any case, a DC path at a low impedance must be established between the Pins TANK and REF. The output signal of the oscillator is fed to the LO divider block of the frequency synthesizer unit which locks the VCO’s frequency on the frequency of a reference signal applied to the Pins REF and NREF. Figure 7 shows the typical phase-noise performance of the oscillator in locked state. Overall Properties of the Signal Path The overall gain of this circuit amounts 21 dB, the gain- control range is about 32 dB. Frequency Synthesizer The frequency synthesizer block consists of an input buffer for a reference signal, a reference divider, an LO divider to divide the frequency of the internal oscillator, a tristate phase detector, a lock detector, a programmable charge pump, a loop filter amplifier, a control interface and a test interface. The control interface is accessed by two control pins, Pins C and S. The test interface provides test signals which represent output signals of the reference and the LO divider. The purpose of this unit is to lock the frequency, f VCO , of the internal VCO on the frequency, fref, of the reference signal applied to the input Pins REF and NREF by a phase-locked loop according to the following equation: f VCO = SF /C0032 fref / SFref where: SF = 2464 SF ref = scaling factor of reference divider according to the following table V oltage at Pin S (Pin 27) SFref Ground 35 V CC / 2 32 Open 48 V CC 36 V CC -supply voltage

Rev. A1, 22-Jul-98 Preliminary Information 4 (12) Reference Divider Four different scaling factors of the reference divider can be selected by the input Pin S: 32, 35, 36, 48. Starting from a reference oscillator frequency of 16.384 MHz/ 17.92 MHz/ 18.432 MHz/ 24.576 MHz these scaling factors result in an output frequency of the reference divider of 512 kHz. If the input control Pin C is left open (high-impedance state), a test signal which monitors the output frequency of the reference divider appears at the output Pin TRD of the test interface. LO Divider The LO divider is operated at the fixed division ratio 2464. Assuming the settings described in the section ‘Reference divider’, the oscillator’s frequency is controlled to be 1261.568 MHz in locked state, the output frequency of the RF divider is 512 kHz. In analogy to the reference divider, a test signal which monitors the output frequency of the RF divider appears at the output Pin TMD of the test interface if the input control Pin C is left open (high-impedance state). Phase Comparator, Charge Pump and Loop Filter The tristate phase detector causes the charge pump to source or to sink current at the output Pin PD depending on the phase relation of its input signals which are provided by the reference and the RF divider respectively. By means of the control Pin C, two different values of this current can be selected, and furthermore the charge-pump current can be switched off. A high-gain amplifier (output Pin CD) which is implemented to construct a loop filter, as shown in the application circuit, can be switched off by means of the control Pin C. In the application circuit figure 3, the loop filter is completed by connecting the Pins PD and CD by an appropriate RC network. An internal lock detector checks if the phase difference of the input signals of the phase detector is smaller than approximately 250 ns in seven subsequent comparisons. If a phase lock is detected, the open collector output Pin PLCK is set to HIGH. It should be noted that the output current of this pin must be limited by external circuitry as it is not limited internally. If the voltage at the control Pin C is chosen to be half the supply voltage, or if this control pin is left open, the lock-detector function is de-activated and the logical value of the PLCK output is undefined. Absolute Maximum Ratings Parameters Symbol Value Unit Supply voltage Pins 3, 9, 20 and 28 V CC –0.3 to +9.5 V RF input voltage Pins 25 and 26 V RF 750 mV pp V oltage at Pin AGC Pin 18 VAGC 0.5 to 6 V V oltage at Pin TH Pin 17 V TH –0.3 to +4.0 V Input voltage at Pin TANK (internal oscillator overdriven) Pin 5 V TANK 1 V pp Current at IF output Pin 19 IIF 4.0 mA Reference input voltage (diff.) Pins 15 and 16 REF, NREF 1 V pp Control input voltage Pins 1, 2 and 27 C, S –0.3 to +9.5 V PLCK output current Pin 14 IPLCK 0.5 mA PLCK output voltage Pin 14 V PLCK –0.3 to +5.5 V Junction temperature Tj 125 °C Storage temperature Tstg –40 to +125 °C Operating Range Parameters Symbol Min. Typ. Max. Unit Supply voltage Pins 3, 9, 20 and 28 V CC 8.0 8.5 9.35 V Ambient temperature Tamb –40 +85 °C

Rev. A1, 22-Jul-98 5 (12) Thermal Resistance Parameters Symbol Value Unit Junction ambient SSO28 (mod.) R thJA t.b.d. K/W

Electrical Characteristics

Operating conditions: VCC = 8.5 V , Tamb = 25°C, application circuit see figure 3, unless otherwise specified Parameters Test Conditions / Pins Symbol Min. Typ. Max. Unit Supply current (max. gain)pRF = –60 dBm IS,MAX 40 51 62 mA Supply current (min. gain)pRF = –10 dBm IS,MIN 44 55 66 mA Overall characteristics Pin 8 → 2 Maximum conversion gain pRF = –60 dBm gc,max 18 21 24 dB Minimum conversion gain pRF = –10 dBm gc,min –14 –11 –8 dB AGC range /C0068gc 32 dB Third order 2 tone intermodulation ratio pRF1 + pRF2 = –6 dBm pRF1 + pRF2 = –15 dBm dim3 20 dB dB DSB noise figure (50-Ω system) Maximum gain Minimum gain NF 9.5 dB dB RF input Pin 26 Frequency range fin,RF 1400 1550 MHz Maximum input power dim3 ≥ 20 dB pin,max,RF –6 dBm Input impedance Zin,RF 200 || 1 /C0087 || pF IF output Pin 19 Frequency range fout,IF 150 250 MHz Output impedance Zout,IF 50 Ω V oltage standing wave ratio VSWR IF 2.0 VCO Pin 5 Frequency fLO 1000 1261.568 1500 MHz Phase noise 100 kHz distance, appli- cation circuit see figure 5 L100kHz –100 dBc/Hz Minimum input power VCO overdriven, appli- pLO,MIN –11 dBm Maximum input power pp cation circuit see figure 6pLO,MAX –5 dBm Frequency synthesizer RF divide factor SF 2464 Reference divide factor Pin S connected to GND Pin S connected to V CC /2 Pin S open Pin S connected to V CC SFref 35

Rev. A1, 22-Jul-98 Preliminary Information 6 (12) Electrical Characteristics (continued) Operating conditions: VCC = 8.5 V , Tamb = 25°C, application circuit see figure 3, unless otherwise specified Parameters Test Conditions / Pins Symbol Min. Typ. Max. Unit REF input REF, NREF Pins 15 and 16 Input frequency range fref 5 50 MHzpq y g Pin S connected to GND Pin S connected to VCC /2 Pin S open Pin S connected to V CC 17.920 16.384 24.576 18.432 MHz MHz MHz MHz Input sensitivity V refs 10 20 mV rms Maximum input signal V refmax 300 mV rms Input impedance Single-ended Zref 2.7k || 2.5 k/C0087 || pF Phase detector Charge-pump current Pin C connected to VCC Pin 13 IPD2 ± 160 ± 203 ± 240 µA Pin C connected to GND IPD1 ± 40 ± 50 ± 60 µA Pin C connected to VCC /2 IPD1,tri ± 100 nA Output voltage PD Pin 2 open Pin 13 V PD 0.3 V Internal reference frequency fPD 512 kHz Typical tuning voltage range Pin 12 V tune 0.3 5 V Lock indication PLCK Pin 14 Leakage current V PLCK = 5.5 V IPLCK 10 µA Saturation voltage IPLCK = 0.5 mA V PLCK,sat 0.5 V Control inputs C and S Pins 2 and 27 Input voltage Pin connected to GND V L 0 0.1 VCC Vpg Pin connected to VCC /2 V M 0.4 VCC 0.6 VCC V Pin open Vopen open Pin connected to VCC V H 0.9 VCC 1 V Test outputs TMD, TRD Pins 10 and 11 Frequency Pin C open ftest 512 kHz V oltage swing R load ≥ 1 M/C0087, Cload ≤ 15 pF, Pin C open V test 400 mV pp

Figure 3. Application circuit

Rev. A1, 22-Jul-98 11 (12)

Package Information

Dimensions in mm 9.10 9.01 0.15 0.05 0.25 0.65 8.45 1.30 5.7 5.3 4.5 4.3 6.6 6.3 0.15 28 15 11 4

Rev. A1, 22-Jul-98 Preliminary Information 12 (12) Ozone Depleting Substances Policy Statement It is the policy of TEMIC Semiconductor GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs). The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. TEMIC Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency (EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively. TEMIC Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances. We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use TEMIC products for any unintended or unauthorized application, the buyer shall indemnify TEMIC against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. TEMIC Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 (0)7131 67 2831, Fax number: 49 (0)7131 67 2423