U2352B TEMIC | Alldatasheet
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Technical content
Rev. A1, 29-May-96 1 (8) PWM Power Control for DC Loads
Description
The U2352B bipolar circuit is a PWM device for control- ling logic level Power MOSFETs and IGBTs. It allows simple power control for dc loads. Integrated load current monitoring with adjustable switch-off threshold also gives the option of measuring the load current via the MOS transistor’s on-state resistance, R DS(on), or via a shunt resistor. Special Features /C0068Pulse width control up to 50 kHz clock frequency /C0068Load current monitoring via the on-state resistance, R DS(on), of the FET or via shunt resistor (optional) /C0068100 mA push-pull output stage /C0068V oltage monitoring /C0068Temperature-compensated supply voltage limitation /C0068Chip temperature monitoring
Applications
/C0068Battery-operated screwdrivers /C0068Battery-operated machine tools /C0068Halogen lamp controllers /C0068Dimmers /C0068Electronic fuses /C0068High-performance clock generators Chip temperature monitoring 140°C Reference voltage V oltage limitation 6.8 V Oscillator Output stage logic Time window current measurement Q S R Load current monitoring POR Push-pull output stage 2 x I GND I 95 9670 V S Q V S Figure 1. Block diagram
Figure 2. Block diagram with typical circuit
Rev. A1, 29-May-96 3 (8) Pin Description Osc V Contr ISet S2OUT V S Output GND S2IN 95 9701 Pin Symbol Function
1 Osc Oscillator
2 V Contr Control voltage input
3 ISet Setpoint value current
4 S2OUT Output, current switch S2
5 S2IN Input, current switch S2
6 GND Ground
7 Output Output
8 V S Supply voltage
Supply, Pin 8 Internal voltage limitation in the U2352B allows a simple supply via a series resistor R1. This enables operation of the circuit under different operating voltages. Supply voltage between Pin 8 (V S) and Pin 6 (GND) builds up via R 1 and is smoothed by C1. The series resistor R1 is calculated as follows: R 1max /C0043V Bmin /C0042V Smax Itot where V Bmin = Minimum operating voltage V Smax = Maximum supply voltage Itot = ISmax + IX ISmax = Maximum current consumption of the IS IX = Current consumption of the external elements Various thresholds are derived from an internal reference voltage source. Voltage Monitoring During build-up and reduction of the operating voltage, uncontrolled output pulses with excessively low ampli- tude are suppressed by the internal monitoring circuit. All latches are reset and the output of the load current detec- tion Pin 4 is switched to ground. Chip Temperature Monitoring U2352B has integrated chip temperature monitoring which switches off the output stage when a temperature of approximately 140°C is reached. The device is not enabled again until cooling has taken place and the supply voltage has been switched off and then back on again. Pulse Width Control, Pins 1 and 2 At the frequency-determining capacitor, Cosc, at Pin 1, switching over of two internal current sources gives rise to a triangular voltage which comparator, K 1, compares with the control voltage at Pin 2. If the voltage, V1, is more negative than the control voltage V2, the output stage is switched on via the output stage logic. When Cosc is charged, the whole process then runs in reverse order (see figure 3). Load Current Monitoring, Pins 3, 4, 5 Load current can be measured with the aid of an external shunt resistor, but this is only appropriate for decreased loads due to additional power loss and component size and costs. This involves the shunt voltage being fed directly to Pin 4 via a protective resistor (see figure 5). In order to save component costs and additional power loss, the integrated load current monitoring allows the load current to be directly measured via the voltage drop at the on-state resistance, R DS(on), of the FET, without an additional shunt resistor. The drain voltage of the FET is supplied via an external protective resistor to Pin 5. During the off-state of the FET, a diode clamp circuit protects the detection input, Pin 5. In the on state, the load current flowing through the FET generates a corresponding voltage drop at its R DS(on), which is in turn converted into a current at Pin 5 by the protective resistor. This current reaches the integration element at Pin 4 via the switch S 2, which is only closed in the on-state of the FET. If the voltage at Pin 4 exceeds the setpoint value set at Pin 3, as a result of a high load current, the shutdown latch is set and the output stage is blocked. To enable the circuit again, it is necessary to switch the operating voltage off and then back on again. Switch-off behavior is adjusted with the resistors at Pin 4 and Pin 5 and also with the capacitor at Pin 4.
Figure 3. Signal characteristics of pulse width control with time window generation
Rev. A1, 29-May-96 5 (8)
Electrical Characteristics
V S = 6 V , Tamb = 25/C0095C, reference point Pin 6, unless otherwise specified Parameters Test Conditions / PinsSymbol Min. Typ. Max. Unit Supply voltage limitationIS = 5 mA Pin 8 IS = 20 mA V S 6.4 6.5 6.8 6.9 7.2 7.3 V Current consumption V S = 6 V Pin 8 IS 2.7 3.5 mA Voltage monitoring Switch-on threshold Switch-off threshold Pin 8 Pin 8 V SON V SOFF 5.2 4.7 5.6 5.1 6.0 5.5 V Oscillator fOSC [kHz ]/C009155 C OSC [nF] /C0032V S [V ] Pin 1 Upper threshold (0.6/C0032V S) Lower threshold (0.3/C0032V S) Charge current Discharge current V Tu V Tl –Ich Idis 3.4 1.7 3.6 1.8 3.8 1.9 V V /C0109A /C0109A Control voltage input Input voltage range Input current, Offset voltage K Window, current measurement Pin 2
0 V ≤ V2 ≤ V8 Pin 2
Pin 2–1 Pin 2–1 V I ±Ii ±V Offs –/C0068V 2 260 300 V 8 500 340 V nA mV mV Load current monitoring Setpoint value input: Input voltage range Input current Pin 3
0 V ≤ V3 ≤ 6 V Pin 3
±Ii 0 6 500 V nA Offset voltage K2 Pin 4–3 ±V Offs 15 mV Load current detection: V oltage limitation V oltage limitation I5 = 1 mA Pin 5 I5 = –1 mA Pin 5 V L –V L 2.3 0.7 V Discharge current at POR Pin 4 Idis 1 mA Switch S2 Pin 5–4 Residual voltage at closed switch V 4 = 0 V , I5 = 50 /C0109A V 4 = 0.1 V , I5 = 50 /C0109A V 4 = 0.3 V , I5 = 50 /C0109A V 4 = 0.3 V , I5 = 100 /C0109A V Sat 175 150 125 200 mV Push-pull output stage Pin 7 Upper saturation voltageI7 = –2 mA Pin 7–8 –V Satu 1 V Lower saturation voltageI7 = 10 mA Pin 7 V Satl 0.3 V Output current ON state OFF state t ≤ 2 /C0109s t ≤ 2 /C0109s –io io 100 100 mA
Rev. A1, 29-May-96 7 (8) Dimensions in mm 94 8873 94 8862
Rev. A1, 29-May-96 8 (8) Ozone Depleting Substances Policy Statement It is the policy of TEMIC TELEFUNKEN microelectronic GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs). The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. TEMIC TELEFUNKEN microelectronic GmbH semiconductor division has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency (EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively. TEMIC can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances. We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use TEMIC products for any unintended or unauthorized application, the buyer shall indemnify TEMIC against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. TEMIC TELEFUNKEN microelectronic GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 (0)7131 67 2831, Fax number: 49 (0)7131 67 2423