TZA3013A PHILIPS | Alldatasheet

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Product specification Supersedes data of 2000 Jun 19 File under Integrated Circuits, IC19

2001 Feb 26

TZA3013A; TZA3013B SDH/SONET STM16/OC48 transimpedance amplifier

2001 Feb 26 2

Philips Semiconductors Product specification SDH/SONET STM16/OC48 transimpedance amplifier TZA3013A; TZA3013B

FEATURES

  • Low equivalent input noise, typically 8 pA/√Hz
  • Wide dynamic range, typically 6µA to 1.7 mA (p-p)
  • Differential transimpedance of 4 kΩ
  • Bandwidth from DC to 1.9 GHz
  • Differential outputs
  • On-chip Automatic Gain Control (AGC)
  • No external components required
  • Single supply voltage 3.3 V
  • Bias voltage for PIN diode
  • Remains linear up to 1.7 mA (p-p) input current (unclipped)
  • Switched output polarity available (types A and B).

APPLICATIONS

  • Digital fibre optic receiver in short, medium and long haul optical telecommunications transmission systems or in high speed data networks
  • Wide-band RF gain block. GENERAL DESCRIPTION The TZA3013 is a transimpedance amplifier with AGC, designed to be used in STM16/OC48 fibre-optic links. It amplifies the current generated by a photo detector (PIN diode or avalanche photodiode) and converts it to a differential output voltage.

ORDERING INFORMATION

TZA3013AU − bare die in waffle pack carriers; die dimensions 0.810× 1.230 mm − TZA3013BU − bare die in waffle pack carriers; die dimensions 0.810× 1.230 mm −

2001 Feb 26 3

Philips Semiconductors Product specification SDH/SONET STM16/OC48 transimpedance amplifier TZA3013A; TZA3013B BLOCK DIAGRAM handbook, full pagewidth MGT099 2 kW 2 kW W W 37, 8 10 270 W 100 pF TZA3013AU GAIN CONTROL BIAS SOURCE INQ low noise amplifier single-ended to differential converter PEAK DETECTOR DREF IN 41 2 OUTSENSE14 OUT13 OUTQ6 OUTQSENSE5 TESTCGNDA GNDD VCC VCC VCCAGC PILOT TESTD Fig.1 Block diagram of TZA3013AU (bare die only). handbook, full pagewidth MGU137 2 kW 2 kW W W 37, 8 10 270 W 100 pF TZA3013BU GAIN CONTROL BIAS SOURCE INQ low noise amplifier single-ended to differential converter PEAK DETECTOR DREF IN 41 2 OUTSENSE5 OUT6 OUTQ13 OUTQSENSE14 TESTCGNDA GNDD VCC VCC VCCAGC PILOT TESTD Fig.2 Block diagram of TZA3013BU (bare die only).

2001 Feb 26 4

Philips Semiconductors Product specification SDH/SONET STM16/OC48 transimpedance amplifier TZA3013A; TZA3013B PINNING Notes 1. DC bias voltage = 0.86 V. 2. This pad goes HIGH when current flows into pad IN. SYMBOL PAD TZA3013AU PAD TZA3013BU TYPE DESCRIPTION DREF 1 1 analog output bias voltage output for PIN diode; connect cathode of PIN diode to this pad IN 2 2 input current input; anode of PIN diode should be connected to this pad; note 1 INQ 3 3 input decision level adjust input; note 1 AGC 4 4 analog output AGC voltage OUTQSENSE 5 14 analog output data sense output for OUTQ; for test purposes OUTQ 6 13 output data output; compliment of OUT GNDA 7 7 ground analog ground GNDA 8 8 ground analog ground TESTC 9 9 input test input; not used in the application GNDD 10 10 ground digital ground TESTD 11 11 input test input; not used in the application PILOT 12 12 analog output pilot tone detection current output OUT 13 6 output data output; compliment of OUTQ; note 2 OUTSENSE 14 5 analog output data sense output for OUT; for test purposes V CC 15 15 supply supply voltage

2001 Feb 26 5

Philips Semiconductors Product specification SDH/SONET STM16/OC48 transimpedance amplifier TZA3013A; TZA3013B FUNCTIONAL DESCRIPTION The TZA3013 is a transimpedance amplifier intended for use in fibre optic links for signal recovery in STM16/OC48 applications. It amplifies the current generated by a photo detector (PIN diode or avalanche photodiode) and converts it to a differential output voltage. The most important characteristics of the TZA3013 are high receiver sensitivity and wide dynamic range. High receiver sensitivity is achieved by minimizing transimpedance amplifier noise. The TZA3013 has a wide dynamic range to handle the signal current generated by the PIN diode which can vary from 6µA to 1.7 mA (p-p). This is implemented by an AGC loop which reduces the preamplifier feedback resistance so that the amplifier remains linear over the whole input range. The AGC loop hold capacitor is integrated on-chip, so an external capacitor is not required. A differential amplifier converts the output of the preamplifier to a differential voltage. The data output circuit is shown in Fig.3. The logic level symbol definitions are shown in Fig.4. handbook, full pagewidth MGT102 2 kΩ 2 kΩ 16 Ω OUTSENSE VCC OUTQSENSE OUT 50 Ω 16 Ω OUTQ 50 Ω Fig.3 Data output circuit. handbook, full pagewidth MGR243 VOO VO(max) VOQH VOH VOQL VOL VO(min) Vo(p-p) VCC Fig.4 Logic level symbol definitions for data outputs OUT and OUTQ.

2001 Feb 26 6

Philips Semiconductors Product specification SDH/SONET STM16/OC48 transimpedance amplifier TZA3013A; TZA3013B PIN diode bias voltage DREF The performance of an optical receiver is largely determined by the combined effect of the transimpedance amplifier and the PIN diode. In particular, the method used to connect the PIN diode to the input and the layout around the input pad strongly influences the main parameters of a transimpedance amplifier, such as sensitivity, bandwidth, and PSRR. Sensitivity is most affected by the value of the total capacitance at the input pad. Therefore, to obtain the highest possible sensitivity requires the value of total capacitance to be as low as possible by reducing the capacitance of the PIN diode and the parasitics around the input pad. To minimize parasitics, the PIN diode should be placed as close as physically possible to the IC. The capacitance of the PIN diode can be reduced by making the value of reverse voltage across it as high as possible. The PIN diode can be connected to the input in two ways. Figure 5 shows the PIN diode connected between pads DREF and IN. Pad DREF provides an easy bias voltage for the PIN diode. The voltage at DREF is derived from V CC by a low-pass filter comprising internal resistor R1 and external capacitor C2 which decouples any supply voltage noise. The value of external capacitor C2 affects the value of PSRR and should have a minimum value of 100 pF. Increasing this value increases the value of PSRR. For a supply voltage of 3.3 V, the reverse voltage across the PIN diode is 2.438 V (3.3 V− 0.862 V). It is preferable to connect the cathode of the PIN diode to a voltage higher than V CC if there is one available on the PCB, leaving pad DREF unconnected. If a negative supply voltage is available, the configuration shown in Fig.6 can be used. It should be noted that in this configuration, the direction of the signal current is reversed to that shown in Fig.5. It is essential that the PIN diode bias voltage is correctly filtered to achieve the highest possible level of sensitivity. handbook, halfpage

270 WC2

Fig.5 The PIN diode connected between the input and pad DREF. handbook, halfpage MGT103 270 W VCC Ii TZA3013 2IN DREF negative supply Fig.6 The PIN diode connected between the input and a negative supply voltage.

2001 Feb 26 7

Philips Semiconductors Product specification SDH/SONET STM16/OC48 transimpedance amplifier TZA3013A; TZA3013B AGC The TZA3013 transimpedance amplifier can handle input currents from 6µA to 1.7 mA which is equivalent to a dynamic range of 49 dB. At low input currents, the transimpedance must be high to obtain enough output voltage, and the noise should be low enough to guarantee a minimum bit error rate. At high input currents however, the transimpedance should be low to avoid pulse width distortion. To achieve the wide dynamic range requires the gain of the amplifier to depend on the level of the input signal. This is achieved in the TZA3013 by an AGC loop. The AGC loop comprises a peak detector, a hold capacitor and a gain control circuit. The peak detector detects the amplitude of the signal and the hold capacitor stores it. The hold capacitor voltage is compared to a threshold voltage which corresponds to an input current of 50µA (p-p). The AGC is only active when the input signal level is larger than the threshold level and is inactive when the input signal is smaller than the threshold level. When the AGC is inactive, the transimpedance is at its maximum value of 4 kΩ differential. When the AGC is active, the feedback resistor value of the transimpedance amplifier is reduced, reducing its transimpedance, to keep the output voltage constant. The transimpedance is regulated from 4 kΩ at low currents (I i<5 0µA) to 80Ω at high currents (Ii= 1.7mA). The AGC allows the amplifier to remain linear over the whole input current range compared to other configurations which clip the large signals, such as those using Schottky diodes, for example. The top half of Fig.7 shows the output voltage at pads OUT and OUTQ (V OUT and VOUTQ ) as a function of DC input current (II) at a supply voltage of 3.3 V. The bottom half of Fig.7 shows the difference between VOUT and VOUTQ . The output voltage changes linearly up to an input current of 50 µA. At this point and above, the AGC becomes active and tries to keep the differential output voltage constant, which is about 220 mV for a large range input current of <1.7 mA. handbook, full pagewidth 300 200 100 MGT104 11 0 210 Ii (µA) Vo (V) Vo(dif) (mV) 104103 2.8 2.9 3.1 3.0 3.2 VCC = 3.3 V VOUT VOUTQ Fig.7 AGC characteristics. Vo(dif)=V OUT − VOUTQ

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Philips Semiconductors Product specification SDH/SONET STM16/OC48 transimpedance amplifier TZA3013A; TZA3013B LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However it is good practice to take normal precautions appropriate to handling MOS devices (see“Handling MOS devices”). CHARACTERISTICS Typical values at Tj=2 5°C and VCC = 3.3 V; minimum and maximum values are valid over the entire ambient temperature range and supply range; all voltages are measured with respect to ground; unless otherwise specified. SYMBOL PARAMETER MIN. MAX. UNIT VCC supply voltage −0.5 +3.8 V Vn DC voltage pads IN and INQ −0.5 +2.0 V pads OUT and OUTQ −0.5 V CC + 0.5 V pads OUTSENSE and OUTQSENSE −0.5 V CC + 0.5 V pad PILOT −0.5 V CC + 0.5 V pad DREF −0.5 V CC + 0.5 V In DC current pads IN and INQ −4.0 +4.0 mA pads OUT and OUTQ −10 +10 mA pad PILOT −0.2 +0.2 mA pad DREF −4.0 +4.0 mA Ptot total power dissipation − 300 mW Tstg storage temperature −65 +150 °C Tj junction temperature − 150 °C Tamb ambient temperature −40 +85 °C SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VCC supply voltage 3.0 3.3 3.6 V ICC supply current AC-coupled; R L =5 0Ω ; without input signal − 26 38 mA Ptot total power dissipation VCC = 3.3 V − 85.8 134 mW Tj junction temperature −40 − +125 °C Tamb ambient temperature −40 +25 +85 °C R tr small-signal transresistance of the receiver measured differentially; AC-coupled R L = ∞ 3.6 7 10 k Ω R L =5 0Ω 1.8 3.5 5.0 k Ω f−3dB(h) high frequency−3 dB point Ci= 0.5 pF 1.7 1.9 − GHz In(tot)(rms) total integrated RMS noise current over bandwidth referenced to input; Δfi= 1.8 GHz third-order Bessel filter; note 1 − 425 − nA

2001 Feb 26 9

Philips Semiconductors Product specification SDH/SONET STM16/OC48 transimpedance amplifier TZA3013A; TZA3013B Notes 2. PSRR is defined as the ratio of change in input current (ΔIi) corresponding to change in supply voltage (ΔVCC ): For example, a 4 mV disturbance on VCC at 10 MHz will typically add an extra 120 nA to Ii (photodiode output current). The value of the external capacitor connected between pads DREF and GND has a significant effect on the value of PSRR. The specification is valid with an external capacitor of 1 nF. PSRR power supply rejection ratio measured differentially; note 2 fi= 100 kHz to 100 MHz− 38 −µ A/V fi= 3 GHz − 3.2 − mA/V Automatic gain control loop: AGC tatt AGC attack time − 10 −µ s tdecay AGC decay time − 10 −µ s Ith(AGC)(p-p) AGC threshold current (peak-to-peak value) referenced to input − 50 −µ A Bias voltage: DREF R DREF resistance between DREF and VCC tested at DC level 240 270 340 Ω Inputs: IN and INQ Ii(p-p) input current (peak-to-peak value) −1700 − +1700 µA VI(bias) input bias voltage 700 860 1100 mV R i small-signal input resistance tested at 1 MHz; Ii<2 0µA (p-p) − 53 −Ω Data outputs: OUT and OUTQ Vo(cm) common mode output voltage AC-coupled; RL =5 0Ω VCC − 0.5 VCC − 0.25 VCC − 0.1 V Vo(se)(p-p) single-ended load output voltage (peak-to-peak value) AC-coupled; R L =5 0Ω ; Ii= 100µA (p-p) 45 110 200 mV VOO differential output offset voltage −100 0 +100 mV R o output resistance single-ended; DC tested 40 53 65 Ω tr rise time 20% to 80% − 200 − ps tf fall time 80% to 20% − 200 − ps SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT PSRR Δ Ii Δ V CC

2001 Feb 26 10

Philips Semiconductors Product specification SDH/SONET STM16/OC48 transimpedance amplifier TZA3013A; TZA3013B TYPICAL PERFORMANCE CHARACTERISTICS handbook, halfpage −40 0 (2) (3) (1) Tj (°C) ICC (mA) 160120 MGT105 Fig.8 Supply current as a function of the junction temperature. (1) VCC = 3.6 V. (2) VCC = 3.3 V. (3) VCC = 3.0 V. handbook, halfpage 3.0 3.2 ICC (mA) VCC (V)3.4 3.6 MGT106 Fig.9 Supply current as a function of the supply voltage. Tj=2 5°C. handbook, halfpage 3.0 3.2 VI(bias) (mV) VCC (V)3.4 3.6 866 862 860 858 864 MGT107 Fig.10 Input bias voltage as a function of the supply voltage. Tj=2 5°C. handbook, halfpage −40 04 0 VI(bias) (mV) 160120 965 725 925 885 845 805 765 MGT108 (3) (1) (2) Tj (°C) Fig.11 Input bias voltage as a function of the junction temperature. (1) VCC = 3.6 V. (2) VCC = 3.3 V. (3) VCC = 3.0 V.

2001 Feb 26 11

Philips Semiconductors Product specification SDH/SONET STM16/OC48 transimpedance amplifier TZA3013A; TZA3013B handbook, halfpage 3.0 3.2 Vo(cm) (mV) VCC (V)3.4 (1) (2) 3.6 290 230 210 190 270 250 MGT109 Fig.12 Common mode output voltage as a function of the supply voltage referenced to VCC . Tj=2 5°C. (1) VCC − VOUT . (2) VCC − VOUTQ . handbook, halfpage −40 0 (2) Vo(cm) (mV) 160120 340 180 300 260 220 MGT110 (1) (3) Tj (°C) Fig.13 Common mode output voltage as a function of the junction temperature referenced to V CC . (1) VCC = 3.6 V. (2) VCC = 3.3 V. (3) VCC = 3.0 V.

2001 Feb 26 12

Philips Semiconductors Product specification SDH/SONET STM16/OC48 transimpedance amplifier TZA3013A; TZA3013B APPLICATION AND TEST INFORMATION handbook, full pagewidth MGT112 VCC DREF 2IN GND TZA3013A

13 OUT

6 OUTQ

Zo = 50 W Zo = 50 W 1 nF 100 pF 680 nF 10 mH VP transmission line 100 nF 100 nF 7, 8, 10 Fig.14 Application diagram. handbook, full pagewidth MGT113 330 Ω R 60 Ω Zo = 50 Ω Zo = 50 Ω Zo = 50 Ω IN GND OUT OUTQ 10 nF VCC 100 nF trigger input SAMPLING OSC PORT 1 PORT 2 NETWORK ANALYZER S-PARAMETER TEST SET 100 nF TZA3013 PATTERN GENERATOR 223−1 PRBS DATA 223−1 PRBS CLOCK Fig.15 Test circuit. Total impedance of the test circuit = ZT and is calculated by the equation where s21 is the insertion loss of ports 1 and 2. Typical values: R = 330Ω , ZIN =7 3Ω . ZT s21 RZ IN+() 2××=

2001 Feb 26 13

Philips Semiconductors Product specification SDH/SONET STM16/OC48 transimpedance amplifier TZA3013A; TZA3013B BONDING PAD LOCATIONS Note 1. All coordinates are referenced, inµm, to the centre of the die. SYMBOL PAD TZA3013AU PAD TZA3013BU COORDINATES (1) xy DREF 1 1 −440 +155 IN 2 2 −440 +10 INQ 3 3 −440 −157 AGC 4 4 −266 −255 OUTQSENSE 5 −− 40 −255 − 14 −40 +255 OUTQ 6 − +116 −255 − 13 +110 +255 GNDA 7 7 +256 −255 GNDA 8 8 +398 −255 TESTC 9 9 +448 −79 GNDD 10 10 +448 +70 TESTD 11 11 +410 +255 PILOT 12 12 +260 +255 OUT 13 − +110 +255 − 6 +116 −255 OUTSENSE 14 −− 40 +255 − 5 −40 −255 V CC 15 15 −266 +255

2001 Feb 26 14

Philips Semiconductors Product specification SDH/SONET STM16/OC48 transimpedance amplifier TZA3013A; TZA3013B handbook, halfpage MGT101 GNDD TESTC DREF IN INQ OUTSENSE OUT PILOT VCCAGC OUTQSENSE OUTQ GNDA TESTDGNDA 810 µm TZA3013AU 45 6 7 8 15 14 13 12 11 x y 1230 µm Fig.16 Bonding pad locations of the TZA3013AU. handbook, halfpage GNDD TESTC DREF IN INQ OUTQSENSE OUTQ PILOT VCCAGC OUTSENSE OUT GNDA TESTDGNDA MGT167 810 µm 1230 µm TZA3013BU 45 6 7 8 15 14 13 12 11 x y Fig.17 Bonding pad locations of the TZA3013BU. Physical characteristics of the bare die PARAMETER VALUE Glass passivation 0.3 µm PSG (PhosphoSilicate Glass) on top of 0.8µm silicon nitride Bonding pad dimension minimum dimension of exposed metallization is 90× 90 µm (pad size = 100× 100 µm) except pads 2 and 3 which have exposed metallization of 80× 80 µm (pad size = 90× 90 µm) Metallization 2.8 µm AlCu Thickness 380 µm nominal Size 0.810 × 1.230 mm (0.996 mm2) Backing silicon; electrically connected to GND potential through substrate contacts Attach temperature <440 °C; recommended die attach is glue Attach time <15 s

2001 Feb 26 15

Philips Semiconductors Product specification SDH/SONET STM16/OC48 transimpedance amplifier TZA3013A; TZA3013B DATA SHEET STATUS Note 1. Please consult the most recently issued data sheet before initiating or completing a design. DATA SHEET STATUS PRODUCT STATUS DEFINITIONS (1) Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. BARE DIE DISCLAIMER All die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of ninety (90) days from the date of Philips' delivery. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There is no post waffle pack testing performed on individual die. Although the most modern processes are utilized for wafer sawing and die pick and place into waffle pack carriers, Philips Semiconductors has no control of third party procedures in the handling, packing or assembly of the die. Accordingly, Philips Semiconductors assumes no liability for device functionality or performance of the die or systems after handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used.

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