TSX8308500GL

TS8308500 ATMEL | Alldatasheet

Document overview

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Technical content

2193A–BDC–06/03 Main Features

• 8-bit Resolution
• 500 Msps (min) Sampling Rate
• Power Consumption: 3.8W Typ
• 500 mVpp Differential or Single-ended Analog Inputs
• Differential or Single-ended 50Ω ECL Compatible Clock Inputs
• ECL or LVDS/HSTL Output Compatibility
• ADC Gain Adjust
• Data Ready Output with Asynchronous Reset
• Gray or Binary Selectable Output Data; NRZ Output Mode
• Enhanced CBGA Package with Ceramic Lid
• Evaluation Board: TSEV8308500GL (Detailed Specification on Request)
• Demultiplexer TS81102G0: Companion Device Available Performance
• 1.3 GHz Full Power Input Bandwidth
• Band Flatness: 0.5 dB up to 500 MHz
• SINAD = 45 dB (7.2 Effective Bits), SFDR = 54 dBc at F S = 500 Msps, FIN = 20 MHz
• SINAD = 43 dB (7.1 Effective Bits), SFDR = 53 dBc at F S = 500 Msps, FIN = 250 MHz
• SINAD = 42 dB (7.0 Effective Bits), SFDR = 52 dBc at F S = 500 Msps, FIN = 500 MHz (-3 dB FS)
• 2-tone IMD: TBD (199.5 MHz, 200.5 MHz) at 500 Msps
• DNL = ±0.3 LSB INL = ±0.7 LSB
• Low Bit Error Rate (10-13) at 500 Msps, Tj = 90°C

Applications

• Digital Sampling Oscilloscopes
• Satellite Receiver
• Electronic Countermeasures/Electronic Warfare
• Direct RF Down-conversion Screening
• Atmel Standard Screening Level
• Temperature Range: –0 °C < Tc; Tj < +90°C

Description

The TS8308500 is a monolithic 8-bit analog-to-digital converter, designed for digitizing wide bandwidth analog signals at very high sampling rates of up to 500 Msps. The TS8308500 is using an innovative architecture, including an on-chip Sample and Hold (S/H), and is fabricated with an advanced high-speed bipolar process. The on-chip S/H has a 1.3 GHz full power input bandwidth, providing excellent dynamic performance in undersampling applications (High IF digitizing). ADC 8-bit

500 Msps

Rev. 2193A–BDC–04/03

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2193A–BDC–04/03 Functional Figure 1. Simplified Block Diagram The TS8308500 is an 8-bit 500 Msps ADC based on an advanced high-speed bipolar technol- ogy featuring a cutoff frequency of 25 GHz. The TS8308500 includes a front-end master/slave Track and Hold stage (S/H), followed by an analog encoding stage and interpolation circuitry. Successive banks of latches are regenerating the analog residues into logical data before entering an error correction circuitry and a resynchronization stage followed by 75Ω differential output buffers. The TS8308500 works in fully differential mode from analog inputs up to digital outputs. The TS8308500 features a full-power input bandwidth of 1.3 GHz. Control pin GORB is provided to select either the Gray or Binary data output format. The gain control pin is provided in order to adjust the ADC gain. A Data Ready output asynchronous reset (DRRB) is available on TS8308500. The TS8308500 uses only vertical isolated NPN transistors together with oxide isolated poly- silicon resistors, which allow enhanced radiation tolerance (no performance drift measured at 150 kRad total dose). Master/Slave Track & Hold Amplifier VIN, VINB Clock Buffer GAIN GORB DATA, DATAB OR, ORBDRRB DR, DRB CLK, CLKB 4 5 4 5 Resistor Chain Analog Encoding Block Interpolation Stages Regeneration Latches Error Correction & Decode Logic Output Latches & Buffers

sink is mandatory (see Thermal characteristics). Table 1. Absolute Maximum Ratings Table 2. Recommended Conditions of Use

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Table 3. Electrical Specifications

Table 3. Electrical Specifications (Continued)

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1. See “Definition of Terms” on page 46
2. Histogram testing based on sampling of a 10 MHz sinewave at 50 Msps
3. Output error amplitude < ±4 lsb around worst code
4. Maximum jitter value obtained for single-ended clock input on the die (chip on board): 200 fs
5. Digital output back termination options depicted in Application Notes
6. At 500 Msps, 50/50 clock duty cycle, TC2 = 2 ns (TC1). TDR - TOD = -100 ps (typ) does not depend on the sampling rate
7. Specified loading conditions for digital outputs:
8. Termination load parasitic capacitance derating values:

1 Gsps (See “Timing Diagrams” on page 9) TD1 4 920 960 1000 ps (2)(13)

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2193A–BDC–04/03 - Unterminated (source terminated) 75Ω controlled impedance lines: 100 ps/pF or 150 ps per additionnal ECLinPS termina- tion load 10. Apply proper 50/75Ω impedance traces propagation time derating values: 6 ps/mm (155 ps/inch) for TSEV8308500GL Eval- uation Board 11. Values for TOD and TDR track each other over temperature, (1% variation for TOD-TDR per 100°C temperature variation). Therefore TOD-TDR variation over temperature is negligible. Moreover, the internal (on-chip) and package skews between each Data TODs and TDR effect can be considered negligible. Consequently, minimum values for TOD and TDR are never more than 100 ps apart. The same is true for the TOD and TDR maximum values (see Advanced Application Notes about “TOD-TDR Variation Over Temperature” on page 22). 12. Min value guarantees performance. Max value guarantees functionality 13. Min value guarantees functionality. Max value guarantees performance 14. Refer to product Application Notes

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2193A–BDC–04/03 Explanation of Test Levels Note: 1. Unless otherwise specified, all tests are pulsed tests : therefore T C = TA where TC and TA are case and ambient temperature. 2. Refer to “Ordering Information” on page 48. 3. Only min and max values are guaranteed (typical values are issued from characterization results). Functions Table 4. Explanation of Test Levels(3)

3 Sample tested only at specified temperatures

4 Parameter is guaranteed by design and characterization testing (thermal steady-state

5 Parameter is a typical value only

Table 5. Functions Description

Table 6. Digital Output Coding

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Figure 4. Integral Non-linearity Figure 5. Differential Non-linearity

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Figure 9. Spectrum for FS = 500 Msps, FIN = 498 MHz (Full Scale Input) Figure 10. Reconstructed Signal for FS = 500 Msps, FIN = 498 MHz (Full Scale Input)

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Figure 13. SFDR: Fs = 500 Msps, FIN = 20 MHz up to 1000 MHz, -1dB Full Scale Input, Tj = 70°C Figure 14. THD: Fs = 500 Msps, FIN = 20 MHz up to 1000 MHz, -1dB Full Scale Input, Tj = 70°C Figure 15. SINAD and SNR: Fs = 500 Msps, FIN = 20 MHz up to 1000 MHz, -1dB Full Scale Input, Tj = 70°C

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Figure 19. Analog Input Frequency: FIN = 250 MHz and FS = 200 Msps to 1400 Msps Figure 20. SFDR: FS = 500 Msps, FIN = 250 MHz, -1dB Full Scale Input, Tj = 0°C to 125°C

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Figure 24. Power Consumption Versus Junction Temperature: FS = 500 Msps; FIN = 250 MHz; Duty cycle = 50% Figure 25. Band Flatness at 1.3 GHz ; -3 dB (-2 dBm Full Power Input)

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2193A–BDC–04/03 TS8308500 Main Features Timing Information Timing Value for TS8308500 Timing values as defined in Table 3 on page 4 are advanced data, issuing from electric simu- lations and are the first characterization results fitted with measurements. Timing values are given for CBGA68 package inputs/outputs, taking into account package internal controlled impedance traces propagation delays, and specified termination loads. Propagation delays in 50/75 Ω impedance traces are NOT taken into account for TOD and TDR. Apply proper derating values corresponding to termination topology. The min/max timing values are valid over the full temperature range in the following conditions: – Specified termination load (differential output Data and Data Ready): 50Ω resistor in parallel with 1 standard ECLinPS register from Motorola, (i.e.: 10E452). (Typical ECLinPS inputs shows a typical input capacitance of 1.5 pF (including package and ESD protections). If addressing an output Dmux, take care if some Digital outputs do not have the same termination load and apply corresponding derating value given below – Output Termination Load derating values for TOD and TDR: ~ 35 ps/pF or 50 ps per additional ECLinPS load – Propagation time delay derating values have also to be applied for TOD and TDR: ~ 6 ps/mm (155 ps/inch) for TSEV8308500 Evaluation Board Apply proper time delay derating value if a different dielectric layer is used. Propagation Time Considerations TOD and TDR timing values ar e given from pin to pin and DO NOT include the additional propagation times between device pins and input/output termination loads. For the TSEV8308500 Evaluation Board, the propagation time delay is 6 ps/mm (155 ps/inch) corre- sponding to 3.4 (at 10 GHz) dielectric constant of the RO4003 used for the Board. If a different dielectric layer is used (for instance Teflon), use appropriate propagation time values. TD does NOT depend on propagation times because it is a differential data. (TD is the time difference between Data Ready output delay and digital Data output delay) TD is also the most straightforward data to measure, again because it is differential: TD can be measured directly onto termination loads, with matched oscilloscopes probes. TOD-TDR Variation Over Temperature Values for TOD and TDR track each other over temperature (1% variation for TOD-TDR per 100°C temperature variation). Therefore TOD-TDR variation over temperature is negligible. Moreover, the internal (on-chip) and package skews between each Data TODs and TDR affect can be considered as negligible.

2193A–BDC–04/03 Consequently, minimum values for TOD and TD R are never more than 100 ps apart. The same is true for the TOD and TDR maximum values. In other words: – If TOD is at 1150 ps, TDR will not be at 1620 ps (maximum time delay for TDR). – If TOD is at 1660 ps, TDR will not be at 1110 ps (minimum time delay for TDR). However, external TOD-TDR values may be dictated by total digital data skews between every TODs (each digital data) and TDR: MCM board , bonding wires and output lines lengths differences, and output termination impedance mismatches. The external (on board) skew effect has NOT been taken into account for the specification of the minimum and maximum values for TOD-TDR. Principle of Operation The Analog input is sampled on the rising edge of the external clock input (CLK, CLKB) after TA (aperture delay) of typically 250 ps . The digitized data is available after 4 clock periods latency (pipeline delay (TPD), on clock ris- ing edge, after 1360 ps typical propagation delay TOD.) The Data Ready differential output signal frequen cy (DR, DRB) is half the external clock fre- quency, that is it switches at the same rate as the digital outputs. The Data Ready output signal (DR, DRB) swit ches on the external clock falling edge after a propagation delay TDR of typically 1320 ps. A Master Asynchronous Reset input command DRRB (ECL compatible single-ended input) is available for initializing the differential Data Ready output signal (DR, DRB). This feature is mandatory in certain applicati ons using interleaved ADCs or using a single ADC with demultiplexed outputs. Actually, without Data Ready signal initialization, it is impos- sible to store the output digital data in a defined order. Principle of Data Ready Signal Control by DRRB Input Command Data Ready Output Signal Reset The Data Ready signal is reset on the falling edge of the DRRB input command, on the ECL logical low level (-1.8V). DRRB may also be tied to V EE = -5V for Data Ready output signal Master Reset. So long as DRRB remains at a logical low level, (or tied to V EE = -5V), the Data Ready output remains at logical zero and is independent of the external free running encoding clock. The Data Ready output signal (DR, DRB) is reset to logical zero after TRDR = 720 ps typical. TRDR is measured between the -1.3V point of the falling edge of the DRRB input command and the zero crossing point of the differential Data Ready output signal (DR, DRB). The Data Ready Reset command may be a pulse of 1 ns minimum time width.

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• The DRRB rising edge occurs when the external encoding clock input (CLK,CLKB) is LOW: The Data Ready output’s first rising edge occurs after half a clock period on the clock falling edge, after a delay time TDR = 1320 ps already defined hereabove.
• The DRRB rising edge occurs when external encoding clock input (CLK,CLKB) is HIGH: The Data Ready output’s first rising edge occurs after one clock period on the clock falling edge, and a delay TDR = 1320 ps. Consequently, as the analog input is sampled on the clock’s rising edge, the first digitized data corresponding to the first acquisition (N) after a Data Ready signal restart (rising edge) is always strobed by the third rising edge of the Data Ready signal. The time delay (TD1) is specified between the last point of a change in the differential output data (zero crossing point) to the rising or falling edge of the differential Data Ready signal (DR,DRB) (zero crossing point). Note: 1. For normal initialization of the Data Ready output signal, the external encoding clock signal frequency and level must be controlled. The minimum encoding clock sampling rate for the ADC is 10 Msps and consequently the clock cannot be stopped. 2. One single pin is used for both the DRRB input command and die junction temperature monitoring. Pin denomination will be DRRB/DIOD. (On former versions the denomination was DIOD.). Temperature monitoring and Data Ready control by DRRB is not possible simultaneously. Analog Inputs (VIN, VINB) The analog input Full Scale range is 0.5V, or -2 dBm into the 50Ω termination resistor. In differential mode input configuration, that means 0.25V on each input, or ±125 mV around 0V. The input common mode is ground. The typical input capacitance is 3 pF for TS8308500 in a CBGA package. Differential Input Voltage Span

Figure 28. Differential Input Voltage Span

entered either in differential mode or single-ended mode. capacitively and inductively coupled noise) as common mode effects. input pin (VINB) grounded through the 50Ω termination resistor. clock inputs in differential mode. Figure 29. Typical Single-ended Analog Input Configuration either the differential or single-ended configuration. which has been designed in order to be entered either in differential or single-ended mode. require the use of a power splitter.

1 MΩ 3 pF

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ended configuration up to 500 Msps Nyquist Conditions (FIN = 250 MHz). ground reference for the inphase clock input). low phase noise sinewave generator must be used for enhanced jitter performance. not exceed 10 dBm to avoid saturation of the preamplifier input transistors. Figure 30. Single-ended Clock Input (Ground Common Mode): Note: Do not exceed 10 dBm into the 50 Ω termination resistor for the single clock input power level. The clock inputs can be driven differentially with nominal -0.8V/-1.8V ECL levels. signals. Biasing tees can be used for offseting the common mode voltage to ECL levels. Figure 31. Differential Clock Inputs (ECL Levels)

input pin CLKB (respectively CLK) connected to -1.3V through the 50Ω termination resistor. The in-phase input amplitude is 1V, centered on -1.3V common mode. Figure 32. Single-ended Clock Input (ECL): Circuit noise immunity performance begins at design level. vides enhanced noise immunity with common mode noise rejection. celed out by these balanced differential amplifiers. of coupled noise on the active inputs. pins, which must be directly connected to the external ground plane. ure 34, Figure 35 on page 29). (outputs unterminated), around -1.2V common mode voltage.

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2193A–BDC–04/03 Three possible line driving and back-termination scenarios are proposed (assuming VPLUSD = 0V): 1. 75 Ω impedance transmission lines, 75Ω differentially terminated (Figure 33): Each output voltage varies between -1V and -1.42V (respectively +1.4V and +1V), leading to ±0.41V = 0.825V in differential, around -1.21V (respectively +1.21V) common mode for VPLUSD = 0V (respectively 2.4V) 2. 50 Ω impedance transmission lines, 50Ω differentially terminated (Figure 34): Each output voltage varies between -1.02V and -1.35V (respectively +1.38V and +1.05V), leading to ±0.33V = 660 mV in differential, around -1.18V (respectively +1.21V) common mode for VPLUSD = 0V (respectively 2.4V) 3. 75 Ω impedance open transmission lines (Figure 35): Each output voltage varies between -1.6V and -0.8V (respectively +0.8V and +1.6V), which are true ECL levels, leading to ±0.8V = 1.6V in differential, around -1.2V (respec- tively +1.2V) common mode for VPLUSD = 0V (respectively 2.4V) Therefore, it is possible to directly drive high input impedance storing registers, without terminating the 75Ω transmission lines. In the time domain, that means that the incident wave will reflect at the 75 Ω transmission line output and travel back to the generator (i.e.: the 75Ω data output buffer). As the buffer output impedance is 75Ω , no back reflection will occur. Note: This is no longer true if a 50 Ω transmission line is used, as the latter is not matching the buffer 75Ω output impedance. Each differential output termination length must be kept identical. It is recommended to decouple the midpoint of the differential termination with a 10 nF capaci- tor to avoid common mode perturbation in case of slight mismatch in the differential output line lengths. Too large mismatches (keep < a few mm) in the differential line lengths will lead to switching currents flowing into the decoupling capacitor leading to switching ground noise. The differential output voltage levels (75 Ω or 50Ω termination) are not ECL standard voltage levels, however, it is possible to drive standard logic ECL circuitry like the ECLinPS logic line from Motorola

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Figure 36. Differential Output: 75Ω Terminated Figure 37. Differential Output: 50Ω Terminated Figure 38. Differential Output: Open Loaded

2193A–BDC–04/03 Out of Range Bit An Out of Range (OR, ORB) bit that goes to logical high state when the input exceeds the pos- itive full scale or falls below the negative full scale is available. When the analog input exceeds the positive full-scale, the digital output datas remain at a high logical state, with (OR, ORB) at logical one. When the analog input falls below the negative full-scale, the digital outputs remain at a logical low state, with (OR, ORB) at logical one again. Gray or Binary Output Data Format Select The TS8308500 internal regeneration latches indecisions (for inputs very close to a latch threshold) that can produce errors in the logic encoding circuitry and lead to large amplitude output errors. This is due to the fact that the latches are regenerating the internal analog residues into logical states with a finite voltage gain value (Av) within a given positive amount of time (t): Av = exp(∆(t)/τ), where τ is the positive feedback regeneration time constant. The TS8308500 has been designed to reduce the probability of occurrence of such errors to approximately 10 -13 (targeted for the TS8308500 at 500 Msps). A standard technique for reducing the amplitude of such errors down to ±1 LSB consists in outputing the digital data in Gray code format. Though the TS8308500 has been designed to feature a bit error rate of 10 -13 with a binary output format, it is possible for the user to select between the Binary or Gray output data format, in order to reduce the amplitude of such errors when they occur, by storing Gray output codes. Digital Data format selection:

• BINARY output format if GORB is floating or V CC.
• GRAY output format if GORB is connected to ground (0V). Diode Pin K1 A single pin is used for both the DRRB input command and die junction monitoring. The pin denomination is DRRB/DIOD. Temperature monitoring and Data Ready control by DRRB is not possible simultaneously. (See “Principle of Data Ready Signal Control by DRRB Input Command” on page 23 for Data Ready Reset input command). The operating die junction temperature must be kept below 145 °C, therefore an adequate cooling system has to be set up. The diode mounted transistor measured Vbe value versus junction temperature is given below.

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Figure 39. Diode Pin K1 Figure 40. ADC Gain Control Pin K6

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Figure 43. Equivalent Data Output Buffer Circuit and ESD Protections Note: The ESD protection equivalent capacitance is 150 fF. Figure 44. ADC Gain Adjust Equivalent Input Circuits and ESD Protections Note: The ESD protection equivalent capacitance is 150 fF.

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2193A–BDC–04/03 TSEV8308500: Device Evaluation Board For complete specification, see the separate “TSEV8308500” document. General The TSEV8308500 Evaluation Board (EB) is a board which has been designed in order to facilitate the evaluation and the characterization of the TS8308500 device up to its 1.3 GHz full power bandwidth at up to 500 Msps in the commercial temperature range. The high speed of the TS8308500 requires careful attention to circuit design and layout to achieve optimal performance. This four metal layer board with internal ground plane has the adequate functions in order to allow a quick and simple evaluation of the TS8308500 ADC performances over the tempera- ture range. The TSEV8308500 Evaluation Board is very straightforward as it only implements the TS8308500 ADC, SMA connectors for input/output accesses and a 2.54 mm pitch connector compatible with HP16500C high frequency probes. The board also implements a de- embedding fixture in order to facilitate the evaluation of the high frequency insertion loss of the input microstrip lines, and a die junction temperature mea- surement setting. The board is constituted by a sandwich of two dielectric layers, featuring low insertion loss and enhanced thermal characteristics for operation in the high frequency domain and extended temperature range. The board dimensions are 130 mm x 130 mm. The board set comes fully assembled and tested, with the TS8308500 and its heatsink installed.

2193A–BDC–04/03 Package Table 7. TS8308500 Pad Description

3 D5B Inverted phase (-) digital output, bit 5

4 D4 In-phase (+) digital output, bit 4

5 D4B Inverted phase (-) digital output, bit 4

7 DR In-phase (+) Data Ready

8 DRB Inverted phase (-) Data Ready

9 D3 In-phase (+) digital output, bit 3

10 D3B Inverted phase (-) digital output, bit 3

12 D2 In-phase (+) digital output, bit 2

13 D2B Inverted phase (-) digital output, bit 2

14 D1 In-phase (+) digital output, bit 1

15 D1B Inverted phase (-) digital output, bit 1

16 D0 In-phase (+) digital output, bit 0, Least Significant Bit

17 D0B Inverted phase (-) digital output, bit 0, Least Significant Bit

18 GORG Gray or Binary data output format select

19 V CC +5V supply (double pad)

20 GND Analog ground (double pad)

22 V EE -5V analog supply (double pad)

23 V CC +5V supply (double pad)

24 GND Analog ground (double pad)

25 CLK In-phase (+) clock input (double pad)

26 GND Analog ground

27 CLKB Inverted phase (-) clock input (double pad)

28 GND Analog ground (double pad)

30 V CC +5V supply (double pad)

31 V EE -5V analog supply (double pad)

32 DIOD/DRRB Diode input for Tj monitoring/Input for asynchronous Data Ready Reset

33 GND Analog ground

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Notes: 1. GORB tied to V CC or floating: Binary output data format. GORB tied to GND: Gray output data format.

1. The common mode level of the output buffers is 1.2V below the positive digital supply.

For ECL compatibility the positive digital supply must be set at 0V (ground). in the name proportion in order to spare power dissipation.

35 GND Analog ground

36 V INB Inverted phase (-) analog input (double pad)

37 GND Analog ground (double pad)

38 GAIN ADC gain adjust input

39 V CC +5V supply (double pad)

40 V CC +5V supply

41 OR In-phase (+) Out of Range digital output

42 ORB Inverted phase (-) Out of Range digital output

43 D7 In-phase (+) digital output, bit 7, Most Significant Bit

44 D7B Inverted phase (-) digital output bit 7

45 D6 In-phase (+) digital output, bit 6

46 D6B Inverted phase (-) digital output, bit 6

Table 7. TS8308500 Pad Description (Continued)

Table 8. TS8308500 Pin Description

40 TS8308500

Figure 47. TS8308500 Pinout of CBGA68 Package

Figure 48. TS8308500 Capacitors and Resistors Implant

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Figure 49. Outline Dimensions - 68 Pins CBGA Corner balls (x4) are not connected (mechanical ball). Balls : 1.27 mm pitch on 11x11 grid.

2193A–BDC–04/03 Cross Section Figure 50. Cross Section Top side with soldered R, C devices (using solder Sn/Pb 63/37) 0.95 max 0.20 T - T - Balls side Balls Sn/Pb 63/37 AI203 substrate AI203 Ceramic Cap. Glued on substrate 0.15 (0.400) 100 pF All units in mm 50 Ω (0.20) (0.25) (2 x 0.20) (0.20) 1.45 ± 0.12

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with no external heatsink added. The typical value for Rthjc is given as 6.7°C/W (8°C/W max). nent (heatsink or PC Board). As an example, 2.0°C/W can be taken for 50 µm of thermal grease. Figure 51. CBGA68 Board Assembly Table 9. Thermal Resistance

2193A–BDC–04/03 Moisture Characteristics This device is sensitive to moisture (MSL3 according to JEDEC standard): Shelf life in sealed bag: 12 months at <40°C and <90% relative humidity (RH). After this bag is opened, devices that will be subjected to infrared reflow, vapor-phase reflow, or equivalent processing (peak package body temperature 220°C) must be:

• mounted within 198 hours at factory conditions of ≤30°C/60% RH, or
• stored at ≤20% RH Devices require baking, before mounting, if Humidity Indicator Card is >20% when read at 23°C ±5°C. If baking is required, devices may be baked for:
• 192 hours at 40 °C +5°C/-0°C and <5% RH for low-temperature device containers, or
• 24 hours at 125 °C ±5°C for high temperature device containers

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2193A–BDC–04/03 Definitions Definition of Terms (BER) Bit Error Rate Probability to exceed a specified error threshold for a sample. An error code is a code that dif- fers by more than ±4 LSB from the correct code. (BW) Full-Power Input Bandwidth (DG) Differential Gain Analog input frequency at which the fundamental component in the digitally reconstructed out- put has fallen by 3 dB with respect to its low frequency value (determined by FFT analysis) for input at full-scale. The peak gain variation (in percent) at five different DC levels for an AC signal of 20% Full- Scale peak to peak amplitude. F IN = 5 MHz (TBC). (DNL) Differential Non- Linearity The Differential Non-Linearity for an output code (i) is the difference between the measured step size of code (i) and the ideal LSB step size. DNL (i) is expressed in LSBs. DNL is the maximum value of all DNL (i). DNL error specification of less than 1 LSB guarantees that there are no missing output codes and that the transfer function is monotonic. (DP) Differential Phase Peak Phase variation (in degrees) at five differ ent DC levels for an AC signal of 20% Full- Scale peak to peak amplitude. F IN = 5 MHz (TBC). (ENOB) Effective Number of Bits Where A is the actual input amplitude and V is the full-scale range of the ADC under test. (IMD) InterModulation Distortion The two tones intermodulation distortion (IMD) rejection is the ratio of either input tone to the worst third order intermodulation products. The input tones levels are at -7 dB full-scale. (INL) Integral Non- Linearity The Integral Non-Linearity for an output code (i) is the difference between the measured input voltage at which the transition occurs and the ideal value of this transition. INL (i) is expressed in LSBs, and is the maximum value of all |INL (i)|. (JITTER) Aperture Uncertainty Sample to sample variation in aperture delay. The voltage error due to jitter depends on the slew rate of the signal at the sampling point. (NPR) Noise Power Ratio The NPR is measured to characterize the ADC performance in response to broad bandwidth signals. When using a notch-filtered broadband white-noise generator as the input to the ADC under test, the Noise Power Ratio is defined as the ratio of the average out-of-notch to the average in-notch power spectral density magnitudes for the FFT spectrum of the ADC output sample test. (NRZ) Non-Return to Zero When the input signal is larger than the upper bound of the ADC input range, the output code is identical to the maximum code and the Out of Range bit is set to logic one. When the input signal is smaller than the lower bound of the ADC input range, the output code is identical to the minimum code, and the Out of Range bit is set to logic one. (It is assumed that the input signal amplitude remains within the absolute maximum ratings). (ORT) Overvoltage Recovery Time Time to recover 0.2% accuracy at the output, after a 150% full-scale step applied on the input is reduced to midscale. SINAD - 1.76 + 20 log (A/V/2) 6.02ENOB =

2193A–BDC–04/03 (PSRR) Power Supply Rejection Ratio Ratio of input offset variation to a change in power supply voltage. (SFDR) Spurious Free Dynamic Range Ratio expressed in dB of the RMS signal amplitude, set at 1 dB below full-scale, to the RMS value of the next highest spectral component (peak spurious spectral component). SFDR is the key parameter for selecting a converter to be used in a frequency domain application (Radar systems, digital receiver, network analyzer, etc.). It may be reported in dBc (i.e.: degrades as signal level is lowered), or in dBFS (i.e.: always related back to converter full scale) (SINAD) Signal to Noise and Distortion Ratio Ratio expressed in dB of the RMS signal amplitude, set to 1 dB below full-scale, to the RMS sum of all other spectral components, including the harmonics except DC. (SNR) Signal to Noise Ratio Ratio expressed in dB of the RMS signal amplitude, set to 1 dB below full-scale, to the RMS sum of all other spectral components excluding the five first harmonics. (TA) Aperture Delay Delay between the rising edge of the differential clock inputs (CLK, CLKB) (zero crossing point), and the time at which (V IN, VINB) is sampled. (TC) Encoding Clock Period TC1 = Minimum clock pulse width (high) TC = TC1 + TC2 TC2 = Minimum clock pulse width (low) (TD1) Time Delay from Data to Data Ready Time delay from Data transition to Data Ready. (TD2) Time Delay from Data Ready to Data General expression is TD1 = TC1 + TDR - TOD with TC = TC1 + TC2 = 1 encoding clock period. (TF) Fall Time Time delay for the output Data signals to fall from 80% to 20% of delta between low level and high level. (THD) Total Harmonic Distorsion Ratio expressed in dBc of the RMS sum of the first five harmonic components, to the RMS value of the measured fundamental spectral component. (TOD) Digital Data Output Delay Delay from the falling edge of the differential clock inputs (CLK, CLKB) (zero crossing point) to the next point of change in the differential output data (zero crossing) with a specified load. (TPD) Pipeline Delay Number of clock cycles between the sampling edge of an input data and the associated output data being made available, (not taking in account the TOD). For the TS8388BF the TPD is 4 clock periods. (TR) Rise Time Time delay for the output Data signals to rise from 20% to 80% of delta between low level and high level. (TRDR) Data Ready Reset Delay Delay between the falling edge of the Data Ready output asynchronous Reset signal (DDRB) and the reset to digital zero transition of the Data Ready output signal (DR). (TS) Settling Time Time delay to achieve 0.2% accuracy at the converter output when a 80% full-scale step func- tion is applied to the differential analog input.

48 TS8308500

2193A–BDC–04/03 Ordering Information Part Number Package Temperature Range Screening Comments TSX8308500GL CBGA 68 Ambient Prototype Prototype version TS8308500CGL CBGA 68 "C" grade 0°C < Tc ; Tj < 90°C Standard TS8308500VGL CBGA 68 "V" grade -40°C < Tc ; Tj < 110°C Standard TSEV8308500GL CBGA 68 Ambient Prototype Evaluation Board (delivered with a heat sink) TSEV8308500GLZA2 CBGA 68 Ambient Prototype Evaluation Board with digital output buffers (delivered with a heat sink)

2193A–BDC–04/03 Datasheet Status These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Atmel customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Atmel for any damages resulting from such improper use or sale. Table 10. Datasheet Status customer and application validation. extended periods may affect device reliability.

Application Information

Where application information is given, it is advisory and does not form part of the specification.

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