TSS463B-TERA-9

TSS463B_04 ATMEL | Alldatasheet

Document overview

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Technical content

Features

 Fully Compliant to VAN Specification ISO/11519-3  Handles All Specified Module Types  Handles All Specified Message Types  Handles Retransmission of Frames on Contention and Errors  3 Separate Line Inputs with Automatic Diagnosis and Selection  Normal or Pulsed (Optical and Radio Mode) Coding  VAN Transfer Rate: 1 Mbit/s Maximum  SPI/SCI Interface  SPI Transfer Rate: 4 Mbits/s Maximum SCI Transfer Rate: 125 Kbits/s Maximum  Idle and Sleep Modes  128 Bytes of General Purpose RAM  14 Identifier Registers with All Bits Individually Maskable  6-source Maskable Interrupt Including an Interrupt-on-reset to Detect Glitches on the Reset Pin  Integrated Crystal or Resonator Oscillator with Internal Baud Rate Generator and Buffered Clock Output  Single +5V Power Supply  0.5 µm CMOS Technology  SO16 Package

Description

The TSS463B is a circuit that allows the transfer of all the status information needed in a car or truck over a single low-cost wire pair, thereby minimizing electrical wire usage. It can be used to interconnect powerful functions and to control and interface car body electronics (lights, wipers, power window, etc.). The TSS463B is fully compliant with the VAN ISO standard 11519-3. This standard supports a wide range of applications such as low-cost remote controlled switches, typically it is used for lamp control, up to complex, highly autonomous, distributed sys- tems that require fast and secure data transfers. The TSS463B is a microprocessor-interfaced line controller for mid-to-high complexity bus-masters and listeners like dashboard controllers, car stereo or mobile telephone CPUs. The microprocessor interface consists of a 256-byte RAM and a register area divided into 11 control registers, 14 channel register sets and 128 bytes of general-purpose RAM, used as a message storage area, and a 6-source maskable interrupt. The circuit operates in the RAM using DMA techniques, controlled by the channel and control registers. This allows virtually any microprocessor, including SPI/SCI interface, to be connected with ease to the TSS463B. Messages are encoded in enhanced Manches ter code, and an optional pulsed code for use with an optical or radio link, at a maximum bit rate of 1 Mbit/s. The TSS463B analyzes the messages received or transmitted according to 6 different criteria includ- ing some higher level checks. In addition, the bus interface has three separate inputs with automatic source diagno- sis and selection, allowing for multibus listening or the automatic selection of the most reliable source at any time if several line receivers are connected to the same bus. VAN Data Link Controller with Serial Interface TSS463B

4102E–AUTO–12/04 Block Diagram

4102E–AUTO–12/04 Pin Configuration 1 16 21 5 31 4 41 3 51 2 6 11 71 0 8 9 MISO SS INT RESET VDD XTAL1 XTAL2 TEST/VSS CKOUT MOSI SCLK GND TXD RXD0 RXD2 RXD1 TOP VIEW Pin Description I/O Type Pin Name Pin No Pin Function O 3-state MISO 1 SPI/SCI Data Output I trigger CMOS SS

2 SPI/SCI Slave Select (active low)

Open-drain INT 3 Interrupt (active low) Power VDD 4 + 5V power supply I CMOS XTAL1 5 Crystal oscillator or clock input pin O XTAL2 64 Crystal oscillator output pin Ground TEST/VSS 7 Test mode input O CKOUT 8 Buffered clock output I CMOS Pull-down RXD1 9 VAN bus input 1 I CMOS Pull-down RXD2 10 VAN bus input 2 I CMOS Pull-down RXD0 11 VAN bus input 0 O 3-state TXD 12 VAN bus output Ground GND 13 I trigger CMOS pull-up RESET

14 Hardware Reset (active low)

I trigger CMOS SCLK 15 SPI/SCI Clock Input I trigger CMOS MOSI 16 SPI/SCI Data Input

face to virtually any microprocessor that includes SPI or SCI interface.  The TSS463B provides one full Motorola© compatible SPI interface.  One 9-bits SCI interface is also integrated. Figure 1. Typical Application With Motorola SPI Mode or the µC RESET pin or unconnected (inactive with internal pull-up).

1. Leaving MISO output pin floating in high impedance mode slightly increases standby

consumption. A 100KΩ pullup/pulldown resistor is recommended.

circuit. These registers appear to the processor as regular memory locations. tion provides information switching from one mode to another. Figure 2. Mode Configuration Byte erate SPI frames by itself).

Figure 4. CPOL and CPHA in the TSS463B Address + n with n = 0 to 28). interface or can assert the RESET pin active or can send an initialization sequence. whether it is a TSS463B Write or Read. Table 1. SPI Control Byte The seven following bits are reserved and must be equal to: 1100000. ’0xAA’during the address byte and ’0x55’during the control byte on its MISO line.

high level at the end of the SCI frame. driven to the serial data register. too (9th bit always equal to 1). SCI Control Byte Same as the SPI control byte. interframe spacing must be apply according to XTAL clock. Intel and Motorola SPI Modes Within an SPI byte, the maximum speed allowed on the MOSI line is 4 Mbits/s. siderations are detailed in Figure 7. Figure 7. SPI Speed Considerations SCI Mode Within an SCI 9-bits data, the maximum speed allowed on the MOSI line is 125 Kbits/s. between SCI bytes are shown in Figure 8.

12 Xtal Min8 Xtal Min 15 Xtal Min4 Xtal Min

4 Mbits/s Max for SCLK

Figure 8. SCI Speed Considerations request is controlled by the internal registers. with processors that have either edge or level sensitive interrupt inputs. Reset The reset is applied asynchronously or synchronously to the XTAL clock. (software asynchronous reset). 1 µF capacitor to GND provides to RESET pin an efficient behavior. “Motorola SPI Mode” on page 5. the TSS463B in the right mode. permanent reset after applying Reset. SCI mode (because the default mode after a hardware reset is the Motorola SPI mode).

12 Xtal Min

15 Xtal Min

125 Kbits/s Max for SCLK

8 Xtal Min4 Xtal Min

Figure 9. Asynchronous Software Reset with UART Intel Mode the input is XTAL1 and the output XTAL2. the schematic given in Figure 39. Note that this pin will behave as a CMOS level compatible Schmitt trigger input. XTAL1 input, without inversion. tor will not operate correctly. tory use, and the functionality of this mode is not specified in any way. ing inspection tests using the test program. code called the clock divider.

4 XTAL Min

Table 2. Clock Divider

8 MHz 6 MHz 4 MHz 2 MHz

able input according to the results. bus is also received simultaneously. (for the higher priority messa ge) collision detection. Figure 10. CSMA/CD Arbritration is imposed on the RxD0 input, and the diagnosis system does not operate correctly. ceivers are not able to receive the signal that they transmit.

4102E–AUTO–12/04 At this point there could be several modules transmitting on the bus, and there is no possibility of knowing if this is the case or not. Therefore, the first field in that arbitration can be performed is the identifier field. Since the logical zeroes on the bus are dominant, and all data is transmitted with the most significant bit (MSB) first, the first module to transmit a logical zero on the bus will be the prioritized module, i.e., the message that is tagged with the lowest identifier will have priority over the other messages. It is, however, possible that two messages transmitted on the bus will have the same identifier. The TSS463B, therefore, continues the arbitration of the bus throughout the whole frame. Moreover, if the identifier in transmission has been programmed for recep- tion as well, it transmits and receives messages simultaneously, right up until the Frame Check Sequence (FCS). Only then, if the TSS463B has transmitted the whole message, it discards the message received. Arbitration loss in the FCS field is considered as a CRC error during transmission. This feature is called full data field arbitration, and it enables the user to extend the iden- tifier. For instance it can be used to transmit the emitting modules address in the first bytes of the data field, thus enabling the ident ifier to specify the contents of the frame and the data field to specify the source of the information. The identifier field of the VAN bus frame is always 12 bits long, and it is always followed by the 4-bit command field:  The first bit of the command is the extension bit (EXT). This bit is defined by the user on transmission and is received and retained by the TSS463B. To conform with the standard, it should be set to 1 (recessive) by the user, else the frame is ignored without any IT generation.  The second bit is the request ACKnowledge bit (RAK). If this bit is a logical one, the receiving module must acknowledge the transfer with an in-frame acknowledgement in the ACK field. If it is set to logical zero, then the ACK field must contain an acknowledge absent sequence.  The third bit is the Read/Write (R/W). This bit indicates the direction of the data in a frame. – If set to zero, it is a ‘write’ message, i.e., data transmitted by one module to be received by another module. – If it is set to one, it implies a ’read’ message, i.e., a request that another module should transmit data to be received by the one that requested the data (reply request message).  Last in the command field is the Remote Transmission Request bit (RTR). This bit is a logical zero if the frame contains data and a logical one if the frame does not contain data. In order to conform with the standard a received frame included the combination R/W. RTR = 01 is ignored without any IT generation. All the bits in the command field are automatically handled by the TSS463B, so the user does not need to be concerned for encoding and decoding these bits. The command bits transmitted on the VAN bus are calculated from the current status of the active message. After the command field comes the data field. This is just a sequence of bytes transmit- ted MSB first. In the VAN standard, the maximum message length is set to 28 bytes, but the TSS463B handles messages up to 30 bytes. The next field is the FCS field. This field is a 15 bit CRC checksum defined by the follow- ing generator polynomial g(x) of order 15: g(x)= x 15 + x11 + x10 + x9 + x8 + x7 + x4 + x3 + x2 + 1

is performed before transmission. sequence (EOF) to terminate the transfer. Figure 16. Acknowledge Sequences master (not shown in the figure). slave module can transmit data by filling it into the appropriate field. compared to the normal frame. are all generated by the replying module. only if this was requested by the initiator through the RAK bit. prepared a reply for a reply request that has been received before. the R/W bit that has changed state.

Figure 17. Normal Data Frame

Figure 20. Deferred Reply Frame

connected to the VAN bus see Figure 1. DATA signals, and is connected to the RxD0 input. (Synchronous Diagnosis Clock) and TIP (Transmission In Progress). nominal mode and re-connects the differential line receiver to the reception logic. A major error occurs when both the VAN bus signals are failed. Figure 21. Diagnosis States

• Default of transitions on the valid input between 2 consecutive SDC rising edges.
• In specified selection mode, every RI pulse when an EOF is detected or through an active SDC.
• In automatic selection mode and SDC active, no failure sampled by 2 consecutive SDC rising edges.

grammed operating mode. This is encoded over three bits: Sa, Sb and Sc.  Sa and Sb bits indicate the four possible states of the VAN bus. Table 3. Status Bits: Sa and Sb in the input comparison analysis performs by the diagnosis system, Sc is set. The only way to reset this status bit is through the RI signal or a general reset. may be corrupted. To avoid such errors, digital filters are implemented. taken into account only if it is observed over five samples (1/16th of timeslot). connected to the reception logic during one SDC period. change to the major error mode.

4102E–AUTO–12/04  Transmission diagnosis The transmission compares RxD1 and RxD2 inputs (through the input comparators and the filters) with the data transmitted on TxD output. At a time when the transmission logic generates a dominant - recessive transition, the inputs can give different values. Taking into account the filtering delay, the bus line seen as dominant is assumed to be correct, the other one, recessive, is considered faulty. The diagnosis mode is changed to reflect that.  Protocol fault The protocol fault is detected by counting the number of consecutive dominant timeslots. If eight consecutive timeslots are dominant, the diagnosis mode will change to the major error mode. Generation of Internal Signals RI Signal (Return to Idle) This signal is used to return to nominal mode in the three specified selection modes (see “Diagnosis States” on page 22 and “Programming Modes” on page 25). The RI signal is disabled in automatic selection mode. The RI signal is a pulse generated when an EOF is detected. Thus, at the end of each frame, regarding the diagnosis status bit Sa, Sb and Sc, the user can make its own choice. SDC Signal (Synchronous Diagnosis Clock) This time base is used by diagnosis sy stem in automatic selection mode (see Section “Programming Modes”, page 25) when no event is recorded on the bus. The SDC is generated either by a special SDC divider connected to the timeslot clock, or can be performed manually. The SDC clock period must be long compared to the timeslot duration. A typical SDC period should be greater than the maximum frame length appearing on the VAN network. TIP Signal (Transmission in Progress) This signal must be enabled to allow the transmission diagnosis (see Section “Transition Analyses”, page 23). The TIP turns on synchronously with the beginning of the transmission:  for asynchronous bus access, the beginning of SOF;  for synchronous bus access, the beginning of the identifier field; and  for a request of in frame reply, the RTR bit of the command field. The TIP turns off synchronously with the end of the transmission: a f t e r E O F ;  after a losing of arbitration or a code violation detection; and  for a requestor of in frame reply, when the arbitration is lost on RTR the bit. This signal is not generated when the transmission logic only sends an ACK.

Table 4. Programming Modes

registers, the Channel registers and the Message data (or Mailbox). Figure 22. Memory Map Notes: 1. All the non specified addresses between 0x00 and 0x7F are considered as absent.

1. (r) means read only register.

(w) means write only register. (r/w) means read/write register.

1. Value after RESET is found after register name. If no value is given, the register is not initialized at RESET.

4102E–AUTO–12/04 Control and Status Registers Line Control Register (0x00)  Read/write register.  Default value after reset: 0 ×00  Reserved: Bit 2, this bit must not be set by the user; a 0 must always be written to this bit. CD[3:0]:Clock Divider They control the VAN Bus rate through a Baud Rate generator according to the formula below: PC: Pulsed Code One : The TSS463B will transmit and receive data using the pulsed coding mode (i.e optical or radio link mode). The use of this mode implies communication via the RxD0 input and the non-functionality of the diagnosis system. Zero: (default at reset) The TSS463B will transmit and receive data using the Enhanced Manchester code. (RxD0, RxD1, RxD2 used). IVTX: Invert TxD output IVRX: Invert RxD inputs The user can invert the logical levels used on either the TxD output or the RxD inputs in order to adapt to different line drivers and receivers. One: A one on either of these bits will invert the respective signals. Zero: (default at reset) The TSS463B will set TxD to recessive state in Idle mode and consider the bus free (recessive states on RxD inputs). Transmit Control Register (0x01)  Read/Write register.  Default value after reset: 0x02 MR[3:0]: Maximum Retries These bits allow the user to control the amount of retries the circuit will perform if any errors occurred during transmission. 76543210 CD3 CD2 CD1 CD0 PC 0 IVTX IVRX fT S C L K() fX T A L1() 76543210 MR3 MR2 MR1 MR0 VER2 VER1 VER0 MT

Table 5. Retries attempts will be performed if bus contention occurs continuously. VER[2:0] = 001 DLC Version after reset. These bits must not be set by user. 001 must always be written to these bits. module (Rank 1) or a slave module (Rank 16).  Default value after reset: 0 ×00.  In its two medium order bits, the diagnosis system mode is controlled: M1, M0.

SDC [3:0]: SDC Divider The input clock is the timeslot clock. Table 6. System Diagnosis Clock Divider SDC calculation: (see “SDC Signal (Synchronous Diagnosis Clock)” on page 24). Notes: 1. For each module, determine the largest interframe spacing, LIFS (*).

1. For the whole network, get the maximum LIFS, MAX-LIFS.

4102E–AUTO–12/04 ETIP: Enable Transmission In Progress The Transmission In Progress (TIP) tells the diagnosis system to enable transmission diagnosis. One: Enable TIP generation Zero: Disable TIP generation. ESDC: Enable System Diagnosis Clock The Synchronous Diagnosis Clock (SDC) controls the cycle time of the synchronous diagnosis. One: Enable SDC divider. Zero: Disable SDC divider. Command Register (0x03)  Write only register.  Reserved: Bit 1, 2. These bits must not be set by the user; a zero must always be written to these bit.  If the circuit is operating at low bitrates, there might be a considerable delay between the writing of this register and the performing of the actual command (worst case 6 timeslots). The user is therefore recommended to verify, by reading the Line Status Register (0x04), that the commands have been performed. GRES: General Reset The Reset circuit command bit performs, if se t, exactly as if the external reset pin was asserted. This command bit has its own auto-reset circuitry. One: Reset active Zero: Reset inactive SLEEP: Sleep command (Section “Sleep Command”, page 51). If the user sets the Sleep bit, the circuit will enter sleep mode. When the circuit is in sleep mode, all non-user registers are setup to mini- mize power consumption. Read/write a ccesses to the TSS463B via the SPI/SCI interface are impossible, the oscillator is stopped. To exit from this mode the user must appl y either an hardware reset (external RESET pin) either an asynchronous software reset (via the SPI/SCI interface). One: Sleep active Zero: Sleep inactive IDLE: Idle command (Section “Idle and Activate Commands”, page 51). If the user sets the Idle bit, the circuit will enter idle mode. In idle mode the oscillator will operate, but the TSS463B will not transmit or receive anything on the bus, and the TxD output will be in tri-state One: Idle active Zero: Idle inactive ACTI: Activate command (Section “Idle and Activate Commands”, page 51). The Activate command will put the circuit in the active mode, i.e it will transmit and receive normally on the bus. When the circuit is in activate mode the TxD tri-state output is enabled. One: Activate active Zero: Activate inactive 76543210 GRES SLEEP IDLE ACTI REAR 0 0 MSDC

messages to be transmitted in order to find the highest priority message to transmit. pulse for the diagnosis system. This MSDC pulse should be high at least 2 timeslot clocks.  Default value after reset: 0bx01xxx00. IDG: Idling Default mode at reset. Table 8. Diagnosis System Status Bits in the input comparison analysis performed by the diagnosis system, Sc is set. The only ways to reset this status bit is through the RI signal or a general reset. or the retry count is exceeded. RXG: Receiving The receiving indicates that there is activity on the bus.

4102E–AUTO–12/04 Transmission Status Register (0x05)  Read only register.  Default value after reset: 0x00.  The transmission Status register contains the number of retries made up-to-date, according to the Table 5., and the channel currently in transmission. NRT [3:0] Number of retries done in transmission. IDT [3:0] Channel number currently in transmission. Last Message Status Register (0x06)  Read only register.  Default value after reset: 0x00.  This register is basically the same as the transmission status register. It contains the last identifier number that was successfully transmitted, received or exceeded its retry count. If it was a successful transmission, the number of retries performed can be seen in this register as well. NRTR [3:0] Number of retries done successfully in transmission. In case of reception NRTR[3:0] is undefined. IDTR [3:0] Channel number that was successfully transmitted, received or exceeded its retry count. Last Error Status Register (0x07)  Read only register.  Default value after reset: 0 ×00.  The Last Error Status Register contains the error code for the last transmission or reception attempt. It is updated after each attempt, i.e. several error codes can be reported during one single transmission (with several retries). BOC: Buffer occupied  when one channel configured in “Reply request” mode has its “received” bit set when it attempts to transmit its request.  BOC with the link capability between two channels sharing the same received buffer, is set when one channel has already set its “received” bit in its “Message length and status Channel register” and a receive is attempt on the other one. One: BOC active Zero: BOC inactive 76543210 NRT3 NRT2 NRT1 NRT0 IDT3 IDT2 IDT1 IDT0 76543210 NRTR3 NRTR2 NRTR1 NRTR0 IDTR3 IDTR2 IDTR1 IDTR0 76543210 X BOC BOV X FCSE ACKE CV FV

than the number of bytes received plus 1, and thus, some data was lost. Figure 23. ACKE Status Bit

4102E–AUTO–12/04 RE: Receive Error Status Flag One: Status flag activated Zero: No status flag. ROK: Receive “with RAK (RAK=1)” OK Status Flag One: Status flag activated Zero: No status flag. RNOK: Receive “with no RAK (RAK=0)” OK Status Flag One: Status flag activated Zero: No status flag. Interrupt Enable Register (0x0A)  Read/write register.  Default value reset: 1xx0 0000 Note: On reset, the Reset Interrupt Enable bit is set to 1 instead of 0, as is the general rule. TEE: Transmit Error Enable One: IT enabled. Zero: IT disabled. TOKE: Transmission OK Enable One: IT enabled. Zero: IT disabled. REE: Reception Error Enable One: IT enabled. Zero: IT disabled. ROKE: Reception “with RAK” OK Enable One: IT enabled. Zero: IT disabled. RNOKE: Reception “with no RAK” OK Enable One: IT enabled. Zero: IT disabled. Interrupt Reset Register (0x0B):  Write only register.  Reserved bit: 5 and 6. This bit must not be set by user; a zero must always be written to this bit. RSTR: Reset Interrupt Reset One: Status flag reset. Zero: Status flag unchanged. TER: Transmit Error Status Flag Reset One: Status flag reset. Zero: Status flag unchanged. TOKR: Transmit OK Status Flag Reset One: Status flag reset. Zero: Status flag unchanged. 76543210

1 X X TEE TOKE REE ROKE RNOKE

RSTR 0 0 TER TOKR RER ROKR RNOKR

Zero: Status flag unchanged. Zero: Status flag unchanged. Zero: Status flag unchanged. Figure 26. Update of the Status Register

4 TS 1 to 2 TS 6 TS

pointers and message status. channel registers start with random values. received and transmitted bits to 1 in the Message Length and Status Register. Table 9. Channel Register Sets Map Table 10. Channel Register Set Structure

4102E–AUTO–12/04 Identifier Tag and Command Registers The identifier tag and command registers are located at the base_address and base_address + 1. It allows the user to specif y the full 12-bit identifier field of the ISO standard and the 4-bit command.  Read/Write registers. ID_T [11:0]: Identifier Tag Upon a reception hit (i.e, a good comparison between the identifier received and an identifier specified, taking the comparison mask into account, as well as a status and command indicating a message to be received), the identifier tag bits value will be rewritten with the identifier bits actually received. EXT, RAK, RNW and RTR (See Section “Message Types”, page 44). No comparison will be done on the command bits, except on EXT bit. The RAK, RNW and RTR bits will be written into the first byte of the Message upon a reception hit. The RNW and RTR bits, as well as the status bits in the length and status register, must be in a valid position for reception or transmission. If not, the message corresponding to this identifier is considered as inactive or invalid. The way of knowing if an acknowledge sequence was requested or not is to check the first byte of the Message. Message Pointer Register The message pointer register at address (base_a ddress + 0x02) is 8 bits wide. It indi- cates where in the Message DATA RAM area the message buffer is located.  Read/Write register. DRAK: Disable RAK (Used in ‘Spy Mode’) In reception: whatever is the RAK bit of the incoming valid frame, no ACK answer will be set. If the message was successfully received, an IT is set (ROK or RNOK). In transmission: no action. One: disable active, “spy mode”. Zero: disable inactive, normal operation. M_P [6:0]: Message Pointer Since the Message DATA RAM area base address is 0x80, the value in this register is the offset from that address. If the message buffer length value is illegal (i.e. zero), this register is redefined as being a link pointer, thus containing the channel number of the channel that contains the actual message pointer, message length and received status. However, the identifier, mask, error and transmitted status used will be that of the origi- nally matched channel. In any case, if a link is intended, the three high bits of M_P [6:0] should be set to 0. This allows several channels to use the same actual reception buffer in Message DATA RAM, thus diminishing the memory usage. Note: Only 1 level of link is supported. 76543210 ID_T 3 ID_T 2 ID_T 1 ID_T 0 EXT RAK RNW RTR base_address + 0x01 76543210 ID_T 11 ID_T 10 ID_T 9 ID_T 8 ID_T 7 ID_T 6 ID_T 5 ID_T 4 base_address + 0x00 76543210 DRAK M_P 6 M_P 5 M_P 4 M_P 3 M_P 2 M_P 1 M_P 0 base_address + 0x02

4102E–AUTO–12/04 Message Length And Status Register The message length and status register at address (base_address + 0x03) is also 8 bits wide. It indicates the length of reserved for the message in the Message DATA RAM area.  Read/Write register. M_L [4:0]: Message Length The 5 high bits of this register allows the user to specify either the length of the message to be transmitted, or the maximum length of a message receivable in the pointed recep- tion buffer. Note: The first byte in this register does not contain data, but the length of the message received. This implies that the length value has to be equal to or greater than the maxi- mum length of a message to be received in this buffer (or the length of a message to be transmitted) plus 1, thus allowing a maximum length of 30 bytes and a minimum length of 0 byte. If the value of this field is “illegal” (i.e 0x00) then this message pointer is defined as being a link (see Message pointer and register and “Linked Channels” on page 52). CHER: Channel Error Status and Abort Command As status, this bit is set by the TSS463B when error occurs in transmission or on a received frame. The user must reset it. To abort the transmission defined in the channel, this bit can be set to 1 by the user (see Section “Activate, Idle and Sleep Modes”, page 51 and “Abort” on page 49) CHTx: Channel Transmitted and Transmit Enable Command CHRx: Channel Received and Receive Enable Command The 2 low order bits of this register contain the message status. Together with the RNW and RTR bits of the command register (base_address + 0x01), they define the message type of this channel (see section “Message Types” on page 44). As a general rule, the status bits are only set by the TSS463B, so the user must reset them to perform a trans- mission (CHTx) or/and a reception (CHRx). The received and transmitted bits are only set if the corresponding frame is without errors or if the retry count has been exceeded. 76543210 M_L 4 M_L 3 M_L 2 M_L 1 M_L 0 CHER CHTx CHRx base_address + 0x03 M_L [4:0] = 0x00 Linked channel M_L [4:0] = 0x01 Frame with no DATA field (1) M_L [4:0] = 0x02 Frame with 1 DATA byte M_L [4:0] = 0x1D Frame with 28 DATA bytes M_L [4:0] = 0x1E Frame with 29 DATA bytes M_L [4:0] = 0x1F Frame with 30 DATA bytes Note: 1. Different of a reply request frame wit h no in-frame reply (deferred reply).

4102E–AUTO–12/04 Identifier Mask Registers The Identifier Mask registers (base_address + 0x06 and base_address + 0x07) allow bitwise masking of the comparison between the identifier received and the identifier specified.  Read/Write registers. ID_M [11:0]: Identifier Mask A value of 1 indicates comparison enabled. A value of 0 indicates comparison disabled. Example: – ID_M[11:0] = 0x0FF8 – Acceptance: ID’s from 0x0FF8 up to 0x0FFF 76543210 I D _ M 3 I D _ M 2 I D _ M 1 I D _ M 0 xxxx base_address + 0x07 76543210 ID_M 11 ID_M 10 ID_M 9 ID_M 8 ID_M 7 ID_M 6 ID_M 5 ID_M 4 base_address + 0x06

0xFF (see Section “Mapping”, page 26 ). Figure 27. Message Buffer Structure for Reception

Figure 28. Message Buffer Structure for Transmission RRAK: Received RAK Bit This bit is the RAK bit coming from the COM field of the received frame. RRNW: Received RNW Bit This bit is the RNW bit coming from the COM field of the received frame. RRTR: Received RTR Bit This bit is the RTR bit coming from the COM field of the received frame. even if the reserved length (Message Length and Status Register) is larger.

Figure 29. Message Status Updating Note: 1. After IT ROK or RNOK. In case of IT RE, the values can be erroneous. DATA0 is the first received (or transmitted) byte, DATAn is the last one.

1. The Mailbox RAM area is a circular buffer. The next location after 0xFF is 0x80.

4102E–AUTO–12/04 Message Types There are 5 basic message types defined in the TSS463B. Two of them (transmit and receive message types) correspond to the normal frame, and the rest correspond to the different versions of reply frames. To transmit a normal data frame on the VAN bus, the user must program an identifier as a Transmit Message. The TSS463B will then transmit this message on the bus until it has succeeded or the retry count is exceeded. The opposite of the transmit message type is the Receive Message type. This message type will not generate any frames on the bus. Instead, it will listen to the bus until a frame passes that matches its identifier, with the mask taken into account, and then receive the data in that frame. The data received will be stored in the message buffer and the length of the message received is stored in the first byte of the message buffer. The actual identifier received is stored in the identifier register itself. This identifier may differ from the identifier specified in the register due to the effect of the mask register. Normally this should not interfere with the next identifier comparison since the bits that may differ are masked via the mask register. The Reply Request Message type is a demand to transmit on the VAN bus a reply request. When this message type is programmed, three things can happen. In the first case no other modules on the bus responded with an in-frame reply, and in this case the TSS463B will set the message type to the after transmission state. When this message type is programmed, the TSS463B will listen on the bus for a deferred reply frame matching this identifier, without transmitting the reply request. Transmit Message RNW RTR CHTx CHRx Initial setup 0 0 0 Don’t care After transmission 0 0 1 Unchanged Receive Message RNW RTR CHTx CHRx Initial setup 0 1 Don’t care 0 After transmission 0 1 Unchanged 1 Reply Request Message RNW RTR CHTx CHRx Initial setup 1 1 0 0 After transmission (Waiting for reply) 11 1 0 After reception (of reply) 11 1 1

4102E–AUTO–12/04 The second case is that another module on the bus replies with an in-frame reply. In this case the message type will pass immediately into the after reception state, without pass- ing the after transmission state. In the third case the TSS463B has not yet started to transmit the reply request, when another module either requests a reply, and gets it, or transmits a deferred reply. Warn- ing! This should be avoided as it may re sult in an illegal message type (Illegal reply Request). The immediate Reply Message will attempt to transmit an in-frame reply, using the data in the message buffer. Above a Deferred Reply Message is shown. This message type will immediately trans- mit a deferred reply frame. Finally there is the Reply Request Detector Message type. Its purpose is to receive a reply request frame and notify the processor, without transmitting an in-frame reply. The table above shows all inactive messages types. The last combination will transmit a reply request, but will not receive the reply since its buffer is tagged as occupied. Reply Request Message without transmission RNW RTR CHTx CHRx Initial setup 1 1 Don’t care 0 After reception 1 1 Unchanged 1 Immediate Reply Message RNW RTR CHTx CHRx Initial setup 1 0 0 0 After transmission 1 0 1 1 Deferred Reply Message RNW RTR CHTx CHRx Initial setup 1 0 0 1 After reception (of reply request) 10 1 1 Reply Request Detection Message RNW RTR CHTx CHRx Initial setup 1 0 1 0 After reception 1 0 1 1 Inactive Message RNW RTR CHTx CHRx Recommended Don’t care Don’t care 1 1 After transmission 0 0 1 Don’t care After reception 0 1 Don’t care 1 Illegal reply request 1 1 0 1

tion. The priorities for the messages in the TSS463B is however slightly different. that will receive the message. will be received by identifier 10. three commands are available only when the TSS463B is producer. Figure 30. Transmit Function

4102E–AUTO–12/04 Retries The purpose of the retries feature is to provide, for the user, the capability of retrying a transmit request in case of failure, when a node tries to reach another node, either on normal DATA frame or on REPLY REQUEST frame. The maximum number of retries is programmable through MR[3:0] of the Transmit Con- trol Register (0x01). When a channel is enable - bit CHTx = 0 of Message Length and Status Register, a 4-bit counter is loaded with MR[3:0]. At each attempt, this counter will count-down to 0, an IT TE is set in the Interrupt Status Register (0x09), and the trans- mission is stopped. MR[3:0] = 1 indicates 1 retry, hence 2 transmission attempts will be performed (see Table 5, “Retries,” on page 28). The number of retries performed, as well as the current channel number associated, can be read in the Transmission Status Register (0x05). The Last Error Status Register (0x07) informs about the trouble uncounted:  Failure cases: – Code viol (CV error bit) – Acknowledge error (ACKE error bit) – CRC error (FCSE error bit)  It should be noticed that contention is considered as normal CSMA/CD protocol and, therefore, is not taken into account in failure cases. So, an 'infinite' number of attempts can be performed if bus contention occurs continuously. There is only one retry counter for all channels. When the user writes the Max_Retries value, all channels start their transmission with this parameter. Rearbitrate The purpose of rearbitrate feature is to postpone a channel already in transmission in order to authorize an higher priority (see Section "Priority Among the Different Chan- nels", page 46) message to be transmit. Typical Example  Max_retries = 1 (2 transmissions attempts).  If Ch8 is in a the retry loop and the user wants to transmit the Ch5 without waiting the end of the loop, the user can use the rearbitrate command.  The TSS463B will then wait until the end of the current transmission, reload the retries counter and enable the Ch5 to transmit.  At the end of this transmission Ch5, either when the attempt is successful or the exceeded retry count is reached, the retries counter is reloaded and the transmission is activated for the Ch8 again.

Figure 33. Disable Channel After Rearbitrate validated), otherwise it stops all attempts on the current channel. 1 the Transmitted bit (CHTx) of the Message Length and Status Register. priority and retries live together in the transmit function. (1) The disable is applied setting the CHTx/Ch8 bit to 1.

Figure 34. Abort Example

12 T imeslots

three commands are general commands for the TSS463B. (CKOUT pin active) but the circuit cannot transmit or receive anything on the VAN bus. TSS463B, the user must set the activate bit (ACTI) and reset the idle bit (IDLE). Figure 35. Idle and Activate Timings In both cases, the idle state can be verified reading the Line Status register (0x04). either an asynchronous software reset (via the SPI/SCI interface). does not run and the only way to awake this application is an external reset.

3 TS 8 TS

5 TS4 TS

channel linked to another channel. the register set of this other Channel. be linked to the Channel i but not to Channel j, already defined as linked to Channel i. All the others can be different between the two channels, for example the ID_Tag. Figure 36. Linkage Mechanism cial communications between the different nodes of the network.

4102E–AUTO–12/04

Electrical Characteristics

Ambient temperature under bias: *NOTICE: Stresses at or above those listed under Absolute Maximum Ratings may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions exceeding those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Table 11. TA = -40°C to 125°C; VCC = 5 V + 10%; VSS = 0 V Notes: 1. Sleep Mode I CCSB is measured according to a VSS Clock Signal.

1. Active mode I CCOP is measured at: XTAL = 8 MHz clock, VAN speed rate = 125 KTS/s.
2. I CC is a function of the Clock Frequency. Figure 38 displays a graph showing ICC versus Clock frequency.
3. RESET , RxD0, RxD1, RxD2 inputs.

4102E–AUTO–12/04 AC Characteristics Table 12. Microprocessor Inrterface CLOAD = 200pF on SPI/SCI lines TA = -40°C to 125°C; VCC = 5V + 10%; VSS = 0V Note: 1. Simulated Data Symbol Characteristic Min Max Unit fOP Operating Frequency SPI SCI dc dc 125 MHz kHZ CYC Cycle Time SPI SCI 250 ns ms LEAD Enable Lead Time 4 - XTAL Period 3t LAG Enable Lead Time 12 - XTAL Period 4t W(SCKH) Clock (SCLK) High Time 100 - ns 5t W(SCKL) Clock (SCLK) Low Time 100 - ns 6 tSU Data Setup Time (Inputs) 40 - ns 7t H Data Hold Time (Inputs) 40 - ns 8t A Slave Access Time (Time to Data Active from High-Impedance State) 0 100 ns DIS Slave Disable Time (Hold Time to High- Impedance State) - 200 ns 10 t V Data Valid (After Enable Edge) - 60 ns 11 t HO Data Hold Time (Outputs After Enable Edge) 0 - ns 12 t IZIL (1) INT Float Pulse Width 20 ns A SS (INPUT) MISO (OUTPUT) MOSI (INPUT) SCLK (INPUT) INT float pulse only when address is 0x08 to 0x0B IZIL t CYCt LEADt W(SCKL)t W(SCKH)t FLAG DISt HOtVtHSUt t IZILt t

4102E–AUTO–12/04 Interface Oscillator Characteristics Figure 39. C2 versus Frequency Note: C1 (no capacitance needed) see Figure 5. External Clock Drive Characteristics (XTAL1) 200 100 12 48 MHz pF Symbol Parameter Min Max Unit tCHCH Oscillator period 120 ns tCHCX High Time 20 ns tCLCX Low Time 20 ns tCLCH Rise Time 20 ns tCHCL Fall Time 20 ns t CHCX tCLCX tCHCH XTAL1 VIH VIL tCLCHtCHCL VIH VIH VIL

4102E–AUTO–12/04 Packaging Information SO16 SO MM Inch A 2.35 2.65 0.093 0.104 A1 0.10 0.30 0.004 0.012 B 0.35 0.49 0.014 0.019 C 0.23 0.32 0.009 0.013 D 10.10 10.50 0.398 0.413 E 7.40 7.60 0.291 0.299 e 1.27 BSC 0.050 BSC H 10.00 10.65 0.394 0.419 h 0.25 0.75 0.010 0.029 L 0.40 1.27 0.016 0.050 N1 6 1 6 a0 ° 8° 0° 8°

4102E–AUTO–12/04

Ordering Information

Note: 1. These products are available in ROHS version. Part Number Supply Voltage Temperature Range Package Packing TSS463B-TESA-9 5V + 10% -40°C - +125°C SO16 Stick TSS463B-TERA-9 5V + 10% -40°C - +125°C SO16 Tape and Reel TSS463B-TERZ-9(1) 5V + 10% -40°C - +125°C SO16 Tape and Reel

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