TSS461C

TSS461C_04 ATMEL | Alldatasheet

Document overview

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Technical content

Features

 Fully Compliant to VAN Specification ISO/11519-3  Handles All Specified Module Types  Handles All Specified Message Types  Handles Retransmission of Frames on Contention and Errors  3 Separate Line Inputs with Automatic Diagnosis and Selection  1 Mbit/s Maximum Transfer Rate  Normal or Pulsed (Optical and Radio Mode) Coding  Intel®, NEC®, Texas Instruments® and Motorola® Compatible 8-bit Microprocessor Interface  Multiplexed Address and Data Bus  Idle and Sleep Modes  128 Bytes of General-purpose RAM  DMA Capabilities for Message Handling  14 Identifier Registers with All Bits Individually Maskable  6-source Maskable Interrupt, Including an Interrupt-on-reset to Detect Glitches on the Reset Pin  Integrated Crystal or Resonator Oscillator with Internal Baud Rate Generator and Buffered Clock Output  Single +5V Power Supply  0.8 µm CMOS Technology  SO24 Package

Description

Cost optimization in car manufacturing is of extreme importance today. Solutions to this problem often implies the use of more advanced and intelligent electronic circuits. The TSS461C is a circuit which allows the transfer of all the status information needed in a car or truck over a single low-cost wi re pair, that minimizes the electrical wire usage. It can be used to interconnect powerful f unctions (ABS, dashboar d, power train con- trol) and to control and interface car body electronics (lights, wipers, power window, etc.). The TSS461C is fully compliant with the ISO Standard 11519-3. This standard sup- ports a wide range of applications such as low-cost remote-control switches. Typically it is used for lamp control; complex, highly-autonomous, distributed systems like engine controls, which require fast and secure data transfers. The TSS461C is a microprocessor-interfaced line controller for mid-to-high complexity bus-masters and listeners like injection/ignition control calculators, dashboard control- lers and car stereo or mobile telephone CPUs. The microprocessor interface consists of a 256-bytes of RAM and a register area divided into 11 control registers, 14 channel register sets and 128 bytes of general purpose RAM, used as a message storage area, and a 6-source maskable interrupt. The circuit operates in RAM using DMA techniques, controlled by the channel and control registers. This allows virtually any microprocessor to interface with ease to the TSS461C, and to use the free RAM as a scratch pad. Messages are encoded in enhanced Manches ter code, and an optional pulsed code for use with an optical or radio link, at a maximum bit rate of 1 Mbit/s. The TSS461C analyzes the messages received or transmitted according to 6 different criteria includ- ing some higher level checks. In addition, the bus interface has three separate inputs with automatic source diagno- sis and selection, that allows for multibus listening or the automatic selection of the most reliable source at any time if several line receivers are connected to the same bus. VAN Data Link Controller TSS461C

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4193G–AUTO–12/04 Block Diagram Message ID registers RAM 128 bytes buffer Protocol controller state machine and Data serializer and deserializer Clock generator and line synchronization logic Multiplexing logic Status and control registersReception logic CRC generator and checker Transmission logic Source diagnosis and selection logic AD[7:0] ALE control bus data bus address bus INT XTAL1 XTAL2 CKOUT TxD status bus RxD0 RxD1 RxD2 RESET TEST VCC GND Address and Data Bus

4193G–AUTO–12/04 Pin Configuration Note: 1. The names in parenthesis refer to the functionalities in Motorola mode. 1 24 2 2 3 3 2 2 4 2 1 5 2 0 6 19 7 1 8 8 1 7 AD4 AD5 AD6 AD7 VCC INT (E) CS XTAL1 TOP VIEW 9 1 6 10 15 11 14 12 13 ALE XTAL2 Test/VSS CKOUT AD3 AD2 AD1 AD0 VSS RESET RXD0 RXD2 TXD RXD1 WR (R/W) RD (VSS)

24 Pin SOP

I/O Type Pin Name Pin Number Pin Function I/O TTL AD0 21 Multiplexed address and data bus. The address is latched on the falling address of ALE. AD1 22 AD2 23 AD3 24 AD4 1 AD5 2 AD6 3 AD7 4 I Trigger TTL ALE 7 Address Latch Enable RD (VSS) 13 Read Command WR (R/W) 14 Write Command CS(E) 8 Chip Select (active high) Open-drain INT 6 Interrupt I Trigger CMOS Pull-down RESET 19 Asynchronous general reset glitch filtered (12 ns)

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4193G–AUTO–12/04 I CMOS Pull-down RXD0 17 VAN bus Inputs RXD1 15 RXD2 16 3-state TXD 18 VAN bus Output I XTAL1 9 Crystal oscillator or clock input pins

0 XTAL2 10

0 CKOUT 12 Buffered clockout output

Ground TEST/VSS 11 Oscillator Ground Power VCC 5 +5V Power Supply Ground VSS 20 I/O Type Pin Name Pin Number Pin Function

optimized to use with the TSC51/TSC251 series of microcontrollers. internal write strobe (typically 20 ns). Figure 1. Typical Application

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circuit. These registers appear to the processor as regular memory locations. address/data bus multiplexed. Table 1. Access Mode Logic To switch on-the-fly from one mode to the other, CS must be inactive. select and the interrupt request pins. address on the multiplexed address and data bus and drive the address strobe pin high. low, and keep the address valid for the required hold time. time drive the chip select pin high. remain high during and after the termination of the cycle.

0 No operation

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4193G–AUTO–12/04 Reset The reset is applied asynchronously regarding XTAL clock. It can be done either by the RESET pin or by software. The RESET pin is a CMOS trigger input with a pull-down resistor (110 kΩ). An external 1 µF capacitor to VCC provides to RESET pin an efficient behavior. The software reset is made through the GRES command bit of the Command Register (0x03). The two resets are ored, filtered and gauged. Then the internal reset, always asserted asynchronously, enables the internal oscillator. Then it waits for eight clock periods for the oscillator stability. The different blocks of the TSS461C need to be turned on synchronously. So the release of the internal reset is synchronous and a loose clock can let the TSS461C in permanent reset after applying Reset.

4193G–AUTO–12/04 Oscillator An oscillator is integrated in the TSS461C, and consists of an inverting amplifier which the input is XTAL1 and the output XTAL2. A parallel resonance quartz crystal or ceramic resonator must be connected to these pins. As shown in Figure 1, two capacitors have to be connected from the crystal pins to ground. The values of C1 depend on the frequency chosen and can be selected using the graphic given in Figure 33. If the oscillator is not used, then a clock signal must be fed to the circuit via the XTAL1 input. Note, that this pin will behave as a CMOS level compatible Schmitt trigger input. In this case, the XTAL2 output should be left unconnected. The oscillator also features a buff- ered clock output pin CKOUT. The signal on this pin is directly buffered from the XTAL1 input, without inversion. There is one more pin used for the oscillator. The TEST/VSS pin is in fact its ground, and unless this pin is firmly connected to ground, with decoupling capacitors, the oscilla- tor will not operate correctly. The test mode itself, i.e., when the TEST/VSS pin is held high, is only intended for fac- tory use, and the functionality of this mode is not specified in any way. Furthermore, it is subject to change without notice, the only exception is for incoming inspection tests using the test program. The clock signal is then fed to the clock generator generate all the necessary timing sig- nals for the operation of the circuit. The clock generator is controlled by a 4-bit code called the clock divider. FTSCLK FXTAL 1

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Table 2. Clock Divider

8 MHz 6 MHz 4 MHz 2 MHz

bus is also received simultaneously. destructive (for the higher priority message) collision detection. Figure 4. CSMA/CD Arbitration imposed on the RxD0 input, and the diagnosis system does not operate correctly. ceivers are not able to receive the signal that they transmit.

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waveform showed in Figure 5, to obtain the correct representations for pulsed coding. Figure 5. State Encoding

1. The Autonomous module, which is a bus master. It can transmit Start Of Frame

(SOF) sequences, it can initiate data transfers and can receive messages.

1. The Synchronous access module. It cannot transmit SOF sequences, but it can

initiate data transfers and can receive messages.

1. The Slave module, which can only transmit using an in-frame mechanism and

Figure 7. Hierarchical Access Methods

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4193G–AUTO–12/04 The IFS is defined to be a minimum of 64 prescaled clocks periods. The TSS461C, accepts an IFS of zero prescaled clocks for the reception only of a SOF sequence. Once the bus is free, the module must now, if it is an autonomous module emits a SOF sequence or, if it is a synchronous access module, wait until it detects a preamble sequence. Until this point there can be several modules transmitting on the bus, and there is no possibility of knowing if this is the case or not. Therefore, the first field in which arbitra- tion can be performed is the identifier field. Since the logical zeroes on the bus are dominant, and all data is transmitted with the most significant bit (MSB) first, the first module to transmit a logical zero on the bus will be the prioritized module, i.e., the mes- sage that is tagged with the lowest identifier will have priority over the other messages. However it is possible that two messages transmitted on the bus will have the same identifier. The TSS461C therefore, continues the arbitration of the bus throughout the whole frame. In addition, if the identifier in transmission has been programmed for reception as well, it transmits and receives messages simultaneously, right up till the Frame Check Sequence (FCS). Only then, if the TSS461C has transmitted the whole message. It discards the message received. Arbitration loss in the FCS field is consid- ered as a CRC error during transmission. This feature is called full data field arbitration, and it enables the user to extend the iden- tifier. For instance, it can be used to transmi t the emitting modules address in the first bytes of the data field, thus enabling the ident ifier to specify the contents of the frame and the data field to specify the source of the information. The identifier field of the VAN bus frame is always 12 bits long, and it is always followed by the 4-bit command field:  The first bit of the command is the extension bit (EXT). This bit is defined by the user on transmission and is received and retained by the TSS461C. To conform with the standard, it should be set to 1 (recessive) by the user, else the frame is ignored without any IT generation.  The second bit is the request ACKnowledge bit (RAK). If this bit is a logical one, the receiving module must acknowledge the transfer with an in-frame acknowledgement in the ACK field. If it is set to logical zero, then the ACK field must contain an acknowledge absent sequence.  The third bit is the Read/Write bit (R/W). This bit indicates the direction of the data in a frame. – If set to zero it is a "write" message, i.e. data transmitted by one module to be received by another module. – If it is set to one it implies a "read" message, i.e., a request that another module should transmit data to be received by the one that requested the data (reply request message).  Last in the command field is the Remote Transmission Request bit (RTR). This bit is a logical zero if the frame contains data and a logical one if the frame does not contain data. In order to conform with the standard a received frame included the combination R/W. RTR = 01 is ignored without any IT generation. All the bits in the command field are automatically handled by the TSS461C, so the user doesn’t need to be concerned for encoding and decoding these bits. The command bits transmitted on the VAN bus are calculated from the current status of the active message.

but the TSS461C handles messages up to 30 bytes. performed before transmission. Frame sequence (EOF) to terminate the transfer. Figure 10. Acknowledge Sequences types specified in the VAN standard, and what module is generating the different fields. master (not shown in the figure). a slave module can transmit data by filling it into the appropriate field. compared to the normal frame. are all generated by the replying module.

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only if this was requested by the initiator through the RAK bit. prepared a reply for a reply request that has been received earlier. Figure 11. Normal Data Frame

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Figure 14. Deferred Reply Frame

DATA signals, and is connected to the RxD0 input. (Synchronous Diagnosis Clock) and TIP (Transmission In Progress). nominal mode and re-connects the differential line receiver to the reception logic. A major error occurs when both the VAN bus signals fail. Figure 15. Diagnosis States

• Default of transitions on the valid input between 2 consecutive SDC rising edges.
• In specified selection mode, every RI pulse when an EOF is detected or through an active SDC.
• In automatic selection mode and SDC active, no failure sampled by 2 consecutive SDC rising edges.

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bits indicate the four possible states of the VAN bus. Table 3. Status Bits Sa and Sb

1. The only way to reset this status bit is through the RI signal or a general reset.

may occur. To avoid such errors, digital filters are implemented. taken into account only if it is observed over five samples (1/16th of timeslot). connected to the reception logic during one SDC period.

4193G–AUTO–12/04 If there are less than four edges during one SDC period, the diagnosis mode will change to the major error mode.  Transmission diagnosis: The transmission compares RxD1 and RxD2 inputs (through the input comparators and the filters) with the data transmitted on TxD output. At a time when the transmission logic generates a dominant (recessive transition), the inputs can give different values. Taking into account the filtering delay, the bus line seen as dominant is assumed to be correct, the other one, recessive, is considered faulty. The diagnosis mode is changed to reflect that.  Protocol fault: The protocol fault is detected by counting the number of consecutive dominant timeslots. If eight consecutive timeslots are dominant, the diagnosis mode will change to the major error mode. Generation of Internal Signals RI Signal (Return to Idle) This signal is used to return to nominal mode in the three specified selection modes (see Section “Diagnosis States” and Section “Programming Modes”). The RI signal is dis- abled in automatic selection mode. The RI signal is a pulse generated when an EOF is detected. So, at the end of each frame, regarding the diagnosis status bit Sa , Sb & Sc, the user can select its own choice. SDC Signal (Synchronous Diagnosis Clock) This time base is used by diagnosis sy stem in automatic selection mode (see Section “Programming Modes”) when no event is recorded on the bus. The SDC is generated either by a special SDC divider connected to the timeslot clock, or manually. The SDC clock period must be longer compared to the timeslot duration. A typical SDC period should be greater than the maximum frame length appearing on the VAN network. TIP Signal (Transmission in Progress) This signal must be enabled to allow the transmission diagnosis (see Section “Transition Analyses”). The TIP turns on synchronously at the beginning of the transmission:  For asynchronous bus access, the beginning of SOF;  For synchronous bus access, the beginning of the identifier field; and  For a request of in frame reply, the RTR bit of the command field. The TIP turns off synchronously at the end of the transmission: a f t e r E O F ;  after a losing of arbitration or a code violation detection; and  for a requester of in frame reply, when the arbitration is lost on RTR the bit. This signal is not generated when the transmission logic only sends an ACK.

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Table 4. Programming Modes

ters, the Channel Registers and the Message Data (or Mailbox). Figure 16. Memory Map Notes: 1. All the non-specified addresses between 0x00 and 0x7F are considered as absent.

1. (r) means read-only register.

(w) means write-only register. (r/w) means read/write register.

1. Value after RESET is found after register name. If no value is given, the register is not initialized at RESET.

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4193G–AUTO–12/04 Control and Status Registers Line Control Register (0x00)  Read/write register.  Default value after reset: 0y00  reserved: Bit 2, this bit cannot be set by the user; a 0 must always be written to this bit. CD[3:0] Clock Divider They control the VAN Bus rate through a Baud Rate generator according to the follow- ing formula: PC Pulsed CodeOne The TSS461C will transmit and receive data using the pulsed coding mode (i.e optical or radio link mode). The use of this mode implies communication via the RXD0 input and the non-functionality of the diagnosis system. Zero: (Default at Reset). The TSS461C will transmit and receive data using the Enhanced Manchester code (RXD0, RXD1, RXD2). IVTX Invert TXD output. IVRX Invert RXD inputs.The user can invert the logical levels used on either the TXD output or the RXD inputs in order to adapt to different line drivers and receivers. One: A one on either of these bits will invert the respective signals. Zero: (Default at Reset). The TSS461C will set TXD to recessive state in Idle mode and consider the bus free (recessive states on RXD inputs). Transmit Control Register (0x01)  Read/Write register  Default value after reset: 0x02 76543210 MR3 MR2 MR1 MR0 VER2 VER1 VER0 MT FTSCLK FXTAL 1 76543210 MR3 MR2 MR1 MR0 VER2 VER1 VER0 MT

errors occurred during transmission. Table 5. Retries attempts will be performed if bus contention occurs continuously. These bits cannot be set by user; 001 must always be written to these bits. ule (Rank 1) or a slave module (Rank 16).

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The diagnosis is discussed in detail in Section “Diagnosis States”. SDC [3:0]: SDC Divider The input clock is the times lot clock. Table 6. System Diagnosis Clock Divider Table 7. Diagnosis System Command Bits Zero: Disable TIP generation.

4193G–AUTO–12/04  The Transmission In Progress (TIP) tells the diagnostic system to enable transmission diagnosis. ESDC: Enable System Diagnosis Clock One: Enable SDC divider. Zero: Disable SDC divider.  The Synchronous Diagnosis Clock (SDC) controls the cycle time of the synchronous diagnosis. Command Register (0x03)  Write only register.  Reserved: Bit 1, 2. These bits cannot be set by the user; a zero must always be written to these bit.  If the circuit is operating at low bit rates, there might be a considerable delay between the writing of this register and the performing of the actual command (worst case 6 timeslots). The user must verify, by reading the Line Status Register (0x04), that the commands have been performed. GRES: General Reset The Reset circuit command bit performs, if set, exactly as if the external reset pin was asserted. This command bit has its own auto-reset circuitry. One: Reset active Zero: Reset inactive SLEEP: Sleep Command If the user sets the Sleep bit, the circuit will enter sleep mode. When the circuit is in sleep mode, all non-user registers are setup to minimize power consumption and the oscillator is stopped. To exit from this mode, the user must set either the idle or activate commands. One: Sleep active Zero: Sleep inactive 76543210 GRES SLEEP IDLE ACTI REAR 0 0 MSDC

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4193G–AUTO–12/04 IDLE: Idle Command If the user sets the Idle bit, the circuit will enter idle mode. In idle mode the oscillator will operate, but the TSS461C will not transmit or receive anything on the bus, and the TXD output will be in three-state One: Idle active Zero: Idle inactive ACTI: Activate Command The Activate command will put the circuit in the active mode, i.e it will transmit and receive normally on the bus. When the circuit is in activate mode the TXD three-state output is enabled. One: Activate active Zero: Activate inactive REAR: Re-Arbitrate Command This command will, after the current attempt, reset the retry counter and re-arbitrate the messages to be transmitted in order to find the highest priority message to transmit. One: Re-arbitrate active Zero: Re-arbitrate inactive MSDC: Manual System Diagnosis Clock Rather than using the SDC divider described in Section “Diagnosis Control Register (0x02)”, the user can use the manual SDC command to generate a SDC pulse for the diagnosis system. This MSDC pulse should be high at least two timeslot clock. Line Status Register (0x04) Read only register.  Default value after reset: 0bx01xxx00.  This register reports the operation mode of the TSS461C in the Sleep an Idle bits (Command Register located at address 0y03) as well as the diagnosis system status bits S2 to S0 discussed in Section “Diagnosis System”. SPG: Sleeping IDG: Idling Default mode at reset Sa, Sb and Sc Diagnosis system status bits  Sa and Sb 76543210 xS P G I D G S cS bS a T X G R X G

Table 8. Diagnosis System Status Bits in the input comparison analysis perform by the diagnosis system, S2 is set. The only way to reset this status bit is through the RI signal or a general reset. or the retry count is exceeded. RXG: Receiving The receiving indicates that there is activity on the bus.  Default value after reset: 0x00. according to Table 3, and the channel currently in transmission.  Default value after reset: 0x00.

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4193G–AUTO–12/04 NRTR [3:0]: Number of retries done successfully in transmission. In case of reception NRTR[3:0] is undefined. IDTR [3:0]: Channel number that was successfully transmitted, received or exceeded its retry count. Last Error Status Register (0x07)  Read only register.  Default value after reset: 0 ×00.  The Last Error Status Register contains the error code for the last transmission or reception attempt. It is updated after each attempt, i.e. several error codes can be reported during one single transmission (with several retries). BOC: Buffer Occupied  When one channel configured in “Reply request” mode has its “received” bit set when it attempts to transmit its request.  BOC with the link capability between two channels sharing the same received buffer is set when one channel has already set its “received” bit in its “Message length and status Channel register” and a receive is attempted on the other one. BOV: Buffer Overflow BOV indicates that the buffer length setup in the Channel Status Register was shorter than the number of bytes received plus 1, therefore, some data got lost. One: BOV active Zero: BOV inactive FCSE: Framing Check Sequence Error FCSE indicates a mismatch between the FCS received and the FCS calculated One: FCSE active Zero: FCSE inactive ACKE: Acknowledge Error ACKE indicates a physical violation or collision on ACK field of the frame when the TSS463 is produced. One: ACKE active Zero: ACKE inactive 76543210 x BOC BOV x FCSE ACKE CV FV

Figure 17. ACKE Status Bit

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Figure 18. FV Status Bit set when a reset is detected. Figure 19. Exceeded Retry with MR[3.0] = 3

4193G–AUTO–12/04 TOK: Transmit OK Status Flag One: Status flag activated Zero: No status flag. RE: Receive Error Status Flag One: Status flag activated Zero: No status flag. ROK: Receive “with RAK (RAK=1)” OK Status Flag One: Status flag activated Zero: No status flag. RNOK: Receive “with no RAK (RAK=0)” OK Status Flag One: Status flag activated Zero: No status flag. Interrupt Enable Register (0x0A)  Read/write register  Default value reset: 0x80 Note: On reset the Reset Interrupt Enable bit is set to 1 instead of 0, as the general rule. TEE: Transmit Error Enable One: IT enabled. Zero: IT disabled. TOKE: Transmission OK Enable One: IT enabled. Zero: IT disabled. REE: Reception Error Enable One: IT enabled. Zero: IT disabled. ROKE: Reception “with RAK” OK Enable One: IT enabled. Zero: IT disabled. RNOKE: Reception “with no RAK” OK Enable One: IT enabled. Zero: IT disabled. Interrupt Reset Register (0x0B)  Write only register.  Reserved bit: 5 and 6. This bit cannot be set by user; a zero must always be written to this bit. 76543210 1 0 0 TEE TOKE REE ROKE RNOKE 76543210 RSTR 0 0 TER TOKR RER ROKR RNOKR

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Figure 20. Update of the Status Register pointers and message status. The base_address of each set is: (0x10 + [0x08 * channel_number]). the channel registers start with random values. received and transmitted bits to 1 in the Message Length & Status Register.

4 TS 1 to 2 TS 6 TS

Table 9. Channel Register Sets Map Table 10. Channel Register Set Structure standard and the 4-bit command.

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4193G–AUTO–12/04 ID_T [11:0]: Identifier Tag Upon a reception hit (i.e, a good comparison between the identifier received and an identifier specified, taking the comparison mask into account, as well as a status and command indicating a message to be received, the identifier tag bits value will be rewrit- ten with the identifier bits actually received. EXT, RAK, RNW & RTR: (See Section “Retries, Rearbitrate and Abort”) No comparison will be done on the command bits, except on EXT bit. The RAK, RNW and RTR bits will be written into the first byte of the Message upon a reception hit. The RNW and RTR bits, as well as the status bits in the length and status register, must be in a valid position for reception or transmission. If not, the message corresponding to this identifier is considered as inactive or invalid. The way of knowing if an acknowledge sequence was requested or not is to check the first byte of the Message. Message Pointer Register The message pointer register at address (base_a ddress + 0x02) is 8 bits wide. It indi- cates where, in the Message DATA RAM area, the message buffer is located.  Read/Write register DRAK: Disable RAK (Used in 'Spy Mode') In reception: whatever is the RAK bit of the incoming valid frame, no ACK answer will be set. If the message was successfully received, an IT is set (ROK or RNOK). In transmission: no action. One: disable active, 'spy' mode. Zero: disable inactive, normal operation. M_P [6:0]: Message Pointer Since the Message DATA RAM area base address is 0x80, the value in this register is the offset from that address. If the message buffer length value is illegal (i.e. zero), this register is redefined as being a link pointer, thus containing the channel number of the channel that contains the actual message pointer, message length and received status. However, the identifier, mask, error and transmitted status used will be the originally matched channel. In any case, if a link is intended, the three high bits of M_P [6:0] should be set to 0. This allows several channels to use the same actual reception buffer in Message DATA RAM, thus diminishing the memory usage. Note that only 1 level of link is supported. 76543210 DRAK M_P 6 M_P 5 M_P 4 M_P 3 M_P 2 M_P 1 M_P 0 base_address + 0x02

4193G–AUTO–12/04 Message Length And Status Register The message length and status register at address (base_address + 0x03) is also 8 bits wide. It indicates the length reserved for the message in the Message DATA RAM area.  Read/Write register. M_L [4:0]: Message Length The 5 high bits of this register allow the user to specify either the length of the message to be transmitted, or the maximum length of a message receivable in the pointed recep- tion buffer. Note that the first byte in this register does not contain data, but the length of the mes- sage received. This implies that the length value has to be equal to or greater than the maximum length of a message to be received in this buffer (or the length of a message to be transmitted) plus 1. Thus allowing a maximum length of 30 bytes and a minimum length of 0 byte. If the value of this field is illegal (i.e 0x00) then this message pointer is defined as being a link (see section “Message Pointer Register” and Section “Linked Channels”). CHER: Channel Error Status and Abort Command As status, this bit is set by the TSS461C when error occurs in transmission or on a received frame. The user must reset it. To abort the transmission defined in the channel, this bit can be set to1 by the user (see Section “Retries, Rearbitrate and Abort” and Section “Abort”). CHTx: Channel Transmitted and Transmit Enable Command 76543210 M_L 4 M_L 3 M_L 2 M_L 1 M_L 0 CHER CHTx CHRx base_address + 0x03 M_L [4:0] = 0x00 Linked channel M_L [4:0] = 0x01 Frame with no DATA field (*) M_L [4:0] = 0x02 Frame with 1 DATA byte M_L [4:0] = 0x1D Frame with 28 DATA bytes M_L [4:0] = 0x1E Frame with 29 DATA bytes M_L [4:0] = 0x1F Frame with 30 DATA bytes (*) Different of a reply request frame wit h no in-frame reply (deferred reply).

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4193G–AUTO–12/04 CHRx: Channel Received and Receive Enable Command The two low order bits of this register contain the message status. Together with the RNW and RTR bits of the command register (base_address + 0x01), they define the message type of this channel (seeSection “Messages Types”). As a general rule (see Section “Abort”), the status bits are only set by the TSS461C, so the user must reset them to perform a transmission (CHTx) or/and a reception (CHRx). The received and transmitted bits are only set if the corresponding frame is without errors or if the retry count has been exceeded. Identifier Mask Registers The Identifier Mask registers (base_address + 0x06 and base_address + 0x07) allow bitwise masking of the comparison between the identifier received and the identifier specified.  Read/Write registers ID_M [11:0]: Identifier Mask A value of 1 indicates comparison enabled. A value of 0 indicates comparison disabled. 76543210 I D _ M 3 I D _ M 2 I D _ M 1 I D _ M 0 xxxx 76543210 ID_M 11 ID_M 10 ID_M 9 ID_M 8 ID_M 7 ID_M 6 ID_M 5 ID_M 4

0xFF (see Section “Mapping”). ter”). This area is a pure RAM, it contains a random value after reset. Figure 21. Message Buffer Structure for Reception

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Figure 22. Message Buffer Structure for Transmission RRAK: Received RAK Bit This bit is the RAK bit coming from the COM field of the received frame. RRNW: Received RNW Bit This bit is the RNW bit coming from the COM field of the received frame. RRTR: Received RTR Bit This bit is the RTR bit coming from the COM field of the received frame. even if the reserved length (Message Length & Status Register) is larger.

Figure 23. Message Status Updating DATA0 is the first received (or transmitted) byte, DATAn is the last one. message string just after DATAn. CRC field, considering these bytes as normal DATA.

1. The Mailbox RAM area is a circular buffer. The next location after 0xFF is 0x80.

(*) After IT ROK or RNOK. In case of IT RE, the values can be erroneous.

42 TSS461C

4193G–AUTO–12/04 Messages Types There are 5 basic message types defined in the TSS461C. Two of them (transmit and receive message types) correspond to the normal frame, and the rest correspond to the different versions of reply frames. To transmit a normal data frame on the VAN bus, the user must program an identifier as a Transmit Message. The TSS461C will then transmit this message on the bus until it has succeeded or the retry count is exceeded. The opposite of the transmit message type is the Receive Message type. This message type will not generate any frames on the bus. Instead, it will listen to the bus until a frame passes that matches its identifier, with the mask taken into account, and then receive the data in that frame. The data received will be stored in the message buffer and the length of the message received is stored in the first byte of the message buffer. The actual identifier received is stored in the identifier register itself. This identifier may differ from the identifier specified in the register due to the effect of the mask register. Normally, this should not interfere with the next identifier comparison since the bits that may differ are masked via the mask register. The Reply Request Message type is a demand to transmit on the VAN bus a reply request. When this message type is programmed, three things can happen. First, no other modules on the bus responded with an in-frame reply, in this case the TSS461C will set the message type to the after transmission state. When this message type is programmed, the TSS461C will listen on the bus for a deferred reply frame matching this identifier, without transmitting the reply request. Transmit Message RNW RTR CHTx CHRx Initial Setup 0 0 0 Don’t Care After Transmission 0 0 1 Unchanged Receive Message RNW RTR CHTx CHRx Initial Setup 0 1 Don’t Care 0 After Transmission 0 1 Unchanged 1 Reply Request Message RNW RTR CHTx CHRx Initial Setup 1 1 0 0 After Transmission (Waiting for reply) 11 1 0 After Reception (of reply) 11 1 1

4193G–AUTO–12/04 Second, another module on the bus replies with an in-frame reply. In this case the mes- sage type will pass immediately into the after reception state, without passing the after transmission state. Third, the TSS461C has not yet started to transmit the reply request, when another module either requests a reply, and gets it, or transmits a deferred reply. Warning! This should be avoided as it may result in an illegal message type (Illegal reply Request). The immediate Reply Message will attempt to transmit an in-frame reply, using the data in the message buffer. A deferred Reply Message is shown below. This message type will immediately transmit a deferred reply frame. Finally, there is the Reply Request Detector Message type. Its purpose is to receive a reply request frame and notify the processor, without transmitting an in-frame reply. The table above shows all inactive messages types. The last combination will transmit a reply request, but will not receive the reply since its buffer is tagged as occupied. Reply Request Message Without Transmission RNW RTR CHTx CHRx Initial Setup 1 1 Don’t Care 0 After Reception 1 1 Unchanged 1 Immediate Reply Message RNW RTR CHTx CHRx Initial Setup 1 0 0 0 After Transmission 1 0 1 1 Deferred Reply Message RNW RTR CHTx CHRx Initial Setup 1 0 0 1 After Reception (of Reply Request) 10 1 1 Reply Request Detection Message RNW RTR CHTx CHRx Initial Setup 1 0 1 0 After Reception 1 0 1 1 Inactive Message RNW RTR CHTx CHRx Recommended Don’t Care Don’t Care 1 1 After Transmission 0 0 1 Don’t care After Reception 0 1 Don’t Care 1 Illegal Reply Request 1 1 0 1

44 TSS461C

4193G–AUTO–12/04 Priority Among the Different Channels The priority handling on the VAN bus is already explained in the Line Interface section. The priorities for the messages in the TSS461C is, however, slightly different. For instance, it's possible that an identifier matches two or more of the identifiers pro- grammed into the registers. In this case, it is the lowest identifier number that has priority. i.e., if both identifier 5 and 10 match th e identifier received, it is the identifier 5 that will receive the message. However, since the identifier 5 will become an inactive message when it has received the frame, the next time the same identifier is seen on the bus, the corresponding data will be received by identifier 10. The same is valid for messages to be transmitted, i.e., if two or more messages are ready to be transmitted, it is the one with the lowest identifier number that will get priority.

commands are available only when the TSS461C is producer. Figure 24. Transmit Function frame or on REPLY REQUEST frame. ciated, can be read in the Transmission Status Register (0x05).

46 TSS461C

attempts can be performed if bus contention occurs continuously. value, all channels start their transmission with this parameter. nels”) message to be transmit. Typical Example  Max_retries = 1 (2 transmissions attempts). the end of the loop, the user can use the rearbitrate command. counter and enable the Ch5 to transmit. transmission is activated for the Ch8 again. Figure 25. Rearbitrate Example

48 TSS461C

1 the Transmitted bit (CHTx) of the Message Length & Status Register. and retries live together in the transmit function. Figure 28. Abort Example Reset

12 T imeslots

three commands are general commands for the TSS461C. (CKOUT pin active) but the circuit cannot transmit or receive anything on the VAN bus. externally or by the line driver to avoid floating state on the VAN bus. Figure 29. Idle and Activate Timings In both cases, the idle state can be verified by reading the Line Status register (0x04). To exit from this mode, the user must set either the idle bit or the activate bit. does not run and the only way to awake this application is an external reset.

3 TS 8 TS

5 TS4 TS

50 TSS461C

channel linked to another channel. in the register set of this other Channel. be linked to the Channel i but not to Channel j, already defined as linked to Channel i. All the others can be different between the two channels, for example the ID_Tag. Figure 30. Linkage Mechanism

4193G–AUTO–12/04

Electrical Characteristics

DC Characteristics TA = -40°C to 125°C; VCC = 5V ± 10%; VSS = 0V Ambient temperature under Bias: Voltage on V Note: Stresses at or above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condi- tions exceeding those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Symbol Parameter Min Max Type Test Conditions VIL Input Low Voltage (except RESET and XTAL1) -0.5 0.8 V VIH Input High Voltage (except RESET and XTAL1) 2.0 V CC+0.5 V VIL1 Input Low Voltage (RESET and XTAL1) -0.5 0.3·V CC V See Figure 2 VIH1 Input High Voltage (RESET and XTAL1) 0.7 V CC VCC+0.5 V VOL Output Low Voltage 0.4 V I OL = 3.2 mA, VCC min VOH Output High Voltage 2.4 I OH = -3.2 mA, VCC min IL Input Leakage Current + 5 µA0 < V IN < VCC RPD Input Pull-down Resistor 110 k Ω 0 < VIN < VCC CIO I/O Buffer Capacitance 10 pF Not tested ICCSB Power Supply Current Sleep Mode 50 µA( N o t e 1 ) ICCOP Power Supply Current Idle or Active Mode mA mA (Notes 2, 4) (Notes 3, 4) Notes: 1. Sleep Mode I CCSB is measured according to Figure 31 with a VSS Clock Signal. 2. Active mode I CCOP is measured at: XTAL = 1 MHz clock, VAN speed rate = 62.5 KTS/s. 3. Active mode I CCOP is measured at: XTAL = 16 MHz clock, VAN speed rate = 250 KTS/s. 4. I CC is a function of the Clock Frequency. Figure 32 displays a graph showing ICC versus Clock frequency. 5. RESET , RxD0, RxD1, RxD2 inputs.

52 TSS461C

Figure 31. ICC Figure 32. ICC versus Clock Frequency at 250 KTimeslot/s

4193G–AUTO–12/04 AC Characteristics Microprocessor Interface TA = -40°C to 125°C; VCC = 5V ± 10%; VSS = 0V Symbol Characteristic Min Max Unit TRESET RESET High Pulse Width (For Power-up Reset) 15 ns 1T LHLL ALE High Pulse Width 10 ns 2T AVLL Address Valid to ALE Low Setup Time 10 ns 3T LLAX ALE Low to Address Invalid Hold Time 10 ns 4T AVWL Address Valid to Command Active Time 20 ns 5T DVWH Data Valid to Write Inactive Setup Time 10 ns

6 TWHDX Write Inactive to Data Invalid Hold Time 12 ns

7T WHLH Write Inactive to ALE High Recovery Time 20 ns 8T RLDV Read Active to Data Valid Access Time 110 ns 9T RHDZ Read Inactive to Data Float Time 20 ns

10 T WHRLIZ Write Inactive or Read Active to IRQ Float Time 90 ns

11 T IZIL IRQ Float Pulse Width 2 20 ns

54 TSS461C

4193G–AUTO–12/04 Oscillator Characteristics Figure 33. C2 versus Frequency Note: C1 (no capacitance needed) see Figure 1. External Clock Drive Characteristics (XTAL1) 200 100 12 48 MHz pF Symbol Parameter Min Max Unit TCHCH Oscillator Period 120 ns TCHCX High Time 20 ns TCLCX Low Time 20 ns TCLCH Rise Time 20 ns TCHCL Fall Time 20 ns t CHCX tCLCX tCHCH XTAL1 VIH VIL tCLCHtCHCL VIH VIH VIL

4193G–AUTO–12/04 Packaging Information SO24 SO MM INCH A 2.35 2.65 0.093 0.104 A1 0.10 0.30 0.004 0.012 B 0.35 0.49 0.014 0.019 C 0.23 0.32 0.009 0.013 D 15.20 15.60 0.599 0.614 E 7.40 7.60 0.291 0.299 e 1.27 BSC 0.050 BSC H 10.00 10.65 0.394 0.419 h 0.25 0.75 0.010 0.029 L 0.40 1.27 0.016 0.050 N2 4 2 4 a0 ° 0°

56 TSS461C

4193G–AUTO–12/04

Ordering Information

Note: 1. These products are available in ROHS version. Part Number Supply Voltage Temperature Range Package Packing TSS461C 5V + 10% -40°C - +125°C SO24 Tube TSS461C:R 5V + 10% -40°C - +125°C SO24 Tape & Reel TSS461C-TDRZ(1) 5V +10% -40°C - +125°C SO24 Tube

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