TSPC860

TSPC860 ATMEL | Alldatasheet

Document overview

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Technical content

Features

 PowerPC® Single Issue Integer Core  Precise Exception Model  Extensive System Development Support – On-chip Watchpoints and Breakpoints – Program Flow Tracking – On-chip Emulation (Once) Development Interface  High Performance (Dhrystone 2.1: 52 MIPS at 50 MHz, 3.3V, 1.3 Watts Total Power)  Low Power (< 241 mW at 25 MHz, 2.4V Internal, 3.3V I/O-core, Caches, MMUs, I/O)  MPC8XX PowerPC System Interface, Including a Periodic Interrupt Timer, a Bus Monitor, and Real-time Clocks  Single Issue, 32-bit Version of the Embedded PowerPC Core (Fully Compatible with Book 1 of the PowerPC Architecture Definition) with 32 × 32-bit Fixed Point Registers – Embedded PowerPC Performs Branch Folding, Branch Prediction with Conditional Prefetch, without Conditional Execution – 4-Kbyte Data Cache and 4-Kbyte Instruction Cache, Each with an MMU – Instruction and Data Caches are Two-way, Set Associative, Physical Address,

4 Word Line Burst, Least Recently Used (LRU) Replacement, Lockable On-line

– MMUs with 32 Entry TLB, Fully Associative Instruction and Data TLBs – MMUs Support Multiple Page Sizes of 4 KB, 16 KB, 256 KB, 512 KB and 8 MB;

16 Virtual Address Spaces and 8 Protection Groups

– Advanced On-chip Emulation Debug Mode  Up to 32-bit Data Bus (Dynamic Bus Sizing for 8- and 16-bit)  32 Address Lines  Fully Static Design  VCC = +3.3V ± 5%  fmax = 66 MHz  Military Temperature Range: -55°C < TC < +125°C  PD = 0.75 W Typical at 66 MHz

Description

The TSPC860 PowerPC QUad Integrated Communication Controller (Power QUICC®) is a versatile one-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications. It particularly excels in communications and networking systems. The Power QUICC (pronounced “quick”) can be described as a PowerPC-based derivative of the TS68EN360 (QUICC ™ ). The CPU on the TSPC860 is a 32-bit PowerPC implementation that incorporates memory management units (MMUs) and instruction and data caches. The communi- cations processor module (CPM) of the TS68EN360 QUICC has been enhanced with the addition of a Two-wire Interface (TWI) compatible with protocols such as I 2C. Mod- erate to high digital signal processing (DSP) functionality has been added to the CPM. The memory controller has been enhanced, enabling the TSPC860 to support any type of memory, including high performance memories and newer dynamic random access memories (DRAMs). Overall system functionality is completed with the addi- tion of a PCMCIA socket controller supporting up to two sockets and a real-time clock. PBGA 357 ZQ suffix Integrated Communication Processor TSPC860 Preliminary Specification β-site Rev. 2129B–HIREL–12/04

2 TSPC860 [Preliminary]

Figure 1. Block Diagram View of the TSPC860

16 Serial DMA

TSPC860 [Preliminary] 2129B–HIREL–12/04 Main Features The Following is a List of the TSPC860’s Important Features:  Fully Static Design  Four Major Power Saving Modes  357-pin Ball Grid Array Packaging (Plastic)  32-bit Address and Data Busses  Flexible Memory Management  4-Kbyte Physical Address, Two- way, Set-associative Data Cache  4-Kbyte Physical Address, Two-way, Set-associative Instruction Cache  Eight-bank Memory Controller – Glueless Interface to SRAM, DRAM, EPROM, FLASH and Other Peripherals – Byte Write Enables and Selectable Parity Generation – 32-bit Address Decodes with Bit Masks  System Integration Unit – Clock Synthesizer – Power Management – Reset Controller – PowerPC Decremen ter And Time Base – Real-time Clock Register – Periodic Interrupt Timer – Hardware Bus Monitor and Software Watchdog Timer – IEEE 1149.1 JTAG Test Access Port  Communications Processor Module – Embedded 32-bit RISC Controller Architecture for Flexible I/O – Interfaces to PowerPC Core Through On-chip Dual-port Ram And Virtual DMA Channel Controller – Continuous Mode Transmission And Reception On All Serial Channels – Serial DMA Channels For Reception And Transmission On All Serial Channels – I/O registers with Open-drain Capability – Memory-memory and Memory-I/O Transfers with Virtual DMA Functionality

4 TSPC860 [Preliminary]

2129B–HIREL–12/04  Four serial communications controllers – Protocols Supported by ROM or Downloadable Microcode and Include, but Limited to, the Digital Portion of: - Ethernet/IEEE 802.3 CS/CDMA - HDLC/SDLC and HDLC bus - Apple Talk - Signaling System #7 (RAM Microcode Only) - Universal Asynchronous Receiver Transmitter (UART) - Synchronous UART - Binary Synchronous (BiSync) Communications - Totally Transparent - Totally Transparent with CRC - Profibus (RAM Microcode Option) - Asynchronous HDLC - DDCMP - V.14 (RAM Microcode Option) - X.21 (RAM Microcode Option) - V.32bis Datapump Filters - IrDA Serial Infrared - Basis Rate ISDN (BRI) in Conjunction with SMC Channels - Primary Rate ISDN (MH Version Only) – Four Hardware Serial Communications Controller Channels Supporting the Protocols – Two Hardware Serial Management Channels - Management for BRI Devices as General Circuit Interface Controller Multiplexed Channels - Low-speed UART operation – Hardware Serial Peripheral Interfaces – Two-wire Interface (TWI) – Time-slot Assigner – Port Supports Centronics Interfaces and Chip-to-chip – Four Independent Baud Rate Generators and Four Input Clock Pins for Supplying Clocks to SMC and SCC Serial Channels – Four Independent 16-bit timers Which Can Be Interconnected as Two 32-bit Timers

Figure 2. Pin Assignment: Top View

6 TSPC860 [Preliminary]

Signal Description This section describes the signals on the TSPC860. Figure 3. TSPC860 External Signals

Figure 4. TSPC860 Signals and Pin Numbers (Part 1)

8 TSPC860 [Preliminary]

Figure 5. TSPC860 Signals and Pin Numbers (Part 2)

System Bus Signals The TSPC860 system bus consists of all si gnals that interface with the external bus. signal’s pin number can be found in Figure 4 and Figure 5. Table 1. Signal Descriptions when an external master starts a transaction on the bus. operand bytes waiting to be transferred in the current bus cycle. TSIZ0 is an input when an external master starts a bus transaction. space in the PCMCIA card is accessed. input when an external master starts a bus transaction. and a logic zero indicates a write to a slave device. external master initiates a transaction on the bus. initiates a transaction on the bus. UPMB takes control of the slave access. bus cycle that transfers data to or from a slave device. relinquish. TS requires the use of an external pull-up resistor. master initiated a transaction.

10 TSPC860 [Preliminary]

the PCMCIA interface or memory controller controls the transaction. transfer as a result of a stwcx. or lwarx. the result of a stwcx. instruction. and reinitiate the transaction after winning in the bus arbitration. and DP1/IRQ4 (if defined as IRQ4). DP0/IRQ3 if defined as IRQ3. Table 1. Signal Descriptions (Continued)

transfers. D0 is the MSB of the data bus. checking is not supported for external masters. CR/IRQ3 (if defined as IRQ3). is not supported for external masters. KR/IRQ4/SPKROUT (if defined as IRQ4). is not supported for external masters. is not supported for external masters. FRZ/IRQ6 (if defined as IRQ6). intended to be initiated (no parking on the bus).

12 TSPC860 [Preliminary]

request is higher than any internal sources requiring a bus transfer. Bus Busy—Asserted low by a master to show that it owns the bus. G3 Bidirectional Freeze—Output asserted to indicate that the core is in debug mode. DP3/IRQ6 (if defined as IRQ6). be configured to be the global chip-select for the boot device. OR6 in the memory controller. OR7 in the memory controller.

line is only asserted if D(0-7) contains valid data. only for accesses to a PC card I/O space. line is only asserted if D(8-15) contains valid data. BS_B2 is asserted only D(16-23) contains valid data. BS_B3 is asserted only if D(24-31) contains valid data.

14 TSPC860 [Preliminary]

access to an external slave controlled by the GPCM. devices at programmed addresses if they are appropriately defined. defined for each signal in the SIUMCR. enter the power-on reset state. address of internal registers is determined in this sequence.

internal oscillator circuitry. internal oscillator circuitry. external capacitor filter for the PLL circuitry. W3 Output Clock Out—This output is the clock system frequency. TEXP High N3 Output Timer Expired—This output reflects the status of PLPRCR[TEXPS]. completion of a transaction on the PCMCIA controlled Slot A. completion of a transaction on the PCMCIA controlled Slot B. reflected in the PIPR and PSCR of the PCMCIA interface. is initiated to an I/O region in socket A of the PCMCIA space.

16 TSPC860 [Preliminary]

initiated by external masters. instruction watchpoint in the program flow executed by the core. socket B in the PCMCIA space. instruction watchpoint in the program flow executed by the core. data watchpoint in the program flow executed by the core.

data watchpoint in the program flow executed by the core. VF1 with VF0 and VF2 when instruction flow tracking is required. transaction is the CPM. If low (0), the transaction initiator is the CPU. This signal is not used for transactions initiated by external masters. asserts this output to indicate an instruction fetch is taking place. data transfer or a program trace indication for an instruction fetch. This signal is not used for transactions initiated by external masters. of a write to the PGCRA register in the PCMCIA interface. of a write to the PGCRB register in the PCMCIA interface. of a write to the PGCRB register in the PCMCIA interface. configure the PLL/clock mode of operation.

18 TSPC860 [Preliminary]

• An internal master in the TSPC860 initiates a transaction on the external bus
• An asynchronous external master initiates a transaction
• A synchronous external master initiates a single beat transaction The memory controller uses BADDR30 to increment the address lines that connect to memory devices when a synchronous external master or an internal master initiates a burst transfer. Register—When an internal master initiates an access to a slave under control of the PCMCIA interface, this signal duplicates the value of TSIZ0/REG . When an external master initiates an access, REG is output by the PCMCIA interface (if it must handle the transfer) to indicate the space in the PCMCIA card being accessed. BADDR(28- 29) Hi-Z M3 Output Burst Address—Outputs that duplic ate A(28-29) values when one of the following occurs:
• An internal master in the TSPC860 initiates a transaction on the external bus
• An asynchronous external master initiates a transaction
• A synchronous external master initiates a single beat transaction The memory controller uses these signals to increment the address lines that connect to memory devices when a synchronous external or internal master starts a burst transfer. AS Hi-Z L3 Input Address Strobe—Input driven by an external asynchronous master to indicate a valid address on A(0-31). The TSPC860 memory controller synchronizes AS and controls the memory device addressed under its control. PA[15] RXD1 Hi-Z C18 Bidirectional General-Purpose I/O Port A Bit 15—Bit 15 of the general-purpose I/O port A. RXD1—Receive data input for SCC1. PA[14] TXD1 D17 Bidirectional (Optional: Open-drain) General-Purpose I/O Port A Bit 14—Bit 14 of the general-purpose I/O port A. TXD1—Transmit data output for SCC1. TXD1 has an open-drain capability. PA[13] RXD2 E17 Bidirectional General-Purpose I/O Port A Bit 13—Bit 13 of the general-purpose I/O port A. RXD2—Receive data input for SCC2. PA[12] TXD2 F17 Bidirectional (Optional: Open-drain) General-Purpose I/O Port A Bit 12—Bit 12 of the general-purpose I/O port A. TXD2—Transmit data output for SCC2. TXD2 has an open-drain capability. PA[11] L1TXDB G16 Bidirectional (Optional: Open-drain) General-Purpose I/O Port A Bit 11—Bit 11 of the general-purpose I/O port A. L1TXDB—Transmit data output for the serial interface TDM port B. L1TXDB has an open-drain capability. PA[10] L1RXDB J17 Bidirectional General-Purpose I/O Port A Bit 10—Bit 10 of the general-purpose I/O port A. L1RXDB—Receive data input for the serial interface TDM port B.

L1TXDA—Transmit data output for the serial interface TDM port A. L1TXDA has an open-drain capability. L1RXDA—Receive data input for the serial interface TDM port A. TIN1—Timer 1 external clock. L1RCLKA—Receive clock for the serial interface TDM port A. BRGCLK1—One of two external clock inputs of the BRGs. TIN2—Timer 2 external clock input. L1TCLKA—Transmit clock for the serial interface TDM port A. TIN3—Timer 3 external clock input. L1RCLKB—Receive clock for the serial interface TDM port B. BRGCLK2—One of the two external clock inputs of the BRGs.

20 TSPC860 [Preliminary]

TIN4—Timer 4 external clock input. L1TCLKB—Transmit clock for the serial interface TDM port B. SPISEL—SPI slave select input. REJECT1—SCC1 CAM interface reject pin. input clock when it is configured as a slave. input data when it is configured as a slave. output data when it is a slave. SMTXD1—SMC1 transmit data output. SMRXD1—SMC1 receive data input.

SMSYN1—SMC1 external sync input. SMSYN2—SMC2 external sync input. SMTXD2—SMC2 transmit data output. L1CLKOB—Clock output from the serial interface TDM port B. SMRXD2—SMC2 receive data input. L1CLKOA—Clock output from the serial interface TDM port A. RTS1—Request to send modem line for SCC1. RTS2—Request to send modem line for SCC2.

22 TSPC860 [Preliminary]

DREQ0—IDMA channel 0 request input. RTS1—Request to send modem line for SCC1. DREQ1—IDMA channel 1 request input. RTS2—Request to send modem line for SCC2. CTS1—Clear to send modem line for SCC1. CD1—Carrier detect modem line for SCC1. TGATE1—Timer 1/timer 2 gate signal. CTS2—Clear to send modem line for SCC2. CD2—Carrier detect modem line for SCC2. TGATE2—Timer 3/timer 4 gate signal.

CTS3—Clear to send modem line for SCC3. L1TSYNCB—Transmit sync input for the serial interface TDM port B. CD3—Carrier detect modem line for SCC3. L1RSYNCB—Receive sync input for the serial interface TDM port B. CTS4—Clear to send modem line for SCC4. L1TSYNCA—Transmit sync input for the serial interface TDM port A. CD4—Carrier detect modem line for SCC4. L1RSYNCA—Receive sync input for the serial interface TDM port A. L1TSYNCA—Input transmit data sync signal to the TDM channel A. L1RSYNCA—Input receive data sync signal to the TDM channel A. L1TSYNCB—Input transmit data sync signal to the TDM channel B. L1RSYNCB—Input receive data sync signal to the TDM channel B. RXD3—Receive data for serial channel 3. TXD3—Transmit data for serial channel 3. RXD4—Receive data for serial channel 4. TXD4—Transmit data for serial channel 4.

24 TSPC860 [Preliminary]

Ethernet frame after it determines the frame address did not match. Ethernet frame after it determines the frame address did not match. Ethernet frame after it determines the frame address did not match. H16 Input Provides clock to scan chain logic or for the development port logic. Should be tied to Vcc if JTAG or development port are not used. power through a pull-up resistor if unused. connected to TRST and cathode to PORESET). Power V DDL—Power supply of the internal logic. VDDSYN—Power supply of the PLL circuitry. VSS—Ground for circuits, except for the PLL circuitry. VSSSYN, VSSSYN1—Ground for the PLL circuitry.

(that is, the pin is constantly driven low). driving (that is, the pin switches to high-impedance).  When disabled as an output or functioning as an input, it should not be driven. to the TSPC860, to the system, or to both. Figure 6. Three-State Buffers and Active Pull-Up Buffers Note: Events 1 and 4 can be in quick succession.

1 Drive high on one edge

2 Switch to Hi-Z on later edge

3 Pull-up resistor maintains logic high state

2 Switch to Hi-Z when threshold voltage

4 Disable buffer as output

5 Pull-up resistor maintains logic high state;

26 TSPC860 [Preliminary]

Table 2 summarizes when active pull-up drivers are enabled as outputs. pull-up resistor was added to TDI/DSDI. No other pins have internal pull-ups or pull-downs. the TSPC860 or should be connected to VCC if the default configuration is used. Table 2. Active Pull-Up Resistors Enabled as Outputs TS, BB When the TSPC860 is the external bus master throughout the entire bus cycle. BI When the TSPC860’s memory controller responds to the access on the external bus, throughout the entire bus cycle.

• For chip-selects controlled by the GPCM set for external TA, the TSPC860’s TA buffer is not enabled as an output.
• For chip-selects controlled by the GPCM set to terminate in n wait-states, TA is enabled as an output on cycle (n-1) and driven high, then is driven low on cycle n, terminating the bus transaction. External logic can drive TA at any point before this, thus terminating the cycle early. [For example, assume the GPCM is programmed to drive TA after 15 cycles. If external logic drives TA before 14 clocks have elapsed then the TA will be accepted by the TSPC860 as a cycle termination.]
• For chip-selects controlled by the UPM, the TA buffer is enabled as an output throughout the entire bus cycle.

TSPC860 [Preliminary] 2129B–HIREL–12/04 MODCK[1-2] must be used to determine the default clocking mode for the TSPC860. After hardware reset, the MODCK[1-2] pins change function and become outputs. Thus, if these alternate functions are also desired, then the MODCK[1-2] configuration should be set with three-state drivers that turn off after HRESET is negated; however, if MODCK[1-2] pins’ alternate output functions are not used in the system, they can be configured with pull-up and pull-down resistors. Signals with open-drain buffers and active pull-up buffers (HRESET, SRESET, TEA, TS, TA, BI , and BB ) must have external pull-up resistors. These signals include the following: Some other input signals do not absolutely r equire a pull-up resistor, as they may be actively driven by external logic. However, if they are not used externally, or if the exter- nal logic connected to them is not always ac tively driving, they may need external pull- up resistors to hold them negated. These signals include the following:  PORESET A S  CR/IRQ3 K R / R E T R Y/IRQ4/SPKROUT (if configured as KR/RETRY or IRQ4)  Any IRQx (if configured as IRQx)  BR (if the TSPC860’s internal bus arbiter is used)  BG (if an external bus arbiter is used) JTAG and Debug Ports TCK/DSCK or ALE_B/DSCK/AT1 (depending on the configuration of the DSCK func- tion) should be connected to ground through a pull-down resistor to disable Debug Mode as a default. When required, a debug mode controller tool externally drives this signal high actively to put the TSPC860 into debug mode. Two pins need special attention, depending on the version of TSPC860 used.  For TSPC860 rev B and later, TDI/DSDI should be pulled up to V CC to keep it from oscillating when unused.  For TSPC860 rev A.3 and earlier, TCK/DSCK should be connected to ground if it is configured for its DSCK function, as stated above. However, for these versions of the TSPC860, the pull-down resistor must be strong (for example, 1 kΩ to overcome the internal pull-up resistor. To allow application of any version of processor, perform both of the above actions. Unused Inputs In general, pull-up resistors should be used on any unused inputs to keep them from oscillating. For example, if PCMCIA is not used, the PCMCIA input pins (WAIT_A, WAIT_B, IP_A[0-8], IP_B[0-8]) should have external pull-up resistors. However, unused pins of port A, B, C, or D can be configured as outputs, and, if they are configured as outputs they do not require external terminations. Unused Outputs Unused outputs can be left unterminated. Signal States During Hardware Reset During hardware reset (HRESET or PORESET), the signals of the TSPC860 behave as follows:  The bus signals are high-impedance  The port I/O signals are configured as inputs, and are therefore high-impedance  The memory controller signals are driven to their inactive state

28 TSPC860 [Preliminary]

accordingly. The behavior of these signals is shown in Table 11. in compliance with MIL-STD-883 class Q or Atmel standard screening.

1. MIL-STD-883: Test methods and procedures for electronics
2. MIL-PRF-38535 appendix A: General specifications for microcircuits

Terminal Connections The terminal connections shall be as shown in the general description. Lead Material and Finish Lead material and finish shall be as specified on page 87. Table 3. Signal States during Hardware Reset

Package The macrocircuits are packaged in 357-lead Plastic Ball Grid Array (BGA) packages. The precise case outlines are described at the end of the specification. ature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

1. Per SEMI G38-87 and JEDEC JESD51-2 wit h the single layer board horizontal.
2. Per JEDEC JESD51-6 with the board horizontal.
3. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on

the top surface of the board near the package.

1. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method

the exposed pas without contact resistance.

1. Thermal characterization parameter indicating the temperature difference between package top and the junction tempera-

Table 4. Thermal Characteristics

30 TSPC860 [Preliminary]

2129B–HIREL–12/04 Note: 1. Typical power dissipation is measured at 3.3V 2. Maximum power dissipation is measured at 3.5V 3. Values in Table 5 represent V DDL-based power dissipation and do not include I/O power dissipation over VDDH. I/O power dissipation varies widely by application due to buffer current, depending on external circuitry

Electrical Characteristics

General Requirements All static and dynamic electrical characteristics specified for inspection purposes and the relevant measurement conditions are given below. Specifications Table 5. Power Dissipation (PD)(3)

66 TBD TBD mW

Table 6. DC Electrical Specification with VCC = 3.3 ± 5% VDC, GND = 0 VDC, -55°C ≤ Tc ≤ 125°C

Notes: 1. VIL(max) for the I 2C interface is 0.8V rather than the 1.5V as specified in the I2C standard.

1. Input capacitance is periodically sampled.

Table 6. DC Electrical Specification with VCC = 3.3 ± 5% VDC, GND = 0 VDC, -55°C ≤ Tc ≤ 125°C (Continued)

32 TSPC860 [Preliminary]

Figure 7. AC Electrical Specifications Control Timing Diagram

Table 7. Bus Operation Timings

33 MHz 40 MHz 50 MHz 66 MHz

34 TSPC860 [Preliminary]

Table 7. Bus Operation Timings (Continued)

36 TSPC860 [Preliminary]

38 TSPC860 [Preliminary]

Notes: 1. Phase and frequency jitter performance results are only va lid if the input jitter is less than the prescribed value.

1. If the rate of change of the frequency of EXTAL is slow (i .e. it does not jump between the minimum and maximum values in
2. The timings specified in B4 and B5 are based on full strength clock.
3. The timing for BR output is relevant when the PC860 is selected to work with the external bus arbiter. The timing for BG out-

put is relevant when the PC860 is selected to work with internal bus arbiter.

1. The timing required for BR input is relevant when the TSPC860 is selected to work with internal bus arbiter. The timing for

BG input is relevant when the TSPC860 is selected to work with internal bus arbiter.

1. The D (0:31) and DP (0:3) input timings B20 and B21 refer to the rising edge of the CLKOUT in which the TA input signal is
2. The D (0:31) and DP (0:3) input timings B20 and B21 refer to the falling edge of the CLKOUT. This timing is valid only for

in the UPM RAM words. (This is only the cases where data is latched on the falling edge of CLKOUT).

1. The timing B30 refers to CS when ACS = 00 and to WE (0:3) when CSNT = 0
2. The signal UPWAIT is considered asynchronous to the CLKO UT and synchronized internally. The timings specified in B37

and B38 are specified to enable the freeze of the UPM output signals as described in Figure 22.

1. The AS signal is considered asynchronous to the CLKOUT. The timing B39 is specified in order to allow the behavior speci-

Figure 8. External Clock Timing

40 TSPC860 [Preliminary]

Figure 11. Synchronous Input Signals Timing Figure 12. Input Data Timing in Normal Case Figure 13. Input Data Timing when controlled by UPM in the Memory Controller

Figure 14. External Bus Read Timing (GPCM Controlled – ACS = ‘00’)

42 TSPC860 [Preliminary]

Figure 15. External Bus Read Timing (GPCM Controlled – TRLX = ‘0’ ACS = ‘10’) Figure 16. External Bus Read Timing (GPCM Controlled – TRLX = ‘0’ ACS = ‘11’)

Figure 17. External Bus Read Timing (GPCM Controlled – TRLX = ‘1’, ACS = ‘10’, ACS = ‘11’)

44 TSPC860 [Preliminary]

Figure 18. External Bus Write Timing (GPCM controlled – TRLX = ‘0’, CSNT = ‘0’)

Figure 19. External Bus Write Timing (GPCM controlled – TRLX = ‘0’, CSNT = ‘1’)

46 TSPC860 [Preliminary]

Figure 20. External Bus Write Timing (GPCM controlled – TRLX = ‘1’, CSNT = ‘1’)

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Figure 23. Asynchronous UPWAIT Negated Detection in UPM Handled Cycles Timing Figure 24. Synchronous External Master Access Timing – GPCM handled ACS = ‘00’

50 TSPC860 [Preliminary]

Figure 27. Interrupt Detection Timing for External Level Sensitive Lines Figure 28. Interrupt Detection Timing for External Edge Sensitive Lines Notes: 1. PSST = 1. Otherwise add PSST times cycle time.

1. PSHT = 1. Otherwise add PSHT times cycle time.

Table 9. PCMCIA Timing

cycle. The WAITx assertion will be effective only if it is detected 2 cycles before the PSL timer expiration. Figure 29. PCMCIA Access Cycles Timing External Bus Read

52 TSPC860 [Preliminary]

Figure 30. PCMCIA Access Cycles Timing External Bus Write Figure 31. PCMCIA WAIT Signals Detection Timing Table 10. PCMCIA Port Timing

54 TSPC860 [Preliminary]

Figure 34. Debug Port Clock Input Timing Figure 35. Debug Port Timings

Figure 36. Reset Timing – Configuration from Data Bus Table 12. RESET Timing

56 TSPC860 [Preliminary]

Figure 37. Reset Timing – TSPC860 Data Bus Weak Drive during Configuration Figure 38. Reset Timing – Debug Port Configuration IEEE 1149.1 Electrical Specifications

58 TSPC860 [Preliminary]

Figure 41. JTAG – TRST Timing Diagram Figure 42. Boundary Scan (JTAG) Timing Diagram

Figure 43. PIP RX (Interlock Mode) Timing Diagram Table 14. PIP/PIO Timing

21 Data-In Setup Time to STBI Low 0 – ns

24 STBO Pulse Width 1 clk - 5 ns – ns

25 Data-Out Setup Time to STBO Low 2 – clk

26 Data-Out Hold Time from STBO High 5 – clk

27 STBI Low to STBO Low (Rx Interlock) – 2 clk

28 STBI Low to STBO High (Tx Interlock) 2 – clk

29 Data-In Setup Time to Clock Low 15 – ns

31 Clock High to Data-Out Valid (CPU Writ es Data, Control, or Direction) – 25 ns

60 TSPC860 [Preliminary]

Figure 44. PIP TX (Interlock Mode) Timing Diagram Figure 45. PIP RX (Pulse Mode) Timing Diagram

Figure 46. PIP TX (Pulse Mode) Timing Diagram Figure 47. Parallel I/O Data-in/Data-out Timing Diagram Figure 48. Port C Interrupt Detection Timing Table 15. Port C Interrupt Timing

35 Port C interrupt pulse width low (edge-triggered mode) 55 – ns

36 Port C interrupt minimum time between active edges 55 – ns

62 TSPC860 [Preliminary]

Figure 49. IDMA External Requests Timing Diagram Figure 50. SDACK Timing Diagram – Peripheral Write, TA Sampled Low at the Falling Edge of the Clock Table 16. IDMA Controller AC Electrical Specifications

40 DREQ Setup Time to Clock High 7 – ns

41 DREQ Hold Time from Clock High 3 – ns

42 SDACK Assertion Delay from Clock High – 12 ns

43 SDACK Negation Delay from Clock Low – 12 ns

44 SDACK Negation Delay from TA Low – 20 ns

45 SDACK Negation Delay from Clock High – 15 ns

46 TA Assertion to Falling Edge of the Clock Setup Time (applies to external TA)7 – n s

64 TSPC860 [Preliminary]

Figure 53. Baud Rate Generator Timing Diagram Figure 54. CPM General-Purpose Timers Timing Diagram Table 17. Baud Rate Generator AC Electrical Specifications

50 BRGO Rise and Fall Time – 10 ns

51 BRGO Duty Cycle 40 60 %

52 BRGO Cycle 40 – ns

Table 18. Timer AC Electrical Specifications

61 TIN/TGATE Rise and Fall Time 10 – ns

62 TIN/TGATE Low Time 1 – clk

63 TIN/TGATE High Time 2 – clk

64 TIN/TGATE Cycle Time 3 – clk

65 CLKO High to TOUT Valid 3 25 ns

Notes: 1. The ratio SyncCLK/L1RCL K must be greater than 2.5/1.

1. Where P = 1/CLKOUT. Thus for a 25 MHz CLKO1 rate, P = 40 ns.
2. These specs are valid for IDL mode only.
3. The strobes and T × D on the first bit of the frame becom e valid after L1CLK edge or L1SYNC, whichever comes later.

Table 19. Serial Interface AC Electrical Specifications

71 L1RCLK, L1TCLK Width Low (DSC = 0) (3) P+10 ns

72 L1TXD, L1ST(1-4), L1RQ, L1CLKO Rise/Fall Time – 15 ns

73 L1RSYNC, L1TSYNC Valid to L1CLK Edge (SYNC Setup Time) 20 – ns

74 L1CLK Edge to L1RSYNC, L1TSYNC Invalid (SYNC Hold Time) 35 – ns

75 L1RSYNC, L1TSYNC Rise/Fall Time – 15 ns

76 L1RXD Valid to L1CLK Edge (L1RXD Setup Time) 17 – ns

77 L1CLK Edge to L1RXD Invalid (L1RXD Hold Time) 13 – ns

78 L1CLK Edge to L1ST(1-4) Valid

79 L1CLK Edge to L1ST(1-4) Invalid 10 45 ns

80 L1CLK Edge to L1TXD Valid 10 55 ns

81 L1CLK Edge to L1TXD High Impedance 0 42 ns

82 L1RCLK, L1TCLK Frequency (DSC = 1) – 16 or SYNCCLK/2 MHz

83 L1RCLK, L1TCLK Width Low (DSC = 1) P+10 – ns

84 L1CLK Edge to L1CLKO Valid (DSC = 1) – 30 ns

85 L1RQ Valid Before Falling Edge of L1TSYNC (4) 1 – L1TCLK

86 L1GR Setup Time (3) 42 – ns

87 L1GR Hold Time 42 – ns

88 L1CLK Edge to L1SYNC Valid (FSD = 00, CNT = 0000, BYT = 0,

66 TSPC860 [Preliminary]

Figure 55. SI Receive Timing Diagram with Normal Clocking (DSC = 0)

Figure 56. SI Receive Timing with Double-Speed Clocking (DSC = 1)

68 TSPC860 [Preliminary]

Figure 57. SI Transmit Timing Diagram (DSC = 0)

Figure 58. SI Transmit Timing with Double Speed Clocking (DSC = 1)

70 TSPC860 [Preliminary]

Figure 59. IDL Timing

Notes: 1. The ratio SyncCLK/RCLK1 and SyncCLK/ TCLK1 must be greater or equal to 2.25/1.

1. Also applies to CD and CTS hold time when they are used as an external sync signals.
2. Also applies to CD and CTS hold time when they are used as an external sync signals.

Table 20. NMSI External Clock Timing

100 RCLK1 and TCLK1 Width High (1) 1/SYNCCLK – ns

101 RCLK1 and TCLK1 Width Low 1/SYNCCLK + 5 – ns

102 RCLK1 and TCLK1 Rise/Fall Time – 15 ns

103 TXD1 Active Delay (From TCLK1 Falling Edge) 0 50 ns

104 RTS1

105 CTS1 Setup Time to TCLK1 Rising Edge 5 – ns

106 RXD1 Setup Time to RCLK1 Rising Edge 5 – ns

107 RXD1 Hold Time from RCLK1 Rising Edge (2) 5– n s

108 CD1 Setup Time to RCLK1 Rising Edge 5 – ns

Table 21. NMSI Internal Clock Timing

100 RCLK1 and TCLK frequency1 (1) 0 SYNCCLK/3 MHz

102 RCLK1 and TCLK1 Rise/Fall Time – – ns

103 TXD1 Active Delay (From TCLK1 Falling Edge) 0 30 ns

105 CTS1 Setup Time to TCLK1 Rising Edge 40 – ns

106 RXD1 Setup Time to RCLK1 Rising Edge 40 – ns

107 RXD1 Hold Time from RCLK1 Rising Edge (2) 0– n s

108 CD1 Setup Time to RCLK1 Rising Edge 40 – ns

72 TSPC860 [Preliminary]

Figure 60. SCC NMSI Receive Timing Diagram Figure 61. SCC NMSI Transmit Timing Diagram

Figure 62. HDLC Bus Timing Diagram

1. SDACK is asserted whenever the SDMA writes the incoming frame DA into memory.

Table 22. Ethernet Electrical Specifications

120 CLSN Width High 40 – ns

121 RCLK1 Rise/Fall Time – 15 ns

122 RCLK1 Width Low 40 – ns

123 RCLK1 Clock Period

124 RXD1 Setup Time 20 – ns

125 RXD1 Hold Time 5 – ns

126 RENA Active Delay (From RCLK1 Rising Edge of the Last Data Bit) 10 – ns

127 RENA Width Low 100 – ns

128 TCLK1 Rise/Fall Time – 15 ns

129 TCLK1 Width Low 40 – ns

130 TCLK1 Clock Period

131 TXD1 Active Delay (From TCLK1 Rising Edge) 10 50 ns

132 TXD1 Inactive Delay (From TCLK1 Rising Edge) 10 50 ns

133 TENA Active Delay (From TCLK1 Rising Edge) 10 50 ns

134 TENA Inactive Delay (From TCLK1 Rising Edge) 10 50 ns

135 RSTRT

136 RSTRT Inactive Delay (From TCLK1 Falling Edge) 10 50 ns

137 REJECT Width Low 1 – CLK

138 CLKO1 Low to SDACK Asserted(2) –2 0 n s

139 CLKO1 Low to SDACK Negated(2) –2 0 n s

74 TSPC860 [Preliminary]

Figure 63. Ethernet Collision Timing Diagram Figure 64. Ethernet Receive Timing Diagram Figure 65. Ethernet Transmit Timing Diagram Notes: 1. Transmit clock invert (TCI) bit in GSMR is set.

1. If RENA is deasserted before TENA, or RENA is not asserted at all during transmit, then the CSL bit is set in the buffer

descriptor at the end of the frame transmission.

Figure 66. CAM Interface Receive Start Timing Diagram Figure 67. CAM Interface REJECT Timing Diagram Note: 1. The ratio SYNCCLK/SMCLK must be greater or equal to 2/1. Table 23. SMC Transparent AC Electrical specifications

150 SMCLK Clock Period (1) 100 – ns

151 SMCLK Width Low 50 – ns

152 SMCLK Rise/Fall Time – 15 ns

153 SMTXD active delay (from SMCLK falling edge) 10 50 ns

154 SMRXD/SMSYNC setup time 20 – ns

155 RXD1/SMSYNC1 Hold Time 5 – ns

76 TSPC860 [Preliminary]

Figure 68. SMC Transparent Timing Diagram Note: 1. This delay is equal to an integer number of “character length” clocks. Table 24. SPI Master AC Electrical Specifications

160 Master Cycle Time 4 1024 t cyc

161 Master Clock (SCK) High or Low Time 2 512 t cyc

162 Master Data Setup Time (Inputs) 50 – ns

163 Master Data Hold Time (Inputs) 0 – ns

164 Master Data Valid (After SCK Edge) – 20 ns

165 Master Data Hold Time (Outputs) 0 – ns

166 Rise Time Output – 15 ns

167 Fall Time Output – 15 ns

78 TSPC860 [Preliminary]

Figure 71. SPI Slave (CP = 0) Timing Diagram Table 25. SPI Slave AC Electrical Specifications

170 Slave Cycle Time 2 – tcyc

171 Slave Enable Lead Time 15 – ns

172 Slave Enable Lag Time 15 – ns

173 Slave Clock (SPICLK) High or Low Time 1 – tcyc

174 Slave Sequential Transfer Delay (Does Not Require

175 Slave Data Setup Time (Inputs) 20 – ns

176 Slave Data Hold Time (Inputs) 20 – ns

177 Slave Access Time – 50 ns

Figure 72. SPI Slave (CP = 1) Timing Diagram The ratio SYNCCLK/(BRGCLK/pre_scaler) must be greater or equal to 4/1. Table 26. I2C AC Electrical Specifications – SCL < 100 kHz

200 SCL Clock Frequency (SLAVE) 0 100 KHz

200 SCL Clock Frequency (MASTER)

207 DATA Hold Time 0 – µs

208 DATA Setup Time 250 – ns

209 SDL/SCL Rise Time – 1 µs

210 SDL/SCL Fall Time – 300 ns

80 TSPC860 [Preliminary]

The ratio SYNCCLK/(BRG_CLK/pre_scaler) must be greater or equal to 4/1. Figure 73. I2C Bus Timing Diagram Table 27. I2C AC Electrical Specifications – SCL > 100 kHz

200 SCL Clock Frequency (SLAVE) fSCL 0 BRGCLK/48 Hz

200 SCL Clock Frequency (MASTER) (1) fSCL BRGCLK/16512 BRGCLK/48 Hz

207 DATA Hold Time 0 – s

208 DATA Setup Time 1/(40 × fSCL) – s

209 SDL/SCL Rise Time – 1/(10 × fSCL) s

210 SDL/SCL Fall Time – 1/(33 × fSCL) s

TSPC860 [Preliminary] 2129B–HIREL–12/04 Preparation For Delivery Packaging Microcircuits are prepared for delivery in accordance with MIL-PRF-38535. Certificate of Compliance Atmel offers a certificate of compliances with each shipment of parts, affirming the prod- ucts are in compliance either with MIL-STD-883 and guarantying the parameters not tested at temperature extremes for the entire temperature range. Power Consideration The average chip-junction temperature, Tj, in °C can be obtained from the equation: Tj = TA + (PD · ΟJA) (1) where T A = Ambient temperature, °C ΟJA = Package thermal resistance, junction to ambient, °C/W PD = PINT + PI/O PINT = IDD × VDD, watts – chip internal power PI/O = Power dissipation on input and output pins – user determined For most applications P I/O < 0.3 · P INT and can be neglected. If P I/O is neglected, an approximate relationship between PD and TJ is: Solving equations (1) and (2) for K gives: K = PD · T (TA + 273°C) + ΟJA · PD 2 (3) where K is a constant pertaining to the particular part. K can be determined from equa- tion (3) by measuring P D (at equilibrium) for a known T A. Using this value of K, the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA. Layout Practices Each VDD pin on the TSPC860 should be provided with a low-impedance path to the board’s supply. Each GND pin should likewise be provided with a low-impedance path to ground. The power supply pins drive distinct groups of logic on chip. The V DD power supply should be bypassed to ground using at least four 0.1 µF bypass capacitors located as close as possible to the four sides of the package. The capacitor leads and associated printed circuit traces connecting to chip V DD and GND should be kept to less than half an inch per capacitor lead. A four-layer board, employing two inner layers as V DD and GND planes is recommended. All output pins on the TSPC860 have fast rise and fall times. Printed circuit (PC) trace interconnection length should be minimized in order to minimize undershoot and reflec- tions caused by these fast output switching times. This recommendation particularly applies to the address and data busses. Maximum PC trace lengths of six inches are recommended. Capacitance calculations should consider all device loads as well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and bypass- ing becomes especially critical in system s with higher capacitive loads because these loads create higher transient current in the V DD and GND circuits. Pull up all unused inputs or signals that will be inputs during re set. Special care should be taken to mini- mize the noise levels on the PLL supply pins.

82 TSPC860 [Preliminary]

2129B–HIREL–12/04 Functional Units The TSPC860 PowerQUICC integrates the Embedded PowerPC Core with high perfor- mance, low power peripherals to extend the Freescale Data Communications family of embedded processors even farther into high end communications and networking prod- ucts. The TSPC860 PowerQUICC is comprised of three modules which all use the 32-bit internal bus: the Embedded PowerPC Core, the System Integration Unit (SIU), and the Communication Processor Module (CPM). The TSPC860 PowerQUICC block diagram is shown in Figure 1. Embedded PowerPC Core The Embedded PowerPC Core is compliant with the Book 1 specification for the Pow- erPC architecture. The Embedded PowerPC Core is a fully static design that consists of two functional blocks; the integer block and the load/store block. It executes all integer and load/store operations directly on the hardware. The core supports integer opera- tions on a 32-bit internal data path and 32-bit arithmetic hardware. The core interface to the internal and external buses is 32 bits. The core uses a two instruction load/store queue, a four instruction prefetch queue, and a six instruction history buffer. The core does branch folding and branch prediction with conditional pre-fetch but without condi- tional execution. The Embedded PowerP C Core can operate on 32-bit external operands with one bus cycle. The PowerPC integer block supports 32 × 32-bit fixed point general purpose registers. It can execute one integer instruction each clock cycle. Each element in the integer block is clocked only when valid data is present in the data queue ready for operation. This assures that the power consumption of the device is held to the absolute minimum required to perform an operation. The Embedded PowerPC Core is integrated with MMU’s as well as 4 kbyte instruction and data caches. Each MMU provides a 32 ent ry, fully associative instruction and data TLB, with multiple page sizes of: 4 KB, 16 KB, 512 KB, 256 KB and 8 MB. It will support 16 virtual address spaces with 8 protection groups. Three special registers are available as scratch registers to support software table walk and update.The instruction cache is 4 kilobytes, two-way, set asso ciative with physical addressing. It allows single cycle access on hit with no added latency for miss. It has four words per line, supporting burst line fill using Least Recently Used (LRU) replacement. The cache can be locked on a per line basis for application critical routines. The data cache is 4 kilobytes, two-way, set associative with physical addressing. It allows single cycle access on hit with one added clock latency for miss. It has four words per line, supporting burst line fill using LRU replacement. The cache can be locked on a per line basis for application critical routines. The data cache can be programmed to support copy-back or write-through via the MMU. The inhibit mode can be programmed per MMU page. The Embedded PowerPC Core with its Instruction and data caches delivers approxi- mately 52 MIPS at 40 MHz, using Dhryst one 2.1, based on the assumption that it is issuing one instruction per cycle with a cache hit rate of 94%. The Embedded PowerPC Core contains a much improved debug interface that provides superior debug capabilities without causing any degradation in the speed of operation. This interface supports six watchpoint pins that are used to detect software events. Internally it has eight comparators, four of which operate on the effective address on the address bus. The remaining four comparators are split, with two comparators the effec- tive address on the data bus, and two comparators operating on the data on the data bus. The Embedded PowerPC Core can compare using =, ≠, <, > conditions to generate watchpoints. Each watchpoint can then generate a breakpoint that can be programmed to trigger in a programmable number of events.

TSPC860 [Preliminary] 2129B–HIREL–12/04 System Interface Unit (SIU) The SIU on the TSPC860 PowerQUICC integr ates general-purpose features useful in almost any 32-bit processor system, enhancing the performance provided by the system integration module (SIM) on the TS68EN360 QUICC device. Although the Embedded PowerPC Core is always a 32-bit device internally, it may be configured to operate with an 8-, 16- or 32-bit data bus. Regardless of the choice of the system bus size, dynamic bus sizing is supported. Bus sizing allows 8-, 16-, and 32-bit peripherals and memory to exist in the 32-bit system bus mode. The SIU also provides power management functions, Reset control, PowerPC decre- menter, PowerPC time base and PowerPC real time clock. The memory controller will support up to eight memory banks with glueless interfaces to DRAM, SRAM, SSRAM, EPROM, Flash EPROM , SRDRAM, EDO and other peripher- als with two-clock access to external SRAM and bursting support. It provides variable block sizes from 32 kilobytes to 256 megabytes. The memory controller will provide 0 to 15 wait states for each bank of memory and can use address type matching to qualify each memory bank access. It provides f our byte enable signals for varying width devices, one output enable signal and one boot chip select available at reset. The DRAM interface supports port sizes of 8, 16, and 32 bits. Memory banks can be defined in depths of 256K, 512k, 1M, 2M, 4M, 8M, 16M, 32M, or 64M for all port sizes. In addition the memory depth can be defined as 64K and 128K for 8-bit memory or 128M and 256M for 32-bit memory. The DRAM controller supports page mode access for suc- cessive transfers within bursts. The TSPC86 0 will support a glueless interface to one bank of DRAM while external buffers are required for additional memory banks. The refresh unit provides CAS before RAS, a programmable refresh timer, refresh active during external reset, disable refresh modes , and stacking up to 7 refresh cycles. The DRAM interface uses a programmable state machine to support almost any memory interface. PCMCIA Controller The PCMCIA interface is a master (socket) controller and is compliant with release 2.1. The interface will support up to two independe nt PCMCIA sockets requiring only exter- nal transceivers/buffers. The interface prov ides 8 memory or I/O windows where each window can be allocated to a particular so cket. If only one PCMCIA port is being used, the unused PCMCIA port may be used as general-purpose input with interrupt capability. Power Management The TSPC860 PowerQUICC supports a wide range of power management features including Full On, Doze, Sleep, Deep Sleep, and Low Power Stop. In Full On mode the TSPC860 processor is fully powered with all internal units operating at the full speed of the processor. A Gear mode is provided which is determined by a clock divider, allowing the OS to reduce the operational frequency of the processor. Doze mode disables core functional units other than the time base decrementer, PLL, memory controller, RTC, and then places the CPM in low power standby mode. Sleep mode disables everything except the RTC and PIT, leaving the PLL for lower power but slower wake-up. Low Power Stop disables all logic in the proc essor except the minimum logic required to restart the device, providing the lowest power consumption but requiring the longest wake-up time.

84 TSPC860 [Preliminary]

2129B–HIREL–12/04 Communications Processor Module (CPM) The TSPC860 PowerQUICC is the next generation TS68EN360 QUICC and like its pre- decessor implements a dual processor archit ecture. This dual processor architecture provides both a high performance general purpose processor for application program- ming use as well as a special purpose communication processor (CPM) uniquely designed for communications needs. The CPM contains features that allow the TSPC860 PowerQUICC to excel in communi- cations and networking products as did the TS68EN360 QUICC which preceded it. These features may be divided into three sub-groups:  Communications Processor (CP)  Sixteen Independent DMA (SDMA) Controllers  Four General-Purpose Timers The CP provides the communication features of the TSPC860 PowerQUICC. Included are a RISC processor, four Serial Communication Controllers (SCC) four Serial Man- agement Controllers (SMC), one Serial Peripheral Interface (SPI), one I

2 Interface, 5

kilobytes of dual-port RAM, an interrupt cont roller, a time slot assigner, three parallel ports, a parallel interface port, four independent baud rate generators, and sixteen serial DMA channels to support the SCCs, SMCs, SPI, and I 2C. The SDMAs provide two chan nels of general-purpose DMA capability for each commu- nications channel. They o ffer high-speed transfers, 32-bit data movement, buffer chaining, and independent request and acknowledge logic. The four general-purpose timers on the CPM are identical to the timers found on the MC68360 and still support the internal cascading of two timers to form a 32-bit timer. The TSPC860 PowerQUICC maintains the best features of the TS68EN360 QUICC, while making changes required to provide for the increased flexibility, integration, and performance requested by customers demanding the performance of the powerPC architecture. The addition of a Multiply-And-Accumulate (MAC) function on the CPM fur- ther enhances the TSPC860 PowerQUICC, enabling various modem and DSP applications. Because the CPM architectural approach remains intact between the TSPC860 PowerQUICC and the TS68EN360 QUICC, a user of the TS68EN360 QUICC can easily become familiar with the TSPC860 PowerQUICC.

some minor changes necessary for supporting the MAC function. the CPM on the TSPC860 processor even simpler. however, a glueless system is maintained. Figure 74. TSPC860 System Configuration

86 TSPC860 [Preliminary]

Packaging Microcircuits are prepared for delivery in accordance with MIL-PRF-38535. tested at temperature extremes for the entire temperature range. The plastic package parameters are as provided in the following list. Table 28. Package Description

Figure 75. Mechanical Dimensions and Bottom Surface Nomenclature of the ZP PBGA Package

0.03 C A B

1. Dimensioning and tolerancing per ASME Y 14.5M, 1994
2. Dimensions in Millimeters
3. Dimension b is the solder ball diameter measured

88 TSPC860 [Preliminary]

Figure 76. Mechanical Dimensions and Bottom Surface Nomenclature of the ZQ PBGA Package

0.03 A B C

1. All dimensions in millimeters
2. Dimensions and tolerance per
3. Maximum solder ball diameter measured

TSPC860 [Preliminary] 2129B–HIREL–12/04

Ordering Information

Applications

These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can r easonably be expected to result in personal injury. Atmel customers using or selling these products for use in such applications do so at their own risk and agree to fully indem nify Atmel for any damages resulting from such improper use or sale. Prototype Temperature range: TC M: -55, +125˚C V: -40, +110˚C PC860 ZQ U 66TS (X) MDSR Version SR Prefix For availability of the different versions, contact your sales office Type Package ZP: PBGA ZQ: PBGA Screening level U: Upscreening Max internal processor speed 66: 66 MHz Revision level D: rev D.4 Definitions Datasheet Status Validity Objective Specification This datasheet contains target and goal specifications for discussion with the customer and application validation Before design phase Target Specification This datasheet contains target or goal specifications for product development Valid during the design phase Preliminary Specification α site This datasheet contains preliminary data. Additional data may be published at a later date and could include simulation results Valid before characterization phase Preliminary Specification β site This datasheet also contains characterization results Valid before the industrialization phase Product Specification This datasheet contains final product specifications Valid for production purpose Limiting Values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

90 TSPC860 [Preliminary]

Table 29 provides a revision history for this hardware specification. Table 29. Document Revision History See “Ordering Information” on page 89.

i TSPC860 [Preliminary] 2129B–HIREL–12/04

ii TSPC860 [Preliminary] 2129B–HIREL–12/04

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