TSOT0410G4

TSOT0410G4 AGERE | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 190

Technical content

Features

I Section overhead (RSOH) and line overhead (MSOH) termination, and path overhead monitoring for one SONET STS-192 (SDH STM-64) or four STS-48 (STM-16) signals. I Supports any valid combination of STS-1 and concatenated payloads from STS-3c to STS-192c. I Microprocessor interface configurable to operate with most commercial microprocessors. I IEEE ® 1149.1 port with memory built-in self-test (BIST), scan, and boundary scan (JTAG). I Low-power 2.5 V operation with 3.3 V (5 V tolerant) inputs and outputs. I EIA®-644, IEEE 1596.3 compliant LVDS buffers*. I 600-pin LBGA package. I –40 °C to +85 °C temperature range. STS-192/STM-64 (Line Interface) I Provides a 16-bit (or 4× 4-bit) wide, 622 MHz differ- ential line interface. I Synchronizes to the receive data frames and detects severely errored framing (SEF) and loss of frame (LOF). Also inserts the framing bytes (A1 and A2) in the transmit data. I Supports enhanced framing (A1, A1, A2, A2). I Performs frame-synchronous scrambling and descrambling of the STS-192/STS-48 data, and loss of signal (LOS) is detected. I Extracts the 64-byte or 16-byte section trace mes- sage (J0) from the receive data and optionally stores it in, or compares it to, an internal register bank. Unstable or mismatched messages are detected, and path alarm indication signal (AIS) may be optionally inserted in the drop data. I Optionally inserts a 64-byte or 16-byte section trace message or a fixed pattern in the J0 byte of the transmit data. I Extracts and outputs, on a serial link, all transport overhead bytes in the receive data and inserts any, or all, transport overhead bytes in the transmit data using a corresponding serial input. I Extracts and outputs, on serial links, the section user channel (F1), orderwire channels (E1, E2), and data communication channels (D1—D3 and D4—D12) for the receive data. Inserts correspond- ing serial input signals into the transmit data. I Extracts, integrates, and stores the automatic pro- tection switch (APS) channel bytes (K1, K2) for the receive data and detects protection switch failure alarms. Inserts APS bytes in the transmit data from internal registers or from add data overhead bytes. I Detects line alarm indication signal (AIS) and remote defect indication (RDI) based on the K2 byte of the receive data. Inserts line AIS and RDI in the transmit data. Optionally inserts line RDI auto- matically due to LOS, LOF, or line AIS defects. I Extracts, integrates, and stores the synchronization status byte (S1) for the receive data. Inserts the synchronization status byte into the transmit data from an internal register or from a value encoded on the transmit frame synchronous input. I Calculates, detects, and counts section and line BIP-8 errors (B1, B2) for the receive data, and inserts BIP-8 in the transmit data. Supports either bit or block error accumulation of B1 errors (sepa- rately provisionable), and bit error accumulation of B2 errors. I Extracts and counts line remote errors (REI) for the receive data (M1), and inserts REI in the transmit data based on B2 errors. I SS bit mode supports SONET (00) or SDH (10) val- ues and defines the value of the SS bits for unequipped signal insertion. In normal mode, SS bits can be passed through or overwritten with a provisioned value. All SS bit provisioning is done at a STM-16 level affecting all AU-3s. I The B1 error mask can be extracted serially on the ROHDAT interface, and the B2 error mask can be extracted serially on the local orderwire, express orderwire, and orderwire clock pins. * Refer to LVDS Receiver Buffer Capabilities section on page 169 for additional details.

2 Agere Systems Inc. Data Sheet May 2003STS-192 Overhead and Path Processor TSOT0410G4 SONET/SDH

Table of Contents (continued) Contents Page Agere Systems Inc. 3 Data Sheet May 2003 STS-192 Overhead and Path Processor TSOT0410G4 SONET/SDH

Table of Contents (continued) Contents Page 4 Agere Systems Inc. Data Sheet May 2003STS-192 Overhead and Path Processor TSOT0410G4 SONET/SDH

Table 88. Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 x 10

12 Agere Systems Inc. Data Sheet May 2003STS-192 Overhead and Path Processor TSOT0410G4 SONET/SDH Features (continued) Add/Drop (Equipment Interface) I Provides sixteen 1-bit serial 622 MHz (STS-12 rate) differential data links at the add and drop interfaces. Path overhead and SPE timing indication is provided by the drop interface. I Clock recovery and data skew compensation are provided at the add interface. Transmit frame alignment synchronization may be controlled via an input (TFRM), or may optionally derived from any one of sixteen add inputs. I Interprets the pointer bytes (H1, H2) for each receive STS and detects loss of pointer (LOP) and path AIS. Generates new pointer bytes in each drop STS to adapt the receive data to the drop frequency and phase. Pointer generation can be bypassed for synchronous applications. I Optionally inserts path AIS in all drop STS pointer bytes during LOS, LOF, SEF, or line AIS (MS-AIS) defects. Optionally inserts path AIS in each drop STS due to LOP or path AIS defects in the corresponding receive STS, or under software control. I Inserts pointer bytes in the transmit data based on values received in the transport overhead bytes of the add data. Optionally inserts path AIS in each transmit STS under control by software, or through bits in the transport overhead of the add data. I Extracts the 64-byte or 16-byte path trace message (J1) from up to four selectable receive STS channels (one per STS-48), and stores it in an internal register bank. Optionally compares the message to an expected message stored in the internal register bank and detects an unstable or mismatched message. I Calculates, detects, and accumulates path BIP-8 errors (B3) for each receive STS (provisionable based on bit or block errors). Provides signal fail detection with provisionable BER. I Extracts and counts path REI for each receive STS (G1). I Detects path unequipped, payload label mismatch (PLM), and optionally, payload defect indication (PDI) in the C2 byte of each receive STS. Optionally inserts unequipped signal in each transmit STS under software control. I Detects 1-bit and enhanced path RDI (3-bit) in each receive STS (G1). I Outputs path alarm information for each receive STS in the overhead bytes of the drop data (E1/F1). I Optional TOH transparency capability on the line interface to/from the TOH on the equipment interface. Either full TOH transparency, or just line overhead (MSOH) transparency with section overhead (RSOH) insertion/extraction, may be selected. In the receive direction, the section overhead will be used for path alarm information if section overhead transparency is not selected. The pointer processor will be automatically bypassed if any of these options are selected. I Optional loopback of the receive data and overhead towards the transmit line interface in STS-192 mode. The transmit clock is replaced by the receive clock at the 622 MHz level external to the chip, with the add interface buffers used to align the data between the receive and transmit clock domains. The TFRM signal is replaced by receive frame timing to transfer from the receive to the transmit clock domains. I Active per-STS-48 transmit line AIS insert controls during receive LOS, receive LOF, or R_CLK failure while in regenerator loopback mode. I The add interface self-sync provides the option to use frame timing being recovered from one of the add pseudo-STS-12 links as the transmit frame sync instead of TFRM. The resynchronizing is inhibited if the selected add pseudo-STS-12 link is out of frame (OOF).

Applications

I SONET/SDH add/drop multiplex equipment. I SONET/SDH terminal equipment. I SONET/SDH digital cross connect equipment. I SONET/SDH regenerator equipment. I SONET/SDH test equipment. I ATM or packet over SONET/SDH equipment.

Figure 2. TSOT0410G4 Block Diagram, STS-48 Mode that may be specific to this device and/or may be unfamiliar to the reader. condition, and 1-bit PM indicates that a condition was present at some time during the last second.

Agere Systems Inc. 15 Data Sheet May 2003 STS-192 Overhead and Path Processor TSOT0410G4 SONET/SDH Description (continued) Receive Direction Overview In the receive direction, the receive line interface can accept either a single STS-192 (STM-64) signal or four STS-48 (STM-16) signals, from optical-to-electrical modules, in 16-bit or 4-bit wide serial 622 MHz format. The receive line interface synchronizes to the frames in each data channel and rotates the data to frame and byte align it. The data may also be optionally descrambled. The aligned data is received by the receive transport overhead processor, and the section (regenerator section) and line (multiplex section) overhead are extracted. Most of the overhead is then either stored internally or pro- vided on external serial outputs, except for the pointer bytes, which are passed to the receive pointer processor. The receive pointer processor interprets the pointer bytes and provides the SONET payload envelope (SPE) timing for the receive-path overhead processor and the receive-drop data aligner (pointer processor). The receive-path overhead processor extracts the path overhead and either stores it internally or processes it for alarms and performance statistics. The receive-drop data aligner then translates the data from the receive clock domain to the drop clock domain using a small elastic store and pointer adjustments to the data. The resulting aligned data is then converted to sixteen 1-bit wide serial 622 MHz streams by the receive payload drop interface and output along with SPE timing signals for use by a payload mapping device. Transmit Direction Overview In the transmit direction, the transmit payload add interface accepts sixteen 1-bit wide serial 622 MHz pseudo* STS-12 (STM-4) signals and recovers the clock for each. The resulting 16 clocks must be synchronous in fre- quency, but can be asynchronous in phase. Each clock is used to frame, byte align, descramble, and then write its associated data stream into a small buffer. The data is then read out of all 16 buffers using transmit clock (T_CLK) and transmit frame (TFRM) timing. The converted data is passed along to the transmit transport overhead processor which adds the appropriate sec- tion and line overhead. This overhead is either provided by internal configuration registers or external serial inputs, except for the pointer bytes, which are received in the add data. The resulting valid STS-192 (STM-64) or STS-48 (STM-16) data is then optionally scrambled, converted to one 16-bit wide or four 4-bit wide serial 622 MHz signals, and output for use by electrical-to-optical modules. Transmit frame alignment synchronization may optionally be derived from any one of the 16 (selectable) add inputs. A software provisioning option allows transmit frame alignment synchronization to be provided using the timing that is being recovered from one of the add pseudo STS-12 links as the transmit frame sync instead of TFRM. * The data is formatted as an STS-12 signal; however, most of the transport overhead bytes are either unused or may be used for proprietary purposes.

16 Agere Systems Inc. Data Sheet May 2003STS-192 Overhead and Path Processor TSOT0410G4 SONET/SDH Description (continued) STS-192 Mode Options TOH Transparency In applications where it is desired, a pass-through capability using software provisioning for the TOH on the line interface to/from the TOH on the equipment interface is provided for the receive and transmit direction. This feature is always supported on individual STS-48 channels and will require all four channels to be provisioned in STS-192 mode. On the receive side, when TOH transparency is enabled, the pointer generators and elastic stores in all path pro- cessing blocks are bypassed. In this case, receive timing will be used by the payload drop interface. The receive direction has the option for full TOH transparency, or just line overhead transparency with section overhead is used for the normal proprietary drop I/F overhead. When TOH transparency is enabled, the pointer processor (PP) will be bypassed on a per STS-48 level. See the Receive Pointer Processor section on page 62 for more information on how this mode effects the device. The transmit direction has the option for full TOH transparency or just line overhead (MSOH) transparency with section (RSOH) overhead inserted. If enabled, AIS insertion due to an E1/F1 code in the add TOH will be disabled. Regenerator Loopback In applications where the receive data and overhead bytes need to be transmitted towards the transmit line inter- face, a software regenerator loopback provisioning option is provided. To use this feature, the transmit clock must be derived from the receive clock at the 622 MHz level external to the device. The add interface buffers align the data between the receive and transmit clock domains. This mode will only function correctly when the device is in STS-192 mode. It will not work in STS-48 mode since the four STS-48 streams need to be aligned through the transmit side. Four received STS-48 streams are unlikely to be aligned to the same clock and frame alignment. The appropriate per STS-48 transmit line AIS insert control will be active during receive LOS, receive LOF, or R_CLK failure while in regenerator loopback. Device Mode Setup The basic operating mode of the TSOT0410G4 is set using external pins. The device can operate as a single STS-192 channel or as four separate STS-48 channels. The STS_MODE pin (AM17) determines which mode is used. Pulling the STS_MODE pin down to VSS selects STS-192 mode. In applications where no rate adaptation is required or desired, the pointer generators and elastic stores in all path processing blocks can be bypassed by pulling up the DRPBYP pin (AP11) to VDD. In this case, receive timing will be used by the payload drop interface. This mode should only be used if the device is in STS-192 mode. See the Receive Pointer Processor section on page 62 for more information on how this mode affects the device. The microprocessor interface can be set up to be synchronous by pulling up the MPMODE pin (E14) to V DD, or asynchronous by pulling down the pin to VSS. See the Microprocessor Interface section on page 93 for more infor- mation. For normal device operation, the TRST_N pin (AP30) should be tied low (to VSS). If TRST_N is high, a TCK clock must be present.

Table 1. Pin Assignments for 600-Pin LBGA by Pin Number Order Note: NC refers to no connect. Do not connect pins so designated.

Table 1. Pin Assignments for 600-Pin LBGA by Pin Number Order (continued) Note: NC refers to no connect. Do not connect pins so designated.

Note: NC refers to no connect. Do not connect pins so designated.

Note: NC refers to no connect. Do not connect pins so designated.

Note: NC refers to no connect. Do not connect pins so designated.

Table 2. Pin Assignments for 600-Pin LBGA by Signal Name Order Note: NC refers to no connect. Do not connect pins so designated.

Table 2. Pin Assignments for 600-Pin LBGA by Signal Name Order (continued) Note: NC refers to no connect. Do not connect pins so designated.

Note: NC refers to no connect. Do not connect pins so designated.

Note: NC refers to no connect. Do not connect pins so designated.

Note: NC refers to no connect. Do not connect pins so designated. Table 3. Pin Descriptions—System Control

1. I = input, Id = input with internal pull-down resistor, I u = input with internal pull-up resistor. The value of all internal pull-up/pull-down re-

sistors is 50 kΩ . All I/Os in Table 3 are 5 V tolerant, 3.3 V TTL. They will tolerate 5 V at their inputs or outputs. held low for a minimum of 26 ns (at least two 77.76 MHz clock cycles). d STS Mode Select. See the Device Mode Setup section on page 16 for details. 0 = Enable pointer generator. is 325 ns (during testing and development, for example).

Table 4. Pin Descriptions—Receive Line Interface

1. I = input, O = output, LVDS = low-voltage differential signal.

STS_MODE = 1: STS-48 receive channel 1 clock (622 MHz). STS_MODE = 0: STS-192 receive channel 1 clock (622 MHz). STS_MODE = 1: STS-48 clock loopback output for channel 1. STS_MODE = 0: STS-192 clock loopback. STS_MODE = 1: STS-48 receive channel 1 bit 1 (LSB). STS_MODE = 0: STS-192 receive channel 1 bit 0 (LSB). STS_MODE = 1: STS-48 receive channel 1 bit 2. STS_MODE = 0: STS-192 receive channel 1 bit 1. STS_MODE = 1: STS-48 receive channel 1 bit 3. STS_MODE = 0: STS-192 receive channel 1 bit 2. STS_MODE = 1: STS-48 receive channel 1 bit 4. STS_MODE = 0: STS-192 receive channel 1 bit 3. STS_MODE = 1: STS-48 receive channel 1 frame sync. STS_MODE = 0: STS-192 receive channel 1 frame sync. STS_MODE = 1: STS-48 receive channel 2 clock (622 MHz). STS_MODE = 1: STS-48 clock loopback output for channel 2. STS_MODE = 0: Copy of receive clock 1 loopback. STS_MODE = 1: STS-48 receive channel 2 bit 1 (LSB). STS_MODE = 0: STS-192 receive channel 1 bit 4. STS_MODE = 1: STS-48 receive channel 2 bit 2. STS_MODE = 0: STS-192 receive channel 1 bit 5. STS_MODE = 1: STS-48 receive channel 2 bit 3. STS_MODE = 0: STS-192 receive channel 1 bit 6. STS_MODE = 1: STS-48 receive channel 2 bit 4. STS_MODE = 0: STS-192 receive channel 1 bit 7. STS_MODE = 1: STS-48 receive channel 2 frame sync. STS_MODE = 1: STS-48 receive channel 3 clock (622 MHz). STS_MODE = 1: STS-48 clock loopback output for channel 3. STS_MODE = 0: Copy of receive clock 1 loopback. STS_MODE = 1: STS-48 receive channel 3 bit 1 (LSB). STS_MODE = 0: STS-192 receive channel 1 bit 8. STS_MODE = 1: STS-48 receive channel 3 bit 2. STS_MODE = 0: STS-192 receive channel 1 bit 9.

Table 4. Pin Descriptions—Receive Line Interface (continued) Table 5. Pin Descriptions—Transmit Line Interface

1. I = input, O = output, LVDS = low-voltage differential signal.

STS_MODE = 1: STS-48 receive channel 3 bit 3. STS_MODE = 0: STS-192 receive channel 1 bit 10. STS_MODE = 1: STS-48 receive channel 3 bit 4. STS_MODE = 0: STS-192 receive channel 1 bit 11. STS_MODE = 1: STS-48 receive channel 3 frame sync. STS_MODE = 1: STS-48 receive channel 4 clock (622 MHz). STS_MODE = 1: STS-48 clock loopback output for channel 4. STS_MODE = 0: Copy of receive clock 1 loopback. STS_MODE = 1: STS-48 receive channel 4 bit 1 (LSB). STS_MODE = 0: STS-192 receive channel 1 bit 12. STS_MODE = 1: STS-48 receive channel 4 bit 2. STS_MODE = 0: STS-192 receive channel 1 bit 13. STS_MODE = 1: STS-48 receive channel 4 bit 3. STS_MODE = 0: STS-192 receive channel 1 bit 14. STS_MODE = 1: STS-48 receive channel 4 bit 4. STS_MODE = 0: STS-192 receive channel 1 bit 15 (MSB). STS_MODE = 1: STS-48 receive channel 4 frame sync.

1. I = input, O = output, LVDS = low-voltage differential signal.

the clock input to the entire transmit section. high for at least 32 more T_CLK periods after the rising edge. Transmit Clock 1 Loopback. Transmit clock output. STS_MODE = 1: STS-48 clock output for channel 1. STS_MODE = 0: STS-192 transmit clock output. STS_MODE = 1: STS-48 transmit channel 1 bit 1 (LSB). STS_MODE = 0: STS-192 transmit channel 1 bit 0 (LSB).

Table 5. Pin Descriptions—Transmit Line Interface (continued)

1. O = output, LVDS = low-voltage differential signal.

STS_MODE = 1: STS-48 transmit channel 1 bit 2. STS_MODE = 0: STS-192 transmit channel 1 bit 1. STS_MODE = 1: STS-48 transmit channel 1 bit 3. STS_MODE = 0: STS-192 transmit channel 1 bit 2. STS_MODE = 1: STS-48 transmit channel 1 bit 4. STS_MODE = 0: STS-192 transmit channel 1 bit 3. Transmit Clock 2 Loopback. Transmit clock output. STS_MODE = 1: STS-48 clock output for channel 2. STS_MODE = 0: Copy of transmit clock 1 loopback. STS_MODE = 1: STS-48 transmit channel 2 bit 1 (LSB). STS_MODE = 0: STS-192 transmit channel 1 bit 4. STS_MODE = 1: STS-48 transmit channel 2 bit 2. STS_MODE = 0: STS-192 transmit channel 1 bit 5. STS_MODE = 1: STS-48 transmit channel 2 bit 3. STS_MODE = 0: STS-192 transmit channel 1 bit 6. STS_MODE = 1: STS-48 transmit channel 2 bit 4. STS_MODE = 0: STS-192 transmit channel 1 bit 7. Transmit Clock 3 Loopback. Transmit clock output. STS_MODE = 1: STS-48 clock output for channel 3. STS_MODE = 0: Copy of transmit clock 1 loopback. STS_MODE = 1: STS-48 transmit channel 3 bit 1 (LSB). STS_MODE = 0: STS-192 transmit channel 1 bit 8. STS_MODE = 1: STS-48 transmit channel 3 bit 2. STS_MODE = 0: STS-192 transmit channel 1 bit 9. STS_MODE = 1: STS-48 transmit channel 3 bit 3. STS_MODE = 0: STS-192 transmit channel 1 bit 10. STS_MODE = 1: STS-48 transmit channel 3 bit 4. STS_MODE = 0: STS-192 transmit channel 1 bit 11. Transmit Clock 4 Loopback. Transmit clock output. STS_MODE = 1: STS-48 clock output for channel 4. STS_MODE = 0: Copy of transmit clock 1 loopback. STS_MODE = 1: STS-48 transmit channel 4 bit 1 (LSB). STS_MODE = 0: STS-192 transmit channel 1 bit 12. STS_MODE = 1: STS-48 transmit channel 4 bit 2. STS_MODE = 0: STS-192 transmit channel 1 bit 13. STS_MODE = 1: STS-48 transmit channel 4 bit 3. STS_MODE = 0: STS-192 transmit channel 1 bit 14. STS_MODE = 1: STS-48 transmit channel 4 bit 4. STS_MODE = 0: STS-192 transmit channel 1 bit 15 (MSB).

Table 6. Pin Descriptions—LVDS Reference, Line Interface

1. I = input. I LVDS term = low-voltage differential signal termination pin.

shown in Figure 3 on page 35. shown in Figure 3 on page 35. AN31 RESHIL I Connect a 100 Ω ± 1% resistor between these pins.

Table 7. Pin Descriptions—Receive Drop Equipment Interface

1. I = input, O = output, I/O = bidirectional pin, LVDS = low-voltage differential signal. All I/O not explicitly stated with a buffer type are 3.3 V TTL.

AN11 D_CLK I/O DRPBYP = 1: output: receive channel 1 clock (78 MHz). DRPBYP = 0: input: receive drop clock (78 MHz)—all channels. AM11 DFRM I/O DRPBYP = 1: output: receive channel 1 frame sync. DRPBYP = 0: input: receive drop frame sync—all channels. Receive drop STS-12 channel 1 serial data (622 MHz). AP15 RDDCC_1 I Receive drop STS-12 channel 1 section DCC serial link. Receive drop STS-12 channel 2 serial data (622 MHz). AN15 RDDCC_2 I Receive drop STS-12 channel 2 section DCC serial link. Receive drop STS-12 channel 3 serial data (622 MHz). AL15 RDDCC_3 I Receive drop STS-12 channel 3 section DCC serial link. Receive drop STS-12 channel 4 serial data (622 MHz). AM15 RDDCC_4 I Receive drop STS-12 channel 4 section DCC serial link. Receive drop STS-12 channels 1—4 timing control (622 MHz). AR15 RDDCK_1 O Receive drop STS-12 channels 1—4 section DCC clock. Receive drop STS-12 channel 5 serial data (622 MHz). AP14 RDDCC_5 I Receive drop STS-12 channel 5 section DCC serial link. Receive drop STS-12 channel 6 serial data (622 MHz). AN14 RDDCC_6 I Receive drop STS-12 channel 6 section DCC serial link. Receive drop STS-12 channel 7 serial data (622 MHz). AL14 RDDCC_7 I Receive drop STS-12 channel 7 section DCC serial link. Receive drop STS-12 channel 8 serial data (622 MHz). AM14 RDDCC_8 I Receive drop STS-12 channel 8 section DCC serial link. Receive drop STS-12 channels 5—8 timing control (622 MHz). AR14 RDDCK_2 O Receive drop STS-12 channels 5—8 section DCC clock.

Table 7. Pin Descriptions—Receive Drop Equipment Interface (continued)

1. I = input, O = output, I/O = bidirectional pin, LVDS = low-voltage differential signal. All I/O not explicitly stated with a buffer type are 3.3 V TTL.

Receive drop STS-12 channel 9 serial data (622 MHz). AN13 RDDCC_9 I Receive drop STS-12 channel 9 section DCC serial link. Receive drop STS-12 channel 10 serial data (622 MHz). AM13 RDDCC_10 I Receive drop STS-12 channel 10 section DCC serial link. Receive drop STS-12 channel 11 serial data (622 MHz). AL13 RDDCC_11 I Receive drop STS-12 channel 11 section DCC serial link. Receive drop STS-12 channel 12 serial data (622 MHz). AR12 RDDCC_12 I Receive drop STS-12 channel 12 section DCC serial link. Receive drop STS-12 channels 9—12 timing control (622 MHz). AP13 RDDCK_3 O Receive drop STS-12 channels 9—12 section DCC clock. Receive drop STS-12 channel 13 serial data (622 MHz). AN12 RDDCC_13 I Receive drop STS-12 channel 13 section DCC serial link. Receive drop STS-12 channel 14 serial data (622 MHz). AM12 RDDCC_14 I Receive drop STS-12 channel 14 section DCC serial link. Receive drop STS-12 channel 15 serial data (622 MHz). AL12 RDDCC_15 I Receive drop STS-12 channel 15 section DCC serial link. Receive drop STS-12 channel 16 serial data (622 MHz). AR11 RDDCC_16 I Receive drop STS-12 channel 16 section DCC serial link. Receive drop STS-12 channels 13—16 timing control (622 MHz). AP12 RDDCK_4 O Receive drop STS-12 channels 13—16 section DCC clock.

Table 8. Pin Descriptions—Transmit Add Equipment Interface

1. I = input, O = output, LVDS = low-voltage differential signal. All I/O not explicitly stated with a buffer type are 3.3 V TTL.

Transmit add STS-12 channel 1 serial data (622 MHz). E9 TADCC_1 O Transmit add STS-12 channel 1 section DCC serial link. Transmit add STS-12 channel 2 serial data (622 MHz). B8 TADCC_2 O Transmit add STS-12 channel 2 section DCC serial link. Transmit add STS-12 channel 3 serial data (622 MHz). C8 TADCC_3 O Transmit add STS-12 channel 3 section DCC serial link. Transmit add STS-12 channel 4 serial data (622 MHz). D8 TADCC_4 O Transmit add STS-12 channel 4 section DCC serial link. Transmit add STS-12 channel 5 serial data (622 MHz). E8 TADCC_5 O Transmit add STS-12 channel 5 section DCC serial link. Transmit add STS-12 channel 6 serial data (622 MHz). B7 TADCC_6 O Transmit add STS-12 channel 6 section DCC serial link. Transmit add STS-12 channel 7 serial data (622 MHz). C7 TADCC_7 O Transmit add STS-12 channel 7 section DCC serial link. Transmit add STS-12 channel 8 serial data (622 MHz). D7 TADCC_8 O Transmit add STS-12 channel 8 section DCC serial link. Transmit add STS-12 channel 9 serial data (622 MHz). E7 TADCC_9 O Transmit add STS-12 channel 9 section DCC serial link. Transmit add STS-12 channel 10 serial data (622 MHz). B6 TADCC_10 O Transmit add STS-12 channel 10 section DCC serial link.

Table 8. Pin Descriptions—Transmit Add Equipment Interface (continued)

1. I = input, O = output, LVDS = low-voltage differential signal. All I/O not explicitly stated with a buffer type are 3.3 V TTL.

Transmit add STS-12 channel 11 serial data (622 MHz). C6 TADCC_11 O Transmit add STS-12 channel 11 section DCC serial link. Transmit add STS-12 channel 12 serial data (622 MHz). D6 TADCC_12 O Transmit add STS-12 channel 12 section DCC serial link. Transmit add STS-12 channel 13 serial data (622 MHz). E6 TADCC_13 O Transmit add STS-12 channel 13 section DCC serial link. Transmit add STS-12 channel 14 serial data (622 MHz). B5 TADCC_14 O Transmit add STS-12 channel 14 section DCC serial link. Transmit add STS-12 channel 15 serial data (622 MHz). C5 TADCC_15 O Transmit add STS-12 channel 15 section DCC serial link. Transmit add STS-12 channel 16 serial data (622 MHz). D5 TADCC_16 O Transmit add STS-12 channel 16 section DCC serial link. D9 TADCK O Transmit add STS-12 section DCC clock—all channels.

Table 9. Pin Descriptions—LVDS Reference, Equipment Interface Figure 3. Suggested Schematic for 1.0 V and 1.4 V Reference Voltages

1. I = input. I LVDS term = low-voltage differential signal termination pin.

through an external 0.01 µF capacitor to ground. through an external 0.01 µF capacitor to ground. through an external 0.01 µF capacitor to ground. through an external 0.01 µF capacitor to ground. AL3 RESHIE I Connect a 100 Ω ± 1% resistor between these pins.

Table 10. Pin Descriptions—Transport Overhead Interface

1. I = input, O = output. All I/O not explicitly stated with a buffer type are 3.3 V TTL.

AP28 REXPOW_1 O STS_MODE = 1: STS-48 receive channel 1 express orderwire. STS_MODE = 0: STS-192 receive channel 1 express orderwire. AL27 RLCLOW_1 O STS_MODE = 1: STS-48 receive channel 1 local orderwire. STS_MODE = 0: STS-192 receive channel 1 local orderwire. AM25 RSUSER_1 O STS_MODE = 1: STS-48 receive channel 1 section user channel. STS_MODE = 0: STS-192 receive channel 1 section user channel. AN26 ROW_CLK_1 O STS_MODE = 1: STS-48 receive channel 1 orderwire/user clock. STS_MODE = 0: STS-192 receive channel 1 orderwire/user clock. AM27 RLDCC_1 O STS_MODE = 1: STS-48 receive channel 1 line DCC. STS_MODE = 0: STS-192 receive channel 1 line DCC. AN27 RLD_CLK_1 O STS_MODE = 1: STS-48 receive channel 1 line DCC clock. STS_MODE = 0: STS-192 receive channel 1 line DCC clock. AP26 RSDCC_1 O STS_MODE = 1: STS-48 receive channel 1 section DCC. STS_MODE = 0: STS-192 receive channel 1 section DCC. AR26 RSD_CLK_1 O STS_MODE = 1: STS-48 receive channel 1 section DCC clock. STS_MODE = 0: STS-192 receive channel 1 section DCC clock. AP27 ROHDAT_1_0 O STS_MODE = 1: STS-48 receive channel 1 TOH data (LSB). STS_MODE = 0: Receive STS-1 channel 1—48 TOH data (LSB). AR27 ROHDAT_1_1 O STS_MODE = 1: STS-48 receive channel 1 TOH data (MSB). STS_MODE = 0: Receive STS-1 channel 1—48 TOH data (MSB). AL26 ROHFP_1 O STS_MODE = 1: STS-48 receive channel 1 TOH frame pulse. STS_MODE = 0: Receive STS-1 channel 1—48 TOH frame pulse. AM26 ROH_CLK_1 O STS_MODE = 1: STS-48 receive channel 1 TOH clock. STS_MODE = 0: Receive STS-1 channel 1—48 TOH clock. E28 TEXPOW_1 I STS_MODE = 1: STS-48 transmit channel 1 express orderwire. STS_MODE = 0: STS-192 transmit channel 1 express orderwire. D28 TLCLOW_1 I STS_MODE = 1: STS-48 transmit channel 1 local orderwire. STS_MODE = 0: STS-192 transmit channel 1 local orderwire. B29 TSUSER_1 I STS_MODE = 1: STS-48 transmit channel 1 section user channel. STS_MODE = 0: STS-192 transmit channel 1 section user channel. E29 TOW_CLK_1 O STS_MODE = 1: STS-48 transmit channel 1 orderwire/user clock. STS_MODE = 0: STS-192 transmit channel 1 orderwire/user clock. C29 TLDCC_1 I STS_MODE = 1: STS-48 transmit channel 1 line DCC. STS_MODE = 0: STS-192 transmit channel 1 line DCC. C30 TLD_CLK_1 O STS_MODE = 1: STS-48 transmit channel 1 line DCC clock. STS_MODE = 0: STS-192 transmit channel 1 line DCC clock.

Table 10. Pin Descriptions—Transport Overhead Interface (continued)

1. I = input, O = output. All I/O not explicitly stated with a buffer type are 3.3 V TTL.

D29 TSDCC_1 I STS_MODE = 1: STS-48 transmit channel 1 section DCC. STS_MODE = 0: STS-192 transmit channel 1 section DCC. B30 TSD_CLK_1 O STS_MODE = 1: STS-48 transmit channel 1 section DCC clock. STS_MODE = 0: STS-192 transmit channel 1 section DCC clock. E30 TOHDAT_1_0 I STS_MODE = 1: STS-48 transmit channel 1 TOH data (LSB). STS_MODE = 0: Transmit STS-1 channel 1—48 TOH data (LSB). B31 TOHDAT_1_1 I STS_MODE = 1: STS-48 transmit channel 1 TOH data (MSB). STS_MODE = 0: Transmit STS-1 channel 1—48 TOH data (MSB). C31 TOHEN_1 I STS_MODE = 1: STS-48 transmit channel 1 TOH insert enable. STS_MODE = 0: Transmit STS-1 channel 1—48 TOH insert enable. D31 TOHFP_1 O STS_MODE = 1: STS-48 transmit channel 1 TOH frame pulse. STS_MODE = 0: Transmit STS-1 channel 1—48 TOH frame pulse. D30 TOH_CLK_1 O STS_MODE = 1: STS-48 transmit channel 1 TOH clock. STS_MODE = 0: Transmit STS-1 channel 1—48 TOH clock. AN25 REXPOW_2 O STS_MODE = 1: STS-48 receive channel 2 express orderwire. AP25 RLCLOW_2 O STS_MODE = 1: STS-48 receive channel 2 local orderwire. AP23 RSUSER_2 O STS_MODE = 1: STS-48 receive channel 2 section user channel. AL23 ROW_CLK_2 O STS_MODE = 1: STS-48 receive channel 2 orderwire/user clock. AR25 RLDCC_2 O STS_MODE = 1: STS-48 receive channel 2 line DCC. AL24 RLD_CLK_2 O STS_MODE = 1: STS-48 receive channel 2 line DCC clock. AM23 RSDCC_2 O STS_MODE = 1: STS-48 receive channel 2 section DCC. AN23 RSD_CLK_2 O STS_MODE = 1: STS-48 receive channel 2 section DCC clock. AM24 ROHDAT_2_0 O STS_MODE = 1: STS-48 receive channel 2 TOH data (LSB). STS_MODE = 0: Receive STS-1 channel 49—96 TOH data (LSB). AN24 ROHDAT_2_1 O STS_MODE = 1: STS-48 receive channel 2 TOH data (MSB). STS_MODE = 0: Receive STS-1 channel 49—96 TOH data (MSB). AP24 ROHFP_2 O STS_MODE = 1: STS-48 receive channel 2 TOH frame pulse. STS_MODE = 0: Receive STS-1 channel 49—96 TOH frame pulse. AR24 ROH_CLK_2 O STS_MODE = 1: STS-48 receive channel 2 TOH clock. STS_MODE = 0: Receive STS-1 channel 49—96 TOH clock.

1. I = input, O = output. All I/O not explicitly stated with a buffer type are 3.3 V TTL.

B26 TEXPOW_2 I STS_MODE = 1: STS-48 transmit channel 2 express orderwire. B25 TLCLOW_2 I STS_MODE = 1: STS-48 transmit channel 2 local orderwire. C26 TSUSER_2 I STS_MODE = 1: STS-48 transmit channel 2 section user channel. C25 TOW_CLK_2 O STS_MODE = 1: STS-48 transmit channel 2 orderwire/user clock. E26 TLDCC_2 I STS_MODE = 1: STS-48 transmit channel 2 line DCC. D25 TLD_CLK_2 O STS_MODE = 1: STS-48 transmit channel 2 line DCC clock. A27 TSDCC_2 I STS_MODE = 1: STS-48 transmit channel 2 section DCC. A26 TSD_CLK_2 O STS_MODE = 1: STS-48 transmit channel 2 section DCC clock. B27 TOHDAT_2_0 I STS_MODE = 1: STS-48 transmit channel 2 TOH data (LSB). STS_MODE = 0: Transmit STS-1 channel 49—96 TOH data (LSB). C27 TOHDAT_2_1 I STS_MODE = 1: STS-48 transmit channel 2 TOH data (MSB). STS_MODE = 0: Transmit STS-1 channel 49—96 TOH data (MSB). D27 TOHEN_2 I STS_MODE = 1: STS-48 transmit channel 2 TOH insert enable. STS_MODE = 0: Transmit STS-1 channel 49—96 TOH insert enable. C28 TOHFP_2 O STS_MODE = 1: STS-48 transmit channel 2 TOH frame pulse. STS_MODE = 0: Transmit STS-1 channel 49—96 TOH frame pulse. B28 TOH_CLK_2 O STS_MODE = 1: STS-48 transmit channel 2 TOH clock. STS_MODE = 0: Transmit STS-1 channel 49—96 TOH clock. AL22 REXPOW_3 O STS_MODE = 1: STS-48 receive channel 3 express orderwire. AM22 RLCLOW_3 O STS_MODE = 1: STS-48 receive channel 3 local orderwire. AN20 RSUSER_3 O STS_MODE = 1: STS-48 receive channel 3 section user channel. AP21 ROW_CLK_3 O STS_MODE = 1: STS-48 receive channel 3 orderwire/user clock. AN22 RLDCC_3 O STS_MODE = 1: STS-48 receive channel 3 line DCC. AP22 RLD_CLK_3 O STS_MODE = 1: STS-48 receive channel 3 line DCC clock.

1. I = input, O = output. All I/O not explicitly stated with a buffer type 3.3 V TTL.

AR21 RSDCC_3 O STS_MODE = 1: STS-48 receive channel 3 section DCC. AM20 RSD_CLK_3 O STS_MODE = 1: STS-48 receive channel 3 section DCC clock. AR22 ROHDAT_3_0 O STS_MODE = 1: STS-48 receive channel 3 TOH data (LSB). STS_MODE = 0: Receive STS-1 channels 97—144 TOH data (LSB). AL21 ROHDAT_3_1 O STS_MODE = 1: STS-48 receive channel 3 TOH data (MSB). STS_MODE = 0: Receive STS-1 channels 97—144 TOH data (MSB). AM21 ROHFP_3 O STS_MODE = 1: STS-48 receive channel 3 TOH frame pulse. STS_MODE = 0: Receive STS-1 channels 97—144 TOH frame pulse. AN21 ROH_CLK_3 O STS_MODE = 1: STS-48 receive channel 3 TOH clock. STS_MODE = 0: Receive STS-1 channels 97—144 TOH clock. E22 TEXPOW_3 I STS_MODE = 1: STS-48 transmit channel 3 express orderwire. C22 TLCLOW_3 I STS_MODE = 1: STS-48 transmit channel 3 local orderwire. D22 TSUSER_3 I STS_MODE = 1: STS-48 transmit channel 3 section user channel. B23 TOW_CLK_3 O STS_MODE = 1: STS-48 transmit channel 3 orderwire/user clock. E23 TLDCC_3 I STS_MODE = 1: STS-48 transmit channel 3 line DCC. C23 TLD_CLK_3 O STS_MODE = 1: STS-48 transmit channel 3 line DCC clock. A24 TSDCC_3 I STS_MODE = 1: STS-48 transmit channel 3 section DCC. D23 TSD_CLK_3 O STS_MODE = 1: STS-48 transmit channel 3 section DCC clock. B24 TOHDAT_3_0 I STS_MODE = 1: STS-48 transmit channel 3 TOH data (LSB). STS_MODE = 0: Transmit STS-1 channels 97—144 TOH data (LSB). C24 TOHDAT_3_1 I STS_MODE = 1: STS-48 transmit channel 3 TOH data (MSB). STS_MODE = 0: Transmit STS-1 channels 97—144 TOH data (MSB). D24 TOHEN_3 I STS_MODE = 1: STS-48 transmit channel 3 TOH insert enable. STS_MODE = 0: Transmit STS-1 channels 97—144 TOH insert enable. A25 TOHFP_3 O STS_MODE = 1: STS-48 transmit channel 3 TOH frame pulse. STS_MODE = 0: Transmit STS-1 channels 97—144 TOH frame pulse.

1. I = input, O = output. All I/O not explicitly stated with a buffer type 3.3 V TTL.

E24 TOH_CLK_3 O STS_MODE = 1: STS-48 transmit channel 3 TOH clock. STS_MODE = 0: Transmit STS-1 channels 97—144 TOH clock. AP20 REXPOW_4 O STS_MODE = 1: STS-48 receive channel 4 express orderwire. AL19 RLCLOW_4 O STS_MODE = 1: STS-48 receive channel 4 local orderwire. AL17 RSUSER_4 O STS_MODE = 1: STS-48 receive channel 4 section user channel. AP18 ROW_CLK_4 O STS_MODE = 1: STS-48 receive channel 4 orderwire/user clock. AM19 RLDCC_4 O STS_MODE = 1: STS-48 receive channel 4 line DCC. AN19 RLD_CLK_4 O STS_MODE = 1: STS-48 receive channel 4 line DCC clock. AR17 RSDCC_4 O STS_MODE = 1: STS-48 receive channel 4 section DCC. AN17 RSD_CLK_4 O STS_MODE = 1: STS-48 receive channel 4 section DCC clock. AP19 ROHDAT_4_0 O STS_MODE = 1: STS-48 receive channel 4 TOH data (LSB). STS_MODE = 0: Receive STS-1 channels 145—192 TOH data (LSB). AN18 ROHDAT_4_1 O STS_MODE = 1: STS-48 receive channel 4 TOH data (MSB). STS_MODE = 0: Receive STS-1 channels 145—192 TOH data (MSB). AL18 ROHFP_4 O STS_MODE = 1: STS-48 receive channel 4 TOH frame pulse. STS_MODE = 0: Receive STS-1 channels 145—192 TOH frame pulse. AM18 ROH_CLK_4 O STS_MODE = 1: STS-48 receive channel 4 TOH clock. STS_MODE = 0: Receive STS-1 channels 145—192 TOH clock. D19 TEXPOW_4 I STS_MODE = 1: STS-48 transmit channel 4 express orderwire. E19 TLCLOW_4 I STS_MODE = 1: STS-48 transmit channel 4 local orderwire. B19 TSUSER_4 I STS_MODE = 1: STS-48 transmit channel 4 section user channel. D20 TOW_CLK_4 O STS_MODE = 1: STS-48 transmit channel 4 orderwire/user clock. B20 TLDCC_4 I STS_MODE = 1: STS-48 transmit channel 4 line DCC. A21 TLD_CLK_4 O STS_MODE = 1: STS-48 transmit channel 4 line DCC clock.

1. I = input, O = output. All I/O not explicitly stated with a buffer type are 3.3 V TTL.

C20 TSDCC_4 I STS_MODE = 1: STS-48 transmit channel 4 section DCC. B21 TSD_CLK_4 O STS_MODE = 1: STS-48 transmit channel 4 section DCC clock. C21 TOHDAT_4_0 I STS_MODE = 1: STS-48 transmit channel 4 TOH data (LSB). STS_MODE = 0: Transmit STS-1 channels 145—192 TOH data (LSB). E21 TOHDAT_4_1 I STS_MODE = 1: STS-48 transmit channel 4 TOH data (MSB). STS_MODE = 0: Transmit STS-1 channels 145—192 TOH data (MSB). D21 TOHEN_4 I STS_MODE = 1: STS-48 transmit channel 4 TOH insert enable. STS_MODE = 0: Transmit STS-1 channels 145—192 TOH insert enable. B22 TOHFP_4 O STS_MODE = 1: STS-48 transmit channel 4 TOH frame pulse. STS_MODE = 0: Transmit STS-1 channels 145—192 TOH frame pulse. A22 TOH_CLK_4 O STS_MODE = 1: STS-48 transmit channel 4 TOH clock. STS_MODE = 0: Transmit STS-1 channels 145—192 TOH clock.

Table 11. Pin Descriptions—Microprocessor Interface

1. I/O = bidirectional pin, I = input, O = output. All I/O not explicitly stated with a buffer type are 5 V tolerant, 3.3 V TTL. T hey will tolerate 5 V

face is in synchronous mode (MPMODE = 1). A14 CS_N I Chip Select (Active-Low). This signal must be low during register access. I Transfer Start or Address Strobe (Active-Low). Transfer start (TS_N) when MPMODE = 1 (synchronous). Address strobe (AS_N) when MPMODE = 0 (asynchronous). mode (MPMODE = 0), indicates that the data is valid for MPU writes. . This signal is used to indicate a read or write operation. acknowledge the completion of a data transfer cycle. when the microprocessor interface is in synchronous mode (MPMODE = 1). alarm that generated the interrupt is cleared.

Table 11. Pin Descriptions—Microprocessor Interface (continued) Table 12. Pin Descriptions—JTAG Interface

1. I/O = bidirectional pin, I = input, O = output. All I/O not explicitly stated with a buffer type are 5 V tolerant, 3.3 V TTL. T hey will tolerate 5 V
2. O = output, Id = input with internal pull-down resistor, I u = input with internal pull-up resistor. The value of all internal pull-up/pull-down

resistors is 50 kΩ . All I/O not explicitly stated with a buffer type are 5 V tolerant, 3.3 V TTL. They will tolerate 5 V at their inputs or outputs. AM29 TCK I d Test Clock. This signal provides timing for test operations. AL29 TDI I d Test Data In. TDI is sampled on the rising edge of TCK. 3-stated except when scanning out test data. AP30 TRST_N I u Test Reset (Active-Low). This signal provides an asynchronous reset for the TAP.

Table 13. Pin Descriptions—PLL References Table 14. Pin Descriptions—Power and Ground

1. I = input. All inputs in Table 13 are 3.3 V TTL.

connected through a 100 kΩ resistor to analog ground (VSSA). externally connected through a 100 kΩ resistor to analog ground (VSSA). externally connected through a 100 kΩ resistor to analog ground (VSSA). externally connected through a 100 kΩ resistor to analog ground (VSSA). externally connected through a 100 kΩ resistor to analog ground (VSSA). VDD P 3.3 V Positive Supply Voltage. DD2P 2.5 V Positive Supply Voltage.

Table 14. Pin Descriptions—Power and Ground (continued) PLL power is 350 mW for the device. I J4 is the power supply for the add interface PLL. between VSSA pins, and between VSS and VSSA. I J5 is the analog ground for the add interface PLL.

Table 15. Pin Summary

1. No connect (NC) pins indicated with a footnote (2) are unused. There is no connection between the pin and the die.

VDD2 through 47 kΩ resistors for normal operation. SS through 47 kΩ resistors for normal operation. NC — No Connect. Do not connect to these pins.

Agere Systems Inc. 47 Data Sheet May 2003 STS-192 Overhead and Path Processor TSOT0410G4 SONET/SDH Functional Description Receive STS-192 Line Interface The receive STS-192 line interface is configured to accept either a single 16-bit wide serial STS-192 stream at 622.08 MHz or four 4-bit wide serial STS-48 streams at 622.08 MHz, and convert them to four STS-48 streams. The conversion process is essentially the same for both input formats, except that for STS-48 data, each function is divided into four independent blocks running on separate clocks, while the STS-192 data is processed in one block and must be passed through a time-slot interchange (TSI) block after the conversion process to demultiplex its four constituent STS-48 channels. Regardless of which line format is being used, each input serial stream is first byte and frame aligned by passing it through a bit rotator to align it. The frame alignment used by the bit rotator is determined by a framer circuit which monitors the nonaligned word. The data from the bit rotator is then passed to a BIP-8 parity calculator before being optionally descrambled. The descrambled data is then either passed directly to one of the STS-48 processing modules when in STS-48 mode, or first passed to a TSI when in STS-192 mode. This TSI reorders the STS-1 slots within the STS-192 to appear as four STS-48 signals, as required by the STS-48 processing modules. In STS-192 mode, all 16 data streams are clocked on the positive edge of R_CLK_1. In STS-48 mode, the four data streams associated with each STS-48 are clocked in on the positive edge of a corresponding clock, R_CLK_n. Loss-of-Signal (LOS) Detector Before the data is optionally descrambled, it is monitored for loss-of-signal (LOS). In STS-192 mode, there is a sin- gle LOS detector. In STS-48 mode, there is a separate LOS detector on each STS-48 input. On powerup, an LOS defect is declared if all zeros data is received continuously for 13.8µs. This time threshold is provisionable through the loss-of-signal (LOS) threshold register for each channel, and can be set to any value from 0 µs (i.e., LOS detection disabled) to 105 µs, with a resolution of 102.88 ns (64 times the period of the 622.08 MHz clock). The LOS defect is subsequently cleared when two successive valid framing patterns are received with no period of all zeros exceeding the time threshold. Detection of an LOS defect is indicated by a latched alarm status bit, a per- sistency bit, and a one second PM bit being set in the corresponding LTE receive channel n registers. In addition, alarm indication signal (AIS) will be inserted by the framer block in all 48 or 192 STS-1 channels affected. If an optical transponder is connected to the receive line interface, the most appropriate method to declare LOS is by monitoring the power level monitor of the received signal from the transponder. In some transponders, the amplifier gain is high enough to cause the LVDS receive data lines to move above zero, even when there is no optical input. Should this occur, the TSOT0410G4 might not indicate an LOS defect. This is not a deficiency of the devices, but is a characteristic of the methods of detecting LOS. If an optical transponder is used, the LOS detector of the TSOT0410G4 monitors the connection from the tran- sponder to the receive line interface. The LOS detector in the TSOT0410G4 is appropriate for monitoring LOS in an electrical SONET or SDH system.

page 97) for details on other occurrences of similar registers. Table 16. LOS Detector Register Summary line, is also supported in STS-192 mode. 0x1F00 should be set to normal mode when the TSOT0410G4 is operating in STS-48 mode. ing (LOF) SONET framing alarms for each channel. The framer FSM is shown in Figure 4 on page 49. I The LOF alarm is asserted if SEF persists for 24 frames (3 ms). FSM enters the in-frame state), provided the SEF state is not re-entered (as per SONET objectives).

1. Qty. refers to the number of registers that are similar to the one shown in the table. There may be more registers to control different chan-

nels, or several registers of similar type used for a particular function.

1. 1st Addr refers to the address (in hex) of the first occurrence of this type of register.
2. Page refers to the relevant page number in this document.

Figure 4. Framer FSM –3. This is greater than the minimum average SONET requirement of 6 minutes. On powerup, detection of an LOF defect causes AIS to be inserted in all affected STS-1 channels by the framer. the framed channels. Parity errors can be forced using the chip-level maintenance register.

Table 17. Framer Register Summary Table 18. Descrambler Register Summary ing. The TSI reorders the data so that the STS-192 is divided into its four constituent STS-48 data streams. starting with the top left of each channel, and then down each column. If the TSOT0410G4 is in STS-48 mode, the data is received on all four channels and the TSI is bypassed.

Table 19. STS-192 Byte Ordering Table 20. STS-48 Byte Ordering Note: STS-12 byte ordering is shown in Table 29 on page 62.

ther processed for alarm or performance monitoring purposes. of each byte is detailed in the subsections that follow. (41.472 MHz). The location of the MSB of the first A1 byte is identified by the ROHFP_n output going high. described in the Receive Overhead Serial Link section on page 175. ROHDAT should synchronize to each of the four channels independently using the individual ROHFP signals. regardless of the mode (STS-48 or STS-192) in which the device is operating. Table 21. Receive Overhead Serial Links Register Summary

Agere Systems Inc. 53 Data Sheet May 2003 STS-192 Overhead and Path Processor TSOT0410G4 SONET/SDH Functional Description (continued) Section Trace (J0) The section trace byte is present in the first STS-1 of the STS-48 or STS-192 only. Specified by the J0 message type control bit, the TOH processor supports extraction of either SONET 64-byte (ASCII, <CR><LF> terminated) or SDH 16-byte (E.164) section trace messages that are stored in internal memory. Processing of the received mes- sage then depends on the J0 message mode control bit. The content of the message is either monitored for a mis- match from a provisioned expected message or monitored for a sustained change (validation) in the received message. If the J0 message mode control bit is set to the provisioned mode, then the incoming message is compared against the software programmed expected message. The expected message is stored in internal memory for each STS-48 channel. A mismatch is declared if a consistent received message differs from the expected message for ten consecutive messages. The mismatch clears when four out of five received messages match the expected message (fixed windowing is used for clearing). This mismatch state is reflected in the J0 message mismatch alarm bit. When the J0 message mode control bit is set to the validated mode, the incoming message is monitored for a sus- tained change. A sustained change is detected when the received message differs from the last stable message for ten consecutive messages. The new message then becomes the stable message, is stored in internal memory, and the processor starts checking for a sustained change from this new stable message (i.e., there is no clearing criteria for a sustained change). The J0 new message alarm bit is set when a sustained change is detected. Selection of the message type, SONET or SDH format, and the content monitoring mode (provisioned or vali- dated), are provisionable on a per STS-48 channel basis through a corresponding LTE receive channel n mainte- nance register. The associated alarms for the two modes are reported in the LTE receive channel n nonservice-affecting interrupt alarm register. The expected messages for all channels are provisioned through the microprocessor interface using the 64-byte J0 access message buffer. This message buffer is also used to read the contents of the expected, stable, or received messages for all channels. Accesses using the data buffer are paged according to direction (transmit and receive), STS-48 channel, and message type (expected/stable or received) through the use of the section trace access register. If the J0 message mode is set to the provisioned mode, the expected message is accessible. If the J0 message mode is set to the validated mode, then the stable message is accessible. Once the section trace access register is configured, the actual access is triggered by writing a 0x0001 value to the section trace access start register. The transfer from internal memory to/from the message buffer is performed on the next message boundary. Completion of the access is indicated by the access done flag being set in the section trace access sta- tus register. Note: To insert J0 into the transmit stream, 0x0020 must be written register 0x1C01 (the enable insertion of provi- sioned J0 message register). See Table 137 on page 131 for detailed register information. Internally, a memory is used to store the currently received section trace message as well as the stable or provi- sioned message. The operation of the memory is monitored using parity, and any errors are reported using the J0 parity error alarm bit.

Table 22. J0 Register Summary tions of the STS-48 or STS-192 J0 byte. counter based on either bit or block errors as provisioned for each channel through the B1 BIP mode control bit. at which point the counter is cleared. The counter will stop at the maximum value and will not roll over. page 52 for details on the ROHDAT interface. mask being set for one frame, with a one-frame delay due to retiming.

ported on individual STS-48 channels and will require all four channels to be provisioned in STS-192 mode. Table 23. B1 Register Summary or SEF (provisionable), 0x7F is constantly output. The data is clocked out on the positive edge of ROWCKn. transmit a constant 0x7F serial stream. put. The data is clocked out on the positive edge of ROWCKn. RSUSER1 pin transmits the F1 byte, while the other pins transmit a constant 0x7F serial stream. stantly output. The data is clocked out on the positive edge of RSDCKn. bytes, while the other pins are set high.

limit of 77. Figure 5 on page 57 illustrates SD detection and clearing using the default values specified in Table 24. SD thresholds of 1 x 10–10 to 1 x 10–15 are supported through software. Table 24. BER Threshold Time and Error Limits for Line SD and SF Detection

Figure 5. Example of STS-192 SD Detection (10–5 BER) and Clearing (10–6 BER) channel n service-affecting alarm register. timing reference when the detection time is expressed in seconds. error count exceeds the value specified in the detect error limit register. specified in the clear error limit register. of the B2 byte is delayed for two frames before it is enabled.

Table 25. B2 Register Summary orderwire (RLCLOWn), express orderwire (REXPOWn), and orderwire clock (OW_CLKn) pins of each STS-48.

1. The appropriate bit definitions are

used to carry line AIS (AIS-L) and line RDI (RDI-L) signals. and K2 bytes, and the generation of the alarms, are not affected by the line AIS status.

I Protection switching byte. This defect occurs when either an inconsistent APS byte or an invalid code is detected. state just before line AIS is declared. alarm status bit to be set in the corresponding LTE receive channel n nonservice-affecting interrupt alarm register. feature prevents a change in the channel mismatch defect state just before line AIS is declared. status bit, persistency bit, and one second PM bit being set in the registers for the affected channel. alarm status bit, persistency bit, and one second PM bit being set in the registers for the affected channel. Table 26. APS Channel (K1 and K2) Register Summary

(622.08 MHz/1080), giving a frequency of 576 kHz and a duty cycle of roughly 50%. nel. In STS-192 mode, only the RLDCC_1 pin transmits these bytes, while the other pins are set high. dated byte is different from the value of the last validated byte. clock is transmitted on the RFRMn pin. Figure 6. Timing Diagram for RFRM Table 26. APS Channel (K1 and K2) Register Summary (continued)

regardless of the RFRM output enable control bit. mode, only the RFRM1 pin transmits the validated synchronization status byte or the 8 kHz clock. Table 27. Synchronization Status (S1) Register Summary which point the counter is cleared. The counter will stop at the maximum value and will not roll over. Table 28. Line REI (M1) Register Summary line AIS, 0x7F is constantly output. The data is clocked out on the positive edge of ROW_CLK_n. REXPOW_1 pin transmits the E2 byte while the other pins transmit a constant 0x7F serial stream. GR-256-CORE that concatenated payloads start on an STS-3 boundary (STS-1 payloads may start anywhere). Note that the terminology used is from SONET, although SDH is also supported.

ever, path trace monitoring is supported on any single STS-1 in each STS-48. shows the STS-1 ordering after the demultiplexers. Table 29. STS-12 Byte Ordering mediate performance monitoring is performed (i.e., the path overhead is not modified). concatenation indication (CONC). The state diagram is shown in Figure 7 on page 63.

Figure 7. Pointer Interpreter State Machine

1. New data flag (NDF) pointer.

considered an increment or decrement. Register 0x3000 bit 4 should be set to 1 for this mode. the pointer to be considered an increment or decrement. Register 0x3000 bit 4 should be set to 0 for this mode. extracted at the new offset.

I Normal NDF with the offset equal to the currently validated offset. I NDF set with a valid offset. I An increment or decrement where all ten I and D bits are correct. concatenation indicator or an AIS pointer is considered invalid. overhead last second bin register. I A per-STS-1 indication of CONC state (RECD_CONC_MAP). Table 30. Pointer Interpreter Register Summary synchronous, the elastic store will remain half filled with the write and read pointers 180 degrees (10 bytes) apart. of ±2 bytes from start-up conditions.

path alarms register is set. Table 31. Elastic Store Register Summary operation will be performed for three frames following any pointer change operation. occurs, causing the read and write pointers to be reset. pointer value is sent along with an NDF for one frame following the termination of the all ones. other bytes in the SONET frames are defined by the receive payload drop interface. used by the payload drop interface. Table 32. Pointer Generator Bypass Register Summary

found in the TOH Transparency section on page 85. in the STS-N pointer processor control (provisioning) register with the AUTO_AIS_DIS bit. Table 33. AIS-P Insertion Conditions H2, and H3 bytes will be generated by the pointer generator and will be normal pointers with the last known offset. interpreter, and any downstream equipment will see the same defects as the pointer interpreter. is intended to be used only in the pointer generator bypass mode.

1. AIS-P affects H1, H2, H3, and all SPE bytes.

1 Flow-Through

Table 34. Path AIS Insertion Register Summary nations up to STS-192c. This allows the TSOT0410G4 to automatically adjust to incoming concatenated payloads. first STS-1 of the unsupported concatenation. the last concatenation is larger than STS-6c, the concatenation map for the next STS-12 must be read. concatenation (including the first) should have the compare enabled with the appropriate compare enable bit.

Table 35. Concatenation Register Summary are transferred to the appropriate registers. tions that can be performed in one second. Table 36. Pointer Justification Binning Register Summary

Agere Systems Inc. 69 Data Sheet May 2003 STS-192 Overhead and Path Processor TSOT0410G4 SONET/SDH Functional Description (continued) Receive Path Overhead (POH) Processor This block accepts the payload mapping information, status, and timing from the receive pointer interpreter, and extracts the path overhead from up to 12 STS channels. The extracted overhead is then stored internally and may be further processed for alarm or performance monitoring purposes. While an STS channel is in AIS or LOP sta- tus, all path overhead processing for the channel is inhibited. The definition and associated storage or processing of each byte is detailed as follows. Path Trace (J1). The path trace (J1) byte is the first POH byte of each unconcatenated STS-1 and carries a repeating message. Path trace messages are 64-bytes long (ASCII, <CR><LF> terminated) in SONET and 16 bytes long (E.164) in SDH systems. The POH processor supports extraction of one path trace message per STS-48. There are four path trace extraction message buffers. In STS-192 mode, there are four path trace extrac- tion message buffers—one for each of the STS-48 streams contained within the STS-192. The content of the message is either monitored for a mismatch from a provisioned expected message or monitored for a sustained change (validation) in the received message. If the message mode control bit is set to the provi- sioned mode, then the incoming message is compared against the software programmed expected message. The expected message is stored in internal memory for each STS-48 channel. A mismatch is declared if the received message differs from this expected message for ten consecutive messages. The mismatch clears when four out of five received messages match the expected message (fixed windowing is used for clearing). If the message mode control bit is set to the validated mode, the incoming message is monitored for a sustained change. A sustained change is detected when the received message differs from the last stable message for ten consecutive mes- sages. The new message then becomes the stable message, is stored in internal memory, and the processor starts checking for a sustained change from this new stable message (i.e., there is no clearing criteria for a sus- tained change). The message mismatch state or the new (sustained) message state are reflected by maskable latched alarm bits in the STS-48 channel path alarms register. For path trace processing, provisioning of the selected STS-1 within the STS-48, SDH, or SONET message type, and validated or provisioned message mode is done using the STS-48 channel path trace control register. The expected messages for the four STS-48 channels are provisioned through the microprocessor interface using the path trace access control and 64-byte message buffer registers. This message buffer is also used to read the contents of the expected/stable or received messages from the internal message memories for all channels. The STS-48 channel and message type (expected/stable or received), and the access type (read/write) are specified using the path trace access control register. Once this register is configured, the actual access is triggered by writ- ing a 0x0001 value to the path trace access start register. The transfer from internal memory to the message buffer is performed on the next message boundary. Completion of the access is indicated by the path trace access com- plete status register. Internally, for each STS-48 channel, a memory is used to store the currently received path trace message as well as the stable or provisioned message. The operation of the memory is monitored using parity, and any errors are reported using the J1 parity error alarm bit.

Table 37. J1 Register Summary where both the window and threshold represent a BER that is 1/10th the detection BER. not have an SF defect, the detection register of the pair defines the error threshold and time window. dow. The four common-time windows each support a 16-bit value that represents the time window in 0.5 ms units.

values for the four common-time windows. overhead bytes for that channel on the drop interface. Table 38. BER Threshold Time Window and Error Limits for Path SF Detection Table 39. Time Window Sizes for Path SF Detection overhead maintenance STS-1 register to the number of the register set that has just been set up.

1. Measurements for STS-48c and STS-192c are not realistic. Refer to SONET/SDH specifications for details.

that an entire clearing window is used for clearing SF. since the clear threshold can never be reached. threshold of more than 32, since a maximum of 32 B3 errors can be detected in 0.5 ms. Table 40. B3 Register Summary

SPE or the status of the payload. See Table 41 for label assignments. Table 41. STS Path Signal Label Assignments do not care during any defect detection or clearing. processed for the following listed defects.

00 Unequipped 12 Asynchronous mapping for DS4NA

01 Equipped—nonspecific payload 13 Mapping for ATM

02 VT-structured STS-1 SPE 14 Mapping for DQDB

03 Locked VT mode 15 Asynchronous mapping for FDDI

04 Asynchronous mapping DS3 16 Mapping for HDLC-PPP (proposed)

not match the provisioned expected signal label code in the per STS-1 path overhead provisioning register. the STS-12 Overhead Insertion and Scrambling section on page 77. 0xFC are valid if the locally provisioned payload is VT-structured (0x02 or 0x03) or equipped nonspecific (0x01). and Scrambling section on page 77. Table 42. Path Signal Label (C2) Alarm Scenarios

00 No Alarms

01 UNEQ-P MATCH MATCH MATCH PDI-P 1

1. If PDI-P detection is provisioned.
2. If extracted, validated C2 code = provisioned C2 code.
3. If extracted, validated C2 code ≠ provisioned C2 code.

Table 43. C2 Register Summary counter is cleared. The counter will stop at the maximum value and will not roll over. the positive edge of the PM_CLK input.

Table 44. RDI-P Codes and Interpretation Table 45. G1 Register Summary ever, most of the transport overhead bytes are either unused or are used for proprietary purposes.

1. These codes are transmitted by STS PTE that do not support enhanced RDI-P. If enhanced RDI-P is not supported, G1 bits 6

and 7 must be set to the same value, and should be set to 00.

1. These codes are transmitted by STS PTE that support enhanced RDI-P.

4 No Defects No ERDI-P Defects

I A1 and A2 positions: carry normal STS-12 framing. STS-12. This value is specified in the J0 trace—STS-12 channel n register. STS-12 links through the BIP-8 error insertion bit in the receive drop STS-48 channel n provisioning register. the same 6-bit value, which encodes the path alarm information, as shown in Table 46. Table 46. Path Alarm Information Encoding is sourced by the RDDCCn (1 to 16) input, and is clocked on the positive edge of RDDCKn (1 to 4). 00111111 Loss of pointer or path AIS. 11111111 Concatenation mismatch or software AIS insertion. 00111110 Unequipped signal label. 00011111 Si gnal degrade (SD). 00011110 Payload label mismatch.

Table 47. Line Alarm Information Encoding Table 48. Drop Interface Overhead and Scrambling Register Summary that corresponds to the STS-48 in which the STS-12 belongs, if drop alignment is bypassed). byte of each STS-12. Thus, there is one byte of timing control for each byte of data from the four STS-12 streams. encoding of the timing enable bits is shown in Table 49 on page 79. puts may be left unconnected if not used.

00111 Loss of Signal

00110 Loss of Frame

00101 Line AIS

00100 Signal Fail (SF)

00011 Signal Degrade (SD)

00000000 No Alarms

Figure 8. STS-12 Data Outputs and Timing Table 49. Timing Enable Bit Definitions for that channel will always indicate a nominal SPE (i.e., no stuffs) with POH in column 4 and no J1 byte. Table 50. Receive Data Path Parity Register Summary

00 TOH bytes

01 SPE bytes

10 POH bytes

11 J1 byte

CHANNEL CHANNEL CHANNEL CHANNEL CHANNEL CHANNEL CHANNEL CHANNEL CHANNEL . . . STS-12 CHANNEL 1 BYTE N STS-12 CHANNEL 1 BYTE N + 1 . . . STS-12 CHANNEL 2 BYTE N STS-12 CHANNEL 2 BYTE N + 1 . . . STS-12 CHANNEL 3 BYTE N STS-12 CHANNEL 3 BYTE N + 1 . . . STS-12 CHANNEL 4 BYTE N STS-12 CHANNEL 4 BYTE N + 1 . . .

face self sync option to transfer from the receive to the transmit clock domains. STS-48 streams are unlikely to be aligned to the same clock and frame alignment. or R_CLK failure while in regenerator loopback. Table 51. LTE Transmit Channel Registers—Regenerator Loopback Summary Table 52. Regenerator Loopback Bit Definitions verts them to STS-48 data. This conversion is performed in three stages. to provide a correctly ordered STS-48 data stream. 1 Regenerator loopback—drop data looped back to add side.

value is extracted and stored in the J0 status register. is inhibited while the STS-12 is OOF, and for one frame following reframe. Table 53. Path AIS Insertion Encoding STS-12 is OOF, an HDLC abort (0x7F) is continually sent. I E2 position: the transmit add interface does not process the E2 byte.

00111111 Path AIS Insertion

Table 54. Add Interface Overhead and Scrambling Register Summary which is indicated by a latched status bit in the transmit add STS-48 channel alarm register. compensated using the transmit frame offset feature described in Add Interface Framing (A1 and A2). visioning register contains a force add buffer overflow bit which allows testing of the add buffer overflow alarm bit. Table 55. Transmit Synchronization Buffer Register Summary

41 C 0 1 1 3 1

Agere Systems Inc. 83 Data Sheet May 2003 STS-192 Overhead and Path Processor TSOT0410G4 SONET/SDH Functional Description (continued) TFRM Framing Signal. The alignment of the generated frame is determined by the TFRM input signal and the value stored in the Tx frame offset register. The TFRM input provides a common frame reference for all add STS-12 data streams. The TFRM input is an 8 kHz signal and is sampled with the 622.08 MHz T_CLK. The frame position is at the rising edge of the TFRM signal when it has been low for at least 32 T_CLK clock periods and then stays high for at least 32 more (i.e., a 0000 1111 pattern). This transition should be present at approximately the average position of the start of the first A1 byte in all of the add interface STS-12 serial inputs. If the TFRM is not aligned to the input data, the frame position can be delayed by the value in the Tx frame offset register, specified in multiples of 12.86 ns (eight 622.08 MHz clock cycles), which produces the transmit frame tim- ing reference. A value of zero specifies no delay and the maximum value for this register is 9719. This range is equivalent to advancing the frame timing reference over an entire STS-12 period. This offset is required to align the transmit frame position with the frame position of the add STS-12 data streams as described in the Transmit Synchronization Buffer section on page 82. If the TFRM rising edge should jitter with respect to the 622.08 MHz T_CLK, jitter on the TFRM input can be com- pensated for up to ±16 T_CLK cycles from the starting position without affecting the generated frame position. This compensation is enabled with the TX_FRM_DEJITTER_EN bit in the LTE transmit provisioning register. If the TFRM input drifts more than ±16 T_CLK cycles from its starting position, the transmit frame position is realigned to the next TFRM frame position (plus any offset added in the offset register), and a TX_FRM_RESYNC alarm is pro- duced. If the TFRM frame signal is not received at least once every eight frames (i.e., 1 kHz), TFRM synchronization loss is indicated in the TFRM LOF alarm bit. During TFRM synchronization loss, AIS-P is inserted as described in the STS Payload Pointer (H1 and H2) section on page 88. While frame synchronization, once established, could be continued by counting clock cycles, the requirement for the TFRM signal to be provided at least once every eight frames provides an important check on system function. The TFRM input is a required signal for the transmit side of the TSOT0410G4. Recovery of TFRM frame sync is described in the Synchronization Status (S1) section on page 91. Add Interface Self-Sync Option. The TFRM input can be obtained from the add interface through a self-sync option to provide a common frame reference for all add STS-12 data streams as an alternate to the TFRM input. The transmit add synchronization enable option provides for the use of the frame timing from one of the add pseudo STS-12 links as the transmit frame sync instead of TFRM. This option provides the frame sync from the add clock domain to the T_CLK clock domain. The option is enabled with the ADD_TX_SYNC (bit 15) in the LTE transmit common provisioning register. When the self-sync option is enabled, the frame is sampled and then the add interface free-runs until either the feature is disabled and reenabled, or when the ADD12 (out of frame on used link) or T_CLK failure alarm is set and clears. Therefore, when changing the ADD12 link, the feature should be dis- abled and then reenabled after the channel is changed. The add interface self-sync feature automatically resynchronizes when a buffer overflow/underflow is detected. This resyncing is inhibited if the selected ADD12 is out-of-frame. The resync function is implemented by resam- pling the selected ADD12 frame timing and using that to realign the buffer write pointer. The only limit to the resync property is that it only resamples the frame timing once after an overflow/underflow and there is no guarantee that the buffer is centered; i.e., if the clock drift continues after the overflow/underflow. When the ADD_TX_SYNC bit in the LTE transmit common provisioning is set to 1, the frame pulse will be derived from the add interface input. Bit 0 through bit 3 in the LTE transmit common provisioning register then select which add channel (1—16) the TFRM will be obtained from. Bits 4—14 are unused in that case. See Table 128 on page 128. The preferred method of provisioning the add interface self-sync option is to provision the ADD_TX_SYNC register with the selected channel first, and then in the next write, provision the ADD_TX_SYNC enable. Note: The add-sync option should be disabled before the regenerator loopback option is enabled. Enabling regenerator loopback before the add sync option can cause transmit timing to corrupt overhead bytes.

Table 56. Frame Pulse Provisioning Bit Definitions Table 57. Transmit Framing Register Summary STS-12 channel to be interleaved in 4-byte chunks. processor interface, or derived. nel carries complete transport overhead, while the other channels only carry framing (A1, A2), Z0, and line BIP-8. enabling line AIS insertion in the memory map. 1 0 Transmit add synchronization enabled. 0 1 TFRM dejitter circuit enable.

sioned to the same mode (i.e., the function cannot be set up differently in transmit and receive directions). head transparency with section overhead used for the normal proprietary drop I/F OH. STS-48 channels and will require all four channels to be provisioned in STS-192 mode. Table 58. LTE Transmit Channel Registers—TOH Transparency Summary Table 59. TOH Transparency Bit Definitions Note: X denotes either state. state dependent on DRPBYP pin). (pointer processor is bypassed automatically). (pointer processor is bypassed).

B1 and B2, the value received is actually used as an XOR corruption mask for the internally calculated values. valid regardless of the mode (STS-48 or STS-192) in which the device is operating. software enabled line or path AIS insertion or path unequipped insertion. Table 60. Transmit Overhead Serial Links Register Summary mode or 0xCC for STS-192 mode. reported in the LTE transmit interrupt alarm register.

Table 61. Transmit Section Trace (J0) Register Summary count register specifies this duration and is shared between the four channels. Table 62. Transmit B1 Register Summary the TLCLOW_n pin, and is inserted in each frame. The data is clocked in on the positive edge of TOW_CLK_n. giving a frequency of 64 kHz and a duty cycle of 33%. TLCLOW_1 pin inputs the E1 byte, while the other pins are unused. each frame. The data is clocked in on the positive edge of TOW_CLK_n. TSUSER_1 pin inputs the F1 byte, while the other pins are unused.

1 Provisioning (R/W)

88 Agere Systems Inc. Data Sheet May 2003STS-192 Overhead and Path Processor TSOT0410G4 SONET/SDH Functional Description (continued) Section Data Communications Channel (D1, D2, and D3) The section data communications channel bytes are located in the first STS-1 of the STS-48 or STS-192 only, and are used as one 192 kHz message-based channel for operations, administration, and maintenance communica- tion. The bytes are input serially, MSB first, on the TSDCC_n pin, and are inserted in each frame. The data is clocked in on the positive edge of TSD_CLK_n. The TSD_CLK_n clock is divided down from the line data communications channel clock, TLD_CLK_n (576 kHz/3), giving a frequency of 192 kHz and a duty cycle of 33%. In STS-48 mode, each of the four TSDCC pins input the section data communication channel bytes for that chan- nel. In STS-192 mode, only the TSDCC_1 pin inputs these bytes, while the other pins are unused. STS Payload Pointer (H1 and H2) The STS payload pointer bytes are normally set to the values received at the transmit payload add interface. These values are overwritten under the following conditions (in order of precedence from highest to lowest): I Line AIS: enabled using the AIS-L insert control bit. I Unequipped signal insertion: enabled on a per STS-1 channel basis using the UNEQ-P insert enable registers; overwrites the pointer bytes (H1, H2) for that channel with 0x60 0x00 or 0x68 0x00, based on SS_MODE (see the SS Bits section below) and the SPE bytes with all zeros. I Software AIS insertion: enabled on a per STS-1 channel basis using the path AIS insert enable registers; overwrites the pointer bytes for that channel with 0xFF 0xFF (H1 H2) and the SPE bytes with all ones. I TFRM loss of frame sync: overwrites the pointer bytes in all STS-1 channels with 0xFF 0xFF (H1 H2) and all SPE bytes with all ones (AIS-P). I TOHDAT insertion: enabled on a per STS-48 channel basis using the TOH data insert control bit; overwrites the pointer bytes with the data serially received on the TOHDAT_n_[1:0] pins if the TOHEN_n pin is high for H1 and H2. The pointer bytes are also automatically overwritten with all ones in the transmit payload add interface under the following conditions: I In all STS channels of an STS-12 due to an OOF on that STS-12 data input. I For the affected STS channel due to a path AIS insert request received for that STS in the STS-12 overhead. SS Bits. The SS bits in the STS payload pointer (H1 and H2) are provisioned using SS_MODE (bit 9) and TX_SS_OVERWRITE_EN (bit 10) in each LTE Tx channel provisioning register. The SS bit mode is set to 0 for SONET (00) or 1 for SDH (10) and defines the value of the SS bits for unequipped signal insertion. The SS bits mode also defines the value of the SS bits that are inserted in all of the outgoing H1 bytes for that OC-48 channel if the Tx SS bit overwrite feature is enabled. The SS bits are passed through untouched if the transmit SS bit over- write feature is not enabled. The overwrite feature is disabled during AIS (line and path) insertion when TOHDAT insertion is enabled for that H1 byte or when the incoming H1 byte is 0xFF.

Table 63. Transmit STS Payload Pointer Register Summary shared between the four channels. Table 64. Transmit B2 Register Summary

11 B 0 2 1 2 8

stored in the K byte register, or using the raw or validated values received at the transmit payload add interface. LOS, SEF, or LOF (SEF and LOF only if AIS insertion is enabled) are detected for the receive STS-48 or STS-192. Table 65. K Byte Select Control Bits Table 66. Transmit APS Channel (K1K2) Register Summary clocked in on the positive edge of TLDCKn. and a duty cycle of roughly 50%. STS-192 mode, only the TLDCC1 pin is used to input these bytes, while the other pins are not used. 00 LTE transmit channel 1 K1K2 byte insert values register. 01 Raw K1K2 byte from the transmit payload add interface. 10 Validated K1K2 byte from the transmit payload add interface. 11 Invalid. Do not program this value.

41 C 0 A 1 3 2

determines which of these two sources to use. bit, is found in the LTE transmit interrupt alarm register. Table 67. Transmit Synchronization Status (S1) Register Summary ber of line BIP-8 errors (truncated at 255) detected in the previous receive frame for the entire STS-48 or STS-192. Table 68. Transmit M1 Register Summary

11 B 0 3 1 2 9

and is inserted in each frame. The data is clocked in on the positive edge of TOW_CLK_n. TEXPOW_1 pin captures the E2 byte, while the other pins are unused. and is multiplexed up to a 622 MHz signal. STS-192 data stream. This is performed by the time-slot multiplexer (TSM). be disabled by the corresponding transmit scrambler disable bit of the LTE transmit channel n provisioning register. Table 69. Transmit Line Scrambler Register Summary and parity errors are reported using the corresponding bit in the LTE transmit channel n interrupt alarm register. Table 70. Transmit Data Path Parity Register Summary

Agere Systems Inc. 93 Data Sheet May 2003 STS-192 Overhead and Path Processor TSOT0410G4 SONET/SDH Microprocessor Interface Architecture The TSOT0410G4 microprocessor interface architecture is configured for glueless interface to two specific micro- processors, the Motorola ® MPC860 and MC68360; however, other processors may also be utilized. Bus transfers using the MC68360 are asynchronous, while the MPC860 transfers are synchronous to the processor clock. There is a difference in definition of MSB and LSB of data, address, and parity pins between the TSOT0410G4 and some microprocessors, such as the Motorola MPC860. For example, the TSOT0410G4 provides Parity_1 and Parity_0. Parity_1 is the odd parity for the data bus MSB, and parity_0 is the odd parity for the data bus LSB. The MPC860 DP0 calculates across the data bus MSB, and DP1 across the data bus LSB. The microprocessor interface operates at the frequency of the microprocessor clock (PCLK) input in synchronous mode. The state of the MPMODE input signal determines whether bus transfers are synchronous or asynchronous with respect to PCLK. The TSOT0410G4 has separate 16-bit wide address and data buses. The microprocessor interface generates an external processor bus error if an internal data acknowledgement is not received in a predetermined period of time or on parity errors. Persistency alarm registers are used in conjunction with interrupt alarm registers to indicate whether alarms are persistent. Transfer Error Acknowledge (TEA_N) The TSOT0410G4 contains a bus time-out counter. When this counter saturates, a bus error is generated to the external processor through the transfer error acknowledge (TEA_N) signal. This feature must be considered with respect to the external processor’s ability to generate its own internal bus time-out. TEA_N will be asserted if an internal data acknowledgement is not received within 32 PCLK periods of the start of the access. This interval is used since all valid internal accesses to the device will be completed in significantly less than 32 PCLK periods. TEA_N is also asserted if the calculated parity value does not match the parity generated by the external micropro- cessor on a data transfer. Interrupt Structure The interrupt structure of the TSOT0410G4 is designed to minimize the effort for software/firmware to isolate the interrupt source. The interrupt structure is comprised of different registers depending on the consolidation level. At the lowest level (source level) there are two registers. The first is an alarm register (AR). An alarm register is typi- cally of the write 1 clear (W1C) type. The second is an interrupt mask (IM) register of the read/write (RW) type. An alarm register latches a raw status alarm. This latched alarm may contribute to an interrupt if its corresponding interrupt mask bit is disabled. Individual latched alarms are consolidated into an interrupt status register (ISR). If any of the latched alarms that are consolidated into a bit of an ISR are set and unmasked, the ISR bit is set. The ISR bit may contribute to an interrupt if its corresponding interrupt mask bit is disabled. ISRs may be consolidated into higher-level ISR in a similar fashion until all alarms are consolidated into the chip-level ISR. The alarm register that causes an interrupt can be determined by traversing the tree of ISRs, starting at the chip-level ISR, until the source alarm is found. The interrupt requests can be selectively disabled on a per-function (per-bit) basis. The interrupt mask register serves this function. A bit position set to 1 indicates that the status flag in the corresponding bit position will not contribute to the generation of an interrupt when it is set (status itself is not affected by the interrupt mask). All interrupts are disabled on RST_N assertion.

94 Agere Systems Inc. Data Sheet May 2003STS-192 Overhead and Path Processor TSOT0410G4 SONET/SDH Microprocessor Interface (continued) Parity Bits There are two parity bits associated with the microprocessor interface. They are only active when the microproces- sor interface is in synchronous mode (MPMODE = 1). PARITY_1 is the odd parity bit for the most significant 8 bits of the data bus (DATA_15 through DATA_8), and PARITY_0 is the odd parity bit for the least significant 8 bits of the data bus (DATA_7 through DATA_0). The parity bits may be ignored when the interface is operating in synchronous mode (MPMODE = 1); however, TEA_N must then be ignored on a write cycle. A TEA_N will never be asserted on a synchronous read cycle since the interface is presenting the parity on the output pins for the microprocessor interface to check. The parity bit pins may be left unconnected if not used. The parity bits are not used by the microprocessor interface when in asynchronous mode (MPMODE = 0), and can be unconnected. Clock Domains There are seven primary clock domains in the TSOT0410G4. Each has a separate clock source, related to the function of the domain. The microprocessor interface is a distinct clock domain and PCLK is its input clock. It con- tains the device-level registers. The clock domains are shown in Figure 9 on page 95. In the event that any domain loses its primary clock source, the microprocessor interface will not be able to access registers related to those regions until the clock is restored. The domain's clock is necessary internally to transfer data between that region of the device and the microprocessor interface. The receive line interface contains four clock domains, each clocked by R_CLK_[1—4], although they are all clocked by R_CLK_1 in STS-192 mode. The receive payload drop interface is a separate clock domain and is clocked by D_CLK. The separation between the receive domains is the receive drop aligner block. The transmit side of the device is an entire clock domain, with T_CLK as its input clock. The TSOT0410G device monitors RX_CLK_n, TX_CLK, and DRP_CLK to effectively detect loss of R_CLK_n, T_CLK, and D_CLK. Each clock is monitored by the same logic. P_CLK is divided by eight to produce a test signal that is less than 1/8th the clocks being monitored. This test signal is sampled using each of the monitored clocks, and then the sample is XORed with the test signal to generate a difference signal. This difference signal is then sampled by P_CLK at the end of each half cycle of the test clock. If the monitored clock is still active, the difference signal should be low by the end of the half cycle and the fail flag will stay low. If the monitored clock fails, the differ- ence signal will be high during one of the half cycles of test signal, causing the fail alarm to strobe high. The status of RX_CLK_n, TX_CLK, and DRP_CLK are monitored using the clock loss alarm/PM clock detection register, address 0x7 (see Table 79 on page 113).

Note: See text for description of the timing domains. Figure 9. TSOT0410G4 Timing Domains

the point at which it was asserted to the point at which it was read by software. attempt to clear the alarm, and its interpretation. At the rising edge of the raw alarm point, the corresponding interrupt alarm and persistency alarm register are set. tency register is now able to be set on the next assertion of the raw alarm point. Figure 10. Persistency Register Operation ues exist, the first refers to STS-48 mode and the second refers to STS-192 mode. do return to default values after a hardware reset. hardware reset should be asserted (RST_N).

Table 71. Register Summary

0 Chip Level Interrupt Status Register 7:0 0x0

1 Chip Level Interrupt Status Mask Register 7:0 0x0

2 Chip ID Register 15:0 0x1515

3 Chip Vintage Register 15:0 0x1

4 Scratch Pad Register 15:0 0x0

5 Chip Level Maintenance Register 0:0 0x0

6 Chip Status Register 2:0 —

7 Clock Loss Alarm Register 6:0 0x0

8 Clock Loss Alarm Mask Register 6:0 0x0

1000 LTE Interrupt Status Register 13:0 0x0

1001 LTE Interrupt Status Mask Register 13:0 0x0

1100 Section Trace (J0) Access Maintenance Register 4:0 0x0

1101 J0 Access Done Register 0 0x0

1102 J0 Access Message Start 0 0x0

1110 J0 Access Message Buffer, Word 1 15:0 0x0

1111 J0 Access Message Buffer, Word 2 15:0 0x0

1112 J0 Access Message Buffer, Word 3 15:0 0x0

1113 J0 Access Message Buffer, Word 4 15:0 0x0

1114 J0 Access Message Buffer, Word 5 15:0 0x0

1115 J0 Access Message Buffer, Word 6 15:0 0x0

1116 J0 Access Message Buffer, Word 7 15:0 0x0

1117 J0 Access Message Buffer, Word 8 15:0 0x0

1118 J0 Access Message Buffer, Word 9 15:0 0x0

1119 J0 Access Message Buffer, Word 10 15:0 0x0

1120 J0 Access Message Buffer, Word 17 15:0 0x0

1121 J0 Access Message Buffer, Word 18 15:0 0x0

1122 J0 Access Message Buffer, Word 19 15:0 0x0

1123 J0 Access Message Buffer, Word 20 15:0 0x0

1124 J0 Access Message Buffer, Word 21 15:0 0x0

1125 J0 Access Message Buffer, Word 22 15:0 0x0

1126 J0 Access Message Buffer, Word 23 15:0 0x0

1127 J0 Access Message Buffer, Word 24 15:0 0x0

1128 J0 Access Message Buffer, Word 25 15:0 0x0

1129 J0 Access Message Buffer, Word 26 15:0 0x0

1300 Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 × 10

1301 Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 × 10–4) 15:0 0x8/0x8

1302 Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 × 10–5) 15:0 0x8/0x8

1303 Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 × 10–6) 15:0 0x3E/0xD

1304 Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 × 10–7) 15:0 0x271/0x82

1305 Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 × 10–8) 15:0 0x1450/

1306 Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 × 10–9) 15:0 0x8015/

1307 Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 × 10–10) 15:0 0x80AA/

1310 Line Signal Degrade/Signal Fail Detect Error Limit (1 × 10–3) 15:0 0x12D2/

1311 Line Signal Degrade/Signal Fail Detect Error Limit (1 × 10–4)1 5 : 0 0 x 3 5 E /

1312 Line Signal Degrade/Signal Fail Detect Error Limit (1 × 10–5) 15:0 0x51/0x166

1313 Line Signal Degrade/Signal Fail Detect Error Limit (1 × 10–6) 15:0 0x3E/0x33

1314 Line Signal Degrade/Signal Fail Detect Error Limit (1 × 10–7) 15:0 0x3E/0x33

1315 Line Signal Degrade/Signal Fail Detect Error Limit (1 × 10–8) 15:0 0x33/0x33

1316 Line Signal Degrade/Signal Fail Detect Error Limit (1 × 10–9) 15:0 0x28/0x28

1320 Line Signal Degrade/Signal Fail Clear Error Limit (1 × 10–4)1 5 : 0 0 x 3 B D /

1321 Line Signal Degrade/Signal Fail Clear Error Limit (1 × 10–5) 15:0 0x72/0x1A7

1322 Line Signal Degrade/Signal Fail Clear Error Limit (1 × 10–6) 15:0 0x5B/0x4D

1323 Line Signal Degrade/Signal Fail Clear Error Limit (1 × 10–7) 15:0 0x5B/0x4D

1324 Line Signal Degrade/Signal Fail Clear Error Limit (1 × 10–8) 15:0 0x4D/0x4D

1325 Line Signal Degrade/Signal Fail Clear Error Limit (1 × 10–9) 15:0 0x3F/0x3F

1326 Line Signal Degrade/Signal Fail Clear Error Limit (1 × 10–10) 15:0 0x34/0x33

Table 71. Register Summary (continued)

1400 LTE Receive Channel 1 Provisioning Register 6:0 0x2

1401 LTE Receive Channel 1 Maintenance Register 6:0 0x20

1402 LTE Receive Channel 1 Loss of Signal (LOS) Threshold 9:0 0x86

1403 LTE Receive Channel 1 K Byte Status Register 15:0 0x0

1404 LTE Receive Channel 1 S1 Byte Status Register 7:0 0x0

1405 LTE Receive Channel 1 Service-Affecting Interrupt Alarm Register 4:0 0x0

1406 LTE Receive Channel 1 Service-Affecting Interrupt Alarm Mask Register 4:0 0x0

1407 LTE Receive Channel 1 Service-Affecting Persistency Alarm Register 2:0 0x0

1408 LTE Receive Channel 1 Nonservice-Affecting Interrupt Alarm Register 10:0 0x0

1409 LTE Receive Channel 1 Nonservice-Affecting Interrupt Alarm Mask Register 10:0 0x0

1410 LTE Receive Channel 1 CV-S Performance Monitoring Register 15:0 0x0

1500 LTE Receive Channel 2 Provisioning Register 6:0 0x2

1501 LTE Receive Channel 2 Maintenance Register 6:0 0x20

1502 LTE Receive Channel 2 Loss of Signal (LOS) Threshold 9:0 0x86

1503 LTE Receive Channel 2 K Byte Status Register 15:0 0x0

1504 LTE Receive Channel 2 S1 Byte Status Register 7:0 0x0

1505 LTE Receive Channel 2 Service-Affecting Interrupt Alarm Register 4:0 0x0

1506 LTE Receive Channel 2 Service-Affecting Interrupt Alarm Mask Register 4:0 0x0

1507 LTE Receive Channel 2 Service-Affecting Persistency Alarm Register 2:0 0x0

1508 LTE Receive Channel 2 Nonservice-Affecting Interrupt Alarm Register 10:0 0x0

1509 LTE Receive Channel 2 Nonservice-Affecting Interrupt Alarm Mask Register 10:0 0x0

1510 LTE Receive Channel 2 CV-S Performance Monitoring Register 15:0 0x0

1600 LTE Receive Channel 3 Provisioning Register 6:0 0x2

1601 LTE Receive Channel 3 Maintenance Register 6:0 0x20

1602 LTE Receive Channel 3 Loss of Signal (LOS) Threshold 9:0 0x86

1603 LTE Receive Channel 3 K Byte Status Register 15:0 0x0

1604 LTE Receive Channel 3 S1 Byte Status Register 7:0 0x0

1605 LTE Receive Channel 3 Service-Affecting Interrupt Alarm Register 4:0 0x0

1606 LTE Receive Channel 3 Service-Affecting Interrupt Alarm Mask Register 4:0 0x0

1607 LTE Receive Channel 3 Service-Affecting Persistency Alarm Register 2:0 0x0

1608 LTE Receive Channel 3 Nonservice-Affecting Interrupt Alarm Register 10:0 0x0

1609 LTE Receive Channel 3 Nonservice-Affecting Interrupt Alarm Mask Register 10:0 0x0

1610 LTE Receive Channel 3 CV-S Performance Monitoring Register 15:0 0x0

1700 LTE Receive Channel 4 Provisioning Register 6:0 0x2

1701 LTE Receive Channel 4 Maintenance Register 6:0 0x20

1702 LTE Receive Channel 4 Loss of Signal (LOS) Threshold 9:0 0x86

1703 LTE Receive Channel 4 K Byte Status Register 15:0 0x0

1704 LTE Receive Channel 4 S1 Byte Status Register 7:0 0x0

1705 LTE Receive Channel 4 Service-Affecting Interrupt Alarm Register 4:0 0x0

1706 LTE Receive Channel 4 Service-Affecting Interrupt Alarm Mask Register 4:0 0x0

1707 LTE Receive Channel 4 Service-Affecting Persistency Alarm Register 2:0 0x0

1708 LTE Receive Channel 4 Nonservice-Affecting Interrupt Alarm Register 10:0 0x0

1709 LTE Receive Channel 4 Nonservice-Affecting Interrupt Alarm Mask Register 10:0 0x0

1710 LTE Receive Channel 4 CV-S Performance Monitoring Register 15:0 0x0

2000 EQPT Interrupt Status Register 12:0 0x0

2001 EQPT Interrupt Mask Register 12:0 0x0

2002 Receive Drop Common Service-Affecting Alarm Register 0 0x0

2003 Receive Drop Common Service-Affecting Alarm Mask Register 0 0x0

2400 Receive Drop STS-48 Channel Provisioning Register 1 1:0 0x0

2401 J0 Trace—STS-12 Channel 1 7:0 0x1

2402 J0 Trace—STS-12 Channel 2 7:0 0x2

2403 J0 Trace—STS-12 Channel 3 7:0 0x3

2404 J0 Trace—STS-12 Channel 4 7:0 0x4

2405 Receive Drop STS-48 Channel Nonservice-Affecting Alarm Register 1 4:0 0x0

2406 Receive Drop STS-48 Channel Nonservice-Affecting Alarm Mask Register 1 4:0 0x0

2500 Receive Drop STS-48 Channel Provisioning Register 2 1:0 0x0

2501 J0 Trace—STS-12 Channel 5 7:0 0x5

2502 J0 Trace—STS-12 Channel 6 7:0 0x6

2503 J0 Trace—STS-12 Channel 7 7:0 0x7

2504 J0 Trace—STS-12 Channel 8 7:0 0x8

2505 Receive Drop STS-48 Channel Nonservice-Affecting Alarm Register 2 4:0 0x0

2506 Receive Drop STS-48 Channel Nonservice-Affecting Alarm Mask Register 2 4:0 0x0

2600 Receive Drop STS-48 Channel Provisioning Register 3 1:0 0x0

2601 J0 Trace—STS-12 Channel 9 7:0 0x9

2602 J0 Trace—STS-12 Channel 10 7:0 0x10

2603 J0 Trace—STS-12 Channel 11 7:0 0x11

2604 J0 Trace—STS-12 Channel 12 7:0 0x12

2605 Receive Drop STS-48 Channel Nonservice-Affecting Alarm Register 3 4:0 0x0

2606 Receive Drop STS-48 Channel Nonservice-Affecting Alarm Mask Register 3 4:0 0x0

2700 Receive Drop STS-48 Channel Provisioning Register 4 1:0 0x0

2701 J0 Trace—STS-12 Channel 13 7:0 0x13

2702 J0 Trace—STS-12 Channel 14 7:0 0x14

2703 J0 Trace—STS-12 Channel 15 7:0 0x15

2704 J0 Trace—STS-12 Channel 16 7:0 0x16

2705 Receive Drop STS-48 Channel Nonservice-Affecting Alarm Register 4 4:0 0x0

2706 Receive Drop STS-48 Channel Nonservice-Affecting Alarm Mask Register 4 4:0 0x0

3000 STS-12 Pointer Processor Provisioning, STS-1 #1 to STS-1 #12 5:0 0x11

3001 STS-12 Pointer Processor Maintenance, STS-1 #1 to STS-1 #12 11:0 0x0

3002 STS-12 Pointer Interpreter PM, Last Second Increments, STS-1 #1 to

3003 STS-12 Pointer Interpreter PM, Last Second Decrements, STS-1 #1 to

3004 STS-12 Pointer Generator PM, Last Second Increments, STS-1 #1 to

3005 STS-12 Pointer Generator PM, Last Second Decrements, STS-1 #1 to

3010 STS-1 #1 Path Overhead Provisioning 15:0 0x0

3011 STS-1 #1 Path Overhead Maintenance 3:0 0x0

3012 STS-1 #1 Path Overhead Status 10:0 0x0

3013 STS-1 #1 Alarm Interrupt Status 6:0 0x0

3014 STS-1 #1 Alarm Interrupt Status Mask 6:0 0x0

3015 STS-1 #1 Alarm Persistency 4:0 0x0

3016 STS-1 #1 PM Last Second Indicators 6:0 0x0

3017 STS-1 #1 Last Second CV-P Count 15:0 0x0

3018 STS-1 #1 Last Second REI-P Count 15:0 0x0

3019 Not Used — —

3020 STS-1 #2 Path Overhead Provisioning 15:0 0x0

3028 STS-1 #2 Last Second REI-P Count 15:0 0x0

3100 STS-12 Pointer Processor Provisioning, STS-1 #13 to STS-1 #24 5:0 0x11

4000 Path Overhead (POH) Interrupt Status Register 15:0 0x0

4001 Path Overhead (POH) Interrupt Status Mask Register 15:0 0x0

4002 Path STS-1 Signal Fail Detect Threshold, Window Size Select 0 15:0 0x40CF

4003 Path STS-1 Signal Fail Clear Threshold, Window Size Select 0 15:0 0x8113

4004 Path STS-1 Signal Fail Detect Threshold, Window Size Select 1 15:0 0x80DE

4005 Path STS-1 Signal Fail Clear Threshold, Window Size Select 1 15:0 0xC115

4006 Path STS-Nc Signal Fail Detect Threshold, Window Size Select 2 15:0 0x4233

4007 Path STS-Nc Signal Fail Clear Threshold, Window Size Select 2 15:0 0x830B

4008 Path STS-Nc Signal Fail Detect Threshold, Window Size Select 3 15:0 0x82B2

4009 Path STS-Nc Signal Fail Clear Threshold, Window Size Select 3 15:0 0xC31B

4010 Path STS-Nc Signal Fail Detect Threshold, Window Size Select 7 15:0 0x8A62

4011 Path STS-Nc Signal Fail Clear Threshold, Window Size Select 7 15:0 0xCBFC

4012 Path Signal Fail Window Size 15:0 0xA

4013 Path Signal Fail Window Size 15:0 0x64

4014 Path Signal Fail Window Size 15:0 0x3E8

4015 Path Signal Fail Window Size 15:0 0x2710

4100 Path Trace Access Control 3:0 0x0

4101 Path Trace Access Complete Status 0 0x0

4102 Path Trace Access Start 0 0x0

4110 Path Trace Buffer Word #1 15:0 0x0

4111 Path Trace Buffer Word #2 15:0 0x0

4112 Path Trace Buffer Word #3 15:0 0x0

4113 Path Trace Buffer Word #4 15:0 0x0

4114 Path Trace Buffer Word #5 15:0 0x0

4115 Path Trace Buffer Word #6 15:0 0x0

4116 Path Trace Buffer Word #7 15:0 0x0

4117 Path Trace Buffer Word #8 15:0 0x0

4118 Path Trace Buffer Word #9 15:0 0x0

4119 Path Trace Buffer Word #10 15:0 0x0

4120 Path Trace Buffer Word #17 15:0 0x0

4121 Path Trace Buffer Word #18 15:0 0x0

4122 Path Trace Buffer Word #19 15:0 0x0

4123 Path Trace Buffer Word #20 15:0 0x0

4124 Path Trace Buffer Word #21 15:0 0x0

4125 Path Trace Buffer Word #22 15:0 0x0

4126 Path Trace Buffer Word #23 15:0 0x0

4127 Path Trace Buffer Word #24 15:0 0x0

4128 Path Trace Buffer Word #25 15:0 0x0

4129 Path Trace Buffer Word #26 15:0 0x0

4400 STS-1 Channel Interrupt Status, STS-1 #1 to STS-1 #16 (STS-48 #1) 15:0 0x0

4401 STS-1 Channel Interrupt Status Mask, STS-1 #1 to STS-1 #16 (STS-48 #1) 15:0 0x0

4402 STS-1 Channel Interrupt Status, STS-1 #17 to STS-1 #32 (STS-48 #1) 15:0 0x0

4403 STS-1 Channel Interrupt Status Mask, STS-1 #17 to STS-1 #32 (STS-48 #1) 15:0 0x0

4404 STS-1 Channel Interrupt Status, STS-1 #33 to STS-1 #48 (STS-48 #1) 15:0 0x0

4405 STS-1 Channel Interrupt Status Mask, STS-1 #33 to STS-1 #48 (STS-48 #1) 15:0 0x0

4406 STS-48 #1 Channel Path Trace Control 9:0 0x200

4407 S/W Concatenation Map STS-1 #1 to STS-1 #12 (STS-48 #1) 11:0 0x0

4408 S/W Concatenation Map STS-1 #13 to STS-1 #24 (STS-48 #1) 11:0 0x0

4409 S/W Concatenation Map STS-1 #25 to STS-1 #36 (STS-48 #1) 11:0 0x0

4410 Received Concatenation Map STS-1 #13 to STS-1 #24 (STS-48 #1) 11:0 0x0

4411 Received Concatenation Map STS-1 #25 to STS-1 #36 (STS-48 #1) 11:0 0x0

4412 Received Concatenation Map STS-1 #37 to STS-1 #48 (STS-48 #1) 11:0 0x0

4413 STS-48 Channel 1, Path Interrupt Status 11:0 0x0

4414 STS-48 Channel 1, Path Interrupt Status Mask 11:0 0x0

4500 STS-1 Channel Interrupt Status, STS-1 #49 to STS-1 #64 (STS-48 #2) 15:0 0x0

4501 STS-1 Channel Interrupt Status Mask, STS-1 #1 to STS-1 #16 (STS-48 #2) 15:0 0x0

4502 STS-1 Channel Interrupt Status, STS-1 #17 to STS-1 #32 (STS-48 #2) 15:0 0x0

4503 STS-1 Channel Interrupt Status Mask, STS-1 #17 to STS-1 #32 (STS-48 #2) 15:0 0x0

4504 STS-1 Channel Interrupt Status, STS-1 #33 to STS-1 #48 (STS-48 #2) 15:0 0x0

4505 STS-1 Channel Interrupt Status Mask, STS-1 #33 to STS-1 #48 (STS-48 #2) 15:0 0x0

4506 STS-48 #2 Channel Path Trace Control 9:0 0x200

4507 S/W Concatenation Map STS-1 #1 to STS-1 #12 (STS-48 #2) 11:0 0x0

4508 S/W Concatenation Map STS-1 #13 to STS-1 #24 (STS-48 #2) 11:0 0x0

4509 S/W Concatenation Map STS-1 #25 to STS-1 #36 (STS-48 #2) 11:0 0x0

4510 Received Concatenation Map STS-1 #13 to STS-1 #24 (STS-48 #2) 11:0 0x0

4511 Received Concatenation Map STS-1 #25 to STS-1 #36 (STS-48 #2) 11:0 0x0

4512 Received Concatenation Map STS-1 #37 to STS-1 #48 (STS-48 #2) 11:0 0x0

4513 STS-48 Channel 2, Path Interrupt Status 11:0 0x0

4514 STS-48 Channel 2, Path Interrupt Status Mask 11:0 0x0

4600 STS-1 Channel Interrupt Status, STS-1 #97 to STS-1 #112 (STS-48 #3) 15:0 0x0

4601 STS-1 Channel Interrupt Status Mask, STS-1 #1 to STS-1 #16 (STS-48 #3) 15:0 0x0

4602 STS-1 Channel Interrupt Status, STS-1 #17 to STS-1 #32 (STS-48 #3) 15:0 0x0

4603 STS-1 Channel Interrupt Status Mask, STS-1 #17 to STS-1 #32 (STS-48 #3) 15:0 0x0

4604 STS-1 Channel Interrupt Status, STS-1 #33 to STS-1 #48 (STS-48 #3) 15:0 0x0

4605 STS-1 Channel Interrupt Status Mask, STS-1 #33 to STS-1 #48 (STS-48 #3) 15:0 0x0

4606 STS-48 #3 Channel Path Trace Control 9:0 0x200

4607 S/W Concatenation Map STS-1 #1 to STS-1 #12 (STS-48 #3) 11:0 0x0

4608 S/W Concatenation Map STS-1 #13 to STS-1 #24 (STS-48 #3) 11:0 0x0

4609 S/W Concatenation Map STS-1 #25 to STS-1 #36 (STS-48 #3) 11:0 0x0

4610 Received Concatenation Map STS-1 #13 to STS-1 #24 (STS-48 #3) 11:0 0x0

4611 Received Concatenation Map STS-1 #25 to STS-1 #36 (STS-48 #3) 11:0 0x0

4612 Received Concatenation Map STS-1 #37 to STS-1 #48 (STS-48 #3) 11:0 0x0

4613 STS-48 Channel 3, Path Interrupt Status 11:0 0x0

4614 STS-48 Channel 3, Path Interrupt Status Mask 11:0 0x0

4700 STS-1 Channel Interrupt Status, STS-1 #145 to STS-1 #160 (STS-48 #4) 15:0 0x0

4701 STS-1 Channel Interrupt Status Mask, STS-1 #1 to STS-1 #16 (STS-48 #4) 15:0 0x0

4702 STS-1 Channel Interrupt Status, STS-1 #17 to STS-1 #32 (STS-48 #4) 15:0 0x0

4703 STS-1 Channel Interrupt Status Mask, STS-1 #17 to STS-1 #32 (STS-48 #4) 15:0 0x0

4704 STS-1 Channel Interrupt Status, STS-1 #33 to STS-1 #48 (STS-48 #4) 15:0 0x0

4705 STS-1 Channel Interrupt Status Mask, STS-1 #33 to STS-1 #48 (STS-48 #4) 15:0 0x0

4706 STS-48 #4 Channel Path Trace Control 9:0 0x200

4707 S/W Concatenation Map STS-1 #1 to STS-1 #12 (STS-48 #4) 11:0 0x0

4708 S/W Concatenation Map STS-1 #13 to STS-1 #24 (STS-48 #4) 11:0 0x0

4709 S/W Concatenation Map STS-1 #25 to STS-1 #36 (STS-48 #4) 11:0 0x0

4710 Received Concatenation Map STS-1 #13 to STS-1 #24 (STS-48 #4) 11:0 0x0

4711 Received Concatenation Map STS-1 #25 to STS-1 #36 (STS-48 #4) 11:0 0x0

4712 Received Concatenation Map STS-1 #37 to STS-1 #48 (STS-48 #4) 11:0 0x0

4713 STS-48 Channel 4, Path Interrupt Status 11:0 0x0

4714 STS-48 Channel 4, Path Interrupt Status Mask 11:0 0x0

indicate if the register is read only (RO), write one clear (W1C), read/write (R/W), or write only (WO). W1C mode will clear bits to which a 1 is written. Bits written to 0 are not cleared. Table 72. Interrupt Status (RO) 0x7, bit 6. See Table 79 on page 113. 0 CHIP_CLK_LOSS Clock Loss Alarms. Source—register 0x7, bits 0—5.

Table 73. Interrupt Status Mask (R/W) Table 74. Chip ID (RO) Table 75. Chip Vintage (RO) 7 CHIP_EQPT_NSA_M EQPT Nonservice-Affecting Alarms Interrupt Mask. 6 CHIP_EQPT_SA_M EQPT Service-Affecting Alarms Interrupt Mask. 5 CHIP_POH_STS48_M POH STS-48 Channel Alarms Interrupt Mask. 4 CHIP_POH_STS1_M POH STS-1 Channel Alarms Interrupt Mask. 3 CHIP_LTE_NSA_M LTE Nonservice-Affecting Alarms Interrupt Mask. 2 CHIP_LTE_SA_M LTE Service-Affecting Alarms Interrupt Mask. 1 CHIP_PM_CLK_M PMCLK Positive Edge Detected Interrupt Mask. 0 CHIP_CLK_LOSS_M Clock Loss Alarms Interrupt Mask.

Table 76. Scratch Pad, Clock Loss Alarm (R/W) Table 77. Chip-Level Maintenance (R/W) Table 78. Chip Status (RO)

0 FRC_PAR_ERR Force Parity Error Alarms (all data paths and

1 = Forces an internal parity error alarm. 2 DRPBYP State of DRPBYP Pin. 1 = Pointer generator is bypassed. 0 = Pointer generator is enabled. 1S T S _ M O D E State of STS_MODE Pin. 1 = Interrupt pin is asserted.

Table 79. Clock Loss Alarm/PM Clock Detection (W1C) 5 D_CLK_FAIL Loss of Clock—D_CLK. 4 T_CLK_FAIL Loss of Clock—T_CLK. 3 R_CLK_4_FAIL Loss of Clock—R_CLK_4. 2 R_CLK_3_FAIL Loss of Clock—R_CLK_3. 1 R_CLK_2_FAIL Loss of Clock—R_CLK_2. 0 R_CLK_1_FAIL Loss of Clock—R_CLK_1.

Table 80. Clock Loss Alarm/PM Clock Detection Mask (R/W) Table 81. Software Chip Reset (WO) (sampled by PCLK) Interrupt Mask. 5 D_CLK_FAIL_M Loss of Clock—D_CLK Interrupt Mask. 4 T_CLK_FAIL_M Loss of Clock—T_CLK Interrupt Mask. 3 R_CLK_4_FAIL_M Loss of Clock—R_CLK_4 Interrupt Mask. 2 R_CLK_3_FAIL_M Loss of Clock—R_CLK_3 Interrupt Mask. 1 R_CLK_2_FAIL_M Loss of Clock—R_CLK_2 Interrupt Mask. 0 R_CLK_1_FAIL_M Loss of Clock—R_CLK_1 Interrupt Mask. tion on page 96 for details.

I LTE J0 Access Registers: used to read and provision J0 messages for both the receive and transmit direction. limit for signal fail and signal degrade detection. These registers are common to all four receive STS-48 channels. receive overhead data (ROHDAT) memory parity error alarm, which is valid in all four channels). between all four transmit STS-48 channels. transmit overhead data (ROHDAT) memory parity error alarm, which is valid in all four channels). Table 82. LTE Interrupt Status (RO)

13 LTE_TX_4_NSA Transmit Channel 4 Nonservice-Affecting

12 LTE_TX_3_NSA Transmit Channel 3 Nonservice-Affecting

11 LTE_TX_2_NSA Transmit Channel 2 Nonservice-Affecting

10 LTE_TX_1_NSA Transmit Channel 1 Nonservice-Affecting

7 LTE_RX_4_NSA Receive Channel 4 Nonservice-Affecting

6 LTE_RX_3_NSA Receive Channel 3 Nonservice-Affecting

5 LTE_RX_2_NSA Receive Channel 2 Nonservice-Affecting

4 LTE_RX_1_NSA Receive Channel 1 Nonservice-Affecting

Table 83. LTE Interrupt Status Mask (R/W)

13 LTE_TX_4_NSA_M Transmit Channel 4 Nonservice-Affecting

12 LTE_TX_3_NSA_M Transmit Channel 3 Nonservice-Affecting

11 LTE_TX_2_NSA_M Transmit Channel 2 Nonservice-Affecting

10 LTE_TX_1_NSA_M Transmit Channel 1 Nonservice-Affecting

9 LTE_TX_COMMON_NSA_M Transmit Nonservice-Affecting Alarms Inter-

8 LTE_TX_COMMON_SA_M Transmit Service-Affecting Alarms Interrupt

7 LTE_RX_4_NSA_M Receive Channel 4 Nonservice-Affecting

6 LTE_RX_3_NSA_M Receive Channel 3 Nonservice-Affecting

5 LTE_RX_2_NSA_M Receive Channel 2 Nonservice-Affecting

4 LTE_RX_1_NSA_M Receive Channel 1 Nonservice-Affecting

Table 83. LTE Interrupt Status Mask (R/W) (continued) sioned J0 message register). See Table 137 on page 131 for detailed register information. Table 84. Section Trace (J0) Access Maintenance (R/W) Note: When the J_Access_Dir bit is set to 1 (transmit), the J_Access_Msg_Type bit is unused.

2 LTE_RX_3_SA_M Receive Channel 3 Service-Affecting Alarms

1 LTE_RX_2_SA_M Receive Channel 2 Service-Affecting Alarms

0 LTE_RX_1_SA_M Receive Channel 1 Service-Affecting Alarms

2 J_ACCESS_DIR J0 Access Direction. 1 J_ACCESS_MSG_TYPE Received Message Type. 0 J_ACCESS_RW Message Read/Write.

Table 85. J0 Access Done (W1C) Note: The J0 access done flag is a write 1 clear (W1C) register, but does not generate an interrupt. Table 86. J0 Access Message Start (WO) Table 87. J0 Access Message Buffers 1—32 (R/W) message buffer is overwritten with the contents of the desired message.

used in STS-192 mode. Both values are given in decimal format. Table 89. Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 x 10–4) (R/W) Table 90. Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 x 10–5) (R/W) Table 91. Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 x 10–6) (R/W) Table 92. Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 x 10–7) (R/W)

Table 93. Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 x 10–8) (R/W) Table 94. Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 x 10–9) (R/W) Table 95. Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 x 10–10) (R/W) Table 96. Line Signal Degrade/Signal Fail Detect Error Limit (1 x 10–3) (R/W) Table 97. Line Signal Degrade/Signal Fail Detect Error Limit (1 x 10–4) (R/W) Table 98. Line Signal Degrade/Signal Fail Detect Error Limit (1 x 10–5) (R/W)

Table 99. Line Signal Degrade/Signal Fail Detect Error Limit (1 x 10–6) (R/W) Table 100. Line Signal Degrade/Signal Fail Detect Error Limit (1 x 10–7) (R/W) Table 101. Line Signal Degrade/Signal Fail Detect Error Limit (1 x 10–8) (R/W) Table 102. Line Signal Degrade/Signal Fail Detect Error Limit (1 x 10–9) (R/W) Table 103. Line Signal Degrade/Signal Fail Clear Error Limit (1 x 10–4) (R/W) Table 104. Line Signal Degrade/Signal Fail Clear Error Limit (1 x 10–5) (R/W) Table 105. Line Signal Degrade/Signal Fail Clear Error Limit (1 x 10–6) (R/W)

Table 106. Line Signal Degrade/Signal Fail Clear Error Limit (1 x 10–7) (R/W) Table 107. Line Signal Degrade/Signal Fail Clear Error Limit (1 x 10–8) (R/W) Table 108. Line Signal Degrade/Signal Fail Clear Error Limit (1 x 10–9) (R/W) Table 109. Line Signal Degrade/Signal Fail Clear Error Limit (1 x 10–10) (R/W) Table 110. LTE Receive Channel 1 Provisioning (R/W) 7 B1_ERROR_MASK_EN B1 Error Mask Enable. 1 = ROHDAT B1 byte error mask. 6 B1_BIP_MODE_1 B1 BIP-8 Mode. 5 K_VALIDATE_LIMIT_SEL_1 K1K2 Validate Select. 1 = Five consecutive frames. 0 = Three consecutive frames. 4 RX_FRM_EN_1 RFRM Output Enable.

1 SEF_AIS_DIS_1 Disable AIS Generation Due to Severely Errored

0 LOF_AIS_DIS_1 Disable AIS Generation Due to Loss of Frame

Table 111. LTE Receive Channel 1 Maintenance (R/W) Table 112. LTE Receive Channel 1 Loss-of-Signal (LOS) Threshold (R/W) Table 113. LTE Receive Channel 1 K Byte Status (RO) Table 114. LTE Receive Channel 1 S1 Byte Status (RO) 6 J_MSG_TYPE_1 J0 Message Type. 5 J_MSG_MODE_1 J0 Message Mode. 4:2 SD_BER_1 Signal Degrade Bit Error Rate. 1:0 SF_BER_1 Signal Fail Bit Error Rate.

Table 115. LTE Receive Channel 1 Service-Affecting Interrupt Alarm (W1C) Table 116. LTE Receive Channel 1 Service-Affecting Interrupt Alarm Mask (R/W) Table 117. LTE Receive Channel 1 Service-Affecting Persistency Alarm (RO) 4 SD_ALARM_1_M Signal Degrade Interrupt Mask. 3 SF_ALARM_1_M Signal Fail Interrupt Mask. 2 RX_LINE_AIS_ALARM_1_M Line AIS Interrupt Mask. 1L O F _ M Loss of Frame Interrupt Mask. 0L O S _ M Loss of Signal Interrupt Mask.

Table 118. LTE Receive Channel 1 Nonservice-Affecting Interrupt Alarm (W1C)

10 RX_OH_MEM_PAR_ERR_1 Receive Overhead Data (ROHDAT)

4 CHANNEL_MISMATCH_ALARM_1 Receive/Transmit K1K2 Byte Channel

1 J_MSG_MISMATCH_INT_1 Received J0 Message Mismatch (with

Table 119. LTE Receive Channel 1 Nonservice-Affecting Interrupt Mask (R/W)

10 RX_OH_MEM_PAR_ERR_1_M Receive Overhead Data (ROHDAT) Memory

Parity Error Interrupt Mask.

9 J_MEM_PARITY_ERR_1_M J0 Message Buffer Parity Error Interrupt

5 INCONSISTENT_APS_ALARM_

4 CHANNEL_MISMATCH_

3 RX_LINE_RDI_ALARM_1_M Line Remote Defect Indication (RDI-L) Inter-

2 J_NEW_MSG_INT_1_M New Validated J0 Message Received Inter-

1 J_MSG_MISMATCH_INT_1_M Received J0 Message Mismatch (with

0 SEF_M Severely Errored Frame (SEF) Interrupt

Table 120. LTE Receive Channel 1 Nonservice-Affecting Persistency Alarm (RO) Table 121. LTE Receive Channel 1 Performance Monitoring (RO) Table 122. LTE Receive Channel 1 REI-L Performance Monitoring (L) (RO) Table 123. LTE Receive Channel 1 REI-L Performance Monitoring (U) (RO) Table 124. LTE Receive Channel 1 CV-L Performance Monitoring (L) (RO) Table 125. LTE Receive Channel 1 CV-L Performance Monitoring (U) (RO)

4 CHANNEL_MISMATCH_PER_1 Receive/Transmit K1K2 Byte Channel

4 RX_LINE_RDI_PM_1 Line Remote Defect Indication (RDI-L) Detect

Table 126. LTE Receive Channel 1 CV-S Performance Monitoring (RO) Table 127. LTE Transmit—Frame Pulse Offset Count (R/W) Table 128. LTE Transmit—Add Interface Self-Sync Option (R/W) Table 129. LTE Transmit—B1 Corrupt Frame Count (R/W) Table 130. LTE Transmit—B2 Corrupt Frame Count (R/W)

14 TX_FRM_DEJITTER_EN TFRM Dejitter Circuit Enable

Transmit Frame Sync Add Channel (1—16). section on page 82 for details. value is greater than or equal to 8064(dec).

Table 131. LTE Transmit—M1 Corrupt Frame Count (R/W) Table 132. LTE Transmit—TFRM S1 Byte (RO) Table 133. LTE Transmit—Interrupt Alarm Register (W1C) A2) section on page 82 for details.

Table 134. LTE Transmit—Interrupt Mask Register (R/W) Table 135. LTE Transmit Channel 1 Provisioning (R/W) 3 TX_FRM_RESYNC_M TFRM Resynchronization Alarm Interrupt Mask. 2 TX_J0_MEM_PARITY_ERR_M Transmit J0 Memory Parity Error Interrupt Mask. 1 TX_FRM_S1_BYTE_INVALID_M Valid S1 Byte Not Received Error Interrupt Mask. 0 TX_FRM_LOF_M TFRM Loss of Frame Error Interrupt Mask.

10 TX_SS_OVERWRITE_EN Enable Insertion of Defined SS Bits in All of the Out-

9S S _ M O D E SS Bit Mode Define SS Bit.

0 TX_TOH_DATA_INSERT_1 Enable Transport Overhead Data (TOHDAT) Inser-

Agere Systems Inc. 131 Data Sheet May 2003 STS-192 Overhead and Path Processor TSOT0410G4 SONET/SDH Microprocessor Interface (continued) Table 136. LTE Transmit Bit Assignment Note: X indicates either value. Table 137. LTE Transmit Channel 1 Maintenance (R/W) Table 138. LTE Transmit Channel 1 Path Unequipped (UNEQ-P) Insert Enable #1 (R/W) Table 139. LTE Transmit Channel 1 Path Unequipped (UNEQ-P) Insert Enable #2 (R/W) Table 140. LTE Transmit Channel 1 Path Unequipped (UNEQ-P) Insert Enable #3 (R/W)

Description

X 0 Section and line terminated (pointer processor state depen- dent on DRPBYP pin). 0 1 Full section and line overhead transparency (pointer proces- sor bypassed automatically). 1 1 Line overhead transparency section is terminated (pointer processor bypassed). Address (Hex) Bit Name Description Reset 1C01 15:6 — Unused. Program to zero. 0 5 TX_J0_MSG_INSERT_EN_1 Enable Insertion of Provisioned J0 Message. 0 4 S1_BYTE_TX_FRM_INSERT_1 Insert Validated S1 Byte from TFRM. 0 3:2 TX_K_BYTES_SELECT_1 K Byte Select. SW(0)/Raw K Bytes(1)/Validated K Bytes(2). 1 RDI_L_SELECT_1 Enable RDI-L Insertion. When set to 1, enables RDI-L when a condition arises to cause RDI-L. 0 TX_LINE_AIS_INSERT_1 Force Line AIS Insertion. Forces AIS_L Insertion when set to 1. Address (Hex) Bit Name Description Reset 1C02 15:12 — Unused. Program to zero. 0 11:0 LTE_TX_1_UNEQ_P_EN_1 Insert UNEQ-P on Specific STS-1 (1 to 12). 0 Address (Hex) Bit Name Description Reset 1C03 15:12 — Unused. Program to zero. 0 11:0 LTE_TX_1_UNEQ_P_EN_2 Insert UNEQ-P on Specific STS-1 (13 to 24). 0 Address (Hex) Bit Name Description Reset 1C04 15:12 — Unused. Program to zero. 0 11:0 LTE_TX_1_UNEQ_P_EN_3 Insert UNEQ-P on Specific STS-1 (25 to 36). 0

Table 141. LTE Transmit Channel 1 Path Unequipped (UNEQ-P) Insert Enable #4 (R/W) Table 142. LTE Transmit Channel 1 Path AIS (AIS-P) Insert Enable #1 (R/W) Table 143. LTE Transmit Channel 1 Path AIS (AIS-P) Insert Enable #2 (R/W) Table 144. LTE Transmit Channel 1 Path AIS (AIS-P) Insert Enable #3 (R/W) Table 145. LTE Transmit Channel 1 Path AIS (AIS-P) Insert Enable #4 (R/W) Table 146. LTE Transmit Channel 1 K1K2 Byte Insert Values (R/W) Table 147. LTE Transmit Channel 1 S1 Byte Insert Value (R/W)

Table 148. LTE Transmit Channel 1 Interrupt Alarm (W1C) Table 149. LTE Transmit Channel 1 Interrupt Alarm Mask (R/W)

1 TX_OH_MEM_PARITY_ERR_1 Transport Overhead Data Memory Parity

1 TX_OH_MEM_PARITY_ERR_1_M Transport Overhead Data Memory Parity

0 TX_DATA_PAR_ERR_1_M Transmit Data Path Internal Parity Error

Table 150. EQPT Interrupt Status (RO)

12 EQPT_RX_DRP_NSA_4 Receive Drop STS-48 Channel Nonservice-Affecting

11 EQPT_RX_DRP_NSA_3 Receive Drop STS-48 Channel Nonservice-Affecting

10 EQPT_RX_DRP_NSA_2 Receive Drop STS-48 Channel Nonservice-Affecting

9 EQPT_RX_DRP_NSA_1 Receive Drop STS-48 Channel Nonservice-Affecting

7 EQPT_TX_ADD_NSA_4 Transmit Add STS-48 Channel 4 Nonservice-Affecting

6 EQPT_TX_ADD_NSA_3 Transmit Add STS-48 Channel 3 Nonservice-Affecting

5 EQPT_TX_ADD_NSA_2 Transmit Add STS-48 Channel 2 Nonservice-Affecting

4 EQPT_TX_ADD_NSA_1 Transmit Add STS-48 Channel 1 Nonservice-Affecting

3 EQPT_TX_ADD_SA_4 Transmit Add STS-48 Channel 4 Service-Affecting

2 EQPT_TX_ADD_SA_3 Transmit Add STS-48 Channel 3 Service-Affecting

1 EQPT_TX_ADD_SA_2 Transmit Add STS-48 Channel 2 Service-Affecting

0 EQPT_TX_ADD_SA_1 Transmit Add STS-48 Channel 1 Service-Affecting

Table 151. EQPT Interrupt Mask (R/W)

12 EQPT_RX_DRP_NSA_4_M Receive Drop STS-48 Channel Nonser-

vice-Affecting Alarms Interrupt Mask.

11 EQPT_RX_DRP_NSA_3_M Receive Drop STS-48 Channel Nonser-

vice-Affecting Alarms Interrupt Mask.

10 EQPT_RX_DRP_NSA_2_M Receive Drop STS-48 Channel Nonser-

vice-Affecting Alarms Interrupt Mask.

9 EQPT_RX_DRP_NSA_1_M Receive Drop STS-48 Channel Nonser-

vice-Affecting Alarms Interrupt Mask.

8 EQPT_RX_DRP_SA_M Receive Drop Common Service-Affecting

7 EQPT_TX_ADD_NSA_4_M Transmit Add STS-48 Channel 4 Nonser-

vice-Affecting Alarms Interrupt Mask.

6 EQPT_TX_ADD_NSA_3_M Transmit Add STS-48 Channel 3 Nonser-

vice-Affecting Alarms Interrupt Mask.

5 EQPT_TX_ADD_NSA_2_M Transmit Add STS-48 Channel 2 Nonser-

vice-Affecting Alarms Interrupt Mask.

4 EQPT_TX_ADD_NSA_1_M Transmit Add STS-48 Channel 1 Nonser-

vice-Affecting Alarms Interrupt Mask.

3 EQPT_TX_ADD_SA_4_M Transmit Add STS-48 Channel 4 Ser-

vice-Affecting Alarms Interrupt Mask.

2 EQPT_TX_ADD_SA_3_M Transmit Add STS-48 Channel 3 Ser-

vice-Affecting Alarms Interrupt Mask.

Table 151. EQPT Interrupt Mask (R/W) (continued) Table 152. Receive Drop Common Service-Affecting Alarm (W1C) Table 153. Receive Drop Common Service-Affecting Alarm Mask (R/W) vice-Affecting Alarms Interrupt Mask.

0 EQPT_TX_ADD_SA_1_M Transmit Add STS-48 Channel 1 Ser-

vice-Affecting Alarms Interrupt Mask. 0 DFRM_LOSS Loss of DFRM Signal. 0 DFRM_LOSS_M Loss of DFRM Signal Interrupt Mask.

Table 154. Receive Drop STS-48 Channel Provisioning Register 1 (R/W) Table 155. J0 Trace—STS-12 Channel 1 (R/W) Table 156. J0 Trace—STS-12 Channel 2 (R/W) Table 157. J0 Trace—STS-12 Channel 3 (R/W) Table 158. J0 Trace—STS-12 Channel 4 (R/W) 1 B1_ERROR_INS Insert BIP-8 Error. 0 SCRM_DISABLE Scrambler Disable. 1 = Disables the receive drop interface scrambler. 0 = Enables the receive drop interface scrambler.

Table 159. Receive Drop STS-48 Channel Nonservice-Affecting Alarm (W1C) Table 160. Receive Drop STS-48 Channel Nonservice Affecting Alarm Mask (R/W)

4 RX_DATA_PAR_ERR_4 Data Path Parity Error Timing Control

4 RX_DATA_PAR_ERR_4_M Data Path Parity Error Timing Control

3 RX_DATA_PAR_ERR_3_M Data Path Parity Error STS-12 Channel 3

2 RX_DATA_PAR_ERR_2_M Data Path Parity Error STS-12 Channel 2

1 RX_DATA_PAR_ERR_1_M Data Path Parity Error STS-12 Channel 1

0 RX_DATA_PAR_ERR_0_M Data Path Parity Error STS-12 Channel 0

Table 161. Transmit Add STS-48 Channel Provisioning (R/W) Table 162. J0 Status Register—1 (RO) Table 163. J0 Status Register—2 (RO) Table 164. J0 Status Register—3 (RO) Table 165. J0 Status Register—4 (RO)

1 FRC_ADD_BUFFER_OVRFLW Force Add Buffer Overflow/Underflow

0 DESCRM_DISABLE Descrambler Disable.

Table 166. AIS Insert Status Register, STS-12 Channel #1 (RO) Table 167. AIS Insert Status Register, STS-12 Channel #2 (RO)

Table 168. AIS Insert Status Register, STS-12 Channel #3 (RO) Table 169. AIS Insert Status Register, STS-12 Channel #4 (RO)

Table 170. Transmit Add STS-48 Channel Alarm (W1C)

13 ADD12_BUFFER_OVRFLW_4 Synchronization Buffer Overflow/Underflow

9 ADD12_BUFFER_OVRFLW_3 Synchronization Buffer Overflow/Underflow

5 ADD12_BUFFER_OVRFLW_2 Synchronization Buffer Overflow/Underflow

1 ADD12_BUFFER_OVRFLW_1 Synchronization Buffer Overflow/Underflow

Table 171. Transmit Add STS-48 Channel Alarm Mask (R/W) 14 B1_ERROR_4_M BIP-8 Error STS-12 Channel 4—NSA Interrupt Mask.

13 ADD12_BUFFER_

Channel 4—NSA Interrupt Mask.

12 OOF_4_M Out-of-Frame Alarm STS-12 Channel 4—SA inter-

10 B1_ERROR_3_M BIP-8 Error STS-12 Channel 3—NSA Interrupt Mask.

9 ADD12_BUFFER_

Channel 3—NSA Interrupt Mask.

8 OOF_3_M Out-of-Frame Alarm STS-12 Channel 3—SA Inter-

6 B1_ERROR_2_M BIP-8 Error STS-12 Channel 2—NSA Interrupt Mask.

5 ADD12_BUFFER_

Channel 2—NSA Interrupt Mask.

4 OOF_2_M Out-of-Frame Alarm STS-12 Channel 2—SA Inter-

2 B1_ERROR_1_M BIP-8 Error STS-12 Channel 1—NSA Interrupt Mask.

1 ADD12_BUFFER_

Channel 1—NSA Interrupt Mask.

0 OOF_1_M Out-of-Frame Alarm STS-12 Channel 1—SA Inter-

are performed at the STS-48 level are also grouped together. one offset from STS-1 number 1). ber 77 is the fifth STS-1 in the STS-12), and the result is 0x3650. Figure 11. Path Register Structure

Table 172. STS-12 Pointer Processor Provisioning, STS-1 #1 to STS-1 #12 (R/W) Table 173. STS-12 Pointer Processor Maintenance, STS-1 #1 to STS-1 #12 (R/W) Table 174. STS-12 Pointer Interpreter PM, Last Second Increments, STS-1 #1 to STS-1 #12 (RO) 5 AUTO_AIS_DIS Disable Automatic AIS Insertion. 1 = Disable automatic AIS insertion. 0 = Enable automatic AIS insertion. 4 INT_SONET_SDH Pointer Increment/Decrement Standard. be considered an increment or decrement. sidered an increment or decrement.

Table 175. STS-12 Pointer Interpreter PM, Last Second Decrements, STS-1 #1 to STS-1 #12 (RO) Table 176. STS-12 Pointer Generator PM, Last Second Increments, STS-1 #1 to STS-1 #12 (RO) Table 177. STS-12 Pointer Generator PM, Last Second Decrements, STS-1 #1 to STS-1 #12 (RO) Table 178. STS-1 #1 Path Overhead Provisioning (R/W) Table 179. STS-1 #1 Path Overhead Maintenance (R/W)

1 CNT_BLK_ERRS Count B3 BIP-8 Errors, and G1 RDI-P and

Table 180. STS-1 #1 Path Overhead Status (RO) Table 181. STS-1 #1 Alarm Interrupt Status (W1C) Table 182. STS-1 #1 Alarm Interrupt Status Mask (R/W) (raw) RDI-P; may differ from PM register).

6 ES_OVRUN_M Elastic Store Overrun/Underrun Interrupt

5 SIG_FAIL_M Signal Fail Interrupt Mask. 4 RDI_P_M Remote Defect Indicator Interrupt Mask. 3 PLM_P_M Payload Label Mismatch Interrupt Mask. 2U N E Q _ P _ M Unequipped Received Interrupt Mask. 1 AIS_P_M AIS Received Interrupt Mask. 0 LOP_P_M Loss of Pointer Interrupt Mask.

Table 183. STS-1 #1 Alarm Persistency (RO) Table 184. STS-1 #1 PM Last Second Indicators (RO) Table 185. STS-1 #1 Last Second CV-P Count (RO) Table 186. STS-1 #1 Last Second REI-P Count (RO)

Table 187. Path Overhead (POH) Interrupt Status (RO) Table 188. Path Overhead (POH) Interrupt Status Mask (R/W) consolidating alarms per STS-1).

14 STS48_CH4_ALARMS3_M STS-48 Channel 3 Path Alarms Interrupt

13 STS48_CH4_ALARMS2_M STS-48 Channel 2 Path Alarms Interrupt

12 STS48_CH4_ALARMS1_M STS-48 Channel 1 Path Alarms Interrupt

Table 189. STS-1 Signal Fail Detect Threshold, Window Size Select 0 (R/W) Table 190. STS-1 Signal Fail Clear Threshold, Window Size Select 0 (R/W) Table 191. STS-1 Signal Fail Detect Threshold, Window Size Select 1 (R/W) Table 192. STS-1 Signal Fail Clear Threshold, Window Size Select 1 (R/W)

Table 193. STS-Nc Signal Fail Detect Threshold, Window Size Select 2 (R/W) Table 194. STS-Nc Signal Fail Clear Threshold, Window Size Select 2 (R/W) Table 195. STS-Nc Signal Fail Detect Threshold, Window Size Select 3 (R/W) Table 196. STS-Nc Signal Fail Clear Threshold, Window Size Select 3 (R/W)

Table 197. STS-Nc Signal Fail Detect Threshold, Window Size Select 4 (R/W) Table 198. STS-Nc Signal Fail Clear Threshold, Window Size Select 4 (R/W) Table 199. STS-Nc Signal Fail Detect Threshold, Window Size Select 5 (R/W) Table 200. STS-Nc Signal Fail Clear Threshold, Window Size Select 5 (R/W) Table 201. STS-Nc Signal Fail Detect Threshold, Window Size Select 6 (R/W) Table 202. STS-Nc Signal Fail Clear Threshold, Window Size Select 6 (R/W)

Table 203. STS-Nc Signal Fail Detect Threshold, Window Size Select 7 (R/W) Table 204. STS-Nc Signal Fail Clear Threshold, Window Size Select 7 (R/W) Table 205. Signal Fail Window Size 0 (R/W) Table 206. Signal Fail Window Size 1 (R/W) Table 207. Signal Fail Window Size 2 (R/W) Table 208. Signal Fail Window Size 3 (R/W)

tion trace registers for a description on how to use the path trace registers. Table 209. Path Trace Access Control (R/W) Table 210. Path Trace Access Complete Status (W1C) Table 211. Path Trace Access Start Table 212. Path Trace Buffer Word #1—Word #32 3:2 CH_SEL STS-48 Channel Select for J1. 1 BUF_MSG_SEL J1 Buffer Message Type Select. 0 BUF_RNW J1 Buffer Access Mode.

Table 213. STS-1 Channel Interrupt Status, STS-1 #1 to STS-1 #16 (RO) Table 214. STS-1 Channel Interrupt Status Mask, STS-1 #1 to STS-1 #16 (R/W) 4401 15 CH_ISR_BIT15_M STS-1 #16 Interrupt Mask. 14 CH_ISR_BIT14_M STS-1 #15 Interrupt Mask. 13 CH_ISR_BIT13_M STS-1 #14 Interrupt Mask. 12 CH_ISR_BIT12_M STS-1 #13 Interrupt Mask. 11 CH_ISR_BIT11_M STS-1 #12 Interrupt Mask.

Table 214. STS-1 Channel Interrupt Status Mask, STS-1 #1 to STS-1 #16 (R/W) (continued) 4401 10 CH_ISR_BIT10_M STS-1 #11 Interrupt Mask. 9 CH_ISR_BIT9_M STS-1 #10 Interrupt Mask. 8 CH_ISR_BIT8_M STS-1 #9 Interrupt Mask. 7 CH_ISR_BIT7_M STS-1 #8 Interrupt Mask. 6 CH_ISR_BIT6_M STS-1 #7 Interrupt Mask. 5 CH_ISR_BIT5_M STS-1 #6 Interrupt Mask. 4 CH_ISR_BIT4_M STS-1 #5 Interrupt Mask. 3 CH_ISR_BIT3_M STS-1 #4 Interrupt Mask. 2 CH_ISR_BIT2_M STS-1 #3 Interrupt Mask. 1 CH_ISR_BIT1_M STS-1 #2 Interrupt Mask. 0 CH_ISR_BIT0_M STS-1 #1 Interrupt Mask.

Table 215. STS-1 Channel Interrupt Status, STS-1 #17 to STS-1 #32 (RO)

Table 216. STS-1 Channel Interrupt Status Mask, STS-1 #17 to STS-1 #32 (R/W) 4403 15 CH_ISR_BIT15_M STS-1 #32 Interrupt Mask. 14 CH_ISR_BIT14_M STS-1 #31 Interrupt Mask. 13 CH_ISR_BIT13_M STS-1 #30 Interrupt Mask. 12 CH_ISR_BIT12_M STS-1 #29 Interrupt Mask. 11 CH_ISR_BIT11_M STS-1 #28 Interrupt Mask. 10 CH_ISR_BIT10_M STS-1 #27 Interrupt Mask. 9 CH_ISR_BIT9_M STS-1 #26 Interrupt Mask. 8 CH_ISR_BIT8_M STS-1 #25 Interrupt Mask. 7 CH_ISR_BIT7_M STS-1 #24 Interrupt Mask. 6 CH_ISR_BIT6_M STS-1 #23 Interrupt Mask. 5 CH_ISR_BIT5_M STS-1 #22 Interrupt Mask.

Table 216. STS-1 Channel Interrupt Status Mask, STS-1 #17 to STS-1 #32 (R/W) (continued) Table 217. STS-1 Channel Interrupt Status, STS-1 #33 to STS-1 #48 (RO) 4403 4 CH_ISR_BIT4_M STS-1 #21 Interrupt Mask. 3 CH_ISR_BIT3_M STS-1 #20 Interrupt Mask. 2 CH_ISR_BIT2_M STS-1 #19 Interrupt Mask. 1 CH_ISR_BIT1_M STS-1 #18 Interrupt Mask. 0 CH_ISR_BIT0_M STS-1 #17 Interrupt Mask.

Table 218. STS-1 Channel Interrupt Status Mask, STS-1 #33 to STS-1 #48 (R/W) 4405 15 CH_ISR_BIT15_M STS-1 #48 Interrupt Mask. 14 CH_ISR_BIT14_M STS-1 #47 Interrupt Mask. 13 CH_ISR_BIT13_M STS-1 #46 Interrupt Mask. 12 CH_ISR_BIT12_M STS-1 #45 Interrupt Mask. 11 CH_ISR_BIT11_M STS-1 #44 Interrupt Mask. 10 CH_ISR_BIT10_M STS-1 #43 Interrupt Mask. 9 CH_ISR_BIT9_M STS-1 #42 Interrupt Mask. 8 CH_ISR_BIT8_M STS-1 #41 Interrupt Mask. 7 CH_ISR_BIT7_M STS-1 #40 Interrupt Mask. 6 CH_ISR_BIT6_M STS-1 #39 Interrupt Mask. 5 CH_ISR_BIT5_M STS-1 #38 Interrupt Mask. 4 CH_ISR_BIT4_M STS-1 #37 Interrupt Mask. 3 CH_ISR_BIT3_M STS-1 #36 Interrupt Mask. 2 CH_ISR_BIT2_M STS-1 #35 Interrupt Mask.

Table 218. STS-1 Channel Interrupt Status Mask, STS-1 #33 to STS-1 #48 (R/W) (continued) Table 219. STS-48 Channel Path Trace Control (R/W) Table 220. S/W Concatenation Map STS-1 #1 to STS-1 #12 (R/W) Table 221. S/W Concatenation Map STS-1 #13 to STS-1 #24 (R/W) 4405 1 CH_ISR_BIT1_M STS-1 #34 Interrupt Mask. 0 CH_ISR_BIT0_M STS-1 #33 Interrupt Mask. 9 MODE_SEL J1 Message Mode Select. 8 TYPE_SEL J1 Message Type Select. other values disable the feature).

Table 222. S/W Concatenation Map STS-1 #25 to STS-1 #36 (R/W) Table 223. S/W Concatenation Map STS-1 #37 to STS-1 #48 (R/W) Table 224. S/W Concatenation Mask STS-1 #1 to STS-1 #12 (R/W) Table 225. S/W Concatenation Mask STS-1 #13 to STS-1 #24 (R/W) Table 226. S/W Concatenation Mask STS-1 #25 to STS-1 #36 (R/W)

Table 227. S/W Concatenation Mask STS-1 #37 to STS-1 #48 (R/W) Table 228. Received Concatenation Map STS-1 #1 to STS-1 #12 (RO) Table 229. Received Concatenation Map STS-1 #13 to STS-1 #24 (RO) Table 230. Received Concatenation Map STS-1 #25 to STS-1 #36 (RO) Table 231. Received Concatenation Map STS-1 #37 to STS-1 #48 (RO)

11 RECD_CONC_MAP_STS12 STS-1 #12 Received Concatenation Map

11 RECD_CONC_MAP_STS24 STS-1 #24 Received Concatenation Map

11 RECD_CONC_MAP_STS36 STS-1 #36 Received Concatenation Map

11 RECD_CONC_MAP_STS48 STS-1 #48 Received Concatenation Map

Table 232. STS-48 Channel Path Alarms 1 (W1C)

11 CONC_MAP_MMCH_4 Concatenation Map Mismatch in

10 CONC_MAP_MMCH_3 Concatenation Map Mismatch in

9 CONC_MAP_MMCH_2 Concatenation Map Mismatch in

8 CONC_MAP_MMCH_1 Concatenation Map Mismatch in

7 UNSUPP_CONC_MAP_4 Unsupported Concatenation in STS-1 #37—

6 UNSUPP_CONC_MAP_3 Unsupported Concatenation in STS-1 #25—

5 UNSUPP_CONC_MAP_2 Unsupported Concatenation in STS-1 #13—

4 UNSUPP_CONC_MAP_1 Unsupported Concatenation in STS-1 #1—

Table 233. STS-48 Channel Path Alarms 1 Mask (W1C)

11 CONC_MAP_MMCH_4_M Concatenation Map Mismatch in

STS-1 #37—STS-1 #48 Interrupt Mask.

10 CONC_MAP_MMCH_3_M Concatenation Map Mismatch in

STS-1 #25—STS-1 #36 Interrupt Mask.

9 CONC_MAP_MMCH_2_M Concatenation Map Mismatch in

STS-1 #13—STS-1 #24 Interrupt Mask.

8 CONC_MAP_MMCH_1_M Concatenation Map Mismatch in

STS-1 #1—STS-1 #12 Interrupt Mask.

7 UNSUPP_CONC_MAP_4_M Unsupported Concatenation in STS-1 #37—

6 UNSUPP_CONC_MAP_3_M Unsupported Concatenation in STS-1 #25—

5 UNSUPP_CONC_MAP_2_M Unsupported Concatenation in STS-1 #13—

4 UNSUPP_CONC_MAP_1_M Unsupported Concatenation in STS-1 #1—

2 J1_BUF_PAR_ERR_M J1 Memory Parity Error Interrupt Mask. 1J 1 _ N E W _ M S G _ M J1 New Validated Message Interrupt Mask. 0 J1_MSG_MMCH_M J1 Message Mismatch Interrupt Mask.

ings for extended periods can adversely affect device reliability. Table 234. Absolute Maximum Ratings model (HBM) and charged-device model (CDM) for ESD-susceptibility testing and protection design evaluation. obtained by using these circuit parameters. Table 235. Recommended Operating Conditions

3.3 V Power

2.5 V Power

3.3 V Power Supply

2.5 V Power Supply

1. The maximum power dissipation for the five analog power supply inputs is 350 mW (5 × 70 mW each). This total is included in P D3.

Agere Systems Inc. 167 Data Sheet May 2003 STS-192 Overhead and Path Processor TSOT0410G4 SONET/SDH Recommended Operating Conditions (continued) I The TSOT0410G4 is packaged in a 9-layer LBGA. The heat sink is not grounded in the TSOT0410G4. I The thermal resistance junction to case, θJC, of the 600-pin LBGA package is 0.4 °C/W. I The thermal resistance junction to ambient (to the nearest 0.5 °C/W), θJA, of the 600-pin LBGA package is given in Table 236. Table 236. Thermal Resistance—Junction to Ambient

Electrical Characteristics

The device power may be applied concurrently to both voltage level inputs. If power sequencing is used for other devices on a board or in a system, it is a preferred that the highest voltage be applied first and removed last. Low-Voltage Differential Signal (LVDS) Buffers The LVDS buffers are compliant with the EIA-644 standard. The only exception to compliance with this standard is associated with the input leakage current. The LVDS input buffers have an input leakage current of 300 µA maxi- mum. The LVDS buffers are also compliant to the IEEE 1596.3 standard. The only exception to compliance with this standard is the input termination resistance. The LVDS input buffers have an input termination resistance of 80 Ω —135 Ω . The LVDS outputs are hot-swap compatible, and can be connected to other vendor’s LVDS I/O buffers. The maxi- mum input current for the Agere LVDS input buffers is 9 mA. Prolonged exposure to higher current levels will have an impact on long-term reliability. CML or open collector transmitters cannot be directly connected to the TSOT0410G4 LVDS inputs. This is not pos- sible, since up to four LVDS inputs share one center tap line with one center tap pin. The 10 µm center tap line is relatively long in the TSOT0410G4; therefore, resistances and capacitances cannot be ignored. Unused LVDS inputs may be left unconnected. There are internal pull-up resistors (nominal 14 kΩ ) that pull open inputs to greater than 2.75 Vdc (the common mode range is 0 Vdc to 2.4 Vdc). A sense circuit becomes active for input voltages above 2.75 Vdc and clamps the buffer output to a defined state. Open inputs will not oscillate for this reason. For board layout, LVDS traces should be run on controlled-impedance layers, and should be specified as 50 Ω line-to-ground. The LVDS buffers support point-to-point connections. They are not intended for bused implementa- tions. Air Speed in Linear Feet per Minute (LFPM) θ JA (°C/W) JEDEC Standard Natural Convection 9 08 . 5 200 6.5 500 6 800 5

Table 238 the ac data, and Table 240 on page 170 the LVDS receiver data. Table 237. LVDS Driver dc Data Table 238. LVDS Driver ac Data refer to Figure 14 on page 168.

Table 239. LVDS Driver Reference Data Table 240. LVDS Receiver Data Table 241. Receive Payload Add Interface

1. Buffer will not produce transition when input is open-circuited.
2. 622.08 Mbits/s scrambled data stream conforming to SONET STS-12 and SDH STM-4 data format using either a PN7 or PN9 sequence:

— PN7 characteristic is 1 + x6 + x7. — PN9 characteristic is 1 + x4 + x9.

1. This sequence should not occur more than once per minute.
2. Translates to a frequency change of 500 ppm.
3. A unit interval for 622.08 Mbits/s data is 1.6075 ns.

Table 242. Receive Payload Drop Interface Table 243. LVTTL 3.3 V Logic Interface Characteristics

timing characteristics for these pins are given in Table 245. Table 245. RLCLOW/RSUSER/REXPOW Timing Table 246. (See Figure 16 on page 173.) Table 246. RSDCC Timing Table 247. RLDCC Timing

pins is intended to occur at the positive edge of the ROH_CLK signal. 51.84 MHz clock cycle (short clock). the data stream, as illustrated in Figure 17. each other. This is due to the possibility of the four channels being asynchronous. The timing characteristics for the receive overhead serial pins are given in Table 248. Figure 17. Receive Overhead Serial Timing Table 248. Receive Overhead Serial Timing

Table 252. TSDCC Timing Table 253. TLDCC Timing

Figure 21. Transmit Overhead Serial Timing zero hold time required on the TOHDAT inputs. The skew between the four TOH_CLK outputs is 1 ns maximum. TOH_DAT signals are brought to a common device, such as an FPGA. The timing characteristics for the transmit overhead serial pins are given in Table 254 on page 181. be generated for the entire byte time (as indicated by dashed line waveforms in Figure 21).

Table 254. Transmit Overhead Serial Timing Figure 22. Receive Frame Timing (Pointer Processor Bypassed) Table 255. Drop Frame Timing (Pointer Processor Bypassed)

1. The frame pulse may occur after either a long clock or a short clock.

622.08 MHz clock for the drop data signals. Figure 23. Receive Frame Timing (Pointer Processor Active) Table 256. Drop Frame Timing (Pointer Processor Active) page 178, the timing characteristics for these pins are given in Table 257. Table 257. RDDCC Timing

transmit add signals for a STS-48/STS-192 channel are expected to be aligned within 75 ns of each other. another device, or across a backplane. Table 258. TADCC Timing read cycle is given in Figure 25 on page 185 and in Table 262 on page 185. should be ignored on a synchronous write.

32 PCLK cycles from the first rising edge of PCLK, where CS_N = 0 and TS_N = 0. Figure 24. Microprocessor Interface Synchronous Write Cycle (MPMODE = 1) Table 259. TA_N/TEA_N Cycle Termination for Synchronous Write Cycle Table 260. Microprocessor Interface Synchronous Write Cycle Specifications 0 0 Write data parity error. 0 1 Normal cycle termination. 1 0 Access to undefined address region—transfer error. 1 1 No cycle termination—processor generated time-out.

Figure 25. Microprocessor Interface Synchronous Read Cycle (MPMODE = 1) Table 261. TA_N/TEA_N Cycle Termination for Synchronous Read Cycle Table 262. Microprocessor Interface Synchronous Read Cycle Specifications 0 0 Not possible during read cycle. 0 1 Normal cycle termination. 1 0 Access to undefined address region—transfer error. 1 1 No cycle termination—processor generated time-out.

in Figure 27 on page 187 and in Table 266 on page 187. PCLK frequency of 77.76 MHz. Figure 26. Microprocessor Interface Asynchronous Write Cycle (MPMODE = 0) Table 263. Microprocessor Interface Asynchronous Write Cycle Specifications

1. This value represents the timing for a transfer error (TA_N = 1, TEA_N = 0). The typical value during normal access would be 9t c .

Table 264. TA_N/TEA_N Cycle Termination for Asynchronous Write Cycle Figure 27. Microprocessor Interface Asynchronous Read Cycle (MPMODE = 0) Table 265. TA_N/TEA_N Cycle Termination for Asynchronous Read Cycle Table 266. Microprocessor Interface Asynchronous Read Cycle Specifications 0 0 Not possible during asynchronous write cycle. 0 1 Normal cycle termination. 1 0 Access to undefined address region—transfer error. 1 1 No cycle termination—processor generated time-out. 0 0 Not possible during read cycle. 0 1 Normal cycle termination. 1 0 Access to undefined address region—transfer error. 1 1 No cycle termination—processor generated time-out.

188 Agere Systems Inc. Data Sheet May 2003STS-192 Overhead and Path Processor TSOT0410G4 SONET/SDH Timing Characteristics (continued) Use of a Synchronous Microprocessor with the TSOT0410G4 in Asynchronous Mode The use of a synchronous microprocessor (such as the M860/M8260) to communicate with a TSOT0410G4 config- ured for asynchronous mode (MPMODE = 0) requires one additional consideration. There is a difference between a synchronous processor, the data is latched on the same edge that detects the assertion of TA_N. In an asynchro- nous processor, the TA_N (DSACK) signal is detected, and the data is latched one clock period later. In both cases, the TSOT0410G4 meets the timing required by these two different processors. However, a synchro- nous processor operating with the TSOT0410G4 configured in asynchronous mode will have problems consis- tently latching the correct data. It will depend on the relationship between the two clocks. As shown in Figure 27 on page 187, the data is presented on the bus 13 ns—15 ns after TA_N is asserted. If the microprocessor has a rising edge within this window, it will capture incorrect data. To operate the TSOT in asynchronous mode with an synchronous processor, add a delay on the TA_N signal from the TSOT0410G4; otherwise, consider using synchronous mode.

Agere Systems Inc. 189 Data Sheet May 2003 STS-192 Overhead and Path Processor TSOT0410G4 SONET/SDH Outline Diagram 600-Pin LBGA Dimensions are in millimeters. 5-9212.a (F) 45.00 45.00 A1 BALL T D H AL F K B P M L J AH R C E Y N U AN G AD V AM AJ AG AE AC AA W AP AK AF AB AR A 34 SPACES @ 1.27 = 43.18

34 SPACES

0.75 ± 0.15 IDENTIFIER ZONE @ 1.27 = 43.18 CORNER 1.95/2.35 SEATING PLANE SOLDER BALL0.60 ± 0.10 0.20 1.45/1.85 ELECTRICALLY ISOLATED HEAT SPREADER2.45/3.05 41.3/42.3 41.3/42.3 30 2628 2432 22 20 18 4 6810121416 234 52325 731 29 15 21 327 11 17 9 13 135 33

May 2003STS-192 Overhead and Path Processor TSOT0410G4 SONET/SDH Copyright © 2003 Agere Systems Inc. All Rights Reserved May 2003 DS02-252SONT-1 (Replaces DS02-252SONT) Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liab ility is assumed as a result of their use or application. Agere, Agere Systems, and the Agere Logo are trademarks of Agere Systems Inc. For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com N. AMERICA: Agere Systems Inc., Lehigh Valley Central Campus, Room 10A-301C, 1110 American Parkway NE, Allentown, PA 18109-9138 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, FAX (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 755-25881122 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 6778-8833, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 1344 296 400

Ordering Information

IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc. EIA is a registered trademark of The Electronic Industries Association. Motorola is a registered trademark of Motorola, Inc. Device Code Package Temperature Comcode TSOT0410G14 600-pin LBGA –40 °C to +85 °C 700017424