TSEV81102G0TPZR3

TS81102G0 ATMEL | Alldatasheet

Document overview

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Technical content

Features

• Programmable DMUX Ratio: – 1:4: Data Rate Max = 1 Gsps – PD (8b/10b) < 4.3/4.7 W (ECL 50 Ω output) – 1:8: Data Rate Max = 2 Gsps – PD (8b/10b) < 6/6.9 W (ECL 50 Ω output) – 1:16 with 1 TS8388B or 1 TS83102G0B and 2 DMUX  Parallel Output Mode  8-/10-bit  ECL Differential Input Data  DataReady or DataReady/2 Input Clock  Input Clock Sampling Delay Adjust  Single-ended Output Data: – Adjustable Common Mode and Swing – Logic Threshold Reference Output – (ECL, PECL, TTL)  Asynchronous Reset  Synchronous Reset  ADC + DMUX Multi-channel Applications: – Stand-alone Delay Adjust Cell for ADCs Sampling Instant Alignment  Differential Data Ready Output  Built-in Self Test (BIST)  Dual Power Supply VEE = -5V, VCC = +5V  Radiation Tolerance Oriented Design (More than 100 Krad (Si) Expected)  TBGA 240 (Cavity Down) Package

Description

The TS81102G0 is a monolithic 10-bit high-speed (up to 2 GHz) demultiplexor, designed to run with all kinds of ADCs and more specifically with Atmel’s high-speed ADC 8-bit 1 Gsps TS8388B and ADC 10-bit 2 Gsps TS83102G0B. The TS81102G0 uses an innovative architecture, including a sampling delay adjust and tunable output levels. It allows users to process the high-speed output data stream down to processor speed and uses the very high-speed bipolar technology (25 GHz NPN cut-off frequency). DMUX 8-/10-bit

2 GHz 1:4/8

Rev. 2105C–BDC–11/03

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Figure 1. Block Diagram

8 Counter

This diagram corresponds to an established operation of the DMUX with Synchronous Reset. Figure 2. Internal Timing Diagram

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2105C–BDC–11/03 Functional The TS81102G0 is a demultiplexer based on an advanced high-speed bipolar technology fea- turing a cutoff frequency of 25 GHz. Its role is to reduce the data rate so that the data can be processed at the DMUX output. The TS81102G0 provides 2 programmable ratios: 1:4 and 1:8. The maximum data rate is 1 Gsps for the 1:4 ratio and 2 Gsps for the 1:8 ratio. The TS81102G0 is able to process 8 or 10-bit data flows. The input clock can be an ECL differential signal or single-ended DC coupled signal. Moreover it can be a DataReady or DataReady/2 clock. The input digital data must be an ECL differential signal. The output signals (Data Ready, digital data and reference voltage) are adjustable with VplusD independent power supply. Typical output modes are ECL, PECL or TTL. The Data Ready output is a differential signal. The digital output data and reference voltages are single-ended signals. The TS81102G0 is started by an Asynchronous Reset. A Synchronous Reset enables the user to re-synchronize the output port selection and to minimize loss of data that could occur within the DMUX. A delay adjust cell is available to ensure a good phase between the DMUX’ input clock and input data. Another delay adjust cell is available to control the ADCss sampling instant alignment, in case of the ADCs interleaving. A 10-bit generator is implemented in the TS81102G0, the Built-In Self Test (BIST). This test sequence is very useful for testing the DMUX at first use. A fine tuning of the output swing is also available. The TS81102G0 can be used with the following Atmel ADCs:  TS8388B(F/FS/GL), 8-bit 1 Gsps ADC  TS83102G0B, 10-bit 2 Gsps ADC

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Figure 5. Asynchronous Reset is active on the high level. During an asynchronous reset, the clock must be in a known state. It is used to start the DMUX. the outputs are active and the first processed data is on port A. Figure 6. Synchronous Reset and generates a 200 ps reset pulse. This reset pulse occurs during a fixed level of Clkln. DMUX, and no data is lost (“Internal Timing Diagram” on page 3). chronous Reset” on page 19).

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mon mode) is available (one level by output port). Figure 9. Single-ended Output Data mode depends on the load to be driven. This corresponds to the “Adjustable Logic Single” in the pinout description. available at the output of these buffers is more like analog than logic. Note: The Max Output Data Rate is given for a typical 50Ω/2 pF load. Table 1. Examples of Application of Buffers

The definition is the same as for single-ended output data, but the buffers are differential. This corresponds to the “Adjustable Logic Differential” in the pinout description. codes is uniformly spread over the 1024 possible codes: 0 or 1/1024. (DataReady ADC clock) to have a different 10-bit code on each output. The complete BIST sequence is available on request. Table 2. Absolute Maximum Ratings

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“Thermal and Moisture Characteristics” on page 26. Table 2. Absolute Maximum Ratings (Continued) Table 3. Recommended Operating Conditions

Tj (typical) = 70°C. Full Temperature Range: -40°C < Tc; Tj < 110°C. Table 4. Electrical Specifications

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Table 4. Electrical Specifications (Continued)

• the typical values correspond to an equal sharing-out of the output buffers between high and low levels.

50% clock duty cycle (CLKIN, CLKINB). Tj (typical) = 70°C. Full temperature range: -40°C < Tc; Tj < 110°C. See Timing Diagrams Figure 10 on page 16 to Figure 19 on page 21. Table 5. Switching Performances

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Table 5. Switching Performances (Continued)

Notes: 1. TCPD is tuned with DMUXDelAdjCtrl: TCPD = 981 ± 250 ps.

1. TCPD is tuned with DMUXDelAdjCtrl: TCPD = 1084 ± 250 ps.
2. TSSR depends on DMUXDelAdjCtrl: TSSR = -580 ± 250 ps. TSSR < 0 because of Clock Path internal delay.
3. TSSR depends on DMUXDelAdjCtrl: TSSR = -477 ± 250 ps. TSSR < 0 because of Clock Path internal delay.
4. THSR depends on DMUXDelAdjCtrl: THSR = 780 ± 250 ps.
5. THSR depends on DMUXDelAdjCtrl: THSR = 677 ± 250 ps.
6. TSCKIN depends on DMUXDelAdjCtrl: TSCKIN = -794 ± 250 ps. TSCKIN < 0 because of Clock Path internal delay.
7. TSCKIN depends on DMUXDelAdjCtrl: TSCKIN = -691 ± 250 ps. TSCKIN < 0 because of Clock Path internal delay.
8. THCKIN depends on DMUXDelAdjCtrl: THCKIN = 994 ± 250 ps.
9. THCKIN depends on DMUXDelAdjCtrl: THCKIN = 891 ± 250 ps.
10. TOD depends on DMUXDelAdjCtrl: TOD = 1820 ± 250 ps. TOD is given for ECL 50Ω/2 pFoutput load.
11. TOD depends on DMUXDelAdjCtrl: TOD = 1717 ± 250 ps. TOD is given for ECL 50Ω/2 pFoutput load.
12. TPD is the number of Clkln clock cycle from selection of Port A to selection of Port H in 1:8 conversion mode, and from

delay, that a data has to stay in the DMUX before being sorted out. This maximum delay occurs for the data sent to Port A. there is an additional delay due to physical propagation time in the DMUX.

1. TROD and TFOD are given for ECL 50Ω/2 pF output load. In TTL mode, the TROD and TFOD are twice the ones for ECL.
2. TDRF depends on DMUXDelAdjCtrl: TDRF = 1856 ± 250 ps. It is given for ECL 50Ω/2 pF output load.
3. TDRF depends on DMUXDelAdjCtrl: TDRF = 1753 ± 250 ps. It is given for ECL 50Ω/2 pF output load.
4. TDRR depends on DMUXDelAdjCtrl: TDRR = 1858 ± 250 ps. It is given for ECL 50Ω/2 pF output load.
5. TDRR depends on DMUXDelAdjCtrl: TDRR = 1725 ± 250 ps. It is given for ECL 50Ω/2 pF output load.
6. TARDR is given for ECL 50Ω/2 pF output load.
7. TSRDR is given for ECL 50Ω/2 pF output load. It is minimum value since RstSync clock is synchronized with Clkln clock.
8. TRDR and TFDR are given for ECL 50Ω/2 pF output load.
9. THBIST depends on the configuration of the DMUX. There must be enough Clkln clock cycles to have all the 512 codes,

(see different Timing Diagrams).

1. With transmission line (ZO = 50Ω) and output load R = 50Ω; C = 2 pF .
2. With transmission line (ZO = 50Ω) and output load R = 50Ω; C = 2 pF .

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Figure 10. Input Clock Figure 11. ADC Delay Adjust Timing Diagram

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is used to obtain good setup and hold times between Clkln and the input data. Figure 14. Start with Asynchronous Reset, 1:4 Ratio, DR Mode gram does not change with the opposite phase of Clkln. Figure 15. Start with Asynchronous Reset, 1:4 Ratio, DR/2 Mode

ports but the last data (d1 to d8) is latched until the next selection of Port H. d9 to d16 are lost. The synchronous Reset ensures a re-synchronization of the port selection. Figure 16. Synchronous Reset, 1:8 Ratio, DR Mode port selection. The de-synchronization event happens after the selection of Port D. ports but the last data (d1 to d4) is latched until the next selection of Port H. d5 to d8 are lost. The synchronous Reset ensures a re-synchronization of the port selection.

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Figure 17. Synchronous Reset, 1:4 Ratio, DR Mode selection. The de-synchronization event happens after the selection of Port D. ports but the last data (d1 to d8) is latched until the next selection of Port H. d9 to d16 are lost. The synchronous Reset ensures a re-synchronization of the port selection. Figure 18. Synchronous Reset, 1:8 ratio, DR/2 Mode selection. The de-synchronization event happens after the selection of Port D. ports but the last data (d1 to d4) is latched until the next selection of Port H. d5 to d8 are lost. The synchronous Reset ensures a re-synchronization of the port selection.

Figure 19. Synchronous Reset, 1:4 ratio, DR/2 Mode the second one. This data is output from the DMUX through port B.

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Notes: 1. The level 1 and 2 tests are performed at 50 MHz.

1. Only MIN and MAX values are guaranteed (typical values are issuing from characterization

Table 6. Explanation of Test Levels 3 Sample tested only at specified temperatures.

4 Parameter is guaranteed by design and characterization testing (thermal steady-state

conditions at specified temperature). 5 Parameter is a typical value only.

Table 7. TS81102G0 Pin Description Digital Inputs I[0…9] Differential ECL Data input. On-chip 100Ω differential termination resistor. Clkln Differential ECL Clock input (Data Ready ADC). On-chip 100Ω differential termination resistor. SwiAdj. 50Ω termination possible. Data ready for channel A to H. SwiAdj. 50Ω termination possible. RefA → RefH Adjustable Single Reference voltage for output channels A to H. Control Signals ClklnType TTL DataReady or Dataready/2: logic 1: Data Ready. Bist TTL Reset and Switch of built-in Self Test (BIST): logic 0: BIST active. SwiAdj 0V ± 0.5V Swing fine adjustment of output buffers. Diode Analog Diode for chip temperature measurement. NbBit TTL Number of bit 8 or 10: logic 1: 10-bit. Synchronization AsyncReset TTL Asynchronous reset: logic 1: reset on. SyncReset Differential ECL Synchronous reset: active on rising edge. ADCDelAdjln Differential ECL Stand-alone delay adjust input for ADC. Differential termination of 100Ω inside the buffer. Stand-alone delay adjust output for ADC. Power Supplies GND Ground 0V Common ground. EE Power -5V Digital negative power supply. Common mode adjustment of output buffers. VCC Power +5V Digital positive power supply.

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2105C–BDC–11/03 Row Col Name Row Col Name Row Col Name Row Col Name A A A A A A A A A A A A A A A A A A A B B B B B B B B B B B B B B B B B B B C C C C C C C C C C C C C C C C C C C D D D NC REFA DEMUXDELADJCTRL RSTSYNCB NC REFC ASYNCRESET DEMUXDELADJCTRLB RSTSYNC REFE VEE VPLUSDOUT VPLUSDOUT VPLUSDOUT VPLUSDOUT VEE VPLUSDOUT VEE VPLUSDOUT VEE VPLUSDOUT VPLUSDOUT VPLUSDOUT GND GND GND DIODE VEE D D D D D D D D D D D D D D D D E E E E E E E E F F F F F F F F G G G G G G G G H H H H H H H H J J J J J J J J K K K K VEE VEE VPLUSDOUT VPLUSDOUT VEE VPLUSDOUT VEE VPLUSDOUT VEE VPLUSDOUT GND VCC VCC GND I0B VPLUSDOUT VEE VEE VEE I1B GND GND GND GND I2B VEE VEE VEE VEE I3B GND GND GND GND CLKINB CLKIN DR REFG VPLUSDOUT VCC VEE VEE I4B SWIADJ DRB VEE VEE K K K K L L L L L L L L M M M M M M M M N N N N N N N N P P P P P P P P R R R R R R R R T T T T T T T T T T T T T T T T VEE GND I5B RATIOSEL VPLUSDOUT VPLUSDOUT VEE VEE I6B GND GND GND GND I7B VPLUSDOUT VPLUSDOUT VEE VEE I8B GND GND GND GND I9B VPLUSDOUT VPLUSDOUT VEE GND ADCDELADJOUT ADCDELADJOUTB REFH VEE VEE VEE VPLUSDOUT VPLUSDOUT VEE VPLUSDOUT VEE VPLUSDOUT VEE VPLUSDOUT VPLUSDOUT GND VEE T T T U U U U U U U U U U U U U U U U U U U V V V V V V V V V V V V V V V V V V V W W W W W W W W W W W W W W W W W W W VEE ADCDELADJIN ADCDELADJINB VEE VPLUSDOUT VPLUSDOUT VPLUSDOUT VPLUSDOUT VEE VPLUSDOUT VEE VPLUSDOUT VEE VPLUSDOUT VPLUSDOUT VPLUSDOUT GND GND GND GND REFD BIST CLKINTYPE ADCDELADJCTRL NC REFF REFB NBBIT ADCDELADJCTRLB NC

Figure 20. TBGA 240 Package: Bottom View

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Figure 21. Package Dimension – 240 Tape Ball Grid Array Notes: 1. All dimensions are in millimeters.

1. "e" represents the basic solder ball grid pitch.
2. "M" represents the basic solder ball matrix size,

of balls after depopulating.

1. Package surface shall be black oxide.
2. Cavity depth various with die thickness.
3. Substrate material base is copper.

10 Bilateral tolerance zone is applied to each side of

5 Dimension "aaa" is measured parallel to primary

6 Primary datum - C - and seatin plane are defined by

the spherical crowns of the solder balls.

through the package body, through balls and through board copper). at 13 to 20°C/W (depending on the board used). The worst value 20°C/W is given for a 1-layer board (13°C for a 4-layer board). with a board. This thermal resistance is estimated to be 4.8°C/W max. Figure 22. Thermal Resistance from Junction to Bottom of Balls

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Figure 23. Temperature Diode Characteristic This device is sensitive to moisture (MSL3 according to the JEDEC standard). The shelf life in a sealed bag is 12 months at < 40°C and < 90% relative humidity (RH).  24 hours at 125°C ± 5°C for high-temperature device containers.

The following diagram depicts a detailed cross section of the DMUX TBGA package. Figure 24. TBGA 240: 1/2 Cross Section spreader, so the copper heat spreader is at -5V. It is necessary to use a heat sink tied to the copper heat speader. one should use adequate low Rth electrical isolation.

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TSEV8388G and TSEV83102G0 ADC evaluation boards. Figure 25. TSEV81102G0 DMUX Evaluation Boards Please refer to the "ADC and DMUX Application Note" for more information.

The DMUX inputs configuration has been optimized to be connected to the TS8388B ADC. crossing the lines (see Table 8). 4-pin shift to make the D0 pin match either the I7 or I0 pin of the DMUX evaluation board. Table 8. ADC to DMUX Connections

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2105C–BDC–11/03 TSEV81102G0TP: Device Evaluation Board General The TSEV81102G0TP DMUX Evaluation Board (EB) is designed to simplify the characteriza- tion and the evaluation of the TS81102G0 device (2 Gsps DMUX). The DMUX EB enables testing of all the DMUX functions: Synchronous and Asynchronous reset functions, selection of the DMUX ratio (1:4 or 1:8), selection of the number of bits (8 or 10), output data common mode and swing adjustment, die junction temperature measurements over military tempera- ture range, etc. The DMUX EB has been designed to enable easy connection to Atme’s ADC Evaluation Boards (such as TSEV8388BGL or TSEV83102G0BGL) for an extended functionality evalua- tion (ADC and DMUX multi-channel applications). The DMUX EB comes fully assembled and tested, with a TS81102G0 device implemented on the board and a heat sink assembled on the device.

2105C–BDC–11/03 Ordering Information Datasheet Status

Applications

These products are not designed for use in life-support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Atmel customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Atmel for any damages resulting from such improper use or sale. Table 9. Ordering Information Table 10. Datasheet Status customer and application validation. periods may affect device reliability.

Application Information

Where application information is given, it is advisory and does not form part of the specification.

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and then when used in the DR/2 mode. Fs/4N in 1:4 ratio, where N is an integer. applications using 2 synchronized DMUXs. Minimum duration of the reset signal at a high level to be taken into account by the DMUX. Operation in DR Mode In DR mode, the DMUX input clock can run at up to 2 GHz in 1:8 ratio or 1 GHz in 1:4 ratio. Both cases are described in the following timing diagrams. Figure 26. Synchronous Reset Operation in DR Mode, 1:4 ratio, 1GHz (Full Speed) – Principle of Operation

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ratio, since the DR/2 clock from the ADC is half the sampling frequency. Both cases are described in the following timing diagrams. Figure 30. Synchronous Reset Operation in DR/2 Mode, 1:4 ratio, 500MHz (Full Speed) – Principle of Operation Figure 31. Synchronous Reset Operation in DR/2 Mode, 1:4 ratio, 500 MHz (Full-speed) – Timings Note: The clock edge to which the reset applies is the one identified by the arrow. represented clock rising edge (first clock rising edge of the schematic, on the left of the edge represented with the arrow). Figure 32. Synchronous Reset Operation in DR/2 Mode, 1:8 ratio, 1GHz (Full Speed) – Principle of Operation

Figure 33. Synchronous Reset Operation in DR/2 Mode, 1:8 ratio, 1GHz (Full-speed) – Timings Note: The clock edge to which the reset applies is the one identified by the arrow. (not represented, on the right of the edge represented with the arrow).

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