TSC80251G2D TEMIC | Alldatasheet

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Rev. A - May 7, 1999 1 TSC80251G2D 8/16-bit Microcontroller with Serial Communication Interfaces 1. Description The TSC80251G2D products are derivatives of the TEMIC Microcontroller family based on the 8/16-bit C251 Architecture. This family of products is tailored to 8/16-bit microcontroller applications requiring an increased instruction throughput, a reduced operating frequency or a larger addressable memory space. The architecture can provide a significant code size reduction when compiling C programs while fully preserving the legacy of C51 assembly routines. The TSC80251G2D derivatives are pin and software compatible with standard 80C51/Fx/Rx/Rx+ with extended on-chip data memory (1 Kbyte RAM) and up to 256 Kbytes of external code and data. Additionally, the TSC83251G2D and TSC87251G2D provide on-chip code memory: 32 Kbytes ROM and 32 Kbytes EPROM/ OTPROM respectively. They provide transparent enhancements to Intel’s 8xC251Sx family with an additional Synchronous Serial Link Controller (SSLC supporting I 2C, µWire and SPI protocols), a Keyboard interrupt interface, a dedicated Baud Rate Generator for UART, and Power Management features. TSC80251G2D derivatives are optimized for speed and for low power consumption on a wide voltage range. Note: This Datasheet provides the technical description of the TSC80251G2D derivatives. For further information on the device usage, please request the TSC80251 Programmer’s Guide and the TSC80251G1D Design Guide. 2. Typical Applications

  • ISDN Terminals
  • High-Speed Modems
  • PABX (SOHO)
  • Line Cards
  • DVD ROM and Players
  • Printers
  • Plotters
  • Scanners
  • Banking Machines
  • Barcode Readers
  • Smart Cards Readers
  • High-End Digital Monitors
  • High-End Joysticks

2 Rev. A - May 7, 1999 TSC80251G2D 3. Features

  • Pin and Software Compatibility with Standard 80C51 Products and 80C51Fx/Rx/Rx+
  • Plug-In Replacement of Intel’s 8xC251Sx
  • C251 core: Intel’s MCS® 251 D-step Compliance
  • 40-byte register file
  • Registers accessible as Bytes, Words or Dwords
  • Three-stage instruction pipeline
  • 16-bit internal code fetch
  • Enriched C51 Instruction Set
  • 16-bit and 32-bit ALU
  • Compare and conditional jump instructions
  • Expanded set of move instructions
  • Linear Addressing
  • 1 Kbyte of On-Chip RAM
  • External Memory Space (Code/Data) Programmable from 64 Kbytes to 256 Kbytes
  • TSC87251G2D: 32 Kbytes of On-Chip EPROM/ OTPROM
  • SINGLE PULSE Programming Algorithm
  • TSC83251G2D: 32 Kbytes of On-Chip Masked ROM
  • TSC80251G2D: ROMless Version
  • Four 8-bit Parallel I/O Ports (Ports 0, 1, 2 and 3 of the standard 80C51)
  • Serial I/O Port: full duplex UART (80C51 compatible) with independent Baud Rate Generator
  • SSLC: Synchronous Serial Link Controller
  • I2C multi-master protocol
  • µ Wire and SPI master and slave protocols
  • Three 16-bit Timers/Counters (Timers 0, 1 and 2 of the standard 80C51)
  • EWC: Event and Waveform Controller
  • Compatible with Intel’s Programmable Counter Array (PCA)
  • Common 16-bit timer/counter reference with four possible clock sources (Fosc/4, Fosc/12, Timer 1 and external input)
  • Five modules, each with four programmable modes: - 16-bit software timer/counter - 16-bit timer/counter capture input and software pulse measurement - High-speed output and 16-bit software pulse width modulation (PWM) - 8-bit hardware PWM without overhead
  • 16-bit watchdog timer/counter capability
  • Secure 14-bit Hardware Watchdog Timer
  • Power Management
  • Power-On reset (integrated on the chip)
  • Power-Off flag (cold and warm resets)
  • Software programmable system clock
  • Idle mode
  • Power-Down mode
  • Keyboard Interrupt Interface on Port 1
  • Non Maskable Interrupt Input (NMI)
  • Real-Time Wait States Inputs (WAIT#/AWAIT#)
  • ONCE mode and full speed Real-Time In-Circuit Emulation support (Third Party Vendors)
  • High Speed Versions:
  • 4.5 to 5.5 V
  • 16 MHz and 24 MHz
  • Typical operating current: 35 mA @ 24 MHz 24 mA @ 16 MHz
  • Typical power-down current: 2µA
  • Low Voltage Version:
  • 2.7 to 5.5 V
  • 16 MHz
  • Typical operating current: 11 mA @ 3V
  • Typical power-down current: 1µA
  • Temperature Ranges:
  • Commercial (0°Ct o+ 7 0°C)
  • Industrial (-40°Ct o+ 8 5°C)
  • Option: extended range (-55°C to +125°C)
  • Packages:
  • PDIL 40, PLCC 44 and VQFP 44
  • CDIL 40 and CQPJ 44 with window
  • Options: known good dice and ceramic packages

Figure 1. TSC80251G2D Block Diagram

1 Kbyte

32 Kbytes

5.1 Pinout

Figure 2. TSC80251G2D 40-pin DIP package Figure 3. TSC80251G2D 44-pin PLCC Package

Figure 4. TSC80251G2D 44-pin VQFP Package Table 1. TSC80251G2D Pin Assignment

5.2 Signals

Table 2. Product NameSignal Descriptions on the values of bits RD0 and RD1 in UCONFIG0 byte (see Table 13, Page 15). on the values of bits RD0 and RD1 in UCONFIG0 byte (see Table 13, Page 15). Upper address lines for the external bus. Multiplexed lower address lines and data for the external memory. address from address/data bus. When this pin is active (low level), the memory cycle is stretched until it becomes high. Not available on DIP package. EA# directs program memory accesses to on-chip or off-chip code memory. For EA#= 0, all program memory accesses are off-chip. ROM; otherwise the access is off-chip. The value of EA# is latched at reset. For devices without ROM on-chip, EA# must be strapped to ground. ECI is the external clock input to the 16-bit PCA timer. slave mode, MISO outputs data to the master controller. slave mode, MOSI receives data from the master controller. are set by a low level on INT1#/INT0#. Holding this pin high for 24 oscillator periods triggers an interrupt. Not available on DIP package.

Rev. A - May 7, 1999 7 TSC80251G2D P1.0:7 I/O Port 1 P1 is an 8-bit bidirectional I/O port with internal pull-ups. P1 provides interrupt capability for a keyboard interface. P2.0:7 I/O Port 2 P2 is an 8-bit bidirectional I/O port with internal pull-ups. A15:8 P3.0:7 I/O Port 3 P3 is an 8-bit bidirectional I/O port with internal pull-ups. PROG# I Programming Pulse input The programming pulse is applied to this input for programming the on-chip EPROM/ OTPROM. PSEN# O Program Store Enable/Read signal output PSEN# is asserted for a memory address range that depends on bits RD0 and RD1 in UCONFIG0 byte (see Table 13, Page 15). RD# O Read or 17 th Address Bit (A16) Read signal output to external data memory depending on the values of bits RD0 and RD1 in UCONFIG0 byte (see Table 13, Page 15). P3.7 RST I Reset input to the chip Holding this pin high for 64 oscillator periods while the oscillator is running resets the device. The Port pins are driven to their reset conditions when a voltage greater than V IH1 is applied, whether or not the oscillator is running. This pin has an internal pull-down resistor which allows the device to be reset by connecting a capacitor between this pin and VDD. Asserting RST when the chip is in Idle mode or Power-Down mode returns the chip to normal operation. RXD I/O Receive Serial Data RXD sends and receives data in serial I/O mode 0 and receives data in serial I/O modes 1, 2 and 3. P3.0 SCL I/O I 2C Serial Clock When I 2C controller is in master mode, SCL outputs the serial clock to slave peripherals. When I2C controller is in slave mode, SCL receives clock from the master controller. P1.6 SCK I/O SPI Serial Clock When SPI is in master mode, SCK outputs clock to the slave peripheral. When SPI is in slave mode, SCK receives clock from the master controller. P1.6 SDA I/O I 2C Serial Data SDA is the bidirectional I2C data line. P1.7 SS# I SPI Slave Select Input When in Slave mode, SS# enables the slave mode. P1.4 T1:0 I/O Timer 1:0 External Clock Inputs When timer 1:0 operates as a counter, a falling edge on the T1:0 pin increments the count. T2 I/O Timer 2 Clock Input/Output For the timer 2 capture mode, T2 is the external clock input. For the Timer 2 clock-out mode, T2 is the clock output. P1.0 T2EX I Timer 2 External Input In timer 2 capture mode, a falling edge initiates a capture of the timer 2 registers. In auto- reload mode, a falling edge causes the timer 2 register to be reloaded. In the up-down counter mode, this signal determines the count direction: 1= up, 0= down. P1.1 TXD O Transmit Serial Data TXD outputs the shift clock in serial I/O mode 0 and transmits data in serial I/O modes 1, 2 and 3. P3.1 VDD PWR Digital Supply Voltage Connect this pin to +5V or +3V supply voltage. VPP I Programming Supply Voltage The programming supply voltage is applied to this input for programming the on-chip EPROM/ OTPROM. Signal Name Type Description Alternate Function

8 Rev. A - May 7, 1999 TSC80251G2D Note: 1. The description of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the Non-Page mode chip configuration. If the chip is configured in Page mode operation, port 0 carries the lower address bits (A7:0) while port 2 carries the upper address bits (A15:8) and the data (D7:0). VSS GND Circuit Ground Connect this pin to ground. VSS1 GND Secondary Ground 1 This ground is provided to reduce ground bounce and improve power supply bypassing. Connection of this pin to ground is recommended. However, when using the TSC80251G2D as a pin-for-pin replacement for a 8xC51 product, VSS1 can be unconnected without loss of compatibility. Not available on DIP package. VSS2 GND Secondary Ground 2 This ground is provided to reduce ground bounce and improve power supply bypassing. Connection of this pin to ground is recommended. However, when using the TSC80251G2D as a pin-for-pin replacement for a 8xC51 product, VSS2 can be unconnected without loss of compatibility. Not available on DIP package. WAIT# I Real-time Synchronous Wait States Input The real-time WAIT# input is enabled by setting RTWE bit in WCON (S:A7h). During bus cycles, the external memory system can signal ‘system ready’ to the microcontroller in real time by controlling the WAIT# input signal. P1.6 WCLK O Wait Clock Output The real-time WCLK output is enabled by setting RTWCE bit in WCON (S:A7h). When enabled, the WCLK output produces a square wave signal with a period of one half the oscillator frequency. P1.7 WR# O Write Write signal output to external memory. P3.6 XTAL1 I Input to the on-chip inverting oscillator amplifier To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, its output is connected to this pin. XTAL1 is the clock source for internal timing. XTAL2 O Output of the on-chip inverting oscillator amplifier To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, leave XTAL2 unconnected. Signal Name Type Description Alternate Function

  • On-chip ROM program/code memory (not present in ROMless devices)
  • On-chip RAM data memory
  • Special Function Registers (SFRs)
  • Configuration array

6.1 Program/Code Memory

internal program/code memory is not used and all the accesses are directed to the external memory. program/code memory and EA# must be tied to a low level. Figure 5. Program/Code Memory Mapping

  1. If the program executes exclusively from on-chip code memory (not from external memory), beware of executing code from the upper eight

8 bytes does not affect Ports 0 and 2.

  1. When PC reaches the end of segment FF:, it loops to the reset address FF:0000h (for compatibility with the C51 Architecture). When PC

segment 01:, it loops to the beginning of segment 00: (this prevents from its going into the reserved area).

32 KbytesEA#= 0 EA#= 1

64 Kbytes

128 Kbytes

6.2 Data Memory

addressable. This on-chip RAM is not accessible through the program/code memory space. not accessible through the region 00:. Figure 6. Data Memory Mapping

6.3 Special Function Registers

(Figure 6). The relative addresses within S: of these SFRs are provided together with their reset values in Table 12.

16 Kbytes

Table 3. C251 Core SFRs

  1. These SFRs can also be accessed by their corresponding registers in the register file.

Table 4. I/O Port SFRs Table 5. Timers SFRs Table 6. Serial I/O Port SFRs Table 7. SSLC SFRs

Table 8. Event Waveform Control SFRs Table 9. System Management SFRs Table 10. Interrupt SFRs Table 11. Keyboard Interface SFRs

Table 12. SFR Addresses and Reset Values

  1. These registers are described in the TSC80251 Programmer’s Guide (C251 core registers).

2C and SPI modes, SSCON is splitted in two separate registers. SSCON reset value is 0000 0000 in I2C mode and 0000 0100 in SPI mode.

  1. In read and write modes, SSCS is splitted in two separate registers. SSCS reset value is 1111 1000 in read mode and 0000 0000 in write mode.

6.4 Configuration Bytes

  • external memory interface (Page mode, address bits, programmed wait states and the address range for RD#, WR#, and PSEN#)
  • source mode/binary mode opcodes
  • selection of bytes stored on the stack by an interrupt
  • mapping of the upper portion of on-chip code memory to region 00: Two user configuration bytes UCONFIG0 (see Figure 7) and UCONFIG1 (see Figure 8) provide the information. When EA# is tied to a low level, the configuration bytes are fetched from the external address space. The TSC80251G2D derivatives reserve the top eight bytes of the memory address space (FF:FFF8h-FF:FFFFh) for an external 8-byte configuration array. Only two bytes are actually used: UCONFIG0 at FF:FFF8h and UCONFIG1 at FF:FFF9h. For the mask ROM devices, configuration information is stored in on-chip memory (see ROM Verifying). When EA# is tied to a high level, the configuration information is retrieved from the on-chip memory instead of the external address space and there is no restriction in the usage of the external memory. UCONFIG0 Configuration Byte 0Notes: 1. UCONFIG0 is fetched twice so it can be properly read both in Page or Non-Page modes. If P2.1 is cleared during the first data fetch, a Page mode configuration is used, otherwise the subsequent fetches are performed in Non-Page mode. 2. This selection provides compatibility with the standard 80C51 hardware which is multiplexing the address LSB and the data on Port 0.

Figure 7. Configuration Byte 0 Set this bit when writing to UCONFIG0.

6 WSA1#

5 WSA0#

4 XALE#

Set to minimize the duration of the ALE pulse to 1·TOSC .

3 RD1 Memory Signal Select bits

1 PAGE#

Clear to select the faster Page mode with A15:8/D7:0 on Port 2 and A7:0 on Port 0. Set to select the non-Page mode(2) with A15:8 on Port 2 and A7:0/D7:0 on Port 0.

0 SRC

Clear to select the binary mode. Set to select the source mode.

  1. The CSIZE is only available on EPROM/OTPROM products.
  2. Two or four bytes are transparently popped according to INTR when using the RETI instruction. INTR must be set if interrupts are used

with code executing outside region FF:.

  1. Use only for Step A compatibility; set this bit when WSB1:0# are used.

Figure 8. Configuration Byte 1 Table 13. Address Ranges and Usage of RD#, WR# and PSEN# Signals

  1. This selection provides compatibility with the standard 80C51 hardware which has separate external memory spaces for data and code.

Clear to select 16 Kbytes of on-chip code memory (TSC87251G1D product). Set to select 32 Kbytes of on-chip code memory (TSC87251G2D product). Set this bit when writing to UCONFIG1. Set this bit when writing to UCONFIG1. Set this bit when writing to UCONFIG1.

4 INTR

Clear so that the interrupts push two bytes onto the stack (the two lower bytes of the PC register).

3 WSB

Clear to generate one wait state for memory region 01:. Set for no wait states for memory region 01:.

2 WSB1#

1 WSB0#

0 EMAP#

space (at 00:C000h-00:FFFFh).

  • Instruction Fetch
  • Instruction Execution Table 20 to Table 34 assume code executing from on-chip memory, then the CPU is fetching 16-bit at a time and this is never limiting the execution speed. If the code is fetched from external memory, a pre-fetch queue will store instructions ahead of execution to optimize the memory bandwidth usage when slower instructions are executed. However, the effective speed may be limited depending on the average size of instructions (for the considered section of the program flow). The maximum average instruction throughput is provided by Table 14 depending on the external memory configuration (from Page Mode to Non-Page Mode and the maximum number of wait states). If the average size of instructions is not an integer, the maximum effective throughput is found by pondering the number of states for the neighbor integer values.

Table 14. Minimum Number of States per Instruction for given Average Sizes providing a fair estimation of the execution speed but only the actual code execution can provide the final value.

7.1 Notation for Instruction Operands

Table 15 to Table 19 provide notation for Instruction Operands. Table 15. Notation for Direct Addressing Table 16. Notation for Immediate Addressing

0 Wait State 1 Wait State 2 Wait States 3 Wait States 4 Wait States

Table 17. Notation for Bit Addressing Table 18. Notation for Destination in Control Instructions Table 19. Notation for Register Operands WR30, is the target address for jump instructions.

7.2 Size and Execution Time for Instruction Families

Table 20. Summary of Add and Subtract Instructions

  1. A shaded cell denotes an instruction in the C51 Architecture.
  2. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
  3. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states).
  4. If this instruction addresses external memory location, add 2(N+2) to the number of states (N: number of wait states).

Table 21. Summary of Increment and Decrement Instructions

  1. A shaded cell denotes an instruction in the C51 Architecture.
  2. If this instruction addresses an I/O Port (Px, x= 0-3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR.

Table 22. Summary of Compare Instructions

  1. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
  2. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states).
  3. If this instruction addresses external memory location, add 2(N+2) to the number of states (N: number of wait states).

Table 23. Summary of Logical Instructions (1/2)

  1. Logical instructions that affect a bit are in Table 29.
  2. A shaded cell denotes an instruction in the C51 Architecture.
  3. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
  4. If this instruction addresses an I/O Port (Px, x= 0-3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR.
  5. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states).
  6. If this instruction addresses external memory location, add 2(N+2) to the number of states (N: number of wait states).

Table 24. Summary of Logical Instructions (2/2)

  1. A shaded cell denotes an instruction in the C51 Architecture.

Table 25. Summary of Multiply, Divide and Decimal-adjust Instructions

  1. A shaded cell denotes an instruction in the C51 Architecture.

Table 26. Summary of Move Instructions (1/3)

  1. A shaded cell denotes an instruction in the C51 Architecture.
  2. Extended memory addressed is in the region specified by DPXL (reset value= 01h).
  3. If this instruction addresses external memory location, add N+1 to the number of states (N: number of wait states).
  4. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states).

Table 27. Summary of Move Instructions (2/3)

  1. Instructions that move bits are in Table 29.
  2. Move instructions from the C51 Architecture.
  3. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
  4. Apply note 3 for each dir8 operand.

Table 28. Summary of Move Instructions (3/3)

  1. Instructions that move bits are in Table 29.
  2. Move instructions unique to the C251 Architecture.
  3. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
  4. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states).
  5. If this instruction addresses external memory location, add 2(N+1) to the number of states (N: number of wait states).
  6. If this instruction addresses external memory location, add 4(N+2) to the number of states (N: number of wait states).

Table 29. Summary of Bit Instructions

  1. A shaded cell denotes an instruction in the C51 Architecture.
  2. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
  3. If this instruction addresses an I/O Port (Px, x= 0-3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR.

Table 30. Summary of Exchange, Push and Pop Instructions

  1. A shaded cell denotes an instruction in the C51 Architecture.
  2. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
  3. If this instruction addresses an I/O Port (Px, x= 0-3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR.

Table 31. Summary of Conditional Jump Instructions (1/2)

  1. A shaded cell denotes an instruction in the C51 Architecture.
  2. States are given as jump not-taken/taken.
  3. In internal execution only, add 1 to the number of states of the ‘jump taken’ if the destination address is internal and odd.

Table 32. Summary of Conditional Jump Instructions (2/2)

  1. A shaded cell denotes an instruction in the C51 Architecture.
  2. States are given as jump not-taken/taken.
  3. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
  4. If this instruction addresses an I/O Port (Px, x= 0-3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR.
  5. If this instruction addresses an I/O Port (Px, x= 0-3), add 3 to the number of states. Add 5 if it addresses a Peripheral SFR.
  6. In internal execution only, add 1 to the number of states of the ‘jump taken’ if the destination address is internal and odd.

Table 33. Summary of unconditional Jump Instructions

  1. A shaded cell denotes an instruction in the C51 Architecture.
  2. In internal execution only, add 1 to the number of states if the destination address is internal and odd.
  3. Add 2 to the number of states if the destination address is external.
  4. Add 3 to the number of states if the destination address is external.

Table 34. Summary of Call and Return Instructions

  1. A shaded cell denotes an instruction in the C51 Architecture.
  2. In internal execution only, add 1 to the number of states if the destination/return address is internal and odd.
  3. Add 2 to the number of states if the destination address is external.
  4. Add 5 to the number of states if INTR= 1.

Rev. A - May 7, 1999 28 TSC80251G2D 8. Programming and Verifying Non-Volatile Memory

8.1 Internal Features

The internal non-volatile memory of the TSC80251G2D derivatives contains five different areas:

  • Code Memory
  • Configuration Bytes
  • Lock Bits
  • Encryption Array
  • Signature Bytes

8.1.1 EPROM/OTPROM Devices

All the internal non-volatile memory but the Signature Bytes of the TSC87251G2D products is made of EPROM cells. The Signature Bytes of the TSC87251G2D products are made of Mask ROM. The TSC87251G2D products are programmed and verified in the same manner as TEMIC ’s TSC87251G1A, using a SINGLE-PULSE algorithm, which programs at VPP= 12.75V using only one 100µs pulse per byte. This results in a programming time of less than 10 seconds for the 32 Kbytes on-chip code memory. The EPROM of the TSC87251G2D products in Window package is erasable by Ultra-Violet radiation(1) (UV). UV erasure set all the EPROM memory cells to one and allows a reprogramming. The quartz window must be covered with an opaque label (2)when the device is in operation. This is not so much to protect the EPROM array from inadvertent erasure, as to protect the RAM and other on-chip logic. Allowing light to impinge on the silicon die during device operation may cause a logical malfunction. The TSC87251G2D products in plastic packages are One Time Programmable (OTP). Then an EPROM cell cannot be reset by UV once programmed to zero. Notes: 1. The recommended erasure procedure is exposure to ultra-violet light (at 2537 Å) to an integrated dose of at least 20 W-sec/cm2. Exposing the EPROM to an ultra-violet lamp of 12000µW/cm 2 rating for 30 minutes should be sufficient. 2. Erasure of the EPROM begins to occur when the chip is exposed to light wavelength shorter than 4000 Å. Since sunlight and fluorescent light have wavelength in this range, exposure to these light sources over an extended time (1 week in sunlight or 3 years in room-level fluorescent lighting) could cause inadvertent erasure.

8.1.2 Mask ROM Devices

All the internal non-volatile memory of TSC83251G2D products is made of Mask ROM cells. They can only be verified by the user, using the same algorithm as the EPROM/OTPROM devices.

8.1.3 ROMless Devices

The TSC80251G2D products do not include on-chip Configuration Bytes, Code Memory and Encryption Array. They only include Signature Bytes made of Mask ROM cells which can be read using the same algorithm as the EPROM/OTPROM devices.

8.2 Security Features

In some microcontrollers applications, it is desirable that the user’s program code be secured from unauthorized access. The TSC83251G2D and TSC87251G2D offer two kinds of protection for program code stored in the on- chip array:

  • Program code in the on-chip Code Memory is encrypted when read out for verification if the Encryption Array is programmed.
  • A three-level lock bit system restricts external access to the on-chip code memory.

8.2.1 Lock Bit System

TSC83251G2D products implement only the first level of security. Level 0 is the level of an erased part and does not enable any security features. Bytes and the Lock Bits. It is never possible to verify the Encryption Array. Level 3 locks the external execution. Table 35. Lock Bits Programming

  1. Returns encrypted data if Encryption Array is programmed.
  2. Returns non encrypted data.
  3. x means don’t care. Level 2 always enables level 1, and level 3 always enables levels 1 and 2.

The security level may be verified according to Table 36. Table 36. Lock Bits Verifying

8.2.2 Encryption Array

To preserve the secrecy of the encryption key byte sequence, the Encryption Array can not be verified.

  1. When a MOVC instruction is executed, the content of the ROM is not encrypted. In order to fully protect the user program code, the lock

bit level 1 (see Table 35) must always be set when encryption is used.

  1. If the encryption feature is implemented, the portion of the on-chip code memory that does not contain program code should be filled with

“random” byte values to prevent the encryption key sequence from being revealed.

8.3 Signature Bytes

Table 37. Signature Bytes (Electronic ID)

8.4 Programming Algorithm

  • The chip has to be put under reset and maintained in this state until the completion of the programming sequence.
  • PSEN# and the other control signals (ALE and Port 0) have to be set to a high level.
  • Then PSEN# has to be to forced to a low level after two clock cycles or more and it has to be maintained in this state until the completion of the programming sequence (see below).
  • The voltage on the EA# pin must be set to VDD .
  • The programming mode is selected according to the code applied on Port 0 (see Table 38). It has to be applied until the completion of this programming operation.
  • The programming address is applied on Ports 1 and 3 which are respectively the Most Significant Byte (MSB) and the Least Significant Byte (LSB) of the address.
  • The programming data are applied on Port 2.
  • The EPROM Programming is done by raising the voltage on the EA# pin to VPP, then by generating a low level pulse on ALE/PROG# pin.
  • The voltage on the EA# pin must be lowered to VDD before completing the programming operation.
  • It is possible to alternate programming and verifying operation (See Paragraph 8.5). Please make sure the voltage on the EA# pin has actually been lowered to V DD before performing the verifying operation.
  • PSEN# and the other control signals have to be released to complete a sequence of programming operations or a sequence of programming and verifying operations. Signature Address Signature Data Vendor T EMIC 30h 58h Architecture C251 31h 40h Memory

32 Kbytes EPROM or OTPROM

32 Kbytes MaskROM or ROMless 77h

Figure 9. Setup for Programming Table 38. Programming Modes

  1. Signature Bytes are not user-programmable.
  2. The ALE/PROG# pulse waveform is shown in Figure 31 page 54.

8.5 Verify Algorithm

  • The chip has to be put under reset and maintained in this state until the completion of the verifying sequence.
  • PSEN# and the other control signals (ALE and Port 0) have to be set to a high level.
  • Then PSEN# has to be to forced to a low level after two clock cycles or more and it has to be maintained in this state until the completion of the verifying sequence (see below).
  • The voltage on the EA# pin must be set to VDD and ALE must be set to a high level.
  • The Verifying Mode is selected according to the code applied on Port 0. It has to be applied until the completion of this verifying operation.
  • The verifying address is applied on Ports 1 and 3 which are respectively the MSB and the LSB of the address.
  • Then device is driving the data on Port 2.
  • It is possible to alternate programming and verification operation (see Paragraph 8.4). Please make sure the voltage on the EA# pin has actually been lowered to V DD before performing the verifying operation.
  • PSEN# and the other control signals have to be released to complete a sequence of verifying operations or a sequence of programming and verifying operations. ROM Area (1) RST EA#/VPP PSEN# ALE/PROG# (2) P0 P2 P1(MSB) P3(LSB) On-chip Code Memory 1 V PP 0 1 Pulse 68h Data 16-bit Address 0000h-7FFFh (32 Kbytes) Configuration Bytes 1 V PP 0 1 Pulse 69h Data CONFIG0: FFF8h CONFIG1: FFF9h Lock Bits 1 V PP 0 1 Pulse 6Bh X LB0: 0001h LB1: 0002h LB2: 0003h Encryption Array 1 V PP 0 1 Pulse 6Ch Data 0000h-007Fh VDD PSEN# ALE/PROG# EA#/VPP XTAL1 VDD 4 to 12 MHz RST V PP 100 µs pulses VSS/VSS1/VSS2 Mode VDD A[7:0] A[14:8] Data P0[7:0] P3[7:0] P1[7:0] P2[7:0] TSC87251G2D

Table 39. Verifying Modes

  1. To preserve the secrecy of on-chip code memory when encrypted, the Encryption Array can not be verified.

Figure 10. Setup for Verifying

  1. Absolute Maximum Rating and Operating Conditions

9.1 Absolute Maximum Rating

Table 40. Absolute Maximum Ratings

9.2 Operating Conditions

Table 41. Operating Conditions the “operating conditions” is not recommended and extended exposure beyond the “Operating Conditions” may affect device reliability.

  • Voltage on any other Pin to VSS.... -65 to +150°C -0.5 to +6.5 V 15 mA 1.5 W
  • Ambient Temperature Under Bias
  • V DD 0t o+ 7 0°C -40 to +85°C 4.5 to 5.5 V 2.7 to 5.5 V
  1. DC Characteristics - Commercial & Industrial

10.1 DC Characteristics: High Speed versions - Commercial & Industrial

Table 42. DC Characteristics; VDD = 4.5 to 5.5 V, TA = -40 to +85°C

  1. Under steady-state (non-transient) conditions, IOL must be externally limited as follows:
  2. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level outputs of ALE and Ports 1, 2, and
  3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins change from high to low. In

ALE or other signals with a Schmitt Trigger or CMOS-level input logic.

  1. Capacitive loading on Ports 0 and 2 causes the V

OH on ALE and PSEN# to drop below the specification when the address lines are stabilizing.

  1. Typical values are obtained using VDD = 5 V and TA=2 5°C. They are not tested and there is not guarantee on these values.
  2. The input threshold voltage of SCL and SDA meets the I2C specification, so an input voltage below 0.3·VDD will be recognized as a logic

0 while an input voltage above 0.7·VDD will be recognized as a logic 1.

  1. The clock prescaler is not used: FOSC =F XTAL .

Figure 11. IDD /IDL Versus Frequency; VDD = 4.5 to 5.5 V

10.2 DC Characteristics: Low Voltage versions - Commercial & Industrial

Table 43. DC Characteristics; VDD = 2.7 to 5.5 V, TA = -40 to +85°C

0.45 V I

  1. Under steady-state (non-transient) conditions, IOL must be externally limited as follows:
  2. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level outputs of ALE and Ports 1, 2, and
  3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins change from high to low. In

ALE or other signals with a Schmitt Trigger or CMOS-level input logic.

  1. Capacitive loading on Ports 0 and 2 causes the V

OH on ALE and PSEN# to drop below the specification when the address lines are stabilizing.

  1. Typical values are obtained using VDD = 3 V and TA=2 5°C. They are not tested and there is not guarantee on these values.
  2. The input threshold voltage of SCL and SDA meets the I2C specification, so an input voltage below 0.3·VDD will be recognized as a logic

0 while an input voltage above 0.7·VDD will be recognized as a logic 1.

  1. The clock prescaler is not used: FOSC = FXTAL .

Figure 12. IDD /IDL Versus XTAL Frequency; VDD = 2.7 to 3.6 V

10.3 DC Characteristics: IDD, IDL and IPD Test Conditions

Figure 13. IDD Test Condition, Active Mode Figure 14. IDL Test Condition, Idle Mode Figure 15. IPD Test Condition, Power-Down Mode

  1. AC Characteristics - Commercial & Industrial

11.1 AC Characteristics - External Bus Cycles

Table 44. External Bus Cycles Timing Symbol Definitions Test conditions: capacitive load on all pins= 50 pF. parameters affected by one ALE wait state, and Note 3 marks parameters affected by PSEN#/RD#/WR# wait states. Figure 16 to Figure 21 show the bus cycles with the timing parameters.

Table 45. Bus Cycles AC Timings; VDD = 4.5 to 5.5 V, TA = -40 to 85°C

  1. Specification for PSEN# are identical to those for RD#.
  2. If a wait state is added by extending ALE, add 2·T
  3. If wait states are added by extending RD#/PSEN#/WR#, add 2N·TOSC (N= 1..3).

12 MHz 16 MHz 24 MHz

Table 46. Bus Cycles AC Timings; VDD = 2.7 to 5.5 V, TA = -40 to 85°C

  1. Specification for PSEN# are identical to those for RD#.
  2. If a wait state is added by extending ALE, add 2·T
  3. If wait states are added by extending RD#/PSEN#/WR#, add 2N·TOSC (N= 1..3).

12 MHz 16 MHz

11.2 AC Characteristics - Real-Time Synchronous Wait State

Table 47. Real-Time Synchronous Wait Timing Symbol Definitions Table 48. Real-Time Synchronous Wait AC Timings; VDD = 2.7 to 5.5 V, TA = -40 to 85°C Figure 22. Real-time Synchronous Wait State: Code Fetch/Data Read

Figure 23. Real-time Synchronous Wait State: Data Write

11.3 AC Characteristics - Real-Time Asynchronous Wait State

Table 49. Real-Time Asynchronous Wait Timing Symbol Definitions Table 50. Real-Time Asynchronous Wait AC Timings; VDD = 2.7 to 5.5 V, TA = -40 to 85°C

  1. N is the number of wait states added (N≥ 1).

Figure 24. Real-time Asynchronous Wait State Timings

11.4 AC Characteristics - Serial Port in Shift Register Mode

Table 51. Serial Port Timing Symbol Definitions Table 52. Serial Port AC Timing -Shift Register Mode; VDD = 2.7 to 5.5 V, TA = -40 to 85°C

  1. For high speed versions only.
  2. TI and RI are set during S1P1 of the peripheral cycle following the shift of the eight bit.

Figure 25. Serial Port Waveforms - Shift Register Mode

12 MHz 16 MHz 24 MHz (1)

11.5 AC Characteristics - SSLC: I2C Interface

Table 53. I2C Interface AC Timing; VDD = 2.7 to 5.5 V, TA = -40 to 85°C

  1. At 100 kbit/s. At other bit-rates this value is inversely proportional to the bit-rate of 100 kbit/s.
  2. Determined by the external bus-line capacitance and the external bus-line pull-up resistor, this must be < 1µs.
  3. Spikes on the SDA and SCL lines with a duration of less than 3·T
  4. T CLCL =T OSC = one oscillator clock period.

Figure 26. I2C Waveforms

0.7 VDD

0.3 VDD

11.6 AC Characteristics - SSLC: SPI Interface

Table 54. SPI Interface Timing Symbol Definitions Table 55. SPI Interface AC Timing; VDD = 2.7 to 5.5 V, TA = -40 to 85°C

  1. Capacitive load on all pins= 200 pF in slave mode.
  2. The value of this parameter depends on software.
  3. Capacitive load on all pins= 100 pF in master mode.

Figure 27. SPI Master Waveforms (SSCPHA= 0)

  1. Not Defined but generally the LSB of the character which has just been received.

Figure 30. SPI Slave Waveforms (SSCPHA= 1)

11.7 AC Characteristics - EPROM Programming and Verifying

Table 56. EPROM Programming and Verifying Timing Symbol Definitions Table 57. EPROM Programming AC timings; V DD = 4.5 to 5.5 V, TA =0t o4 0°C

11.8 AC Characteristics - External Clock Drive and Logic Level References

Table 59. External Clock Timing Symbol Definitions Table 60. External Clock AC Timings; VDD = 4.5 to 5.5 V, TA = -40 to +85°C Figure 33. External Clock Waveform During AC testing, all inputs are driven at VDD -0.5 V for a logic 1 and 0.45 V for a logic 0. Timing measurements are made on all outputs at VIH min for a logic 1 and VIL max for a logic 0. Figure 34. AC Testing Input/Output Waveforms OH /VOL level occurs with IOL /IOH = ±20 mA. Figure 35. Float Waveforms

12.1 List of Packages

  • PDIL 40
  • CDIL 40 with window
  • PLCC 44
  • CQPJ 44 with window
  • VQFP 44 (10 x10)

12.2 PDIL 40 - Mechanical Outline

Figure 36. Plastic Dual In Line Table 61. PDIL Package Size

12.3 CDIL 40 with Window - Mechanical Outline

Figure 37. Ceramic Dual In Line Table 62. CDIL Package Size

12.4 PLCC 44 - Mechanical Outline

Figure 38. Plastic Lead Chip Carrier Table 63. PLCC Package Size

12.5 CQPJ 44 with Window - Mechanical Outline

Figure 39. Ceramic Quad Pack J Table 64. CQPJ Package size

12.6 VQFP 44 (10x10) - Mechanical Outline

Figure 40. Shrink Quad Flat Pack (Plastic) Table 65. VQFP Package Size

Rev. A - May 7, 1999 61 TSC80251G2D 13. Ordering Information

13.1 TSC80251G2D ROMless

Note: 1. Dry Pack mandatory for VQFP package.

13.2 TSC83251G1D 16 Kbytes Mask ROM

Notes: 1. Dry Pack mandatory for VQFP package. 2. xxx: means ROM code, is Cxxx in case of encrypted code.

13.3 TSC83251G2D 32 Kbytes MaskROM

Notes: 1. Dry Pack mandatory for VQFP package. 2. xxx: means ROM code, is Cxxx in case of encrypted code. TEMIC Part Number ROM Description High Speed Versions 4.5 to 5.5 V, Commercial and Industrial TSC80251G2D-16CB ROMless 16 MHz, Commercial 0 ° to 70°C, PLCC 44 TSC80251G2D-24CB ROMless 24 MHz, Commercial 0 ° to 70°C, PLCC 44 TSC80251G2D-24CED ROMless 24 MHz, Commercial 0 ° to 70°C, VQFP 44, Dry pack(1) TSC80251G2D-24IA ROMless 24 MHz, Industrial -40 ° to 85°C, PDIL 40 TSC80251G2D-24IB ROMless 24 MHz, Industrial -40 ° to 85°C, PLCC 44 Low Voltage Versions 2.7 to 5.5 V, Commercial TSC80251G2D-L16CB ROMless 16 MHz, Commercial, PLCC 44 TSC80251G2D-L16CED ROMless 16 MHz, Commercial, VQFP 44, Dry pack (1) TEMIC Part Number (2) ROM Description High Speed Versions 4.5 to 5.5 V, Commercial and Industrial TSC251G1Dxxx-16CB 16K MaskROM 16 MHz, Commercial 0 ° to 70°C, PLCC 44 TSC251G1Dxxx-24CB 16K MaskROM 24 MHz, Commercial 0 ° to 70°C, PLCC 44 TSC251G1Dxxx-24CED 16K MaskROM 24 MHz, Commercial 0 ° to 70°C, VQFP 44, Dry pack(1) TSC251G1Dxxx-24IA 16K MaskROM 24 MHz, Industrial -40 ° to 85°C, PDIL 40 TSC251G1Dxxx-24IB 16K MaskROM 24 MHz, Industrial -40 ° to 85°C, PLCC 44 Low Voltage Versions 2.7 to 5.5 V, Commercial TSC251G1Dxxx-L16CB 16K MaskROM 16 MHz, Commercial 0 ° to 70°C, PLCC 44 TSC251G1Dxxx-L16CED 16K MaskROM 16 MHz, Commercial 0 ° to 70°C, VQFP 44, Dry pack(1) TEMIC Part Number (2) ROM Description High Speed Versions 4.5 to 5.5 V, Commercial and Industrial TSC251G2Dxxx-16CB 32K MaskROM 16 MHz, Commercial 0 ° to 70°C, PLCC 44 TSC251G2Dxxx-24CB 32K MaskROM 24 MHz, Commercial 0 ° to 70°C, PLCC 44 TSC251G2Dxxx-24CED 32K MaskROM 24 MHz, Commercial 0 ° to 70°C, VQFP 44, Dry pack(1) TSC251G2Dxxx-24IA 32K MaskROM 24 MHz, Industrial -40 ° to 85°C, PDIL 40 TSC251G2Dxxx-24IB 32K MaskROM 24 MHz, Industrial -40 ° to 85°C, PLCC 44 Low Voltage Versions 2.7 to 5.5 V, Commercial TSC251G2Dxxx-L16CB 32K MaskROM 16 MHz, Commercial 0 ° to 70°C, PLCC 44 TSC251G2Dxxx-L16CED 32K MaskROM 16 MHz, Commercial 0 ° to 70°C, VQFP 44, Dry pack(1)

62 Rev. A - May 7, 1999 TSC80251G2D

13.4 TSC87251G2D OTPROM

Note: 1. Dry Pack mandatory for VQFP package.

13.5 TSC87251G2D EPROM - UV Window package

13.6 Options(Please consult TEMIC sales)

  • ROM code encryption
  • Tape & Real or Dry Pack
  • Known good dice
  • Ceramic packages
  • Extended temperature range: -55°C to +125°C

13.7 Starter Kit

13.8 Products Marking

Note: 1. Dry Pack letter (D) not included in the marking. TEMIC Part Number ROM Description High Speed Versions 4.5 to 5.5 V, Commercial and Industrial TSC87251G2D-16CB 32K OTPROM 16 MHz, Commercial 0 ° to 70°C, PLCC 44 TSC87251G2D-24CB 32K OTPROM 24 MHz, Commercial 0 ° to 70°C, PLCC 44 TSC87251G2D-24CED 32K OTPROM 24 MHz, Commercial 0 ° to 70°C, VQFP 44, Dry pack(1) TSC87251G2D-24IA 32K OTPROM 24 MHz, Industrial -40 ° to 85°C, PDIL 40 TSC87251G2D-24IB 32K OTPROM 24 MHz, Industrial -40 ° to 85°C, PLCC 44 Low Voltage Versions 2.7 to 5.5 V, Commercial TSC87251G2D-L16CB 32K OTPROM 16 MHz, Commercial 0 ° to 70°C, PLCC 44 TSC87251G2D-L16CED 32K OTPROM 16 MHz, Commercial 0 ° to 70°C, VQFP 44, Dry pack(1) TEMIC Part Number ROM Description High Speed Versions 4.5 to 5.5 V, Industrial TSC87251G2D-24IC 32K EPROM 24 MHz, Industrial -40 ° to 85°C, window CQPJ 44 TSC87251G2D-24IJ 32K EPROM 24 MHz, Industrial -40 ° to 85°C, window CDIL 40 Low Voltage Versions 2.7 to 5.5 V, Industrial TSC87251G2D-L16IC 32K EPROM 16 MHz, Commercial -40 ° to 85°C, window CQPJ 44 TEMIC Part Number Description TSC80251-SK TSC80251 Starter Kit ROMless versions TEMIC Customer Part number Temic Part number INTEL’97 YYWW . Lot Number Mask ROM versions TEMIC Temic Part number (1) INTEL’97 YYWW . Lot Number OTP versions TEMIC Temic Part number (1) INTEL’97 YYWW . Lot Number MMM C C C

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