TSC80251G2D ATMEL | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 76
Technical content
Features
- Pin and Software Compatibility with Standard 80C51 Products and 80C51Fx/Rx/Rx+
- Plug-In Replacement of Intel’s 8xC251Sx
- C251 Core: Intel’s MCS®251 D-step Compliance
- 40-byte Register File
- Registers Accessible as Bytes, Words or Dwords
- Three-stage Instruction Pipeline
- 16-bit Internal Code Fetch
- Enriched C51 Instruction Set
- 16-bit and 32-bit ALU
- Compare and Conditional Jump Instructions
- Expanded Set of Move Instructions
- Linear Addressing
- 1 Kbyte of On-Chip RAM
- External Memory Space (Code/Data) Programmable from 64 kilobytes to 256 kilobytes
- TSC87251G2D: 32 kilobytes of On-Chip EPROM/OTPROM – SINGLE PULSE Programming Algorithm
- TSC83251G1D: 16 kilobytes of On-Chip Masked ROM
- TSC83251G1D: 32 kilobytes of On-Chip Masked ROM
- TSC80251G1D: ROMless Version
- Four 8-bit Parallel I/O Ports (Ports 0, 1, 2 and 3 of the Standard 80C51)
- Serial I/O Port: Full Duplex UART (80C51 Compatible) With Independent Baud Rate Generator
- SSLC: Synchronous Serial Link Controller
- TWI Multi-master Protocol
- μWire and SPI Master and Slave Protocols
- Three 16-bit Timers/Counters (Timers 0, 1 and 2 of the Standard 80C51)
- EWC: Event and Waveform Controller
- Compatible with Intel’s Programmable Counter Array (PCA)
- Common 16-bit Timer/Counter Reference with Four Possible Clock Sources (Fosc/4, Fosc/12, Timer 1 and External Input)
- Five Modules, Each with Four Programmable Modes: – 16-bit Software Timer/Counter – 16-bit Timer/Counter Capture Input and Software Pulse Measurement – High-speed Output and 16-bit Software Pulse Width Modulation (PWM) – 8-bit Hardware PWM Without Overhead
- 16-bit Watchdog Timer/Counter Capability
- Secure 14-bit Hardware Watchdog Timer
- Power Management
- Power-On Reset (Integrated on the Chip)
- Power-Off Flag (Cold and Warm Resets)
- Software Programmable System Clock
- Idle Mode
- Power-down Mode
- Keyboard Interrupt Interface on Port 1
- Non Maskable Interrupt Input (NMI)
- Real-Time Wait States Inputs (WAIT#/AWAIT#)
- ONCE Mode and Full Speed Real-time In-circuit Emulation Support (Third Party Vendors)
- High Speed Versions: – 4.5V to 5.5V – 16 MHz and 24 MHz
- Typical Operating Current: 35 mA at 24 MHz 24 mA at 16 MHz
- Typical Power-down Current: 2 μA
- Low Voltage Version: – 2.7V to 5.5V – 16 MHz 8/16-bit Microcontroller with Serial Communication Interfaces TSC80251G2D TSC83251G2D TSC87251G2D AT80251G2D AT83251G2D AT87251G2D
4135D–8051–08/05
- Typical Operating Current:11 mA at 3V
- Typical Power-down Current: 1 μA
- Temperature Ranges: Commercial (0°C to +70°C), Industrial (-40°C to +85°C)
- Option: Extended Range (-55°C to +125°C)
- Packages: PDIL 40, PLCC 44 and VQFP 44, CDIL 40 and CQPJ 44 with Window
- Options: Known Good Dice and Ceramic Packages
Description
The TSC80251G2D products are derivatives of the Atmel Microcontroller family based on the 8/16-bit C251 Architecture. This family of products is tailored to 8/16-bit microcontroller applications requiring an increased instruction throughput, a reduced operating frequency or a larger addressable memory space. The architecture can provide a significant code size reduction when compiling C programs while fully preserving the legacy of C51 assembly routines. The TSC80251G2D derivatives are pin and software compatible with standard 80C51/Fx/Rx/Rx+ with extended on-chip data memory (1 Kbyte RAM) and up to 256 kilobytes of external code and data. Additionally, the TSC83251G2D and TSC87251G2D provide on-chip code memory: 32 kilobytes ROM and 32 kilobytes EPROM/OTPROM respectively. They provide transparent enhancements to Intel’s 8xC251Sx family with an additional Synchronous Serial Link Controller (SSLC supporting TWI, μWire and SPI protocols), a Keyboard interrupt interface, a dedicated Baud Rate Generator for UART, and Power Management features. TSC80251G2D derivatives are optimized for speed and for low power consumption on a wide voltage range. Note: 1. This Datasheet provides the technical description of the TSC80251G2D derivatives. For further information on the device usage, please request the TSC80251 Programmer’s Guide and the TSC80251G1D Design Guide and errata sheet. Typical Applications ISDN Terminals High-Speed Modems PABX (SOHO) Line Cards DVD ROM and Players Printers Plotters Scanners Banking Machines Barcode Readers Smart Cards Readers High-End Digital Monitors High-End Joysticks High-end TV’s
4135D–8051–08/05 Block Diagram 16-bit Memory Code 16-bit Memory Address 16-bit Instruction Bus 24-bit Program Counter Bus 8-bit Data Bus 24-bit Data Address Bus 8-bit Internal Bus Peripheral Interface Unit VDD VSS VSS1 P3(A16) P1(A17) P2(A15-8) P0(AD7-0) RST XTAL2 XTAL1 NMI EA#/VPP ALE/PROG# PSEN# Timers 0, 1 and 2 Event and Waveform Controller TWI/SPI/mWire Controller Watchdog Timer Power Management Clock Unit Clock System Prescaler Keyboard Interface Bus Interface Unit CPU PORTS 0-3 Interrupt Handler Unit RAM
1 Kbyte
AWAIT# EPROM OTPROM 32 KB VSS2
Figure 3. TSC80251G2D 44-pin VQFP Package
Table 1. TSC80251G2D Pin Assignment
4135D–8051–08/05 Signals Table 2. Product Name Signal Description O 18th Address Bit Output to memory as 18th external address bit (A17) in extended bus applications, depending on the values of bits RD0 and RD1 in UCONFIG0 byte (see Table 13, Page 20). P1.7 A16 O 17th Address Bit Output to memory as 17th external address bit (A16) in extended bus applications, depending on the values of bits RD0 and RD1 in UCONFIG0 byte (see Table 13, Page 20). P3.7 A15:8(1) O Address Lines Upper address lines for the external bus. P2.7:0 AD7:0(1) I/O Address/Data Lines Multiplexed lower address lines and data for the external memory. P0.7:0 ALE O Address Latch Enable ALE signals the start of an external bus cycle and indicates that valid address information are available on lines A16/A17 and A7:0. An external latch can use ALE to demultiplex the address from address/data bus. AWAIT# I Real-time Asynchronous Wait States Input When this pin is active (low level), the memory cycle is stretched until it becomes high. When using the Product Name as a pin-for-pin replacement for a 8xC51 product, AWAIT# can be unconnected without loss of compatibility or power consumption increase (on-chip pull-up). Not available on DIP package. CEX4:0 I/O PCA Input/Output pins CEXx are input signals for the PCA capture mode and output signals for the PCA compare and PWM modes. P1.7:3 EA# I External Access Enable EA# directs program memory accesses to on-chip or off-chip code memory. For EA# = 0, all program memory accesses are off-chip. For EA# = 1, an access is on-chip ROM if the address is within the range of the on-chip ROM; otherwise the access is off-chip. The value of EA# is latched at reset. For devices without ROM on-chip, EA# must be strapped to ground. ECI O PCA External Clock input ECI is the external clock input to the 16-bit PCA timer. P1.2 MISO I/O SPI Master Input Slave Output line When SPI is in master mode, MISO receives data from the slave peripheral. When SPI is in slave mode, MISO outputs data to the master controller. P1.5 MOSI I/O SPI Master Output Slave Input line When SPI is in master mode, MOSI outputs data to the slave peripheral. When SPI is in slave mode, MOSI receives data from the master controller. P1.7 INT1:0# I External Interrupts 0 and 1 INT1#/INT0# inputs set IE1:0 in the TCON register. If bits IT1:0 in the TCON register are set, bits IE1:0 are set by a falling edge on INT1#/INT0#. If bits IT1:0 are cleared, bits IE1:0 are set by a low level on INT1#/INT0#. P3.3:2
4135D–8051–08/05 NMI I Non Maskable Interrupt Holding this pin high for 24 oscillator periods triggers an interrupt. When using the Product Name as a pin-for-pin replacement for a 8xC51 product, NMI can be unconnected without loss of compatibility or power consumption increase (on-chip pull-down). Not available on DIP package. P0.0:7 I/O Port 0 P0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high impedance inputs. To avoid any paraitic current consumption, Floating P0 inputs must be polarized to VDD or VSS. AD7:0 P1.0:7 I/O Port 1 P1 is an 8-bit bidirectional I/O port with internal pull-ups. P1 provides interrupt capability for a keyboard interface. P2.0:7 I/O Port 2 P2 is an 8-bit bidirectional I/O port with internal pull-ups. A15:8 P3.0:7 I/O Port 3 P3 is an 8-bit bidirectional I/O port with internal pull-ups. PROG# I Programming Pulse input The programming pulse is applied to this input for programming the on-chip EPROM/OTPROM. PSEN# O Program Store Enable/Read signal output PSEN# is asserted for a memory address range that depends on bits RD0 and RD1 in UCONFIG0 byte (see ). RD# O Read or 17th Address Bit (A16) Read signal output to external data memory depending on the values of bits RD0 and RD1 in UCONFIG0 byte (see Table 13, Page 20). P3.7 RST I Reset input to the chip Holding this pin high for 64 oscillator periods while the oscillator is running resets the device. The Port pins are driven to their reset conditions when a voltage greater than VIH1 is applied, whether or not the oscillator is running. This pin has an internal pull-down resistor which allows the device to be reset by connecting a capacitor between this pin and VDD. Asserting RST when the chip is in Idle mode or Power-Down mode returns the chip to normal operation. RXD I/O Receive Serial Data RXD sends and receives data in serial I/O mode 0 and receives data in serial I/O modes 1, 2 and 3. P3.0 SCL I/O TWI Serial Clock When TWI controller is in master mode, SCL outputs the serial clock to slave peripherals. When TWI controller is in slave mode, SCL receives clock from the master controller. P1.6 SCK I/O SPI Serial Clock When SPI is in master mode, SCK outputs clock to the slave peripheral. When SPI is in slave mode, SCK receives clock from the master controller. P1.6 SDA I/O TWI Serial Data SDA is the bidirectional TWI data line. P1.7 SS# I SPI Slave Select Input When in Slave mode, SS# enables the slave mode. P1.4 Table 2. Product Name Signal Description (Continued)
4135D–8051–08/05 T1:0 I/O Timer 1:0 External Clock Inputs When timer 1:0 operates as a counter, a falling edge on the T1:0 pin increments the count. I/O Timer 2 Clock Input/Output For the timer 2 capture mode, T2 is the external clock input. For the Timer 2 clock-out mode, T2 is the clock output. P1.0 T2EX I Timer 2 External Input In timer 2 capture mode, a falling edge initiates a capture of the timer 2 registers. In auto-reload mode, a falling edge causes the timer 2 register to be reloaded. In the up-down counter mode, this signal determines the count direction: 1 = up, 0 = down. P1.1 TXD O Transmit Serial Data TXD outputs the shift clock in serial I/O mode 0 and transmits data in serial I/O modes 1, 2 and 3. P3.1 VDD PWR Digital Supply Voltage Connect this pin to +5V or +3V supply voltage. VPP I Programming Supply Voltage The programming supply voltage is applied to this input for programming the on-chip EPROM/OTPROM. VSS GND Circuit Ground Connect this pin to ground. VSS1 GND Secondary Ground 1 This ground is provided to reduce ground bounce and improve power supply bypassing. Connection of this pin to ground is recommended. However, when using the TSC80251G2D as a pin-for-pin replacement for a 8xC51 product, VSS1 can be unconnected without loss of compatibility. Not available on DIP package. VSS2 GND Secondary Ground 2 This ground is provided to reduce ground bounce and improve power supply bypassing. Connection of this pin to ground is recommended. However, when using the TSC80251G2D as a pin-for-pin replacement for a 8xC51 product, VSS2 can be unconnected without loss of compatibility. Not available on DIP package. WAIT# I Real-time Synchronous Wait States Input The real-time WAIT# input is enabled by setting RTWE bit in WCON (S:A7h). During bus cycles, the external memory system can signal ‘system ready’ to the microcontroller in real time by controlling the WAIT# input signal. P1.6 WCLK O Wait Clock Output The real-time WCLK output is enabled by setting RTWCE bit in WCON (S:A7h). When enabled, the WCLK output produces a square wave signal with a period of one half the oscillator frequency. P1.7 WR# O Write Write signal output to external memory. P3.6 XTAL1 I Input to the on-chip inverting oscillator amplifier To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, its output is connected to this pin. XTAL1 is the clock source for internal timing.
4135D–8051–08/05 Note: The description of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the Non-Page mode chip con- figuration. If the chip is configured in Page mode operation, port 0 carries the lower address bits (A7:0) while port 2 carries the upper address bits (A15:8) and the data (D7:0). XTAL2 O Output of the on-chip inverting oscillator amplifier To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, leave XTAL2 unconnected.
Figure 4. Program/Code Memory Mapping
from its going into the reserved area). are redirected to the external memory. Figure 5. Data Memory Mapping
categories detailed in Table 1 to Table 9. SFRs are bit-addressable using the C251 instruction set. Table 1. C251 Core SFRs
- These SFRs can also be accessed by their corresponding registers in the register
Table 2. I/O Port SFRs Table 3. Timers SFRs
Table 4. Serial I/O Port SFRs Table 5. SSLC SFRs Table 6. Event Waveform Control SFRs
Table 7. System Management SFRs Table 8. Interrupt SFRs Table 9. Keyboard Interface SFRs
- These registers are described in the TSC80251 Programmer’s Guide (C251 core registers).
- In TWI and SPI modes, SSCON is splitted in two separate registers. SSCON reset value is 0000 0000 in TWI mode and
- In read and write modes, SSCS is splitted in two separate registers. SSCS reset value is 1111 1000 in read mode and 0000
Table 10. SFR Descriptions
4135D–8051–08/05 Configuration Bytes The TSC80251G2D derivatives provide user design flexibility by configuring certain operating features at device reset. These features fall into the following categories: external memory interface (Page mode, address bits, programmed wait states and the address range for RD#, WR#, and PSEN#) source mode/binary mode opcodes selection of bytes stored on the stack by an interrupt mapping of the upper portion of on-chip code memory to region 00: Two user configuration bytes UCONFIG0 (see Table 11) and UCONFIG1 (see Table 12) provide the information. When EA# is tied to a low level, the configuration bytes are fetched from the external address space. The TSC80251G2D derivatives reserve the top eight bytes of the mem- ory address space (FF:FFF8h-FF:FFFFh) for an external 8-byte configuration array. Only two bytes are actually used: UCONFIG0 at FF:FFF8h and UCONFIG1 at FF:FFF9h. For the mask ROM devices, configuration information is stored in on-chip memory (see ROM Verifying). When EA# is tied to a high level, the configuration information is retrieved from the on-chip memory instead of the external address space and there is no restriction in the usage of the external memory.
4135D–8051–08/05 Table 11. Configuration Byte 0
- UCONFIG0 is fetched twice so it can be properly read both in Page or Non-Page
used, otherwise the subsequent fetches are performed in Non-Page mode.
- This selection provides compatibility with the standard 80C51 hardware which is mul-
tiplexing the address LSB and the data on Port 0. Set this bit when writing to UCONFIG0. WSA1# Wait State A bits Select the number of wait states for RD#, WR# and PSEN# signals for external memory accesses (all regions except 01:). WSA1# WSA0# Number of Wait States WSA0# XALE# Extend ALE bit Clear to extend the duration of the ALE pulse from TOSC to 3·TOSC. Set to minimize the duration of the ALE pulse to 1·TOSC. RD1 Memory Signal Select bits Specify a 18-bit, 17-bit or 16-bit external address bus and the usage of RD#, WR# and PSEN# signals (see Table 13). RD0 PAGE# Page Mode Select bit(1) Clear to select the faster Page mode with A15:8/D7:0 on Port 2 and A7:0 on Port 0. Set to select the non-Page mode(2) with A15:8 on Port 2 and A7:0/D7:0 on Port SRC Source Mode/Binary Mode Select bit Clear to select the binary mode. Set to select the source mode.
4135D–8051–08/05 Table 12. Configuration Byte 1
- The CSIZE is only available on EPROM/OTPROM products.
- Two or four bytes are transparently popped according to INTR when using the RETI
- Use only for Step A compatibility; set this bit when WSB1:0# are used.
On-Chip Code Memory Size bit(1) Clear to select 16 KB of on-chip code memory (TSC87251G1D product). Set to select 32 KB of on-chip code memory (TSC87251G2D product). TSC80251G2D TSC83251G2D Reserved Set this bit when writing to UCONFIG1. Reserved Set this bit when writing to UCONFIG1. Reserved Set this bit when writing to UCONFIG1. INTR Interrupt Mode bit(2) Clear so that the interrupts push two bytes onto the stack (the two lower bytes of the PC register). Set so that the interrupts push four bytes onto the stack (the three bytes of the PC register and the PSW1 register). WSB Wait State B bit(3) Clear to generate one wait state for memory region 01:. Set for no wait states for memory region 01:. WSB1# Wait State B bits Select the number of wait states for RD#, WR# and PSEN# signals for external memory accesses (only region 01:). WSB1# WSB0# Number of Wait States WSB0# EMAP# On-Chip Code Memory Map bit Clear to map the upper 16 KB of on-chip code memory (at FF:4000h- FF:7FFFh) to the data space (at 00:C000h-00:FFFFh). Set not to map the upper 16 KB of on-chip code memory (at FF:4000h- FF:7FFFh) to the data space.
Table 13. Address Ranges and Usage of RD#, WR# and PSEN# Signals
- This selection provides compatibility with the standard 80C51 hardware which has
separate external memory spaces for data and code.
4135D–8051–08/05 Instruction Set Summary This section contains tables that summarize the instruction set. For each instruction there is a short description, its length in bytes, and its execution time in states (one state time is equal to two system clock cycles). There are two concurrent processes limiting the effective instruction throughput: Instruction Fetch Instruction Execution Table 20 to Table 32 assume code executing from on-chip memory, then the CPU is fetching 16-bit at a time and this is never limiting the execution speed. If the code is fetched from external memory, a pre-fetch queue will store instructions ahead of execution to optimize the memory bandwidth usage when slower instructions are executed. However, the effective speed may be limited depending on the average size of instructions (for the considered section of the program flow). The maximum aver- age instruction throughput is provided by Table 14 depending on the external memory configuration (from Page Mode to Non-Page Mode and the maximum number of wait states). If the average size of instructions is not an integer, the maximum effective throughput is found by pondering the number of states for the neighbor integer values. Table 14. Minimum Number of States per Instruction for given Average Sizes tion speed but only the actual code execution can provide the final value. Table 15 to Table 19 provide notation for Instruction Operands. Table 15. Notation for Direct Addressing
0 Wait
1 Wait
2 Wait States
3 Wait States
4 Wait States
A direct 8-bit address. This can be a memory address (00h-7Fh) or a SFR address (80h-FFh). It is a byte (default), word or double word depending on the other operand. dir16 A 16-bit memory address (00:0000h-00:FFFFh) used in direct addressing.
4135D–8051–08/05 Table 16. Notation for Immediate Addressing Table 17. Notation for Bit Addressing Table 18. Notation for Destination in Control Instructions #data An 8-bit constant that is immediately addressed in an instruction #data16 A 16-bit constant that is immediately addressed in an instruction #0data16 #1data16 A 32-bit constant that is immediately addressed in an instruction. The upper word is filled with zeros (#0data16) or ones (#1data16). #short A constant, equal to 1, 2, or 4, that is immediately addressed in an instruction. Direct Address A directly addressed bit (bit number = 00h-FFh) in memory or an SFR. Bits 00h-7Fh are the 128 bits in byte locations 20h-2Fh in the on-chip RAM. Bits 80h-FFh are the 128 bits in the 16 SFRs with addresses that end in 0h or 8h, S:80h, S:88h, S:90h,..., S:F0h, S:F8h. bit A directly addressed bit in memory locations 00:0020h-00:007Fh or in any defined SFR. Direct Address A signed (two’s complement) 8-bit relative address. The destination is -128 to +127 bytes relative to the next instruction’s first byte. addr11 An 11-bit target address. The target is in the same 2-Kbyte block of memory as the next instruction’s first byte. addr16 A 16-bit target address. The target can be anywhere within the same 64-Kbyte region as the next instruction’s first byte. addr24 A 24-bit target address. The target can be anywhere within the 16- Mbyte address space.
4135D–8051–08/05 Table 19. Notation for Register Operands A memory location (00h-FFh) addressed indirectly via byte registers R0 or R1 Rn n Byte register R0-R7 of the currently selected register bank Byte register index: n = 0-7 Rm Rmd Rms m, md, ms Byte register R0-R15 of the currently selected register file Destination register Source register Byte register index: m, md, ms = 0-15 WRj WRjd WRjs at WRj at WRj +dis16 j, jd, js Word register WR0, WR2, ..., WR30 of the currently selected register file Destination register Source register A memory location (00:0000h-00:FFFFh) addressed indirectly through word register WR0-WR30, is the target address for jump instructions. A memory location (00:0000h-00:FFFFh) addressed indirectly through word register (WR0-WR30) + 16-bit signed (two’s complement) displacement value Word register index: j, jd, js = 0-30 DRk DRkd DRks at DRk at DRk +dis16 k, kd, ks Dword register DR0, DR4, ..., DR28, DR56, DR60 of the currently selected register file Destination register Source register A memory location (00:0000h-FF:FFFFh) addressed indirectly through dword register DR0-DR28, DR56 and DR60, is the target address for jump instruction A memory location (00:0000h-FF:FFFFh) addressed indirectly through dword register (DR0-DR28, DR56, DR60) + 16-bit (two’s complement) signed displacement value Dword register index: k, kd, ks = 0, 4, 8..., 28, 56, 60
Table 20. Summary of Add and Subtract Instructions
- A shaded cell denotes an instruction in the C51 Architecture.
- If this instruction addresses an I/O Port (Px, x = 0-3), add 1 to the number of states.
Add 2 if it addresses a Peripheral SFR.
- If this instruction addresses external memory location, add N+2 to the number of
states (N: number of wait states).
- If this instruction addresses external memory location, add 2(N+2) to the number of
states (N: number of wait states). Table 21. Summary of Increment and Decrement Instructions
- A shaded cell denotes an instruction in the C51 Architecture.
- If this instruction addresses an I/O Port (Px, x = 0-3), add 2 to the number of states.
Add 3 if it addresses a Peripheral SFR.
Table 22. Summary of Compare Instructions
- If this instruction addresses an I/O Port (Px, x = 0-3), add 1 to the number of states.
Add 2 if it addresses a Peripheral SFR.
- If this instruction addresses external memory location, add N+2 to the number of
states (N: number of wait states).
- If this instruction addresses external memory location, add 2(N+2) to the number of
states (N: number of wait states).
4135D–8051–08/05 Logical AND(1)ANL <dest>, <src>dest opnd ← dest opnd Λ src opnd Logical OR(1)ORL <dest>, <src>dest opnd ← dest opnd ς src opnd Logical Exclusive OR(1)XRL <dest>, <src>dest opnd ← dest opnd ∀ src opnd Clear(1)CLR A(A) ← 0 Complement(1)CPL A(A) ← ∅ (A) Rotate LeftRL A(A)n+1 ← (A)n, n = 0..6 (A)0 ← (A)7 Rotate Left CarryRLC A(A)n+1 ← (A)n, n = 0..6 (CY) ← (A)7 (A)0 ← (CY) Rotate RightRR A(A)n-1 ← (A)n, n = 7..1 (A)7 ← (A)0 Rotate Right CarryRRC A(A)n-1 ← (A)n, n = 7..1 (CY) ← (A)0 (A)7 ← (CY) Mnemonic <dest>, <src>(1) Comments Binary Mode Source Mode Bytes States Bytes States ANL ORL XRL A, Rn register to ACC A, dir8 Direct address (on-chip RAM or SFR) to ACC 1(3) 1(3) A, at Ri Indirect address to ACC A, #data Immediate data to ACC dir8, A ACC to direct address 2(4) 2(4) dir8, #data Immediate 8-bit data to direct address 3(4) 3(4) Rmd, Rms Byte register to byte register WRjd, WRjs Word register to word register Rm, #data Immediate 8-bit data to byte register WRj, #data16 Immediate 16-bit data to word register Rm, dir8 Direct address (on-chip RAM or SFR) to byte register 3(3) 2(3) WRj, dir8 Direct address (on-chip RAM or SFR) to word register Rm, dir16 Direct address (64K) to byte register 3(5) 2(5) WRj, dir16 Direct address (64K) to word register 4(6) 3(6) Rm, at WRj Indirect address (64K) to byte register 3(5) 2(5) Rm, at DRk Indirect address (16M) to byte register 4(5) 3(5) CLR A Clear ACC CPL A Complement ACC RL A Rotate ACC left RLC A Rotate ACC left through CY RR A Rotate ACC right RRC A Rotate ACC right through CY
- Logical instructions that affect a bit are in Table 27.
- A shaded cell denotes an instruction in the C51 Architecture.
- If this instruction addresses an I/O Port (Px, x = 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
- If this instruction addresses an I/O Port (Px, x = 0-3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR.
- If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states).
- If this instruction addresses external memory location, add 2(N+2) to the number of states (N: number of wait states).
Table 23. Summary of Logical Instructions (2/2)
- A shaded cell denotes an instruction in the C51 Architecture.
Table 24. Summary of Multiply, Divide and Decimal-adjust Instructions
- A shaded cell denotes an instruction in the C51 Architecture.
Table 25. Summary of Move Instructions (1/3)
- A shaded cell denotes an instruction in the C51 Architecture.
- Extended memory addressed is in the region specified by DPXL (reset value = 01h).
- If this instruction addresses external memory location, add N+1 to the number of
states (N: number of wait states).
- If this instruction addresses external memory location, add N+2 to the number of
states (N: number of wait states).
Table 26. Summary of Move Instructions (2/3)
- Instructions that move bits are in Table 27.
- Move instructions from the C51 Architecture.
- If this instruction addresses an I/O Port (Px, x = 0-3), add 1 to the number of states.
Add 2 if it addresses a Peripheral SFR.
- Apply note 3 for each dir8 operand.
4135D–8051–08/05 Move(1)MOV <dest>, <src>dest opnd ← src opnd Mnemonic <dest>, <src>(1) Comments Binary Mode Source Mode Bytes States Bytes States MOV Rmd, Rms Byte register to byte register MOV WRjd, WRjs Word register to word register MOV DRkd, DRks Dword register to dword register MOV Rm, #data Immediate 8-bit data to byte register MOV WRj, #data16 Immediate 16-bit data to word register MOV DRk, #0data16 zero-ext 16bit immediate data to dword register MOV DRk, #1data16 one-ext 16bit immediate data to dword register MOV Rm, dir8 Direct address (on-chip RAM or SFR) to byte register 3(3) 2(3) MOV WRj, dir8 Direct address (on-chip RAM or SFR) to word register MOV DRk, dir8 Direct address (on-chip RAM or SFR) to dword register MOV Rm, dir16 Direct address (64K) to byte register 3(4) 2(4) MOV WRj, dir16 Direct address (64K) to word register 4(5) 3(5) MOV DRk, dir16 Direct address (64K) to dword register 6(6) 5(6) MOV Rm, at WRj Indirect address (64K) to byte register 3(4) 2(4) MOV Rm, at DRk Indirect address (16M) to byte register 4(4) 3(4) MOV WRjd, at WRjs Indirect address (64K) to word register 4(5) 3(5) MOV WRj, at DRk Indirect address (16M) to word register 5(5) 4(5) MOV dir8, Rm Byte register to direct address (on-chip RAM or SFR) 4(3) 3(3) MOV dir8, WRj Word register to direct address (on-chip RAM or SFR) MOV dir8, DRk Dword register to direct address (on-chip RAM or SFR) MOV dir16, Rm Byte register to direct address (64K) 4(4) 3(4) MOV dir16, WRj Word register to direct address (64K) 5(5) 4(5) MOV dir16, DRk Dword register to direct address (64K) 7(6) 6(6) MOV at WRj, Rm Byte register to indirect address (64K) 4(4) 3(4) MOV at DRk, Rm Byte register to indirect address (16M) 5(4) 4(4) MOV at WRjd, WRjs Word register to indirect address (64K) 5(5) 4(5) MOV at DRk, WRj Word register to indirect address (16M) 6(5) 5(5) MOV Rm, at WRj +dis16 Indirect with 16-bit displacement (64K) to byte register 6(4) 5(4) MOV WRj, at WRj +dis16 Indirect with 16-bit displacement (64K) to word register 7(5) 6(5) MOV Rm, at DRk +dis24 Indirect with 16-bit displacement (16M) to byte register 7(4) 6(4)
4135D–8051–08/05 Notes: 1. Instructions that move bits are in Table 27. 2. Move instructions unique to the C251 Architecture. 3. If this instruction addresses an I/O Port (Px, x = 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR. 4. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states). 5. If this instruction addresses external memory location, add 2(N+1) to the number of states (N: number of wait states). 6. If this instruction addresses external memory location, add 4(N+2) to the number of states (N: number of wait states). MOV WRj, at WRj +dis24 Indirect with 16-bit displacement (16M) to word register 8(5) 7(5) MOV at WRj +dis16, Rm Byte register to indirect with 16-bit displacement (64K) 6(4) 5(4) MOV at WRj +dis16, WRj Word register to indirect with 16-bit displacement (64K) 7(5) 6(5) MOV at DRk +dis24, Rm Byte register to indirect with 16-bit displacement (16M) 7(4) 6(4) MOV at DRk +dis24, WRj Word register to indirect with 16-bit displacement (16M) 8(5) 7(5)
Table 27. Summary of Bit Instructions
- A shaded cell denotes an instruction in the C51 Architecture.
- If this instruction addresses an I/O Port (Px, x = 0-3), add 1 to the number of states.
Add 2 if it addresses a Peripheral SFR.
- If this instruction addresses an I/O Port (Px, x = 0-3), add 2 to the number of states.
Add 3 if it addresses a Peripheral SFR.
Table 28. Summary of Exchange, Push and Pop Instructions
- A shaded cell denotes an instruction in the C51 Architecture.
- If this instruction addresses an I/O Port (Px, x = 0-3), add 1 to the number of states.
Add 2 if it addresses a Peripheral SFR.
- If this instruction addresses an I/O Port (Px, x = 0-3), add 2 to the number of states.
Add 3 if it addresses a Peripheral SFR.
Table 29. Summary of Conditional Jump Instructions (1/2)
- A shaded cell denotes an instruction in the C51 Architecture.
- States are given as jump not-taken/taken.
- In internal execution only, add 1 to the number of states of the ‘jump taken’ if the des-
tination address is internal and odd.
Table 30. Summary of Conditional Jump Instructions (2/2)
- A shaded cell denotes an instruction in the C51 Architecture.
- States are given as jump not-taken/taken.
- If this instruction addresses an I/O Port (Px, x = 0-3), add 1 to the number of states.
Add 2 if it addresses a Peripheral SFR.
- If this instruction addresses an I/O Port (Px, x = 0-3), add 2 to the number of states.
Add 3 if it addresses a Peripheral SFR.
- If this instruction addresses an I/O Port (Px, x = 0-3), add 3 to the number of states.
Add 5 if it addresses a Peripheral SFR.
- In internal execution only, add 1 to the number of states of the ‘jump taken’ if the des-
tination address is internal and odd. Table 31. Summary of Unconditional Jump Instructions
- A shaded cell denotes an instruction in the C51 Architecture.
- In internal execution only, add 1 to the number of states if the destination address is
- Add 2 to the number of states if the destination address is external.
- Add 3 to the number of states if the destination address is external.
Table 32. Summary of Call and Return Instructions
- A shaded cell denotes an instruction in the C51 Architecture.
- In internal execution only, add 1 to the number of states if the destination/return
address is internal and odd.
- Add 2 to the number of states if the destination address is external.
- Add 5 to the number of states if INTR = 1.
4135D–8051–08/05 Programming and Verifying Non-volatile Memory Internal Features The internal non-volatile memory of the TSC80251G2D derivatives contains five differ- ent areas: Code Memory Configuration Bytes Lock Bits Encryption Array Signature Bytes EPROM/OTPROM Devices All the internal non-volatile memory but the Signature Bytes of the TSC87251G2D prod- ucts is made of EPROM cells. The Signature Bytes of the TSC87251G2D products are made of Mask ROM. The TSC87251G2D products are programmed and verified in the same manner as Atmel’s TSC87251G1A, using a SINGLE-PULSE algorithm, which programs at VPP = 12.75V using only one 100µs pulse per byte. This results in a programming time of less than 10 seconds for the 32 kilobytes on-chip code memory. The EPROM of the TSC87251G2D products in Window package is erasable by Ultra- Violet radiation(1) (UV). UV erasure set all the EPROM memory cells to one and allows reprogramming. The quartz window must be covered with an opaque label(2) when the device is in operation. This is not so much to protect the EPROM array from inadvertent erasure, as to protect the RAM and other on-chip logic. Allowing light to impinge on the silicon die during device operation may cause a logical malfunction. The TSC87251G2D products in plastic packages are One Time Programmable (OTP). An EPROM cell cannot be reset by UV once programmed to zero. Notes: 1. The recommended erasure procedure is exposure to ultra-violet light (at 2537 Å) to an integrated dose of at least 20 W-sec/cm2. Exposing the EPROM to an ultra-violet lamp of 12000 µW/cm2 rating for 30 minutes should be sufficient. 2. Erasure of the EPROM begins to occur when the chip is exposed to light wavelength shorter than 4000 Å. Since sunlight and fluorescent light have wavelength in this range, exposure to these light sources over an extended time (1 week in sunlight or 3 years in room-level fluorescent lighting) could cause inadvertent erasure. Mask ROM Devices All the internal non-volatile memory of TSC83251G2D products is made of Mask ROM cells. They can only be verified by the user, using the same algorithm as the EPROM/OTPROM devices. ROMless Devices The TSC80251G2D products do not include on-chip Configuration Bytes, Code Memory and Encryption Array. They only include Signature Bytes made of Mask ROM cells which can be read using the same algorithm as the EPROM/OTPROM devices. Security Features In some microcontroller applications, it is desirable that the user’s program code be secured from unauthorized access. The TSC83251G2D and TSC87251G2D offer two kinds of protection for program code stored in the on-chip array: Program code in the on-chip Code Memory is encrypted when read out for verification if the Encryption Array isprogrammed. A three-level lock bit system restricts external access to the on-chip code memory.
Level 0 is the level of an erased part and does not enable any security features. Bytes and the Encryption Array. Level 3 locks the external execution. Table 33. Lock Bits Programming
- Returns encrypted data if Encryption Array is programmed.
- Returns non encrypted data.
- x means don’t care. Level 2 always enables level 1, and level 3 always enables levels
The security level may be verified according to Table 34. Table 34. Lock Bits Verifying all 1s), the user program code is placed on the data bus in its original, unencrypted form. encrypted and cannot be used without knowledge of the key byte sequence.
- When a MOVC instruction is executed, the content of the ROM is not encrypted. In
always be set when encryption is used.
- If the encryption feature is implemented, the portion of the on-chip code memory that
the encryption key sequence from being revealed. values are listed in Table 35. Table 35. Signature Bytes (Electronic ID) PSEN# and the other control signals (ALE and Port 0) have to be set to a high level. The voltage on the EA# pin must be set to VDD. Table 36). It has to be applied until the completion of this programming operation. Most Significant Byte (MSB) and the Least Significant Byte (LSB) of the address. The programming data are applied on Port 2. then by generating a low level pulse on ALE/PROG# pin. lowered to VDD before performing the verifying operation.
programming operations or a sequence of programming and verifying operations. Figure 6. Setup for Programming Table 36. Programming Modes
- Signature Bytes are not user-programmable.
- The ALE/PROG# pulse waveform is shown in Figure 23 page 59.
PSEN# and the other control signals (ALE and Port 0) have to be set to a high level. The voltage on the EA# pin must be set to VDD and ALE must be set to a high level. applied until the completion of this verifying operation.
1 Pulse
Then device is driving the data on Port 2. been lowered to VDD before performing the verifying operation. verifying operations or a sequence of programming and verifying operations. Table 37. Verifying Modes
- To preserve the secrecy of on-chip code memory when encrypted, the Encryption
Figure 7. Setup for Verifying
Table 38. External Bus Cycles Timing Symbol Definitions Test conditions: capacitive load on all pins = 50 pF. wait state, and Note 3 marks parameters affected by PSEN#/RD#/WR# wait states. Figure 8 to Figure 13 show the bus cycles with the timing parameters.
Table 39. Bus Cycles AC Timings; VDD = 4.5 to 5.5 V, TA = -40 to 85°C
- Specification for PSEN# are identical to those for RD#.
- If a wait state is added by extending ALE, add 2·TOSC.
- If wait states are added by extending RD#/PSEN#/WR#, add 2N·TOSC (N = 1..3).
12 MHz
16 MHz
24 MHz
Table 40. Bus Cycles AC Timings; VDD = 2.7 to 5.5 V, TA = -40 to 85°C
- Specification for PSEN# are identical to those for RD#.
- If a wait state is added by extending ALE, add 2·TOSC.
- If wait states are added by extending RD#/PSEN#/WR#, add 2N·TOSC (N = 1..3).
Table 43. Real-Time Asynchronous Wait Timing Symbol Definitions Table 44. Real-Time Asynchronous Wait AC Timings; VDD = 2.7 to 5.5 V, TA = -40 to
- N is the number of wait states added (N≥ 1).
Figure 16. Real-time Asynchronous Wait State Timings Table 45. Serial Port Timing Symbol Definitions
Table 46. Serial Port AC Timing -Shift Register Mode; VDD = 2.7 to 5.5 V, TA = -40 to
- For high speed versions only.
Figure 17. Serial Port Waveforms - Shift Register Mode
- TI and RI are set during S1P1 of the peripheral cycle following the shift of the eight bit.
24 MHz(1)
Table 47. TWI Interface AC Timing; VDD = 2.7 to 5.5 V, TA = -40 to 85°C
- At 100 kbit/s. At other bit-rates this value is inversely proportional to the bit-rate of
- Determined by the external bus-line capacitance and the external bus-line pull-up
resistor, this must be < 1 μs.
- Spikes on the SDA and SCL lines with a duration of less than 3·TCLCL will be filtered
- TCLCL = TOSC = one oscillator clock period.
Figure 18. TWI Waveforms
0.3 VDD
0.7 VDD
Table 48. SPI Interface Timing Symbol Definitions
Table 49. SPI Interface AC Timing; VDD = 2.7 to 5.5 V, TA = -40 to 85°C
- Capacitive load on all pins = 200 pF in slave mode.
- The value of this parameter depends on software.
- Capacitive load on all pins = 100 pF in master mode.
Table 51. EPROM Programming AC timings; VDD = 4.5 to 5.5 V, TA = 0 to 40°C Figure 23. EPROM Programming Waveforms
4135D–8051–08/05 Absolute Maximum Rating and Operating Conditions Absolute Maximum Ratings Ambient Temperature Under Bias VDD *NOTICE: Stressing the device beyond the “Absolute Maxi- mum Ratings” may cause permanent damage. These are stress ratings only. Operation beyond the “operating conditions” is not recommended and extended exposure beyond the “Operating Conditions” may affect device reliability.
Table 55. DC Characteristics; VDD = 4.5 to 5.5 V, TA = -40 to +85°C
0.45 V < VIN < VDD
- Under steady-state (non-transient) conditions, IOL must be externally limited as follows:
- Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level outputs of ALE and Ports
0.8 V. It may be desirable to qualify ALE or other signals with a Schmitt Trigger or CMOS-level input logic.
- Capacitive loading on Ports 0 and 2 causes the VOH on ALE and PSEN# to drop below the specification when the address
- Typical values are obtained using VDD = 5 V and TA = 25°C. They are not tested and there is not guarantee on these values.
- The input threshold voltage of SCL and SDA meets the TWI specification, so an input voltage below 0.3·VDD will be recog-
nized as a logic 0 while an input voltage above 0.7·VDD will be recognized as a logic 1. Figure 28. IDD/IDL Versus Frequency; VDD = 4.5 to 5.5 V
- The clock prescaler is not used: FOSC = FXTAL.
- Under steady-state (non-transient) conditions, IOL must be externally limited as follows:
Table 56. DC Characteristics; VDD = 2.7 to 5.5 V, TA = -40 to +85°C
Figure 33. Plastic Dual In Line Table 57. PDIL Package Size
Figure 34. Ceramic Dual In Line Table 58. CDIL Package Size
Figure 35. Plastic Lead Chip Carrier Table 59. PLCC Package Size
1.27 BSC
Figure 36. Ceramic Quad Pack J Table 60. CQPJ Package Size
1.27 TYP
0.86 TYP
Figure 37. Shrink Quad Flat Pack (Plastic) Table 61. VQFP Package Size
0.64 REF
0.80 BSC
0.35 BSC
4135D–8051–08/05 AT/TSC8x251G2D
Ordering Information
Note: 1. xxx: means ROM code, is Cxxx in case of encrypted code. Part Number ROM High Speed Versions 4.5 to 5.5 V, Commercial and Industrial TSC80251G2D-16CB ROMless
16 MHz, Commercial 0° to 70°C, PLCC 44
24 MHz, Commercial 0° to 70°C, PLCC 44
24 MHz, Commercial 0° to 70°C, VQFP 44
24 MHz, Industrial -40° to 85°C, PDIL 40
24 MHz, Industrial -40° to 85°C, PLCC 44
24 MHz, Industrial & Green -40° to 85°C, PLCC 44
24 MHz, Industrial & Green -40° to 85°C, PDIL 40
24 MHz, Industrial & Green -40° to 85°C, VQFP 44
Low Voltage Versions 2.7 to 5.5 V TSC80251G2D-L16CB ROMless
16 MHz, Commercial, PLCC 44
16 MHz, Commercial, VQFP 44
16 MHz, Industrial & Green, PLCC 44
16 MHz, Industrial & Green, VQFP 44
Part Number(1) ROM High Speed Versions 4.5 to 5.5 V, Commercial and Industrial TSC251G2Dxxx-16CB 32K MaskROM Low Voltage Versions 2.7 to 5.5 V TSC251G2Dxxx-L16CB 32K MaskROM
16 MHz, Commercial 0° to 70°C, VQFP 44
4135D–8051–08/05 AT/TSC8x251G2D AT/TSC87251G2D OTPROM Part Number ROM High Speed Versions 4.5 to 5.5 V, Commercial and Industrial TSC87251G2D-16CB 32K OTPROM Low Voltage Versions 2.7 to 5.5 V TSC87251G2D-L16CB 32K OTPROM
16 MHz, Industrial & Green, 0° to 70°C, PLCC 44
16 MHz, Industrial & Green, 0° to 70°C, VQFP 44
4135D–8051–08/05 AT/TSC8x251G2D Options (Please consult Atmel sales) ROM code encryption Tape & Reel or Dry Pack Known good dice Extended temperature range: -55°C to +125°C Product Markings ROMless versions ATMEL Customer Part number Part Number YYWW . Lot Number Mask ROM versions ATMEL Part number YYWW . Lot Number OTP versions ATMEL Part number YYWW . Lot Number
Printed on recycled paper. 4135D–8051–08/05 © Atmel Corporation 2005. All rights reserved. Atmel®, logo and combinations thereof, are registered trademarks, and Everywhere You AreSM are the trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise,to anyintellectu- alproperty right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORYWAR- RANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICU- LARPURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMA- TION) ARISING OUTOF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAM- AGES. Atmel makes norepresentationsor warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specificationsand product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for useas components in applications intended to support or sustainlife. Atmel Corporation Atmel Operations
2325 Orchard Parkway
San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza
77 Mody Road Tsimshatsui
Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Memory San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 Microcontrollers San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602
44306 Nantes Cedex 3, France
13106 Rousset Cedex, France
1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743 RF/Automotive Theresienstrasse 2 Postfach 3535
74025 Heilbronn, Germany
1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom Avenue de Rochepleine BP 123
38521 Saint-Egreve Cedex, France
www.atmel.com/literature