TSC80251G1D-L12CED

TSC87251G1A TEMIC | Alldatasheet

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1Rev. A – September 21, 1998 Extended 8–bit Microcontroller with Serial Communication Interfaces 1. Description The TSC87251G1A products are derivatives of the TEMIC Microcontroller family based on the extended 8–bit C251 Architecture. This family of products is tailored to 8–bit microcontroller applications requiring an increased instruction throughput, a reduced operating frequency or a larger addressable memory space. The architecture can provide a significant code size reduction when compiling C programs while fully preserving the legacy of C51 assembly routines. The TSC87251G1A derivatives are pin–out and software compatible with standard 80C51/Fx/Rx with extended on–chip data memory (1 Kbyte RAM), on–chip memory (16 Kbytes EPROM/OTPROM) and up to 256 Kbytes of external code and data. They provide transparent enhancements to Intel’s 87C251Sx family with an additional Synchronous Serial Link Controller (SSLC supporting I 2C, µWire and SPI protocols), a Keyboard interrupt interface and Power Monitoring and Management features. Notes: This Datasheet provides the technical description of the TSC87251G1A derivatives. For further information on the device usage, please request the TSC80251 Programmers’ Guide and the TSC80251G1 Design Guide. For information on the Mask ROM and ROMless devices, please refer to the TSC87251G1D Datasheet.2. Typical Applications ISDN terminals High–Speed modems PABX (SOHO) Networking Line cards Computer peripherals Printers Plotters Scanners Banking machines Barcode readers Smart cards readers High–end digital monitors High–end joysticks Purchase of TEMIC I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.

2 Rev. A – September 21, 1998 3. Features Pin–Out and software compatibility with standard 80C51 products and 80C51FA/FB/RA/RB Plug–in replacement of Intel’s 80C251Sx C251 core: Intel’s MCS/C0082251 step A compliance /C0071125 ns Instruction cycle time at 16 MHz /C007140–byte Register File /C0071Registers Accessible as Bytes, Words or Dwords /C0071Six–stage instruction Pipeline /C007116–bit Internal Code Fetch Enriched C51 Instruction Set /C007116–bit and 32–bit ALU /C0071Compare and Conditional Jump Instructions /C0071Expanded Set of Move Instructions Linear Addressing

1 Kbyte of on–chip RAM

External memory space (Code/Data) programmable from 64 Kbytes to 256 Kbytes TSC87251G1A: 16 Kbytes of on–chip EPROM/ OTPROM (production with TSC83251G1D: on–chip masked ROM version) SINGLE–PULSE Programming Algorithm Four 8–bit parallel I/O Ports (Ports 0, 1, 2 and 3 of the standard 80C51) Serial I/O Port: full duplex UART (80C51 compatible) with independent Baud Rate Generator SSLC: Synchronous Serial Link Controller /C0071I2C master only protocol /C0071µWire and SPI master only protocol Three 16–bit Timers/Counters (Timers 0, 1 and 2 of the standard 80C51) EWC: Event and Waveform Controller /C0071Compatible with Intel’s Programmable Counter Array (PCA) /C0071Common 16–bit Timer/Counter reference with four possible clock sources (Fosc/4, Fosc/12, Timer 1 and external input) /C0071Five modules with four programmable modes: – 16–bit software Timer/Counter – 16–bit Timer/Counter Capture Input and software pulse measurement – High–speed output and 16–bit software Pulse Width Modulation (PWM) – 8–bit hardware PWM without overhead /C007116–bit Watchdog Timer/Counter capability Secured 14–bit Hardware Watchdog Timer Power Monitoring and Management /C0071Power–Fail reset /C0071Power–On reset (integrated on the chip) /C0071Power–Off flag (cold and warm resets) /C0071Software programmable system clock /C0071Idle and Power–Down modes Keyboard interrupt interface on Port 1 ONCE mode and full speed Real–Time In–Circuit Emulation support (Third Party Vendors) Speed ranges: /C00710 to 16 MHz Supply ranges: /C00715 V ±10 % Temperature ranges: /C0071Commercial (0°C to +70°C) /C0071Industrial (–40°C to +85°C) /C0071Option: extended range (–55°C to +125°C) Packages: /C0071PDIL 40, PLCC 44 /C0071UV–Window CQPJ 44 /C0071Options: known good dice and ceramic packages

1 Kbyte

16 Kbytes

Figure 1. TSC87251G1A Block Diagram

Table 1. TSC87251G1A Pin Assignment

1 VSS1 23 VSS2

12 NC 34 NC

Table 2. TSC87251G1A Signal Descriptions on the values of bits RD0 and RD1 in UCONFIG0 byte (see Table 13). on the values of bits RD0 and RD1 in UCONFIG0 byte (see Table 13). Upper address lines for the external bus. Multiplexed lower address lines and data for the external memory. EA# directs program memory accesses to on–chip or off–chip code memory. For EA#= 0, all program memory accesses are off-chip. chip EPROM/OTPROM; otherwise the access is off-chip. The value of EA# is latched at reset.

6 Rev. A – September 21, 1998 Alternate FunctionDescriptionTypeSignal Name ECI O PCA External Clock input ECI is the external clock input to the 16–bit PCA timer. P1.2 MISO I/O SPI Master Input Slave Output line When SPI is in master mode, MISO receives data from the slave peripheral. When SPI is in slave mode, MISO outputs data to the master controller. P1.5 MOSI I/O SPI Master Output Slave Input line When SPI is in master mode, MOSI outputs data to the slave peripheral. When SPI is in slave mode, MOSI receives data from the master controller. P1.7 INT1:0# I External Interrupts 0 and 1. INT1#/INT0# inputs set IE1:0 in the TCON register. If bits IT1:0 in the TCON register are set, bits IE1:0 are set by a falling edge on INT1#/INT0#. If bits IT1:0 are cleared, bits IE1:0 are set by a low level on INT1#/INT0# P3.3:2 P0.0:7 I/O Port 0 P0 is an 8–bit open–drain bidirectional I/O port. AD7:0 P1.0:7 I/O Port 1 P1 is an 8–bit bidirectional I/O port with internal pull–ups. P1 provides interrupt capability for a keyboard interface. P2.0:7 I/O Port 2 P2 is an 8–bit bidirectional I/O port with internal pull–ups. A15:8 P3.0:7 I/O Port 3 P3 is an 8–bit bidirectional I/O port with internal pull–ups. PROG# O Programming Pulse input The programming pulse is applied to this input for programming the on–chip EPROM/ OTPROM. PSEN# O Program Store Enable/Read signal output PSEN# is asserted for a memory address range that depends on bits RD0 and RD1 in UCON- FIG0 byte (see Table 13). RD# O Read or 17th Address Bit (A16) Read signal output to external data memory depending on the values of bits RD0 and RD1 in UCONFIG0 byte (see Table 13). P3.7 RST I Reset input to the chip Holding this pin high for 64 oscillator periods while the oscillator is running resets the device. The Port pins are driven to their reset conditions when a voltage greater than VIH1 is applied, whether or not the oscillator is running. This pin has an internal pull-down resistor which allows the device to be reset by connecting a capacitor between this pin and VDD. Asserting RST when the chip is in Idle mode or Power–Down mode returns the chip to normal operation. RXD I/O Receive Serial Data RXD sends and receives data in serial I/O mode 0 and receives data in serial modes I/O 1, 2 and 3. P3.0 SCL I/O I2C Serial Clock SCL outputs the serial clock to slave peripherals. P1.6 SCK I/O SPI Serial Clock SCK outputs clock to the slave peripheral. P1.6 SDA I/O I2C Serial Data SDA is the bidirectional I2C data line. P1.7 T1:0 I/O Timer 1:0 External Clock Inputs When timer 1:0 operates as a counter, a falling edge on the T1:0 pin increments the count.

7Rev. A – September 21, 1998 Alternate FunctionDescriptionTypeSignal Name T2 I/O Timer 2 Clock Input/Output For the timer 2 capture mode, T2 is the external clock input. For the Timer 2 clock–out mode, T2 is the clock output. P1.0 T2EX I Timer 2 External Input In timer 2 capture mode, a falling edge initiates a capture of the timer 2 registers. In auto–reload mode, a falling edge causes the timer 2 register to be reloaded. In the up–down counter mode, this signal determines the count direction: 1= up, 0= down. P1.1 TXD I/O Transmit Serial Data TXD outputs the shift clock in serial I/O mode 0 and transmits data in serial I/O modes 1, 2 and 3. P3.1 VDD PWR Digital Supply Voltage Connect this pin to +5V or +3V supply voltage. VSS GND Circuit Ground Connect this pin to ground. VSS1 GND Secondary Ground 1 This ground is provided to reduce ground bounce and improve power supply bypassing. Con- nection of this pin to ground is recommended. However, when using the TSC87251G1A as a pin–for–pin replacement for a 8xC51 product, VSS1 can be unconnected without loss of com- patibility. Not available on DIP package. VSS2 GND Secondary Ground 2 This ground is provided to reduce ground bounce and improve power supply bypassing. Con- nection of this pin to ground is recommended. However, when using the TSC87251G1A as a pin–for–pin replacement for a 8xC51 product, VSS2 can be unconnected without loss of com- patibility. Not available on DIP package. VPP I Programming Supply Voltage The programming supply voltage is applied to this input for programming the on–chip EPROM/ OTPROM WR# O Write Write signal output to external memory. P3.6 XTAL1 I Input to the on–chip inverting oscillator amplifier To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, its output is connected to this pin. XTAL1 is the clock source for internal tim- ing. XTAL2 O Output of the on–chip inverting oscillator amplifier To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, leave XTAL2 unconnected. Note: 1. The description of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the non–page mode chip configuration. If the chip is configured in page mode operation, port 0 carries the lower address bits (A7:0) while port 2 carries the upper address bits (A15:8) and the data (D7:0).

program/code memory is not used and all the accesses are directed to the external memory.

48 Kbytes

64 Kbytes

128 Kbytes

Figure 4. Program/Code Memory Mapping the beginning of segment 00: (this prevents from its going into the reserved area).

RAM is not accessible through the program/code memory space.

8 Kbytes

56 Kbytes

Figure 5. Data Memory Mapping (Figure 5). The relative addresses within S: of these SFRs are provided together with their reset values in Table 12. in the TSC80251G1 Design Guide. All the SFRs are bit–addressable using the C251 instruction set.

Table 3. C251 Core SFRs

1. These SFRs can also be accessed by their corresponding registers in the register file.

Table 4. I/O Port SFRs Table 5. Timers SFRs Table 6. Serial I/O Port SFRs Table 7. SSLC SFRs

Table 8. Event Waveform Control SFRs Table 9. System Management SFRs Table 10. Interrupt SFRs Table 11. Keyboard Interface SFRs

Table 12. SFR Addresses and Reset Values

1. These registers are described in the TSC80251 Programmer’ s Guide (C251 core registers).
2. In read and write modes, SSCS is splitted in two separate registers. SSCS reset value is 1111 1000 in read mode and 0000 0000 in write mode.

The TSC87251G1A derivatives provide user design flexibility by configuring certain operating features at device reset. Two user configuration bytes CONFIG0 (see Figure 6) and CONFIG1 (see Figure 7) provide the information. For TSC87251G1A devices, configuration information is stored in on–chip separate memory (see paragraph 8. Set this bit when writing to CONFIG0. Set this bit when writing to CONFIG0.

5 WSA

Clear to generate one wait state for all memory region except 01:. Set for no wait states for all memory region except 01:.

4 XALE#

Clear to extend the duration of the ALE pulse from TOSC to 3×TOSC. Set to minimize the duration of the ALE pulse to 1×TOSC .

3 RD1 Memory Signal Select bits

2 RD0

1 PAGE#

Clear to select the faster page mode with A15:8/D7:0 on Port 2 and A7:0 on Port 0.

0 SRC

Clear to select the binary mode. Set to select the source mode.

1. This selection provides compatibility with the standard 80C51 hardware which is multiplexing the address LSB and the data on Port 0.

Figure 6. Configuration Byte 0

Set this bit when writing to CONFIG1. Set this bit when writing to CONFIG1. Set this bit when writing to CONFIG1.

4 INTR

Clear so that the interrupts push two bytes onto the stack (the two lower bytes of the PC register).

3 WSB

Clear to generate one wait state for memory region 01:. Set for no wait states for memory region 01:. Set this bit when writing to CONFIG1. Set this bit when writing to CONFIG1.

0 EMAP#

Set not to map the upper 8 Kbytes of on–chip code memory (at FF:2000h–FF:3FFFh) to the data space.

1. Two or four bytes are transparently popped according to INTR when using the RETI instruction. INTR must be set if interrupts are used with code

executing outside region FF:. Figure 7. Configuration Byte 1 Table 13. Address Ranges and Usage of RD#, WR# and PSEN# Signals

256 Kbytes

1. This selection provides compatibility with the standard 80C51 hardware which has separate external memory spaces for data and code.

is never limiting the execution speed. maximum effective throughput is found by pondering the number of states for the neighbor integer values. Table 14. Minimum Number of States per Instruction for given Average Sizes a fair estimation of the execution speed but only the actual code execution can provide the final value. Table 15 to Table 19 provide Notation for Instruction Operands. Table 15. Notation for Direct Addressing (80h-FFh). It is a byte (default), word or double word depending on the other operand. Table 16. Notation for Immediate Addressing with zeros (#0data16) or ones (#1data16).

Table 17. Notation for Bit Addressing 16 SFRs with addresses that end in 0h or 8h, S:80h, S:88h, S:90h,..., S:F0h, S:F8h. Table 18. Notation for Destination in Control Instructions relative to the next instruction’s first byte. next instruction’s first byte. Table 19. Notation for Register Operands WR0-WR30, is the target address for jump instructions.

Table 20. Summary of Add and Subtract Instructions

1. A shaded cell denotes an instruction in the C51 Architecture.
2. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
3. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states).
4. If this instruction addresses external memory location, add 2(N+2) to the number of states (N: number of wait states).

Table 21. Summary of Increment and Decrement Instructions

1. A shaded cell denotes an instruction in the C51 Architecture.
2. If this instruction addresses an I/O Port (Px, x= 0-3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR.

Table 22. Summary of Compare Instructions

1. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
2. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states).
3. If this instruction addresses external memory location, add 2(N+2) to the number of states (N: number of wait states).

Table 23. Summary of Logical Instructions (1/2)

1. Logical instructions that affect a bit are in Table 29.
2. A shaded cell denotes an instruction in the C51 Architecture.
3. If this instruction addresses an I/O Port (Px, x= 0–3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
4. If this instruction addresses an I/O Port (Px, x= 0–3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR.
5. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states).
6. If this instruction addresses external memory location, add 2(N+2) to the number of states (N: number of wait states).

Table 24. Summary of Logical Instructions (2/2)

1. A shaded cell denotes an instruction in the C51 Architecture.

Table 25. Summary of Multiply, Divide and Decimal-adjust Instructions

1. A shaded cell denotes an instruction in the C51 Architecture.

Table 26. Summary of Move Instructions (1/3)

1. A shaded cell denotes an instruction in the C51 Architecture.
2. Extended memory addressed is in the region specified by DPXL (reset value= 01h).
3. If this instruction addresses external memory location, add N+1 to the number of states (N: number of wait states).
4. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states).

Table 27. Summary of Move Instructions (2/3)

1. Instructions that move bits are in Table 29.
2. Move instructions from the C51 Architecture.
3. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
4. Apply note 3 for each dir8 operand.

Table 28. Summary of Move Instructions (3/3)

1. Instructions that move bits are in Table 29.
2. Move instructions unique to the C251 Architecture.
3. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
4. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states).
5. If this instruction addresses external memory location, add 2(N+1) to the number of states (N: number of wait states).
6. If this instruction addresses external memory location, add 4(N+2) to the number of states (N: number of wait states).

Table 29. Summary of Bit Instructions

1. A shaded cell denotes an instruction in the C51 Architecture.
2. If this instruction addresses an I/O Port (Px, x= 0–3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
3. If this instruction addresses an I/O Port (Px, x= 0–3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR.

Table 30. Summary of Exchange, Push and Pop Instructions

1. A shaded cell denotes an instruction in the C51 Architecture.
2. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
3. If this instruction addresses an I/O Port (Px, x= 0-3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR.

Table 31. Summary of Conditional Jump Instructions (1/2)

1. A shaded cell denotes an instruction in the C51 Architecture.
2. States are given as jump not-taken/taken.
3. In internal execution only, add 1 to the number of states of the ‘jump taken’ if the destination address is internal and odd.

Table 32. Summary of Conditional Jump Instructions (2/2)

1. A shaded cell denotes an instruction in the C51 Architecture.
2. States are given as jump not-taken/taken.
3. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
4. If this instruction addresses an I/O Port (Px, x= 0-3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR.
5. If this instruction addresses an I/O Port (Px, x= 0-3), add 3 to the number of states. Add 5 if it addresses a Peripheral SFR.
6. In internal execution only, add 1 to the number of states of the ‘jump taken’ if the destination address is internal and odd.

Table 33. Summary of unconditional Jump Instructions

1. A shaded cell denotes an instruction in the C51 Architecture.
2. In internal execution only, add 1 to the number of states if the destination address is internal and odd.
3. Add 2 to the number of states if the destination address is external.
4. Add 3 to the number of states if the destination address is external.

Table 34. Summary of Call and Return Instructions

1. A shaded cell denotes an instruction in the C51 Architecture.
2. In internal execution only, add 1 to the number of states if the destination/return address is internal and odd.
3. Add 2 to the number of states if the destination address is external.
4. Add 5 to the number of states if INTR= 1.

27Rev. A – September 21, 1998 8. EPROM Programming 8.1. Internal ROM Features The internal ROM of the TSC87251G1A products contains five different areas: Code Memory Configuration Bytes Lock Bits Encryption Array Signature Bytes 8.1.1. EPROM/OTPROM Devices All the Internal ROM but the Signature Bytes of the TSC87251G1A products is made of EPROM cells. The Signature Bytes of the TSC87251GxD products are made of Mask ROM. The TSC87251G1A products are programmed and verified in the same manner as TEMIC ’s TSC87251G1 and TSC87251A1A, using a SINGLE–PULSE algorithm, which programs at VPP= 12.75V using only one 100 µs pulse per byte. This results in a programming time of less than 5 seconds for the 16 Kbytes on–chip code memory. The EPROM of TSC87251G1A products in Window CQPJ is erasable by Ultra–Violet radiation (UV). UV erasure set all the EPROM memory cells to one and allows a reprogramming. The quartz window must be covered with an opaque label when the device is in operation. This is not so much to protect the EPROM array from inadvertent erasure, as to protect the RAM and other on–chip logic. Allowing light to impinge on the silicon die during device operation may cause a logical malfunction. Note: Erasure of the EPROM begins to occur when the chip is exposed to light wavelength shorter than 4000Å. Since sunlight and fluorescent light have wavelength in this range, exposure to these light sources over an extended time (1 week in sunlight or 3 years in room–level fluorescent lighting) could cause inadvertent erasure. The TSC87251G1A products in plastic packages are One Time Programmable (OTP). Then an EPROM cell cannot be reset by UV once programmed to zero. 8.1.2. Security Features In some microcontrollers applications, it is desirable that the user program code be secured from unauthorized access. The TSC87251G1A offers two kinds of protection for program code stored in the on–chip array: Program code in the on–chip Code Memory is encrypted when read out for verification if the Encryption Array is programmed. A three–level lock bit system restricts external access to the on–chip code memory. 8.1.3. Lock Bit System The TSC87251G1A products implement 3 levels of security for User’s program as described in Table 35. The first level locks the programming of the User’s internal Code Memory, the Configuration Bytes and the Encryption Array. The second level locks the verifying of the User’s internal Code Memory. It is always possible to verify the Configura- tion Bytes and the Lock Bits. It is never possible to verify the Encryption Array. The third level locks the external execution.

Table 35. Lock bits Programming

1. Returns encrypted data if Encryption Array is programmed.
2. Returns non encrypted data.

Level 1 should be set before programming Level 2; Level 2 should be set before programming Level 3. The security level may be verified according to Table 36. Table 36. Lock bits Verifying code is encrypted and cannot be used without knowledge of the key byte sequence. To preserve the secrecy of the encryption key byte sequence, the Encryption Array can not be verified.

1. When a MOVC instruction is executed, the content of the ROM is not encrypted. In order to fully protect the user program code, the lock bit

level 1 (see Table 1) must always be set when encryption is used.

1. If the encryption feature is implemented, the portion of the on–chip code memory that does not contain program code should be filled with

“random” byte values to prevent the encryption key sequence from being revealed.

Table 38. Programming Modes

1. Signature Bytes are not user–programmable.
2. The ALE/PROG# pulse waveform is shown in Figure 24 page 46.

The chip has to be put under reset and maintained in this state until the completion of the verifying sequence. PSEN# and the other control signals (ALE and Port 0) have to be set to a high level. until the completion of the verifying sequence (see below). The voltage on the EA# pin must be set to VDD and ALE must be set to a high level. The verifying address is applied on Ports 1 and 3 which are respectively the MSB and the LSB of the address. Then device is driving the data on Port 2. on the EA# pin has actually been lowered to VDD before performing the verifying operation. sequence of programming and verifying operations. Table 39. Verifying Modes

1. To preserve the secrecy of on–chip code memory when encypted, the Encryption Array can not be verified.

Figure 9. Setup for EPROM Verifying

1. Absolute Maximum Rating and Operating Conditions

Table 40. Absolute Maximum Ratings Table 41. Operating Conditions “operating conditions” is not recommended and extended exposure beyond the “Operating Conditions” may affect device reliability.

1. DC Characteristics – Commercial & Industrial

Table 42. DC Characteristics; VDD = 4.5 to 5.5 V , TA = –40 to +85°C

1. Under steady–state (non–transient) conditions, IOL must be externally limited as follows:

Maximum Total IOL for all: Output Pins 71 mA . . .

1. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low–level outputs of ALE and Ports 1, 2, and 3. The noise is

Schmitt Trigger or CMOS–level input logic.

1. Capacitive loading on Ports 0 and 2 causes the VOH on ALE and PSEN# to drop below the specification when the address lines are stabilizing.
2. Typical values are obtained using VDD = 5 V and TA = 25°C with no guarantee.

They are not tested and there is not guarantee on these values.

1. The input threshold voltage of SCL and SDA meets the I2C specification, so an input voltage below 0.3.VDD will be recognized as a logic 0 while an

input voltage above 0.7.VDD will be recognized as a logic 1.

1. The clock prescaler is not used: FOSC = FXTAL .

Figure 10. IDD /IDL versus Frequency; VDD = 4.5 to 5.5 V

1. AC Characteristics – Commercial & Industrial

Table 43. External Bus Cycles Timing Symbol Definitions Test conditions: capacitive load on all pins= 50 pF. wait state, and Note 3 marks parameters affected by one PSEN#/RD#/WR# wait state. Figure 14 to Figure 19 show the bus cycles with the timing parameters.

Table 44. Bus Cycles AC Timings; VDD = 4.5 to 5.5 V , TA = –40 to 85°C

16 MHz FOSC Variable

1. Specification for PSEN# are identical to those for RD#.
2. If a wait state is added by extending ALE, add 2×T
3. If a wait state is added by extending RD#/PSEN#/WR#, add 2×TOSC .

Table 45. Serial Port Timing Symbol Definitions Table 46. Serial Port AC Timing –Shift Register Mode; VDD = 4.5 to 5.5 V , TA = –40 to 85°C

1. TI and RI are set during S1P1 of the peripheral cycle following the shift of the eight bit.

Figure 20. Serial Port Waveforms – Shift Register Mode

Table 47. I2C Interface AC Timing; VDD = 4.5 to 5.5 V , TA = –40 to 85°C

1. At 100 kbit/s. At other bit–rates this value is inversely proportional to the bit–rate of 100 kbit/s.
2. Determined by the external bus–line capacitance and the external bus–line pull–up resistor, this must be < 1 µs.
3. Spikes on the SDA and SCL lines with a duration of less than 3×T
4. TCLCL = TOSC = one oscillator clock period.

0.7 VDD

0.3 VDD

Figure 21. I2C Waveforms

Table 48. SPI Interface Timing Symbol Definitions Table 49. SPI Interface AC Timing; VDD = 4.5 to 5.5 V , TA = –40 to 85°C

1. Capacitive load on all pins= 100 pF in master mode.

Table 50. EPROM Programming & Verifying Timing Symbol Definitions Table 51. EPROM Programming and Verifying AC timings; VDD = 4.5 to 5.5 V , TA = 0 to 40°C

48 Rev. A – September 21, 1998 12. Packages 12.1. List of Packages PDIL 40 PLCC 44 CQPJ 44 12.2. PDIL 40 – Mechanical Outline Figure 29: Plastic Dual In Line Table 54: PDIL Package Size MM INCH Min Max Min Max A – 5.08 – .200 A1 0.38 – .015 – A2 3.18 4.95 .125 .195 B 0.36 0.56 .014 .022 B1 0.76 1.78 .030 .070 C 0.20 0.38 .008 .015 D 50.29 53.21 1.980 2.095 E 15.24 15.87 .600 .625 E1 12.32 14.73 .485 .580 eB – 17.78 – .700 L 2.93 3.81 .115 .150 D1 0.13 – .005 –

49Rev. A – September 21, 1998 12.3. PLCC 44 – Mechanical Outline Figure 30: Plastic Lead Chip Carrier Table 55: PLCC Package Size MM INCH Min Max Min Max A 4.20 4.57 .165 .180 A1 2.29 3.04 .090 .120 D 17.40 17.65 .685 .695 D1 16.44 16.66 .647 .656 D2 14.99 16.00 .590 .630 E 17.40 17.65 .685 .695 E1 16.44 16.66 .647 .656 E2 14.99 16.00 .590 .630 e 1.27 BSC .050 BSC G 1.07 1.22 .042 .048 H 1.07 1.42 .042 .056 J 0.51 – .020 – K 0.33 0.53 .013 .021 Nd 11 11 Ne 11 11

50 Rev. A – September 21, 1998 12.4. CQPJ 44 with Window – Mechanical Outline Figure 31: Ceramic Quad Pack J Table 56: CQPJ Package size MM INCH Min Max Min Max A – 4.90 – .193 C 0.15 0.25 .006 .010 D – E 17.40 17.55 .685 .691 D1 – E1 16.36 16.66 .644 .656 e 1.27 TYP .050 TYP f 0.43 0.53 .017 .021 J 0.86 1.12 .034 .044 Q 15.49 16.00 .610 .630 R 0.86 TYP .034 TYP N1 11 11 N2 11 11

51Rev. A – September 21, 1998 13. Ordering Information 13.1. TSC87251G1A OTP (Step A) High Speed Versions 4.5 to 5.5 V , Commercial and Industrial TEMIC Part Number ROM Description TSC87251G1A–16CA 16K OTP ROM 16 MHz, Commercial 0° to 70°C, PDIL 40 TSC87251G1A–16CB 16K OTP ROM 16 MHz, Commercial 0° to 70°C, PLCC 44 TSC87251G1A–16IA 16K OTP ROM 16 MHz, Industrial –40° to 85°C, PDIL 40 TSC87251G1A–16IB 16K OTP ROM 16 MHz, Industrial –40° to 85°C, PLCC 44 13.2. TSC87251G1A EPROM – UV Window package (Step A) High Speed Versions 4.5 to 5.5 V , Industrial TEMIC Part Number ROM Description TSC87251G1A–16IC 16K EPROM 16 MHz, Industrial –40° to 85°C, window CQPJ 44 13.3. TSC80251G1D ROMless (Step D) High Speed Versions 4.5 to 5.5 V , Commercial and Industrial TEMIC Part Number (2) ROM Description TSC80251G1D–24CA ROMless 24 MHz, Commercial 0° to 70°C, PDIL 40 TSC80251G1D–24CB ROMless 24 MHz, Commercial 0° to 70°C, PLCC 44 TSC80251G1D–24CED ROMless 24 MHz, Commercial 0° to 70°C, VQFP 44, Dry pack (1) TSC80251G1D–16CA ROMless 16 MHz, Commercial 0° to 70°C, PDIL 40 TSC80251G1D–16CB ROMless 16 MHz, Commercial 0° to 70°C, PLCC 44 TSC80251G1D–16CED ROMless 16 MHz, Commercial 0° to 70°C, VQFP 44, Dry pack (1) TSC80251G1D–16IA ROMless 16 MHz, Industrial –40° to 85°C, PDIL 40 TSC80251G1D–16IB ROMless 16 MHz, Industrial –40° to 85°C, PLCC 44 Low Voltage Versions 2.7 to 5.5 V , Commercial TEMIC Part Number (2) ROM Description TSC80251G1D–L12CB ROMless 12 MHz, Commercial, PLCC 44 TSC80251G1D–L12CED ROMless 12 MHz, Commercial, VQFP 44, Dry pack (1)

52 Rev. A – September 21, 1998 13.4. TSC83251G1D Mask ROM (Step D) High Speed Versions 4.5 to 5.5 V , Commercial and Industrial TEMIC Part Number (2) ROM Description TSC251G1Dxxx–24CA 16K MaskROM 24 MHz, Commercial 0° to 70°C, PDIL 40 TSC251G1Dxxx–24CB 16K MaskROM 24 MHz, Commercial 0° to 70°C, PLCC 44 TSC251G1Dxxx–24CED 16K MaskROM 24 MHz, Commercial 0° to 70°C, VQFP 44, Dry pack (1) TSC251G1Dxxx–16CA 16K MaskROM 16 MHz, Commercial 0° to 70°C, PDIL 40 TSC251G1Dxxx–16CB 16K MaskROM 16 MHz, Commercial 0° to 70°C, PLCC 44 TSC251G1Dxxx–16CED 16K MaskROM 16 MHz, Commercial 0° to 70°C, VQFP 44, Dry pack (1) TSC251G1Dxxx–16IA 16K MaskROM 16 MHz, Industrial –40° to 85°C, PDIL 40 TSC251G1Dxxx–16IB 16K MaskROM 16 MHz, Industrial –40° to 85°C, PLCC 44 Low Voltage Versions 2.7 to 5.5 V , Commercial TEMIC Part Number (2) ROM Description TSC251G1Dxxx–L12CB 16K MaskROM 12 MHz, Commercial 0° to 70°C, PLCC 44 TSC251G1Dxxx–L12CED 16K MaskROM 12 MHz, Commercial 0° to 70°C, VQFP 44, Dry pack (1) Notes: 1. Dry Pack mandatory for VQFP package. 2. xxx: means ROM code, is Cxxx in case of encrypted code. 13.5. Options (Please consult TEMIC sales) /C0071ROM code encryption /C0071Tape & Real or Dry Pack /C0071Known good dice /C0071Ceramic packages /C0071Extended temperature range: –55°C to +125°C 13.6. Starter Kit TEMIC Part Number Description TSC80251–SK TSC80251 Starter Kit 13.7. Product Marking Mask ROM versions TEMIC Temic Part number  INTEL’97 YYWW . Lot Number ROMless versions TEMIC Temic Part number  INTEL’95 YYWW . Lot Number OTP versions TEMIC Customer Part number Temic Part number  INTEL’97 YYWW . Lot Number