TS80C31X2 TEMIC | Alldatasheet
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Rev. A - Mar. 19, 1999 1 Preliminary TS80C31X2 8-bit CMOS Microcontroller 0-60 MHz 1. Description TEMIC TS80C31X2 is high performance CMOS and ROMless versions of the 80C51 CMOS single chip 8- bit microcontroller. The TS80C31X2 retains all features of the TEMIC TSC80C31 with 128 bytes of internal RAM, a 5-source, 4 priority level interrupt system, an on-chip oscilator and two timer/counters. In addition, the TS80C31X2 has a dual data pointer, a more versatile serial channel that facilitates multiprocessor communication (EUART) and a X2 speed improvement mechanism. The fully static design of the TS80C31X2 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data. The TS80C31X2 has 2 software-selectable modes of reduced activity for further reduction in power consumption. In the idle mode the CPU is frozen while the timers, the serial port and the interrupt system are still operating. In the power-down mode the RAM is saved and all other functions are inoperative. 2. Features
- 80C31 Compatible
- 8031 pin and instruction compatible
- Four 8-bit I/O ports
- Two 16-bit timer/counters
- 128 bytes scratchpad RAM
- High-Speed Architecture
- 40 MHz @ 5V, 30MHz @ 3V
- X2 Speed Improvement capability (6 clocks/ machine cycle)
30 MHz @ 5V, 20 MHz @ 3V (Equivalent to
60 MHz @ 5V, 40 MHz @ 3V)
- Dual Data Pointer
- Asynchronous port reset
- Interrupt Structure with
- 5 Interrupt sources,
- 4 priority level interrupt system
- Full duplex Enhanced UART
- Framing error detection
- Automatic address recognition
- Power Control modes
- Idle mode
- Power-down mode
- Power-off Flag
- Once mode (On-chip Emulation)
- Power supply: 4.5-5.5V, 2.7-5.5V
- Temperature ranges: Commercial (0 to 70oC) and Industrial (-40 to 85oC)
- Packages: PDIL40, PLCC44, VQFP44 1.4, PQFP F1 (13.9 footprint)
2 Rev. A - Mar. 19, 1999 Preliminary TS80C31X2 3. Block Diagram Timer 0 INT RAM 128x8 RxD TxD WR RD EA PSEN ALE/ XTAL2 XTAL1 EUART CPU Timer 1 INT1 CtrlINT0 (1) (1) C51 CORE (1) (1) (1) (1) Port 0 Port 1Port 2Port 3 Parallel I/O Ports & Ext. Bus IB-bus RESET PROG (1)(1) (1): Alternate function of Port 3
- C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1
- I/O port registers: P0, P1, P2, P3
- Timer registers: TCON, TH0, TH1, TMOD, TL0, TL1
- Serial I/O port registers: SADDR, SADEN, SBUF, SCON
- Power and clock control registers: PCON
- Interrupt system registers: IE, IP, IPH
- Others: CKCON
Table 1. All SFRs with their address and their reset value
4 Rev. A - Mar. 19, 1999 Preliminary TS80C31X2 5. Pin Configuration P1.7 P1.4 RST P3.0/RxD P3.1/TxD P1.3 P1.5 P1.6 P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS P2.0 P2.1 P2.2 P2.3 P2.4 P0.4 P0.6 P0.5 P0.7 ALE PSEN EA P2.7 P2.5 P2.6 P1.0 P1.2 P1.1 VCC P0.0 P0.1 P0.2 P0.3PDIL40 5 4 3 2 1 6 44 43 42 41 40 P1.4 P1.0 P1.1 P1.3 P1.2 VSS1/NIC* VCC P0.0/AD0 P0.2/AD2 P0.1/AD1 P0.4/AD4 P0.6/AD6 P0.5/AD5 P0.7/AD7 ALE PSEN EA NIC* P2.7/A15 P2.5/A13 P2.6/A14 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 43 42 41 40 3944 38 37 36 35 34 P1.4 P1.0 P1.1 P1.3 P1.2 VSS1/NIC* VCC P0.0/AD0 P0.2/AD2 P0.3/AD3 P0.1/AD1 P0.4/AD4 P0.6/AD6 P0.5/AD5 P0.7/AD7 ALE PSEN EA NIC* P2.7/A15 P2.5/A13 P2.6/A14 P1.5 P1.6 P1.7 RST P3.0/RxD NIC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P1.5 P1.6 P1.7 RST P3.0/RxD NIC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P0.3/AD3 NIC* NIC* *NIC: No Internal Connection PLCC44 PQFP44 18 19 20 21 22 23 24 25 26 27 28 12 13 14 15 16 17 18 19 20 21 22 VQFP44VQFP44
Table 2. Pin Description for 40/44 pin packages Vss1 1 39 I Optional Ground: Contact the Sales Office for ground connection. source current because of the internal pull-ups. that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR. features of the 80C51 family, as listed below. using only an external capacitor to VCC. access to external data memory. to fetch code from external program memory locations.
- TS80C31X2 Enhanced Features
- The X2 option.
- The Dual Data Pointer.
- The 4 level interrupt priority system.
- The power-off flag.
- The ONCE mode.
- Enhanced UART
6.1 X2 Feature
- Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.
- Save power consumption while keeping same CPU power (oscillator power saving).
- Save power consumption by dividing dynamically operating frequency by 2 in operating and idle modes.
- Increase CPU power by 2 while keeping same crystal frequency. In order to keep the original C51 compatibility, a divider by 2 is inserted between the XTAL1 signal and the main clock input of the core (phase generator). This divider may be disabled by software.
6.1.1 Description
diagram. X2 bit is validated on XTAL1÷2 rising edge to avoid glitches when switching from X2 to STD mode. Figure 2. shows the mode switching waveforms. Figure 1. Clock Generation Diagram state machine: 6 clock cycles.
Figure 2. Mode Switching Waveforms 4800 baud rate will have 9600 baud rate.
Table 3. CKCON Register The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. Clear to select 12 clock periods per machine cycle (STD mode, FOSC =FXTAL /2). Set to select 6 clock periods per machine cycle (X2 mode, FOSC =FXTAL ).
6.2 Dual Data Pointer Register Ddptr
DPS = AUXR1/bit0 (See Table 5.) that allows the program code to switch between them (Refer to Figure 3). Figure 3. Use of Dual Pointer
Table 4. AUXR1: Auxiliary Register 1 pointer and the other one as a "destination" pointer. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit.
0 DPS
Rev. A - Mar. 19, 1999 11 Preliminary TS80C31X2 ASSEMBLY LANGUAGE ; Block move using dual data pointers ; Destroys DPTR0, DPTR1, A and PSW ; note: DPS exits opposite of entry state ; unless an extra INC AUXR1 is added 00A2 AUXR1 EQU 0A2H 0000 909000MOV DPTR,#SOURCE ; address of SOURCE 0003 05A2 INC AUXR1 ; switch data pointers 0005 90A000 MOV DPTR,#DEST ; address of DEST
0008 LOOP:
0008 05A2 INC AUXR1 ; switch data pointers 000A E0 MOVX A,@DPTR ; get a byte from SOURCE 000B A3 INC DPTR ; increment SOURCE address 000C 05A2 INC AUXR1 ; switch data pointers 000E F0 MOVX @DPTR,A ; write the byte to DEST 000F A3 INC DPTR ; increment DEST address 0010 70F6 JNZ LOOP ; check for 0 terminator 0012 05A2 INC AUXR1 ; (optional) restore DPS INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. However, note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it. In simple routines, such as the block move example, only the fact that DPS is toggled in the proper sequence matters, not its actual value. In other words, the block move routine works the same whether DPS is '0' or '1' on entry. Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in the opposite state.
6.3 TS80C31X2 Serial I/O Port
The serial I/O port in the TS80C31X2 is compatible with the serial I/O port in the 80C31.
- Framing error detection
- Automatic address recognition
6.3.1 Framing Error Detection
bit error detection feature, set SMOD0 bit in PCON register (See Figure 4). Figure 4. Framing Error Block Diagram is not found, the Framing Error bit (FE) in SCON register (See Table 5.) bit is set.
RI rises on stop bit instead of the last data bit (See Figure 5. and Figure 6.). Figure 5. UART Timings in Mode 1 Figure 6. UART Timings in Modes 2 and 3
6.3.2 Automatic Address Recognition
(SM2 bit in SCON register is set). the CPU is not interrupted by command frames addressed to other devices. device’s address and is terminated by a valid stop bit. To support automatic address recognition, a device is identified by a given address and a broadcast address. register in mode 0 has no effect).
14 Rev. A - Mar. 19, 1999 Preliminary TS80C31X2
6.3.3 Given Address
Each device has an individual address that is specified in SADDR register; the SADEN register is a mask byte that contains don’t-care bits (defined by zeros) to form the device’s given address. The don’t-care bits provide the flexibility to address one or more slaves at a time. The following example illustrates how a given address is formed. To address a device by its individual address, the SADEN mask byte must be1111 1111b. For example: SADDR 0101 0110b SADEN11111100b Given 0101 01XXb The following is an example of how to use given addresses to address different slaves: Slave A: SADDR 1111 0001b SADEN11111010b Given 1111 0X0Xb Slave B: SADDR 1111 0011b SADEN11111001b Given 1111 0XX1b Slave C: SADDR 1111 0010b SADEN11111101b Given 1111 00X1b The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1. To communicate with slave A only, the master must send an address where bit 0 is clear (e.g.1111 0000b). For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit. To communicate with slaves B and C, but not slave A, the master must send an address with bits 0 and 1 both set (e.g.1111 0011b). To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1 clear, and bit 2 clear (e.g.1111 0001b).
6.3.4 Broadcast Address
A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as don’t-care bits, e.g.: SADDR 0101 0110b SADEN 1111 1100b Broadcast =SADDR OR SADEN 1111 111Xb The use of don’t-care bits provides flexibility in defining the broadcast address, however in most applications, a broadcast address is FFh. The following is an example of using broadcast addresses: Slave A: SADDR 1111 0001b SADEN11111010b Broadcast 1111 1X11b, Slave B: SADDR 1111 0011b SADEN11111001b Broadcast 1111 1X11B, Slave C: SADDR= 1111 0010b SADEN11111101b Broadcast 1111 1111b For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the master must send an address FFh. To communicate with slaves A and B, but not slave C, the master can send and address FBh.
Rev. A - Mar. 19, 1999 15 Preliminary TS80C31X2
6.3.5 Reset Addresses
On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and broadcast addresses areXXXX XXXXb(all don’t-care bits). This ensures that the serial port will reply to any address, and so, that it is backwards compatible with the 80C51 microcontrollers that do not support automatic address recognition. SADEN - Slave Address Mask Register (B9h) Reset Value = 0000 0000b Not bit addressable SADDR - Slave Address Register (A9h) Reset Value = 0000 0000b Not bit addressable 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Table 5. SCON Register Clear to reset the error state, not cleared by a valid stop bit. Set by hardware when an invalid stop bit is detected. Refer to SM1 for serial port mode selection.
6 SM1
5 SM2
Clear to disable multiprocessor communication feature.
4 REN
Clear to disable serial reception. Set to enable serial reception.
3 TB8
Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3. Clear to transmit a logic 0 in the 9th bit. Set to transmit a logic 1 in the 9th bit.
2 RB8
Cleared by hardware if 9th bit received is a logic 0. Set by hardware if 9th bit received is a logic 1. In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used. Clear to acknowledge interrupt. Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0, see Figure 5. and Figure 6. in the other modes.
Table 6. PCON Register Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset doesn’t affect the value of this bit.
7 SMOD1 Serial port Mode bit 1
Set to select double baud rate in mode 1, 2 or 3.
6 SMOD0
Clear to select SM0 bit in SCON register. Set to to select FE bit in SCON register. The value read from this bit is indeterminate. Do not set this bit.
4 POF
Clear to recognize next reset type. Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software.
3 GF1
Cleared by user for general purpose usage. Set by user for general purpose usage.
2 GF0
Cleared by user for general purpose usage. Set by user for general purpose usage. Cleared by hardware when reset occurs. Set to enter power-down mode.
0 IDL
Clear by hardware when interrupt or reset occurs.
6.4 Interrupt System
(timers 0 and 1) and the serial port interrupt. These interrupts are shown in Figure 7. Figure 7. Interrupt Control System a bit in the Interrupt Priority register (See Table 9.) and in the Interrupt Priority High register (See Table 10.). shows the bit values and priority levels associated with each combination.
Table 7. Priority Level Bit Values A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt source. Table 8. IE Register Table 9. IP Register Clear to disable all interrupts. Set to enable all interrupts. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. Clear to disable serial port interrupt. Set to enable serial port interrupt.
3 ET1
Clear to disable timer 1 overflow interrupt. Set to enable timer 1 overflow interrupt.
2 EX1
Clear to disable external interrupt 1. Set to enable external interrupt 1.
1 ET0
Clear to disable timer 0 overflow interrupt. Set to enable timer 0 overflow interrupt.
0 EX0
Clear to disable external interrupt 0. Set to enable external interrupt 0.
20 Rev. A - Mar. 19, 1999 Preliminary TS80C31X2 IP - Interrupt Priority Register (B8h) Reset Value = XXX0 0000b Bit addressable 7 6 5 4 3 2 1 0 - - - PS PT1 PX1 PT0 PX0 Bit Number Bit Mnemonic Description 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit.
4 PS Serial port Priority bit
Refer to PSH for priority level.
3 PT1 Timer 1 overflow interrupt Priority bit
Refer to PT1H for priority level.
2 PX1 External interrupt 1 Priority bit
Refer to PX1H for priority level.
1 PT0 Timer 0 overflow interrupt Priority bit
Refer to PT0H for priority level.
0 PX0 External interrupt 0 Priority bit
Refer to PX0H for priority level.
Table 10. IPH Register The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit.
4 PSH
3 PT1H
2 PX1H
1 PT0H
0 PX0H
6.5 Idle mode
An instruction that sets PCON.0 causes that to be the last instruction executed before going into the Idle mode. at the time Idle was activated. ALE and PSEN hold at logic high levels. be executed will be the one following the instruction that put the device into idle. terminated by an interrupt, the interrupt service routine can examine the flag bits. hardware reset needs to be held active for only two machine cycles (24 oscillator periods) to complete the reset.
6.6 Power-Down Mode
To save maximum power, a power-down mode can be invoked by software (Refer to Table 6., PCON register). instruction executed. The internal RAM and SFRs retain their value until the power-down mode is terminated. is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize. and configured as level or edge sensitive interrupt input. Holding the pin low restarts the oscillator but bringing the pin high completes the exit as detailed in Figure 8. that put TS80C31X2 into power-down mode. Figure 8. Power-Down Exit Waveform Exit from power-down by either reset or external interrupt does not affect the internal RAM content. PD and IDL bits are cleared and idle mode is not entered.
Table 11. The state of ports during idle and power-down modes
6.7 ONCE Mode (ON Chip Emulation)
- Pull ALE low while the device is in reset (RST high) andPSEN is high.
- Hold ALE low as RST is deactivated. While the TS80C31X2 is in ONCE mode, an emulator or test CPU can be used to drive the circuit Table 26. shows the status of the port pins during ONCE mode. Normal operation is restored when normal reset is applied.
Table 12. External Pin Status during ONCE Mode
6.8 Power-Off Flag
The power-off flag allows the user to distinguish between a “cold start” reset and a “warm start” reset. the device and could be generated for example by an exit from power-down. Table 13. PCON Register Set to select double baud rate in mode 1, 2 or 3. Clear to select SM0 bit in SCON register. Set to to select FE bit in SCON register. The value read from this bit is indeterminate. Do not set this bit. Clear to recognize next reset type. CC rises from 0 to its nominal voltage. Can also be set by software. Cleared by user for general purpose usage. Set by user for general purpose usage. Cleared by user for general purpose usage. Set by user for general purpose usage. Cleared by hardware when reset occurs. Set to enter power-down mode. Clear by hardware when interrupt or reset occurs.
26 Rev. A - Mar. 19, 1999 Preliminary TS80C31X2 7. Electrical Characteristics
7.1 Absolute Maximum Ratings(1)
Ambiant Temperature Under Bias: C = commercial 0 °Ct o7 0°C I = industrial -40 °Ct o8 5°C Storage Temperature -65 °Ct o+1 5 0°C Voltage on VCC to VSS - 0 . 5Vt o+7V Voltage on Any Pin to VSS - 0 . 5Vt oVCC + 0.5 V Power Dissipation 1 W (2) NOTES 1. Stresses at or above those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. 2. This value is based on the maximum allowable die temperature and the thermal resistance of the package.
7.2 DC Parameters for Standard Voltage
Table 14. DC Parameters in Standard Voltage
7.3 DC Parameters for Low Voltage
Table 15. DC Parameters for Low Voltage
- Operating ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH , TCHCL = 5 ns (see Figure 12.), VIL = VSS + 0.5 V ,
- Idle ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH ,TCHCL = 5 ns, VIL =V SS + 0.5 V , VIH =V CC - 0.5 V; XTAL2
N.C; Port 0 = VCC ;EA = RST = VSS (see Figure 10.).
- Power Down I CC is measured with all output pins disconnected;EA = VSS, PORT 0 = VCC ; XTAL2 NC.; RST = VSS (see Figure 11.).
- Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL s of ALE and Ports 1 and 3. The noise is
cases (capacitive loading 100pF), the noise pulse on the ALE line may exceed 0.45V with maxi VOL peak 0.6V . A Schmitt Trigger use is not necessary.
- Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and 5V .
- Under steady state (non-transient) conditions, IOL must be externally limited as follows:
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.
- For other values, please contact your sales office.
Figure 12. Clock Signal Waveform for ICC Tests in Active and Idle Modes
7.4 AC Parameters
7.4.1 Explanation of the AC Symbols
a list of all the characters and what they stand for. AVLL = Time for Address Valid to ALE Low. TLLPL = Time for ALE Low to PSEN Low. Table 16., Table 19. and Table 22. give the description of each AC symbols. Table 17., Table 20. and Table 23. give for each range the AC parameter.
7.4.2 External Program Memory Characteristics
Table 17. AC Parameters for Fix Clock Table 16. Symbol Description
Table 18. AC Parameters for a Variable Clock
7.4.3 External Program Memory Read Cycle
Figure 13. External Program Memory Read Cycle
12 TCLCL
7.4.4 External Data Memory Characteristics
Table 19. Symbol Description
Table 20. AC Parameters for a Fix Clock
Table 21. AC Parameters for a Variable Clock
7.4.5 External Data Memory Write Cycle
Figure 14. External Data Memory Write Cycle
7.4.6 External Data Memory Read Cycle
Figure 15. External Data Memory Read Cycle
7.4.7 Serial Port Timing - Shift Register Mode
Table 23. AC Parameters for a Fix Clock Table 22. Symbol Description
Table 24. AC Parameters for a Variable Clock
7.4.8 Shift Register Timing Waveforms
Figure 16. Shift Register Timing Waveforms
7.4.9 External Clock Drive Characteristics (XTAL1)
7.4.10 External Clock Drive Waveforms
Figure 17. External Clock Drive Waveforms
7.4.11 AC Testing Input/Output Waveforms
Figure 18. AC Testing Input/Output Waveforms are made at VIH min for a logic “1” and VIL max for a logic “0”.
7.4.12 Float Waveforms
Figure 19. Float Waveforms Table 25. AC Parameters
to float when a 100 mV change from the loaded VOH /VOL level occurs. IOL /IOH ≥± 20mA.
7.4.13 Clock Waveforms
Valid in normal clock mode. In X2 mode XTAL2 signal must be changed to XTAL2 divided by two. Figure 20. Clock Waveforms are incorporated in the AC specifications.
Table 26. Maximum Clock Frequency