TRU050 VECTRON | Alldatasheet
Document overview
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- PDF pages: 14
Technical content
Features
- Output Frequencies to 65.536 MHz
- 5.0 V or 3.3Vdc Operation
- Tri-State Output
- Holdover on Loss of Signal Alarm
- VCXO with CMOS Outputs
- 0/70° or –40/85°C Temperature Range
- Ceramic SMD Package
- RoHS/Lead Free Compliant
Description
The VI TRU050 is a user-configurable crystal-based PLL integrated circuit. It includes a digital phase detector, op-amp, VCXO and additional integrated functions for use in digital synchronization applications. Loop filter software is available as well SPICE models for circuit simulation.
Applications
- Frequency Translation
- Clock Smoothing
- NRZ Clock Recovery
- DSLAM, ADM, ATM, Aggregation, Optical Switching/Routing, Base Station
- Low Jitter PLL’s
Figure 1. TRU050 Block Diagram
Table 1. Electrical Performance
- A good quality 0.01uF in parrallel with a 0.1 uf capacitor should be located as close to pin 16 to ground as possible.
- Figure 1 defines these parameters. Figure 2 illustrates the equivalent five-gate TTL load and operating conditions under which these parameters are
tested and specified. Loads greater than 15 pF will adversely effect rise/fall time and duty cycle.
- Symmetry is defined as (ON TIME/PERIOD with Vs=-1.4 V for both 5V and 3.3V operation.
Figure 2. Output Waveform Figure 3. OUT1, OUT2, RDATA and RCLK
Table 2. Absolute Maximum Ratings The TRU050 is capable of meeting the following qualification tests. Table 3. Environmental Compliance parameters used to define the model. Table 4. ESD Ratings
The phase detector has two buffered inputs, DATAIN and CLKIN, which are designed to switch at 1.4 volts. more than a few hundred millivolts. centered in the middle of the DATAIN signal, see figure 6. signals, but 0.25 could be used as a starting point for data density. such as 8kHz frequency translation, see figures 8 and 9. according to the input frequency offset, but PHO will remain relatively constant. Figure 4. Simplified Phase Detector Block Diagram
TRU050, VCXO Based PLL Vectron International, 267 Lowell Rd, Hudson NH 03051-4916 Tel: 1-88-VECTRON-1 • Web: www.vectron.com Page 6 of 14 Rev: 26Aug2008 VCXO and Absolute Pull Range (APR) Specification The TRU050’s VCXO is a varactor tuned crystal oscillator, which produces an output frequency proportional to the control voltage (pin 1). The frequency deviation of the TRU050 VCXO is specified in terms of Absolute Pull Range (APR). APR provides the user with a guaranteed specification for minimum available frequency deviation over all operating conditions. Operating conditions include operating temperature range, power supply variation, and differences in output loading and changes due to aging. A TRU050 VCXO with an APR of +/-50 ppm will track a +/-50 ppm reference source over all operating conditions. The fourth character of the product code in Table 6 specifies absolute Pull Range (APR). Please see Vectron’s web site, www.vectron.com, for the APR Application Note. VCXO Aging Quartz stabilized oscillators typically exhibit a small shift in output frequency during aging. The major factors, which lead to this shift, are changes in the mechanical stress on the crystal and mass-loading of foreign material on the crystal. As the oscillator ages, relaxation of the crystal mounting stress or transfer of environmental stress through the package to the crystal mounting arrangement can lead to frequency variations. VI has minimized these two effects through the use of a miniature AT-Cut strip resonator crystal, which allows a superior mounting arrangement, and results in minimal relaxation and almost negligible environmental stress transfer. VI has eliminated the impact of mass loading by ensuring hermetic integrity and minimizing outgassing by limiting the number of internal components through the use of ASIC technology. Mass-loading on the crystal generally results in a frequency decrease and is typically due to outgassing of material within a hermetic package or from contamination by external material in a less than hermetic package. Under normal operating conditions with an operating temperature of 40°C, the TRU050 will typically exhibit 2 ppm aging in the first year of operation. The device will then typically exhibit 1 ppm aging the following year with a logarithmic decline each year thereafter. Divide-By Feature The lowest available VCXO OUT 1 frequency is 12.000MHz. To achieve lower frequencies, such as 1.544 or 2.048 MHz, OUT1 is divided by a 2n counter , where n=1 to 8 and is the OUT2 frequency. This results in a divide by 2,4,8…256 option and is wire- bonded at the factory, so it is user selectable upon ordering only. To achieve 1.544 or 2.048MHz, a TRU050 at 24.704 with a divide by 16 or a TRU050 16.384 with a divide-by 8 would be used. Additional external divide-by circuits can be used to further lower or change the input frequency range. A disabled Out2 is available.
TRU050, VCXO Based PLL Vectron International, 267 Lowell Rd, Hudson NH 03051-4916 Tel: 1-88-VECTRON-1 • Web: www.vectron.com Page 7 of 14 Rev: 26Aug2008 Loop Filter A PLL is a feedback system which forces the output frequency to lock in both phase and frequency to the input frequency. While there will be some phase error, theory states there is no frequency error. The loop filter design will dictate many key parameters such as jitter reduction, stability, lock range and acquisition time. Be advised that many textbook equations describing loop dynamics, such as capture range or lockin time, are based on ideal systems. Such equations may not be accurate for real systems due to nonlinearities, DC offsets, noise and don’t take into account the limited VCXO bandwidth. This section deals with some real world design examples. Also, there is loop filter software on the Vectron web site, plus experienced applications engineers are eager to assist in this process. Common TRU050 PLL applications are shown in figures 7 and 8 (frequency translation), 9 (clock recovery) and 10 (clock smoothing). Of primary concern to the designer is selecting a loop filter that insures lock-in, stability and provides adequete filtering of the input signal. A good starting point for the the loop filter bandwidth is 100ppm times the DATAIN frequency. An example would be translating an 8kHz signal to 44. 736MHz – DS3 – which is = 100 ppm x kHz = 8Hz . So for 8kHz inputs, ~ 8 Hz loop bandwidth may be reasonable and figures 7 and 8 show and 8kHz to DS3 and 8kHz to 19.440 MHz frequency translation designs. It’s fairly easy to set a low loop bandwidth for large frequency translations such as 8kHz to 44.736MHz, but becomes more difficult for clock smoothing applications such as 19.440MHz in and 19.440MHz output. In this example, 100ppm x 19.440MHz is about 2kHz and may be too high to reject kow frequency jitter. A good way to resolve this is to lower the input frequency such as dividing the input frequency down. The loop filter bandwidth becomes lower since 100ppm * DATAIN is lowered. Figure 10 shows an example of how to design a low loop bandwith on a relatively high input signal and still maintain a wide lock range. The “100ppm * DATAIN frequency” loop filter bandwidth can then be tailored to the application, since lower bandwidthds are desriable to clean up and or translate clock signals and higher bandwidths may be needed for clock recovery of NRZ signals. There is no known accurate formula for calculating acquisition time and so the best way to provide realisitc figures is to measure the lock time for a TRU050. Aquistion time was measured to be 3 to 5 seconds by measuring the control voltage in an 8kHz to 34.368 MHz frequency translation application - similar to the application in figure 7 and 8, to sub 10 milliseconds for NRZ data patterns such as figure 9. It may be tempting reduce the damping factor to 0.7 or 1.0 in order to increase aquisition time; but, it degrades stability and will not signifigantly decrease lock time. This is due to the fact that most VCXO’s have a 10kHz bandwidth so setting a 100kHz loop bandwidth is impossible. A damping factor of 4 is fairly conservative and allows for excellent stability. Some general quidelines for selecting loop filter include: Values should be less than 1Megohm and at least 10Kohm between the PHO and OPN, the capacitor should be low leakage and a polarized capacitor is acceptable, the R/C’s should be located physically close to the TRU050 . Also, the loop filter software available on the web site was written for 5 volt operation, a simple way to calculate values for 3.3 volt operation is to times the data density by 0.66 (3.3V / 5V). SPICE models are another design aid. In most cases a new PLL TRU050 design is calculated by using the software and verified with SPICE models, and depending on the circumstances evaluated in the applications lab. The simple active pi model is in figure 7. Loop filter values can be modified to suit the system requirements and application. There are many excellent references on designing PLL’s, such as “Phase- Locked Loops, Theory, Design and Applications”, by Roland E Best McGraw-Hill; however, there is loop filter software on the Vectron web site, plus experienced applications engineers eager to assist in this process.
Figure 7. SPICE Model by values, and are from figure 11.
leakage and polarized capacitors are allowed keeping this is mind. ECL output). Loading unused outputs will only increase current consumption. The above loop has a 11 Hz bandwidth. Figure 8. 8kHz to DS3 Frequency Translation
44.736 MHz
The above loop has a 10 Hz bandwidth. Figure 9. 8kHz to 19.44MHz Frequency Translation The above loop has a 4.5 kHz bandwidth. Figure 10. DS3 NRZ Clock Recovery
44.736 Mb/s (Pin 7)
The above loop has a 125 Hz bandwidth. Figure 11. 19.440 Clock Smoothing Table 5. Reflow Profile (IPC/JEDEC J-STD-020C) Figure 12. Suggested IR profile
19.440 MHz
2.430 MHz
Figure 15. “Thru Hole Lead” Package Table 7. Pin Functions
1 V C VCXO Control Voltage
2 OPN Op-Amp Negative Input
3 OPOUT Op-Amp Output
4 OPP Op-Amp Positive Input
5 LOSIN INPUT (Used with LOS)
Logic 0, VCXO control voltage is enabled.
6 PHO Phase detector output
7 DATAIN Phase detector Input signal (TTL switching thresholds)
8 GND Cover and Electrical Ground
9 CLKIN Phase detector Clock signal (TTL switching thresholds)
10 LOS OUTPUT (Used with LOSIN)
CLKIN. As soon as a transition occurs at DATAIN, LOS is set to logic low.
11 RCLK Recovered Clock
12 RDATA Recovered Data
13 Output 2 Divided-down VCXO Output, or No Output
14 HIZ INPUT
Logic 0, OUT1, OUT2, RCLK, RDATA are set to a high impedance state. Logic 1, OUT1, OUT2, RCLK, RDATA are active.
15 Output 1 VCXO Output
TRU050, VCXO Based PLL Vectron International, 267 Lowell Rd, Hudson NH 03051-4916 Tel: 1-88-VECTRON-1 • Web: www.vectron.com Page 14 of 14 Rev: 26Aug2008
Ordering information
Table 8. Standard OUT1 Frequencies Table 9. Part Number Builder is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information.
Revision History
26AUG2008 BW Part number frequency format revised from xx.xxx MHz to xxMxxxxxxx.