TRCV012G5 AGERE | Alldatasheet
Document overview
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Technical content
Features
■ TRCV012G5 supports OC-48/STM-16 data rate ■ TRCV012G7 supports: — OC-48/STM-16 data rate — RS (255, 239) forward error correction (FEC) OC-48/STM-16 data rate ■ Fully-integrated limiting amplifier, clock recovery, 1:16 data demultiplexer ■ No reference clock required for CDR ■ 2.5 Gbits/s data output and 2.5 GHz recovered clock output available for wavelength division multiplex (WDM) or regenerator applications ■ Programmable limiting amplifier offset ■ Programmable data sampling phase ■ Additional CML serial data input for system loopback ■ Parity bit generation ■ Analog and digital loss of signal (LOS) indicators ■ Optional demultiplexer powerdown mode conserves power ■ Single 3.3 V supply ■ Available in either MBIC 025 BiCMOS technology or lower-power MBIC 025 silicon germanium BiCMOS technology ■ High-speed LVPECL digital I/O ■ Jitter tolerance, transfer, and generation compliant with the following: Telcordia Technologies* GR-253 — ITU-T G.825 — ITU-T G.958 ■ Loss of signal compliant with the following: Telcordia Technologies GR-253 * Telcordia Technologies is a registered trademark of Bell Com- munications Research, Inc.
Applications
■ SONET/SDH line termination equipment ■ SONET/SDH add/drop multiplexers ■ SONET/SDH cross connects ■ SONET/SDH test equipment
Description
The Lucent Technologies Microelectronics Group TRCV012G5 operates at the OC-48/STM-16 data rate of 2.5 Gbits/s. The TRCV012G7 device operates at either 2.5 Gbits/s or the RS FEC OC-48/STM-16 data rate of 2.7 Gbits/s. For clarity, this data sheet refers to the TRCV012G5 serial data rate as
2.5 Gbits/s and the parallel data and reference clock
frequency as 155 MHz. (The precise rates are 2.48832 Gbits/s and 155.52 MHz.) When using the TRCV012G7 at the FEC rate, the 2.5 Gbits/s data rate should be interpreted as 2.7 Gbits/s and the par- allel and clock frequency should be interpreted as 166 MHz. (The precise rates are 2.66606 Gbits/s and 166.62 MHz.) The devices contain a limiting amplifier with 30 dB gain, a clock and data recovery PLL with high-speed serial clock and data outputs, and a 1:16 demulti- plexer with differential PECL data and clock outputs. The device provides improved optical receiver perfor- mance when used in optically amplified systems due to a direct slice adjust input pin and a 6 ps adjust- ment capability in the slicing decision time. Both devices are available in either BiCMOS or in SiGe BiCMOS technology for lower power operation.
TRCV012G5 and TRCV012G7 Preliminary Data Sheet Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer August 2000 2 Lucent Technologies Inc. Table of Contents Contents Page
pendently powered down in applications where they are not required. The device may be used with the TTRN012G5 or TTRN012G7 transmit synthesizer and multiplexer. Note: Diagram is representative of device functionality and conceptual signal flow. Internal implementation details may be different than shown. Figure 1. Functional Block Diagram
Figure 2. Pin Diagram of 128-Pin QFP (Top View)
Table 1. Pin Descriptions—2.5 Gbits/s and Related Signals
- Differential pins are indicated by the P and N suffixes. For nondifferential pins, N at the end of the symbol name designates active-low.
resistance of 50 Ω on this pin. 30 LAINP I Analog Limiting Amplifier Inputs (2.5 Gbits/s). ■ Pins are high impedance when END2G5N = 1.
51 D2G5N
122 END2G5N I
u CMOS Enable D2G5P/N Data Outputs (Active-Low). 118 MUTE2G5N I u CMOS Mute D2G5P/N Data Output (Active-Low). 123 ENCK2G5N I u CMOS Enable CK2G5P/N Clock Output (Active-Low). 119 LOSAN O Open Drain Loss of Analog Signal (Active-Low). voltage is scaled (see Figure 7 on page 16). 120 LOSDN O Open Drain Loss of Digital Data (Active-Low). 18 LFP O Analog Loop Filter PLL. Connect LFP to VCP, and LFN to VCN.
17 LFN
19 VCP I Analog VCO Control. Connect VCP to LFP , and VCN to LFN.
16 VCN
Table 1. Pin Descriptions—2.5 Gbits/s and Related Signals (continued)
- Differential pins are indicated by the P and N suffixes. For nondifferential pins, N at the end of the symbol name designates active-low.
external DATCKP/N clock to demultiplexer.
46 DATAP I
as data source rather than limiting amplifier output. 37 ASTREF I Analog Adjustable Sampling Circuit Reference Resistor. decrements) of 6.25 ps in the sampling instant.
Table 2. Pin Descriptions—155.52 Mbits/s and Related Signals
- Differential pins are indicated by the P and N suffixes. For nondifferential pins, N at the end of the symbol name designates active-low.
resistance of 50 Ω on this pin. 101 D15P O LVPECL Data Output (155 Mbits/s). 155 Mbits/s differential data output.
100 D15N
98 D14P LVPECL
97 D14N
96 D13P LVPECL
95 D13N
93 D12P LVPECL
92 D12N
91 D11P LVPECL
90 D11N
88 D10P LVPECL
87 D10N
85 D9P LVPECL
84 D9N
83 D8P LVPECL
82 D8N
80 D7P LVPECL
79 D7N
78 D6P LVPECL
77 D6N
75 D5P LVPECL
74 D5N
73 D4P LVPECL
72 D4N
70 D3P LVPECL
69 D3N
63 D2P LVPECL
62 D2N
61 D1P LVPECL
60 D1N
58 D0P LVPECL
57 D0N
Table 2. Pin Descriptions—155.52 Mbits/s and Related Signals (continued)
- Differential pins are indicated by the P and N suffixes. For nondifferential pins, N at the end of the symbol name designates active-low.
115 PDDMXN I u CMOS Powerdown Demultiplexer Circuit (Active-Low). 117 MUTEDMXN I u CMOS Mute Data to Demultiplexer Circuit (Active-Low). 108 CK155P O LVPECL Recovered Clock Output (155 MHz). but forced to differential logic low when MUTE155N = 0.
107 CK155N
CK155P/N to logic low when MUTE155N is active. TRCV012G7 at the 0C-48/STM-16 rate of 2.48832 GHz.
110 REFCLKN
113 REFSELN I
REFCLKP/N as the input to the CDR PLL.
Table 3. Pin Descriptions—Global Signal
- Differential pins are indicated by the P and N suffixes. For nondifferential pins, N at the end of the symbol name designates active-low.
Table 4. Pin Descriptions—Power and No-Connect Signals Note:VCCA, VCCLA, and VCCD have the same dc value, which is represented as VCC unless otherwise specified. However, high-frequency filtering is suggested between the individual supplies.
- Differential pins are indicated by the P and N suffixes. For nondifferential pins, N at the end of the symbol name designates active-low.
barred data outputs are in the high state. 9, 10, 22, 23 V CCA IP o w e r Analog Power Supply (3.3 V). 24, 27, 35 V CCLA IP o w e r Limiting Amplifier Power Supply (3.3 V). CCD IP o w e r Digital Power Supply (3.3 V). 11, 12, 14, 126 NC No Connection. These pins must be left open.
frequency reference when data timing is lost. The limiting amplifier receives the input serial 2.5 Gbits/s data waveform from a transimpedance amplifier interface. A typical interface between the lightwave receiver and the limiting amplifier is shown in Figure 3. Note: It is recommended to use a differential interface from the lightwave receiver device with ac coupling. form in accordance with the specifications shown in Table 9. Figure 3. Typical TIA to Limiting Amplifier Interface approximated as 166 Mbits/s. The exact frequencies are used only when necessary for clarity.
2.5 GHz recovered clock are available as outputs, as well as a 155 MHz clock derived from the recovered clock. loop dynamic response (see Table 5). Table 5. Clock Recovery Loop Filter Component Values
- Capacitor C1 should be either ceramic or nonpolar.
Figure 4. Clock Recovery PLL Loop Filter Components signal or a 223 – 1 PRBS data signal is applied. Table 9 on page 20, and the data sequence is a valid OC-48 SONET/SDH signal. Table 6. Clock and Data Recovery Generated Jitter Specifications
- This denotes the device specification for system SONET/SDH compliance when the loop filter in Table 5 and Figure 4 is used.
TRCV012G5 and TRCV012G7 Preliminary Data Sheet Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer August 2000 12 Lucent Technologies Inc. Clock and Data Recovery (CDR) (continued) CDR Input Jitter Tolerance The limiting amplifier plus CDR’s jitter tolerance performance meets the requirement shown in Figure 5 on page 13 when the limiting amplifier’s input signal is within the valid level range given in Table 9 on page 20, the loop filter in Figure 4 is used, and the data sequence is a valid OC-48 SONET/SDH signal. CDR Jitter Transfer Using the loop filter in Figure 4, the CDR’s jitter transfer performance meets the requirement shown in Figure 6 when the input jitter magnitude is within the jitter tolerance requirements given in Figure 5 and the data sequence is a valid OC-48 SONET/SDH signal. This specification applies to the jitter transferred from the limiting amplifier’s input to the 2.5 Gbits/s recovered clock pins (CK2G5P/N).
TRCV012G5 and TRCV012G7 Preliminary Data Sheet Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer August 2000 14 Lucent Technologies Inc. Clock and Data Recovery (CDR) (continued) Data Path Configuration Option (ENDATAN) Either the limiting amplifier (LAINP/N) or a CML logic level input (DATAP/N) can be selected as the source of the 2.5 Gbits/s data signal. The DATAP/N input can be used if the limiting amplifier is not needed, or it can be used as a system loopback path when the limiting amplifier is the normal data path. If the limiting amplifier is not used in normal operation, the LAINP/N pins should be grounded through a series ac coupling of 0.1 µF. High-Speed Serial Clock and Data Output Enables (ENCK2G5N, END2G5N) Separate output enables are provided for the 2.5 GHz recovered clock output (CK2G5P/N) and the 2.5 Gbits/s data output (D2G5P/N). These enables are active-low CMOS inputs with internal pull-up resistors. A ground or logic low applied to the pin enables the corresponding output. When disabled, the pins should be either left floating, or be connected to a load which returns to V CC . The high-speed serial clock and data outputs must not be con- nected directly to ground when they are disabled. High-Speed Serial Data Output Mute (MUTE2G5N) The 2.5 Gbits/s data output (D2G5P/N) may be forced to a logic-low state using MUTE2G5N. This may be desir- able if the quality of the input data is suspect, as may be the case under LOSA or LOSD conditions. MUTE2G5N is an active-low CMOS input. Data and CDR Configuration Options (REFSELN, INLOSN, MUTEDMXN) A 155 MHz clock (REFCLKP/N) may optionally be provided as a frequency reference to the clock recovery PLL in order to control the recovered clock frequency when data timing is lost, as may be the case under LOSA or LOSD conditions. If REFCLKP/N is provided, REFSELN can be used to select REFCLKP/N as the frequency reference to the clock recovery PLL. The INLOSN pin will force the VCO to decrease to its minimum frequency. This will prevent the VCO frequency from drifting to a high value during invalid signal conditions. INLOSN may be used to limit the recovered clock fre- quency in systems that do not provide a REFCLKP/N signal. The MUTEDMXN pin will force logic-low data into the demultiplexer, and therefore, keep all demultiplexer outputs in the logic-low state. MUTEDMXN will not affect the operation of the CDR circuits. This may be desirable if the quality of the input data is suspect as may be the case under LOSA or LOSD conditions. The user may utilize the REFSELN, INLOSN, and MUTEDMXN pins in any combination to achieve the desired response under LOS conditions.
The AST control bit configurations and corresponding offset times are shown in Table 7. Table 7. Adjustable Sampling Time (AST) Control Code step should be scaled down by 7%.
requirements on declaring loss of signal. fier’s input may be amplified and appear to be a data transition. This may change the state of LOSDN. (LOSA) threshold. As shown in Figure 7, applying a voltage to the PRG_LOSA pin will adjust the LOSA trip point. CC and ground may be used to set the PRG_LOSA level if the VCC tolerance and variability is adequate. Figure 7. Typical LOSA Threshold vs. PRG_LOSA Voltage vs. Data Pattern
the serial input data stream. Figure 8. Serial Input to Parallel Output Data Relationship the parity pin is a logic 1 when the number of 1s in the output register is an odd number.
vide a dc path when using an ac-coupled load. schematic of a typical CML output structure is shown in Figure 9. Figure 9. Typical CML Output Structure flexibility in termination schemes.
periods can adversely affect device reliability. Table 8. Recommended Operating Conditions
TRCV012G5 and TRCV012G7 Preliminary Data Sheet Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer August 2000 20 Lucent Technologies Inc.
Electrical Characteristics
Limiting Amplifier Specifications Table 9. Limiting Amplifier Characteristics to maintain the CDR frequency lock without any data input. applied to the REFCLKP/N input. clock can be applied to the REFCLKP/N input. Table 10 provides the characteristics of the REFCLKP/N input. Table 10. Reference Frequency Characteristics requiring a reduced temperature range may specify the reference frequency oscillator accordingly.
100 MHz—2 GHz
2 GHz—3 GHz
- For Table 11 through Table 18, VCC = 3.3 V ± 5%, TA = –40 °C to +85 °C; these tables apply to both MBIC 025
BiCMOS and MBIC 025 SiGe BiCMOS technologies.
- For more information on interpreting CML specifications, see the CML Output Structure (Used on Pins
D2G5P/N, CK2G5P/N) section on page 18. Table 11. LVPECL Input Pin Characteristics Table 12. LVPECL Output Pin Characteristics Table 13. CMOS Input Pin Characteristics Table 14. Open Drain Output Pin Characteristics
Table 15. CML Input Pin dc Characteristics Table 16. CML Output Pin dc Characteristics
- Applies when RREF1 = 1 kΩ.
† Applies when RREF1 = 1.8 kΩ. ‡ Applies when RREF1 = 6 kΩ.
data (D[15:0]P/N) and the output parity (PARITYP/N) are shown in Figure 10. Figure 10. Transmit Timing Waveform with 155 MHz or 166 MHz Clock The 155 MHz or 166 MHz output clock and data signals from Figure 10 are characterized in Table 17. Table 17. LVPECL Output Pin ac Timing Characteristics
2.7 Gbits/s output data (D2G5P/N) is shown in Figure 11. Figure 11. Transmit Timing Waveform with 2.5 GHz or 2.7 GHz Clock The 2.5 GHz or 2.7 GHz output clock and data signals from Figure 11 are characterized in Table 18. Table 18. CML Output Pin ac Timing Characteristics
2.66606 GHz Clock Period — 375 — ps
Preliminary Data Sheet TRCV012G5 and TRCV012G7 August 2000 Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer 25Lucent Technologies Inc. Outline Diagram 128-Pin QFP Dimensions are in millimeters. 5-8416(F)r.2 3.30 (REF) 0.50 (TYP) 2.80 (REF) 38 65 102 103128 17.20 ± 0.20 19.86 ± 0.10 6439 LUCENT Code Name YYWWL XXXXXKNV 0.38 (REF) DETAIL A 11.43 ± 0.18 23.20 ± 0.20 13.89 ± 0.10 8.13 (REF) 2.89 (REF) 17.52 ± 0.18 8.13 (REF) 0.20 ± 0.06 0.000 TO 0.100 8.13 (REF)2.89 (REF) (8.13)2 x 0.305 HEAT SINK 5.87 (REF) 0.800 ± 0.150 1.600 ± 0.150 DETAIL A
Figure 12. Heat Sink Ground Pattern application more heat sinking may be required. be greater than 300 °C and the soldering time for each lead must not exceed 5 seconds. Table 19. Thermal Resistance
0.050 HEAT SINK
Preliminary Data Sheet TRCV012G5 and TRCV012G7 August 2000 Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer 27Lucent Technologies Inc.
Ordering Information
DS00-234HSPL Replaces DS00-154HSPL to Incorporate the Following Updates 1. Added a second technology, MBIC 025 SiGe BiCMOS, to the data sheet. 2. Page 8, REFCLKP/N pins, corrected definition. 3. Page 11, Table 5, updated C1, R1, and R2 values in Clock Recovery Loop Filter Component Values. 4. Page 19, Absolute Maximum Ratings, added maximum power supply value of 4.0 V. 5. Page 19, Handling Precautions, corrected ESD threshold value from TBD to ≥200 V. 6. Page 19, Table 8, corrected BiCMOS power dissipation from TBD to 3.43 W in Recommended Operating Con- ditions; added MBIC 025 SiGe BiCMOS power dissipation values. 7. Page 19, Table 8, added junction temperature in Recommended Operating Conditions. 8. Page 21, Table 12, corrected values in LVPECL Output Pin Characteristics. 9. Page 23, Table 17, updated minimum duty cycle from 40% to 48%, maximum duty cycle from 60% to 52%, and tDD1 minimum value from 2.5 ns to 2.9 ns in LVPECL Output Pin ac Timing Characteristics. 10. Page 26, added the section Board Installation Recommendations and Thermal Considerations (MBIC 025 BiCMOS and MBIC 025 SiGe BiCMOS). 11. Page 27, Ordering Information, added MBIC 025 SiGe BiCMOS comcodes. Device Code Package Temperature Comcode (Ordering Number) TRCV012G5: TRCV012G5 (BiCMOS) TRCV012G53XE1 (SiGe BiCMOS) 128-pin QFP 128-pin QFP –40 °C to +85 °C –40 °C to +85 °C 108419953 108700675 TRCV012G7: TRCV012G7 (BiCMOS) TRCV012G73XE1 (SiGe BiCMOS) 128-pin QFP 128-pin QFP –40 °C to +85 °C –40 °C to +85 °C 108560343 108700683 —— — —
TRCV012G5 and TRCV012G7 Preliminary Data Sheet Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer August 2000 Lucent T echnologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information. Copyright © 2000 Lucent T echnologies Inc. All Rights Reserved August 2000 DS00-234HSPL (Replaces DS00-154HSPL) For additional information, contact your Microelectronics Group Account Manager or the following: INTERNET: http://www.lucent.com/micro E-MAIL: docmaster@micro.lucent.com N. AMERICA: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, P A 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA P ACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA: Microelectronics Group, Lucent T echnologies (China) Co., Ltd., A-F2, 23/F , Zao Fong Universe Building, 1800 Zhong Shan Xi Road, Shanghai 200233 P . R. China Tel. (86) 21 6440 0468, ext. 325, FAX (86) 21 6440 0652 JAP AN: Microelectronics Group, Lucent T echnologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, T okyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: MICROELECTRONICS GROUP DA T ALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 T echnical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 3507670 (Helsinki), IT AL Y: (39) 02 6608131 (Milan), SP AIN: (34) 1 807 1441 (Madrid)