TPP206080-QFMR-S

TPP20608 3PEAK | Alldatasheet

Document overview

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• PDF pages: 22

Technical content

Features

• Ultra-low RDS(ON) 18-mΩ and 15-mΩ MOSFETs
• 200-kHz to 1.6-MHz Adjustable Switching Frequency
• Integrated PLL to Synchronize with External Clock
• Adjustable UVLO Voltage and Hysteresis
• Under-voltage and Over-voltage Power Good Output
• Adjustable Soft-Start and Sequencing
• Full-Current Range Low-dropout Operation
• Hiccup Current Limit
• 0.6-V (TPP206080) / 0.8-V (TPP206081) 1% Internal Voltage Reference
• 14-Pin QFN3.5X3.5-14 with Exposed Pad Package
• −40°C to 125°C Ambient Temperature Range

Applications

• 5-V, 12-V Industrial Power Application
• High-Density Point-of-Load Regulation
• Telecom & Communication Equipment Power

Description

The TPP20608x is a series of 17-V, 6-A output, synchronous, step-down, switch-mode converters with integrated power MOSFETs. The TPP20608x series employs current mode control supporting simple external compensation and flexible component selection. With the integrated phase-locked loop, the TPP20608x series can synchronize with external clock source with wide frequency selection, optimized for efficiency, physical dimensions, and electromagnetic interference (EMI). Protection and diagnostics features protect the device as well as the system power supply. By using open-drain power-good output, the system is able to distinguish if the output supply is within the target voltage range. Soft-start features, which control the output ramping, can be set independently by an external resistor or to sequencing/tracking mode. Current-limit and over- temperature protection improve system-level robustness. Typical Application Circuit PHVIN GND BOOT VSENSE COMP EN RT/CLK SS/TR PWRGD VOUT VIN 4.5 – 17V TPP20608 EN LO TPP20608x 17-V Input, 6-A, Synchronous Step-Down DC-DC Voltage Converter www.3peak.com 1 / 22 EA20230403A2

17-V Input, 6-A, Synchronous Step-Down DC-DC Voltage Converter www.3peak.com 2 / 22 EA20230403A2

Revision History

2022-11-28 Rev.A.0 Initial revision. 2023-04-24 Rev.A.1 Updated TPP206081 reference voltage and minor fix. 2023-11-07 Rev.A.2 Misc. update on package and reel infomation TPP20608x 17-V Input, 6-A, Synchronous Step-Down DC-DC Voltage Converter www.3peak.com 3 / 22 EA20230403A2

Table 1. Pin Functions: TPP36208 BOOT 13 Bootstrap capacitor between BOOT and PH. Recommend using a 0.1-µF ceramic capacitor with a 10-V or higher voltage rating. COMP 8 Error amplifier output and input to the PWM comparator. Connect the frequency compensation network to this pin. PWRGD 14 Open-drain power-good output. VIN 4, 5, 6 Supply voltage with 4.5-V to 17-V operating range. VSENSE 7 Feedback input, connected to the internal inverting input of gm error amplifier.

Absolute Maximum Ratings (1) Parameter Min Max Unit VIN Supply Voltage −0.3 20 V PH Switching Node Voltage −1 20 V PH 5-ns Transient Switching Node Voltage −4 20 V PH 10-ns Transient Switching Node Voltage −3 20 V BOOT-PH Bootstrap Voltage −0.3 6.5 V VSENSE Feedback Voltage −0.3 3 V COMP Compensation −0.3 3 V EN Enable Input −0.3 6 V PWRGD Power Good −0.3 6 V SS/TR −0.3 3 V RT/CLK −0.3 6 V TJ Maximum Junction Temperature 150 °C TA Operating Junction Temperature Range −40 125 °C TSTG Storage Temperature Range −65 150 °C TL Lead Temperature (Soldering 10 sec) 260 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. (2) The inputs are protected by ESD protection diodes to each power supply. If the input extends more than 300 mV beyond the power supply, the input current should be limited to less than 10 mA. (3) A heat sink may be required to keep the junction temperature below the absolute maximum. This depends on the power supply voltage and how many amplifiers are shorted. Thermal resistance varies with the amount of PC board metal connected to the package. The specified values are for short traces connected to the leads. ESD, Electrostatic Discharge Protection Symbol Parameter Condition Minimum Level Unit HBM Human Body Model ESD ANSI/ESDA/JEDEC JS-001 (1) 2 kV CDM Charged Device Model ESD ANSI/ESDA/JEDEC JS-002 (2) 1 kV (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. TPP20608x 17-V Input, 6-A, Synchronous Step-Down DC-DC Voltage Converter www.3peak.com 5 / 22 EA20230403A2

Recommended Operating Conditions Parameter Min Typ Max Unit VIN Input Voltage 4.5 17 V IOUT Output Current 6 A TJ Operating Junction Temperature −40 150 ℃ Thermal Information Package Type θJA θJC Unit QFN3.5X3.5-14 30.8 39.1 °C/W TPP20608x 17-V Input, 6-A, Synchronous Step-Down DC-DC Voltage Converter www.3peak.com 6 / 22 EA20230403A2

Electrical Characteristics

All test condition is at VIN = 4.5 V to 17 V, Tj = −40°C to +125°C, unless otherwise noted. Parameter Conditions Min Typ Max Unit Power Supply VIN Operating Voltage Range 4.5 17 V V(UVLO) Internal Undervoltage Lockout Threshold Rising Threshold 4 4.5 V V(UVLO,hys) 150 mV IQ Quiescent Supply Current EN = 5 V, TA = 25 °C, V(VSENSE) = 0.81 V, TPP206080 1.1 1.7 mA IQSD Shut-down Supply Current EN = 0 V, TA = 25 °C 2 5 μA VSENSE Voltage V(VSENSE) VSENSE Voltage TPP206080 0.594 0.6 0.606 V TPP206081 0.792 0.8 0.808 V MOSFFET HSRDSON HS Switching on Resistance VIN = 12 V, BOOT − SW =

6 V 18 32 mΩ

LSRDSON LS Switching on Resistance VIN = 12 V 15 28 mΩ Current Limit ILimit-HS High-side Switch Current Limit Threshold 8 11 14 A ILimit-LS-source Low-side Switch Sourcing Current Limit Threshold 6.5 10 15 A ILimit-LS-sink Low-side Switch Sinking Current Limit Threshold 2 3 4 A NHiccup-deg Number of Clock Cycle for Hiccup Deglitch 512 Cycles NHiccup-prot Number of Clock Cycle for Hiccup Protection 16384 Cycles Error Amplifier I(SENSE) Input Current 1 nA gm Error Amplifier Transconductance −2 μA < ICOMP < 2 μA, VCOMP = 1 V 1300 μMhos ADC Error Amplifier Gain V(FB) = 0.8 V 86 V/V I(COMP) Error Amplifier Output Current Capability V(COMP) = 1 V , 100mV overdrive ±130 μA gCOMP-SW COMP to SW Current Transconductance 16 A/V TPP20608x 17-V Input, 6-A, Synchronous Step-Down DC-DC Voltage Converter www.3peak.com 7 / 22 EA20230403A2

Parameter Conditions Min Typ Max Unit Thermal Shutdown TSD Thermal Shut-down Temperature 175 °C THYS Thermal Hysteresis 15 °C Power Good (PWRGD) Vth(UV-falling) Output Undervoltage Falling Threshold 92 % Vth(UV-rising) Output Undervoltage Rising Threshold 94 % Vth(OV-falling) Output Overvoltage Falling Threshold 106 % Vth(OV-rising) Output Overvoltage Rising Threshold 104 % Ilkg(PWRGD) PWRGD Leakage Current(1) V(PWRGD) = 5.5 V 30 100 nA Rdson(PWRGD) PWRGD on-resistance I(PWRGD) = 3 mA , VFB <

0.79 V 30 Ω

V(minVIN,PWRGD Minimal VIN for Defined Output V(PWRGD) < 0.5 V , I(PWRGD) = 100 μA 1.8 2.4 V Soft Start and Tracking (SS/TR) I(SS/TR) Soft-start Charging Current V(SS/TR) = 0.4V 2.3 μA ∆V(SS/TR) SS/TR to FB Matching Error V(SS/TR) = 0.4V 20 mV I(SS/TR),disch Max SS/TR Discharge Current V(FB) = 0 V, V(SS/TR) = 0.4V 1300 μA V(SS/TR), disch SS/TR Discharge Voltage V(FB) = 0 V 30 mV V(SS/TR), th SS/TR to Reference Cross-over Threshold 1.16 V LOGIC VEN_rising EN Rising Threshold Voltage 1.21 1.26 V VEN_falling EN Falling Threshold Voltage 1.1 1.17 V IEN EN threshold + 50 mV −4.6 μA EN threshold − 50 mV −0.58 −1.2 −1.8 μA IEN,hys EN Hysteresis −2.2 −3.4 −4.5 μA Vth(RT/CLK),rising RT/CLK Rising Threshold 1.55 2 V Vth(RT/ CLK),falling RT/CLK Falling Threshold 0.8 1.2 V Timing Characteristics tOCP Over-current Protection Delay 60 ns td,EN Enable COMP Delay 540 μs tCLK,min Minimal CLK Input Pulse Width 15 ns td,CLK RT/CLK falling edge to SW rising edge delay fSW = 500 kHz 55 ns TPP20608x 17-V Input, 6-A, Synchronous Step-Down DC-DC Voltage Converter www.3peak.com 8 / 22 EA20230403A2

Parameter Conditions Min Typ Max Unit fSW Switching Frequency RT = 240 kΩ 160 200 240 kHz RT = 100 kΩ 400 480 560 kHz RT = 29 kΩ 1440 1600 1760 kHz Switching frequency using RT mode (1) 100 1600 kHz Switching frequency using CLK mode 160 1600 kHz Dmax Maximum dutycycle TPP20608x supports maximum full- on 100% tPLL PLL lock in time fSW = 500 kHz 78 μs (1) Guranteed by design. TPP20608x 17-V Input, 6-A, Synchronous Step-Down DC-DC Voltage Converter www.3peak.com 9 / 22 EA20230403A2

device employs peak-current-mode control mechanism to improve transient performance as well as line and load regulations. The low-Rdson MOSFETs are designed to optimize low output voltage applications with current up to 6 A. external clock using PLL mode when a clock signal is detected on RT/PLL. has open-drain power good indicator PWRGD if the VSENSE pin voltage is within the desired range. Figure 12. Functional Block Diagram

Fixed Frequency Peak Current Mode Control The TPP20608x employs peak current mode control with adjustable switching frequency. The feedback voltage is sensed through VSENSE pin to compare with internal voltage reference by an error amplifier. The output of the error amplifier is compared by PWM comparator with internal voltage ramp and controls power switch. Internal oscillator controls the frequency of switching high-side MOSFET. The high-side switching current is sensed internally as part of the voltage ramp. Once the PWM comparator detects peak switching current reaches the threshold level set by COMP voltage, the high-side MOSFET is switched off and the low-side MOSFET is switched on. During light-load operation, the device will enter forced-PWM mode with the same switching frequency. The transconductance error amplifier converts the error voltage between VSENSE pin voltage and internal voltage, whichever lower of the soft-start voltage or internal voltage reference V REF, to current with transconductance gm of 1300 μMhos during normal operation conditions. It is recommended to connect compensation network between COMP and GND pin to ensure stability across all working ranges. The details are discussed in the application chapter. Setting Output Voltage The precision internal voltage reference produces a 0.6-V voltage reference (TPP206080) and 0.8-V voltage reference (TPP206081) with ±1% tolerance across operating temperature and voltage ranges. The resistor divider from output voltage to FB pin sets the output voltage. RH = RL × VOUT − VFB VFB (1) Soft-Start with Pre-Biased Capability The device uses SS node to implement a programmable soft-start feature by controlling ramping up reference voltage. The reference voltage will be the lower of internal reference voltage and SS voltage. The timing of soft-start is programmable via external capacitor connected to SS node. An internal constant-current source of 2.3 µA charges up the external SS/TR capacitor to an internally clamped 2.7V. The timing can be calculated as below equation, measured from 10% to 90%. Reference voltage is 0.6V for TPP206080 and 0.8V for TPP206081. TSS = VREF × CSS × 90% − 10% ISS (2) To ensure proper start-up, the device will discharge SS/TR voltage upon powering up if SS/TR voltage is above 54 mV. During any case the device stops switching, such as undervoltage lockout (UVLO), EN pulled low or over temperature protection, the device will discharge SS/TR below 54mV before switching. The device also supports using SS/TR input for tracking as well as power supply sequencing. Sequencing needs to be carefully designed to ensure the system is able to recover from any fault. RT/CLK The device supports wide switching frequency from 200kHz to 1600kHz. The frequency is programmable via resistor connected between RT/CLK and GND. The switching frequency will affect solution size, efficiency, and minimal duty cycle. It is suggested that all factors taken care of when selecting switching frequency. The resistor can be calculated via equation RRT kΩ = 48000⋅fSW −0.997 − 2 (3) TPP20608x 17-V Input, 6-A, Synchronous Step-Down DC-DC Voltage Converter www.3peak.com 13 / 22 EA20230403A2

The device switching clock supports external clock sources for synchronization. Once a square wave is applied at the RT/CLK pin, the rising edge of SW synchronizes to the falling edge of RT/CLK. It is also suggested to connect a frequency set resistor to RT/CLK pin in case external clock source is not available. The first rising edge of RT/CLK sets the device from free-running frequency mode to synchronization mode. The internal 0.5V voltage source is removed and the RT/CLK is set to high impedance mode. It takes 78µs to lock on external clock frequency; When external clock source stops, the device will switch back to free running frequency mode with frequency set by external resistor. During the transition, the device frequency will stay at 70kHz and then switch to the free-running frequency. Protection Undervoltage Lockout (UVLO) The device has undervoltage lockout feature with default rising threshold of 4V. It can be adjusted by using EN pin with external resistors. A weak current source of 1.2 µA pulls up the EN pin to internal voltage rail. Another 3.4-µA hysteresis current source provides hysteresis voltage between rising and falling threshold. The resistor values can be calculated via below equations. VSYS_UVLO_His the desired system level undervoltage protection rising threshold voltage, VSYS_UVLO_Lis the desired system level undervoltage protection falling threshold voltage. RUVLOH and RUVLOL are depicted in Figure 13. RUVLOH = VSYS_UVLO_H ⋅ VEN_rising VEN_falling − VSYS_UVLO_L IEN ⋅ 1 − VEN_rising VEN_falling + IEN, hys (4) RUVLOL = RUVLOH ⋅VEN_falling VSYS_UVLO_L − VEN_falling + RUVLOH ⋅ IEN + IEN, hys (5) V EN I EN I EN_hys EN VIN R UVLOH R UVLOL Figure 13. Over-Current Protection The device employs peak current mode control by controlling the peak current of internal high-side power transistor. The high side transistor current is converted to a voltage signal and compared to COMP pin. When the peak switching current is above the threshold set by COMP voltage, the device turns off high-side power transistor. When the device is in over current scenario, the output voltage is pulled low and device will increase switching current threshold until it reaches the internal current limit threshold. Once the switching current is above the threshold, the device will turn off the transistor as current limit. Delay needs to be taken in to account that may cause the peak inductor current slightly higher than open-loop current limit. Once the over current load is removed, the device will resume normal operation in the following cycle. Power Good The device uses an open-drain output PWRGD to signal if the output voltage is operating within the boundaries. If the FB voltage is within the 94% and 104% of internal reference voltage, the PWRGD pull-down will be disabled and pulled up by TPP20608x 17-V Input, 6-A, Synchronous Step-Down DC-DC Voltage Converter www.3peak.com 14 / 22 EA20230403A2

externally resistor. The external pull up voltage source is recommended to be less than 5.5V with a 1kΩ resistor. If FB voltage is lower than 92% or greater than 106% of internal reference voltage, the PWRGD will be pulled low. If UVLO, over temperature protection or EN going low, the PWRGD will also be pulled low. When supply voltage is below 2.4V, the PWRGD may not be at any defined state. Over-Voltage Protection The device stops high-side FET switching when it detects FB voltage above the over voltage protection (OVP) rising threshold (106% of internal reference voltage). When the voltage falls below the falling threshold (104% of internal reference voltage), it resumes switching high-side FET. With the OVP feature, the device can minimize voltage overshoot during load transient with low output capacitance. Over-Temperature Shutdown When the devices sense the junction temperature above the internal rising threshold of 175°C, the device stops high-side FET switching. Once the device junction temperature falls below falling threshold 165°C, the device restart the device with power up sequence. The device will discharge the SS/TR to GND as part of power up sequence. Care must be taken that the SS/TR is able to be pulled low to avoid deadlock scenario that may prevent the device re-start. TPP20608x 17-V Input, 6-A, Synchronous Step-Down DC-DC Voltage Converter www.3peak.com 15 / 22 EA20230403A2

Application and Implementation Note Information in the following application sections is not part of the 3PEAK’s component specification and 3PEAK does not warrant its accuracy or completeness. 3PEAK’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

Application Information

As an easy-to-use step-down voltage regulator, also known as a buck regulator, the TPP20608x series usually converts a higher input voltage to the desired output voltage set by the VSENSE resistor divider. The maximum output current is 6 A. The below section depicts a simplified design flow of circuitry for the TPP20608x series. In most 12-V systems, lower voltage rail such as 3.3 V is a typical need for microcontrollers, I/Os, and other low-voltage components. The below application lists the typical schematic for a 3.3-V buck regulator. This application describes detailed information about the design of a switching regulator and a few parameters must be known to start the design process. These parameters are typically determined at the system level. For this application, begin with the known parameters listed in Table 2. Table 2. Application Parameter Selection

• The VIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor with X5R or X7R dielectric, and the bypass capacitor should also be located as close as possible to the IC PIN.
• It is needed to minimize the loop area formed by the bypass capacitor connections, the VIN pins, and the ground connections.
• Because of the switching node PH, the output inductor should be located close to the PH pins, and the area of the PCB conductor is minimized to prevent excessive capacitive coupling.
• The RT/CLK pin is sensitive to noise so the RT resistor must be located as close as possible to the IC pin. Layout Recommendations Top Layer Bottom Layer TPP20608x 17-V Input, 6-A, Synchronous Step-Down DC-DC Voltage Converter www.3peak.com 17 / 22 EA20230403A2

(mm) (mm) (mm) (mm) (mm) (mm) (mm) Pin1 Quadrant TPP206080- QFMR-S QFN3.5X3. 5-14 330 17.6 3.75 3.75 1.0 8 12 Q1 TPP206081- QFMR-S QFN3.5X3. 5-14 330 17.6 3.75 3.75 1.0 8 12 Q1 TPP206080- QFMR QFN3.5X3. 5-14 330 17.6 3.75 3.75 1.0 8 12 Q1 TPP206081- QFMR QFN3.5X3. 5-14 330 17.6 3.75 3.75 1.0 8 12 Q1 TPP20608x 17-V Input, 6-A, Synchronous Step-Down DC-DC Voltage Converter www.3peak.com 18 / 22 EA20230403A2

Package Outline Dimensions QFN3.5X3.5-14 TPP20608x 17-V Input, 6-A, Synchronous Step-Down DC-DC Voltage Converter www.3peak.com 19 / 22 EA20230403A2

Order Number Operating Temperature Range Package Marking Information MSL Transport Media, Quantity Eco Plan TPP206080-QFMR-S −40 to 125°C QFN3.5X3.5-14 2680 3 Tape and Reel, 4000 Green TPP206081-QFMR-S −40 to 125°C QFN3.5X3.5-14 2681 3 Tape and Reel, 4000 Green TPP206080-QFMR −40 to 125°C QFN3.5X3.5-14 2680 3 Tape and Reel, 4000 Green TPP206081-QFMR −40 to 125°C QFN3.5X3.5-14 2681 3 Tape and Reel, 4000 Green Green: 3PEAK defines "Green" to mean RoHS compatible and free of halogen substances. TPP20608x 17-V Input, 6-A, Synchronous Step-Down DC-DC Voltage Converter www.3peak.com 20 / 22 EA20230403A2

IMPORTANT NOTICE AND DISCLAIMER Trademarks. Any of the 思瑞浦 or 3PEAK trade names, trademarks, graphic marks, and domain names(“Trademarks”) contained in this document/material are the property of 3PEAK. You may NOT reproduce, modify, publish, transmit or distribute any Trademark without the prior written consent of 3PEAK. Performance Information. Performance tests or performance range contained in this document/material are results of design simulation or actual tests conducted under designated testing environment. Any differences in testing environment or simulation environment, including but not limited to testing method, testing process or testing temperature, may affect actual performance of the product. Forward-Looking Statements. The information in this document/material may contain forward-looking statements, except for statements or descriptions of historical facts. These forward-looking statements are based upon our current understanding of our industry, management philosophy and certain assumptions and speculative calculations. These forward-looking statements are subject to risks and uncertainties and our actual results may differ. Please do not rely solely on the above information to make your business decisions. Disclaimer. 3PEAK provides technical and reliability data (including data sheets), design resources (including reference designs), application or other design recommendations, networking tools, security information and other resources "As Is". 3PEAK makes no warranty as to the absence of defects, and makes no warranties of any kind, express or implied, including, without limitation, implied warranties as to merchantability, fitness for a particular purpose or non-infringement of any third-party’s intellectual property rights. TPP20608x 17-V Input, 6-A, Synchronous Step-Down DC-DC Voltage Converter www.3peak.com 21 / 22 EA20230403A2

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