TPM27224 3PEAK | Alldatasheet

Document overview

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  • PDF pages: 16

Technical content

Features

  • Industry-Standard Pin-out
  • 4.5-V to 23-V Single-Supply Range
  • Dual Independent Channels
  • 2-A Peak Source and Sink-Drive Current
  • Independent-Enable Function for Each Output
  • TTL and CMOS Compatible Threshold
  • Outputs Held Low during VDD-UVLO or Input Floating
  • Low Propagation Delay (13-ns Typical)
  • Fast Rise and Fall Times (7-ns and 6-ns Typical)
  • <1-ns Typical Delay Matching Between Two Channels
  • Two Outputs can be used in Parallel for Higher Drive Current
  • ESD Protection Exceeds JESD 22 – 4-kV HBM, 1.5-kV CDM
  • Available in SOP8 and DFN2X2-8 Packages

Applications

  • Switched-Mode Power Supplies
  • DC-DC Converters
  • Motor Control, Solar Inverters
  • Gate & IGBT Drive
  • Piezo Driver

Description

The TPM2722x family is a series of dual-channel low-side gate drivers for MOSFET, IGBT, and GaN power switches. High sourcing and sinking current capability of 2 A allows for improving switching efficiencies by minimizing slew time and switching loss. The device supports maximum 25-V supply voltage and −5 V DC input voltage capability, which improves system robustness, especially in noisy industrial applications. Ultra-low propagation delay and excellent matching between two channels are designed for applications with tight timing requirements. The TPM2722x family consists of a set of gate drivers with different polarities, allowing customers to select based on application needs. Typical Application Circuit ENA INA GND INB ENB OUTA VDD OUTB TPM27224 TPM27224 Dual 2-A High-Speed, Low-Side Gate Driver www.3peak.com 1 / 16 EA20220902A1

Dual 2-A High-Speed, Low-Side Gate Driver www.3peak.com 2 / 16 EA20220902A1

Revision History

2023-11-16 Rev.A.0 Initial released version 2024-03-11 Rev.A.1 Misc. correction TPM27224 Dual 2-A High-Speed, Low-Side Gate Driver www.3peak.com 3 / 16 EA20220902A1

Table 1. Pin Functions: TPM27224

1 ENA Input Channel A Enable Input

8 ENB Input Channel B Enable Input

3 GND Ground Device Ground

2 INA Input Non-inverting Input

4 INB Input Non-inverting Input

7 OUTA Output Channel A Output

5 OUTB Output Channel B Output

6 VDD Power Power Supply Input

Absolute Maximum Ratings(1) Parameter Min Max Unit Power Supply Voltage, VDD –0.3 25 V Output Voltage Range OUTA, OUTB –0.3 VDD + 0.3 V –2 VDD + 0.3 (200-ns pulse) Input Voltage Range INA, INB, ENA, ENB –5 20 V Pulsed Output Channel Current OUTA, OUTB (500 ns) –2 2 A Operating Junction Temperature Range –40 150 °C TSTG Storage Temperature Range –65 150 °C TL Lead Temperature (Soldering, 10 sec) 260 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. (2) The inputs are protected by ESD protection diodes to each power supply. If the input extends more than 300 mV beyond the power supply, the input current should be limited to less than 10 mA. (3) Power dissipation and thermal limits must be observed. ESD, Electrostatic Discharge Protection Parameter Condition Minimum Level Unit HBM Human Body Model ESD ANSI/ESDA/JEDEC JS-001 (1) ±4 kV CDM Charged Device Model ESD ANSI/ESDA/JEDEC JS-002 (2) ±1.5 kV (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Recommended Operating Conditions Parameter Min Max Unit Power Supply Voltage, VDD 4.5 23 V Input Voltage Range INA, INB, ENA, ENB 0 20 V Operating Ambient Temperature Range –40 125 °C Thermal Information Package Type θJA θJC Unit SOP8 122.3 60.4 °C/W DFN2X2-8 55 50 °C/W TPM27224 Dual 2-A High-Speed, Low-Side Gate Driver www.3peak.com 5 / 16 EA20220902A1

Electrical Characteristics

All test conditions: VDD = 18 V, TJ = −40 °C to 150 °C, and 1-μF capacitor between VDD and GND, unless otherwise noted. Parameter Conditions Min Typ Max Unit IDD(off) Start-up Current VDD = INA = INB = 3.4 V 54 80 μA VON Supply under Voltage Lock Out Rising Threshold TJ = −40 °C – 150 °C 3.5 3.85 4.2 V VOFF Supply Under Voltage Lock-out Falling Threshold TJ = −40 °C – 150 °C 3.3 3.6 4 V VDD_H Supply Under Voltage Lock-out Hysteresis 0.25 V VEN_H Enable High Threshold Enable high threshold 1.7 2.1 V VEN_L Enable Low Threshold Enable low threshold 1 1.15 V VEN_HYS Enable Hysteresis 0.55 V VIN_H Input Signal High Threshold Input high threshold 1.7 2.1 V VIN_L Input Signal Low Threshold Input low threshold 1 1.15 V VIN_HYS Input Hysteresis 0.55 V IOUT Output Peak Current CLOAD = 0.22 μF, FSW = 1 kHz ±2 A ROH Output Pull-up Resistance, PMOS Pull-up only IOUT = −10 mA 3 6 10 Ω ROL Output Pull-down Resistance IOUT = 10 mA 0.5 0.93 1.6 Ω VOH Output Pull-up Voltage, PMOS pull- up only, VDD – VOUT IOUT = −10 mA 100 mV VOL Output Pull-down Voltage IOUT = 10 mA 3 16 mV tR Output Rise-Time CLOAD= 1 nF 9 ns tF Output Fall-Time CLOAD = 1 nF 8 ns tM Delay matching between OUTA and OUTB INA = INB, OUTA and OUTB measured at 50% 1 4 ns tD1 Input to Output Propagation Delay CLOAD = 1 nF, 5-V INx pulse 18 ns tD2 Input to Output Propagation Delay CLOAD = 1 nF, 5-V INx pulse 14 ns tD3 Enable to Output Propagation Delay CLOAD = 1 nF, 5-V ENx pulse 18 ns tD4 Enable to Output Propagation Delay CLOAD = 1 nF, 5-V ENx pulse 14 ns TPM27224 Dual 2-A High-Speed, Low-Side Gate Driver www.3peak.com 6 / 16 EA20220902A1

Figure 1. Input Timing Diagram Figure 2. Enable Timing Diagram

300 Input = GNDInput = VDD

Figure 3. Quiescent Current vs. Temperature

4.5 UVLO RisingUVLO Falling

Figure 4. UVLO Threshold vs Temperature

2.8 INA High ThresholdINA Low ThresholdINB High ThresholdINB Low Threshold

Figure 5. Input Threshold vs Temperature

2.8 ENA High ThresholdENB High ThresholdENA Low ThresholdENB Low Threshold

Figure 6. Enable Threshold vs Temperature

10 CH ACH B

Figure 7. Output Pull-up Resistance vs Temperature

2 CH ACH B

Figure 8. Output Pull-down Resistance vs Temperature Figure 9. Channel A Rising Edge by INA Figure 10. Channel A Falling Edge by INA Figure 11. Channel B Rising Edge by INB Figure 12. Channel B Falling Edge by INB

controls, and inverters. Designed with industrial standard pin-out and package, the TPM27224 accelerates design process. Figure 19. Functional Block Diagram

Low Propagation Delay Driver Outputs The low-propagation-delay design allows the device to achieve industrial leading low propagation delay between inputs and outputs. The low delay enhances driver performance in high-frequency switching regulators. Matching between two channels is optimized to support parallel driving. 3PEAK recommends tying IN1 and IN2 locally together with a high input slew rate, to avoid shoot-through between the two well-matched channels. Capacitors are not recommended on IN1 and IN2 nodes when used in parallel. Supply and UVLO The device monitors supply voltage with under-voltage lock-out (UVLO). When the supply voltage is below the UVLO threshold, the outputs are held low in UVLO to avoid glitches during power rising and falling. The device quiescent current and operating current are measured as shown in Figure 5. The current is related to internal quiescent current consumption as well as the output current. The output current can be calculated using external transistor gate charge times switching frequency fsw. Channel Input The input of the TPM27224 gate drivers supports TTL and CMOS input with threshold voltage independent of the supply voltage. The threshold is also designed as temperature independent to support a wide range of ambient temperatures. Wide hysteresis enhances system-level noise immunity. The integrated pull-up and pull-down resistors set the device state when inputs are floating. EN supports the NC connection with the help of internal pull-up resistors. Inputs can withstand DC −5 V, to improve robustness on ground bouncing. Output Stage The TPM27224 output stage is able to deliver high-current sourcing and sinking up to 2-A with low-propagation delay. The delay matching between dual channels is also optimized within 1-ns. In the case of higher output driving capabilities needed, the TPM27224 allows paralleling the dual channel to achieve a higher driving current. In this case, it is recommended to use a high slew rate on IN1 and IN2 and connect IN1 and IN2 to avoid shoot through between channels. TPM27224 Dual 2-A High-Speed, Low-Side Gate Driver www.3peak.com 11 / 16 EA20220902A1

（mm） （mm） （mm） （mm） （mm） （mm） （mm） Pin1 Quadrant TPM27224- TPM27224- TPM27224 Dual 2-A High-Speed, Low-Side Gate Driver www.3peak.com 12 / 16 EA20220902A1

Package Outline Dimensions SOP8 TPM27224 Dual 2-A High-Speed, Low-Side Gate Driver www.3peak.com 13 / 16 EA20220902A1

Dual 2-A High-Speed, Low-Side Gate Driver www.3peak.com 14 / 16 EA20220902A1

Order Number Operating Ambient Temperature Range Package Marking Information MSL Transport Media, Quantity Eco Plan TPM27224-SO1R -40 °C to 125 °C (1) SOP8 224 3 Tape and Reel, 4000 Green TPM27224-DF4R -40 °C to 125 °C (1) DFN2X2-8 224 3 Tape and Reel, 3000 Green (1) Ambient temperature indicates device operation condition range. Application thermal behavior needs to be taken care of when operating in high-temperature scenarios. Green: 3PEAK defines "Green" to mean RoHS compatible and free of halogen substances. TPM27224 Dual 2-A High-Speed, Low-Side Gate Driver www.3peak.com 15 / 16 EA20220902A1

IMPORTANT NOTICE AND DISCLAIMER Copyright© 3PEAK 2012-2024. All rights reserved. Trademarks. Any of the 思瑞浦 or 3PEAK trade names, trademarks, graphic marks, and domain names contained in this document /material are the property of 3PEAK. You may NOT reproduce, modify, publish, transmit or distribute any Trademark without the prior written consent of 3PEAK. Performance Information. Performance tests or performance range contained in this document/material are either results of design simulation or actual tests conducted under designated testing environment. Any variation in testing environment or simulation environment, including but not limited to testing method, testing process or testing temperature, may affect actual performance of the product. Disclaimer. 3PEAK provides technical and reliability data (including data sheets), design resources (including reference designs), application or other design recommendations, networking tools, security information and other resources "As Is". 3PEAK makes no warranty as to the absence of defects, and makes no warranties of any kind, express or implied, including without limitation, implied warranties as to merchantability, fitness for a particular purpose or non-infringement of any third- party’s intellectual property rights. Unless otherwise specified in writing, products supplied by 3PEAK are not designed to be used in any life-threatening scenarios, including critical medical applications, automotive safety-critical systems, aviation, aerospace, or any situations where failure could result in bodily harm, loss of life, or significant property damage. 3PEAK disclaims all liability for any such unauthorized use. TPM27224 Dual 2-A High-Speed, Low-Side Gate Driver www.3peak.com 16 / 16 EA20220902A1