TPL9208-S

TPL9208-S 3PEAK | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 30

Technical content

Features

• Input Voltage Range of DFN Package: – 1.4 V to 6.5 V
• Output Voltage Range of DFN Package: – Adjustable Output Voltage: 0.8 V to 5.2 V
• Input Voltage Range of QFN Package: – Without BIAS: 1.4 V to 6.5 V – With BIAS: 1.1 V to 6.5 V
• Output Voltage Range of QFN Package: – Adjustable Output Voltage: 0.8 V to 5.2 V – Fixed Output Voltage: 0.8 V to 3.95 V
• ±1% Output Accuracy over Line, Load Regulation, and Operating Temperature Range
• 2-A Maximum Output Current
• Dropout Voltage: 200 mV Maximum at 2 A
• PSRR: – 72 dB at 1 kHz – 60 dB at 1 MHz
• 3.3-μVRMS Output Voltage Noise
• Excellent Transient Response
• Enable and Adjustable Soft-Start Control
• Open-Drain Power-Good Output
• Stable with a 22-μF or Greater Ceramic Capacitor
• Over-Current and Over-Temperature Protection
• Operating Temperature: −40°C to +125°C
• Package Options: – DFN2.5X2.5-10 – QFN5X5-20

Applications

• Communication: CPU, ASIC, FPGA, CPLD, DSP
• High-Performance Analog: ADC, DAC, LVDS, VCO
• Noise-Sensitive Imaging: CMOS Sensors, Video ASICs

Description

The TPL9208 series of products are 2-A high-current, 3.3-μVRMS low-noise, high-PSRR, high-accuracy linear regulators with typically 150-mV ultra-low dropout voltage at 2-A load condition. The TPL9208 series of products support both fixed output voltage ranging from 0.8 V to 3.95 V and adjustable output voltage ranging from 0.8 V to 5.2 V with external resistor dividers. Ultra-low noise, high-PSRR, and high-output-current capabilities make the TPL9208 series an ideal power supply for noise-sensitive applications, such as high-speed communication facilities, test and measurement devices, or high-definition imaging equipment. Accurate output voltage tolerance, output voltage remote sensing, excellent transient response, and flexible soft-start control ensure the TPL9208 series an optimal power supply for large- scale processors and digital loads, such as CPU, ASIC, FPGA, CPLD, and DSP. The TPL9208 series of products provide 10-pin DFN2.5X2.5 and 20-pin QFN5X5 packages with guaranteed operating junction temperature ranging from −40°C to +125°C. Typical Application Circuit IN EN OUT FB PG NR/SS GND GND C NR/SS C IN VIN Digital I/O or VIN C OUT VOUT TPL9208 DFN2.5X2.5 -10 IN BIAS EN 1.6V 800mV 400mV 200mV 100mV 50mV SNS OUT FB PG NR/SS GND GND Optional VBIAS C NR/SS C BIAS C IN VIN Digital I/O or VIN C OUT VOUT TPL9208 QFN5X5 -20 TPL9208-S Series 2-A Output, High-PSRR, Low-Noise LDO Regulator www.3peak.com 1 / 30 DA20221003A3

2-A Output, High-PSRR, Low-Noise LDO Regulator www.3peak.com 2 / 30 DA20221003A3

Order Number Output Voltage (V) Package TPL9208AD-DF5R-S Adjustable (0.8 V ~ 5.2 V) DFN2.5X2.5-10 TPL9208AD-QF7R-S Adjustable (0.8 V ~ 5.2 V) QFN5X5-20

Revision History

2022-02-15 Rev.Pre.0 Preliminary Revision. 2022-04-11 Rev.Pre.1 Updated Order Information. 2022-10-28 Rev.Pre.2 Updated Typical Performance Characteristics. 2022-12-15 Rev.A.0 Initial Released. 2023-11-16 Rev.A.1 Updated Typical Performance Characteristics. 2024-02-07 Rev.A.2 Updated Electrical Characteristics (QFN Package). 2024-04-06 Rev.A.3 Updated Thermal Information and Noise Test Waveforms. TPL9208-S Series 2-A Output, High-PSRR, Low-Noise LDO Regulator www.3peak.com 3 / 30 DA20221003A3

Table 1. Pin Functions: TPL9208 open when using external resistor dividers.

17 IN I

previous-stage power supply. 6 – NC – No internal connection.

Pin Name I/O DescriptionDFN2.5X 2.5-10 QFN5X5- 1, 2 1, 19, 20 OUT O Regulated output voltage pin. A 22-μF or larger ceramic capacitor from OUT to ground (as close as possible to OUT pin) is required to ensure regulator stability. 5 4 PG O Open-drain power-good output pin. Leave PG pin open when not used. – 2 SNS I Output voltage sense input pin. Connect this pin to the load side of the output trace only when using fixed output voltage. Leave this pin open when using external resistor divider. TPL9208-S Series 2-A Output, High-PSRR, Low-Noise LDO Regulator www.3peak.com 5 / 30 DA20221003A3

Absolute Maximum Ratings (1) Parameter Min Max Unit IN, BIAS, EN, PG −0.3 7 V OUT, SNS −0.3 VIN + 0.3 (2) V NR/SS, FB −0.3 3.6 V 50 mV, 100 mV, 200 mV, 400 mV, 800 mV, 1.6 V −0.3 VOUT + 0.3 V TJ Maximum Junction Temperature −40 150 °C TSTG Storage Temperature Range −65 150 °C TL Lead Temperature (Soldering 10 sec) 260 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. (2) The absolute maximum rating is VIN + 0.3 V or 7.0 V, whichever is smaller. ESD, Electrostatic Discharge Protection Parameter Condition Minimum Level Unit HBM Human Body Model ESD ANSI/ESDA/JEDEC JS-001 (1) ±4 kV CDM Charged Device Model ESD ANSI/ESDA/JEDEC JS-002 (2) ±1.5 kV (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. TPL9208-S Series 2-A Output, High-PSRR, Low-Noise LDO Regulator www.3peak.com 6 / 30 DA20221003A3

Recommended Operating Conditions Parameter Min Typ Max Unit IN Input Voltage Range of DFN Package 1.4 6.5 V IN Input Voltage Range of QFN Package 1.1 6.5 V BIAS BIAS Voltage Range of QFN Package 3 6.5 V OUT Output Voltage 0.8 5.2 V CIN Input Capacitor 10 µF COUT Output Capacitor 10 22 µF CNR/SS NR/SS Capacitor 10 1000 nF RPG Power-good Pull-up Resistor 10 100 kΩ TJ Junction Temperature Range –40 125 °C Thermal Information Package Type θJA θJB θJC,TOP Unit QFN5X5-20 34.13 8.14 20.8 °C/W TPL9208-S Series 2-A Output, High-PSRR, Low-Noise LDO Regulator www.3peak.com 7 / 30 DA20221003A3

Electrical Characteristics (General) All test conditions: TJ = −40°C to +125°C (typical value at T J = +25°C), VIN = VOUT(NOM) + 0.4 V or 1.4 V, whichever is greater; VOUT(NOM) = 0.8 V, V EN = 1.1 V, C IN = 10 µF, C OUT = 10 µF, C NR/SS = 0 nF, C FF = 0 nF, OUT connect to 50 Ω to ground, PG connected to 100 kΩ to OUT, unless otherwise noted. Parameter Conditions Min Typ Max Unit Enable and Power Good VIH(EN) EN High-level Input Voltage Device enable 1.1 6.5 V VIL(EN) EN Low-level Input Voltage Device disable 0 0.4 V IEN EN Pin Current VIN = 6.5 V, VEN = 0 V to 6.5 V −0.5 0.5 µA VPG PG Pin Threshold VOUT falling 82% 84% 88% × VOUT Hysteresis 2% × VOUT VOL(PG) PG Low-level Output Voltage VOUT < VPG, source 1 mA to PG pin 0.4 V IPG PG Pin Leakage Current VOUT > VPG, apply 6.5 V at PG pin 1 µA Regulated Output Voltage and Current VOUT Output Voltage Range 0.8 5.2 V Accuracy (1) VOUT = 0.8 V to 5.2 V, IOUT = 5 mA to 2 A −1% 1% ΔVOUT Line Regulation VIN = 1.4 V to 6.5 V, IOUT = 5 mA 0.03 mV/V Load Regulation VIN = 1.4 V, IOUT = 5 mA to 2 A 0.7 mV/A VFB Feedback Voltage 0.8 V IFB FB Pin Leakage Current VIN = 6.5 V, stress VFB = 0.8V −100 100 nA VNR/SS NR/SS Pin Voltage 0.8 V ILIM Output Current Limit VIN = VOUT(NOM) + 0.4 V, VOUT is forced at 90% × VOUT(NOM) 2.1 3.4 A ISC Short-circuit Current Limit RLOAD ≤ 20 mΩ 1.5 A RDIS Output Discharge Resistance VEN = 0 250 Ω Temperature Range TSD Thermal Shutdown Threshold Temperature increasing 160 °C Hysteresis 20 °C TJ Operating Temperature −40 125 °C (1) Resistor tolerances are not included. The device is not tested under conditions where VIN > VOUT + 2.5 V and IOUT = 2 A because the power dissipation is higher than the maximum rating of the package. TPL9208-S Series 2-A Output, High-PSRR, Low-Noise LDO Regulator www.3peak.com 8 / 30 DA20221003A3

Electrical Characteristics (DFN Package) All test conditions: TJ = −40°C to +125°C (typical value at T J = +25°C), VIN = VOUT(NOM) + 0.4 V or 1.4 V, whichever is greater; VOUT(NOM) = 0.8 V, V EN = 1.1 V, C IN = 10 µF, C OUT = 10 µF, C NR/SS = 0 nF, C FF = 0 nF, OUT connect to 50 Ω to ground, PG connected to 100 kΩ to OUT, unless otherwise noted. Parameter Conditions Min Typ Max Unit Supply Voltage and Current VIN (1) Input Supply Voltage Range 1.4 6.5 V UVLO Input Supply UVLO VIN rising 1.39 V Hysteresis 200 mV IGND GND Pin Current VIN = 6.5 V, IOUT = 5 mA 5 15 mA VIN = 1.4 V, IOUT = 2 A 5 15 mA ISD Shutdown Current VIN = 6.5 V, VEN = 0.5 V, PG = open 68 µA Regulated Output Voltage and Current INR/SS NR/SS Pin Charging Current VIN = 6.5 V, VNR/SS = 0 6 7.8 9 µA VDO Dropout Voltage VIN = 1.4 V, IOUT = 1 A, VFB = 0.8 V − 3% 40 100 mV VIN = 1.4 V, IOUT = 2 A, VFB = 0.8 V − 3% 80 200 mV VIN = 5.4 V, IOUT = 2 A, VFB = 0.8 V − 3% 80 200 mV VIN = 5.6 V, IOUT = 2 A, VFB = 0.8 V − 3% 80 200 mV PSRR and Noise PSRR Power Supply Ripple Rejection VIN = 1.4 V, VOUT = 0.8 V, IOUT = 2 A, COUT = 22 μF, CNR/SS = 10 nF, CFF = 10 nF 1 kHz 63 dB 10 kHz 60 dB

1 MHz 60 dB

Noise Output Noise Voltage BW = 10 Hz to 100 kHz, VIN = 1.4 V, VOUT = 0.8 V, IOUT = 2 A, COUT = 22 μF, CNR/SS = 10 nF, CFF = 10 nF 3.3 μVRMS BW = 10 Hz to 100 kHz, VIN = 5.5 V, VOUT = 5.2 V, IOUT = 2 A, COUT = 22 μF, CNR/SS = 10 nF, CFF = 10 nF 10 μVRMS (1) Minimum VIN = VOUT(NOM) + VDO or 1.4 V, whichever is greater. TPL9208-S Series 2-A Output, High-PSRR, Low-Noise LDO Regulator www.3peak.com 9 / 30 DA20221003A3

Electrical Characteristics (QFN Package) All test conditions: TJ = −40°C to +125°C (typical value at T J = +25°C), VIN = VOUT(NOM) + 0.4 V or 1.4 V, whichever is greater; VBIAS = open, V OUT(NOM) = 0.8 V, V EN = 1.1 V, CIN = 10 µF, COUT = 10 µF, CNR/SS = 0 nF, CFF = 0 nF, OUT connect to 50 Ω to ground, PG connected to 100 kΩ to OUT, unless otherwise noted. Parameter Conditions Min Typ Max Unit Supply Voltage and Current VIN (1) Input Supply Voltage Range 1.1 6.5 V VBIAS Bias Supply Voltage Range VIN = 1.1 V 3 6.5 V UVLOIN1 Input Supply UVLO VIN rising, VBIAS = 3 V 1.09 V Hysteresis 200 mV UVLOIN2 Input Supply UVLO VIN rising, VBIAS = open 1.39 V Hysteresis 200 mV UVLOBIA S BIAS Supply UVLO VBIAS rising, VIN = 1.1 V 2.9 V Hysteresis 200 mV IGND GND Pin Current VIN = 6.5 V, IOUT = 5 mA 5 15 mA VIN = 1.4 V, IOUT = 2 A 5 15 mA VIN = 1.1 V, VBIAS = 3 V, IOUT = 2 A 5 15 mA ISD Shutdown Current VIN = 6.5 V, VEN = 0.5 V, PG = open 68 µA IBIAS BIAS Pin Current VIN = 1.1 V, VBIAS = 6.5 V, IOUT = 2 A 2.5 5 mA Regulated Output Voltage and Current VOUT Output Voltage Range Fixed 0.8 3.95 V Adjustable 0.8 5.2 V INR/SS NR/SS Pin Charging Current VIN = 6.5 V, VNR/SS = 0 6 7.8 9 µA VDO Dropout Voltage VIN = 1.4 V, IOUT = 1 A, VFB = 0.8 V − 3% 40 100 mV VIN = 1.4 V, IOUT = 2 A, VFB = 0.8 V − 3% 80 200 mV VIN = 5.4 V, IOUT = 2 A, VFB = 0.8 V − 3% 80 200 mV VIN = 5.6 V, IOUT = 2 A, VFB = 0.8 V − 3% 80 200 mV VIN = 1.1 V, VBIAS = 3 V, IOUT = 1 A, VFB =

0.8 V − 3% 40 100 mV

VIN = 1.1 V, VBIAS = 3 V, IOUT = 2 A, VFB =

0.8 V − 3% 80 200 mV

VIN = 5.5 V, VOUT = 5.2 V, IOUT = 2 A, CNR/SS = 10 nF, CFF = 10 nF 1 kHz 72 dB VIN = 5.5 V, VOUT = 5.2 V, VBIAS = 3 V, IOUT = 2 A, CNR/SS = 10 nF, CFF = 10 nF 1 kHz 72 dB 2-A Output, High-PSRR, Low-Noise LDO Regulator www.3peak.com 10 / 30 DA20221003A3

Parameter Conditions Min Typ Max Unit VN Output Noise Voltage BW = 10 Hz to 100 kHz, VIN = 1.1 V, VBIAS = 3 V, VOUT = 0.8 V, IOUT = 2 A, COUT = 22 μF, CNR/SS = 10 nF, CFF = 10 nF 3.3 μVRMS BW = 10 Hz to 100 kHz, VIN = 5.5 V, VOUT = 5.2 V, IOUT = 2 A, COUT = 22 μF, CNR/SS = 10 nF, CFF = 10 nF 10 μVRMS (1) Minimum VIN = VOUT(NOM) + VDO or 1.4 V or 1.1 V with VBIAS = 3 V, whichever is greater. TPL9208-S Series 2-A Output, High-PSRR, Low-Noise LDO Regulator www.3peak.com 11 / 30 DA20221003A3

CPU, ASIC, FPGA, CPLD, and DSP. Figure 18. Functional Block Diagram (DFN Package)

Figure 19. Functional Block Diagram (QFN Package) off, and when the VEN ramps above VIH(EN), the LDO device turns on. down below VIL(EN), the output voltage is discharged through the internal resistive path. package only) or adjustable output voltage by external resistors. Equation 1 to calculate the output voltage. Table 2 provides a full list of different output voltage targets and the corresponding pin settings.

Table 2. Fixed Output Voltage Setting

calculate the output voltage.

• the feedback voltage VFB is 0.8 V
• R1 is the high-side feedback resistor
• R2 is the low-side feedback resistor Table 3 provides a list of recommended resistor combinations to achieve the common output voltage values.

Table 3. External Resistor Combinations

Output Soft-Start Control (NR/SS) The TPL9208 series integrates an adjustable soft-start function to control the output voltage ramp-up slew rate and start-up time. By selecting the external capacitor at the NR/SS pin (CNR/SS), the output start-up time can be calculated with Equation 3. tSTRATUP = 1.25 ×VNR/SS × CNR/SS INR/SS (3) Where,

• the typical value of VNR/SS is 0.8 V
• the typical value of INR/SS is 7.8 uA
• CNR/SS is the external capacitor at the NR/SS pin Charge Pump Noise The TPL9208 series integrates a charge pump to improve the PSRR and transient response under low input voltage conditions, and the TPL9208 series generates a minimal amount of noise at the frequency of around 15 MHz. It is recommended to use 10-nF to 100-nF bypass capacitors close to the load a ferrite bead between the LDO output and the load input capacitors, forming a pi-filter to reduce the high-frequency noise level. Power Good (PG) The TPL9208 series integrates an open-drain output power good indicator. Connect the PG pin to a pull-up voltage through a resistor from 10 kΩ to 100 kΩ if the power good function is used. Or left the PG pin open if it is not used. After regulator startup, the PG pin keeps low impendence until the output voltage reaches the power good threshold V PG,TH. When the output voltage is higher than V PG,TH, the PG pin turns to high output impedance, and PG is pulled up to a high voltage level to indicate the output voltage is ready. Output Active Discharge The TPL9208 series integrates an output discharge path from OUT to GND. When the device is disabled, and either EN or VIN is lower than the turn-on threshold, the output will actively discharge the output voltage through an internal resistor of several hundred ohms. Do not rely on this active discharge circuit for discharging large output capacitors when the input voltage falls below the output voltage. Reverse current flow through internal power MOSFET can permanently damage the device, and external current protection is essential in this condition. Over-Current Protection and Short-to-Ground Protection The TPL9208 series integrates an internal current limit that helps to protect the device during fault conditions.
• When the output is pulled down below the target output voltage, over-current protection starts to work and limit the output current to a typical value of 3.4 A.
• When the output is shorted to ground directly, short-to-ground protection starts to work and limit the output current to ISC. Under over-current conditions, the internal junction temperature ramps up quickly. When the junction temperature is high enough, it will cause over-temperature protection. Over-Temperature Protection The recommended operating junction temperature range is from −40°C to 125°C. When the junction temperature is between 125°C and the thermal shutdown (TSD) threshold, the regulator can still work well, but will reduce the device lifetime for long-term use. TPL9208-S Series 2-A Output, High-PSRR, Low-Noise LDO Regulator www.3peak.com 19 / 30 DA20221003A3

The over-temperature protection works when the junction temperature exceeds the thermal shutdown (TSD) threshold, which turns off the regulator immediately. When the device cools down and the junction temperature falls below a value, which equals to thermal shutdown threshold minus thermal shutdown hysteresis, the regulator turns on again. TPL9208-S Series 2-A Output, High-PSRR, Low-Noise LDO Regulator www.3peak.com 20 / 30 DA20221003A3

To ensure loop stability, the TPL9208 series requires a 10- μF or greater output capacitor. 3PEAK recommends selecting an X7R-type 22-μF ceramic capacitor with low ESR over temperature. Both input capacitors and output capacitors must be placed as close to the device pins as possible. Power Dissipation During normal operation, LDO junction temperature should not exceed 125°C. Using below equations to calculate the power dissipation and estimate the junction temperature. The power dissipation can be calculated using Equation 4. PD = VIN − VOUT × IOUT + VIN × IGND (4) The junction temperature can be estimated using Equation 5. θJA is the junction-to-ambient thermal resistance. TJ = TA + PD × θJA (5) TPL9208-S Series 2-A Output, High-PSRR, Low-Noise LDO Regulator www.3peak.com 23 / 30 DA20221003A3

• Both input capacitors and output capacitors must be placed to the device pins as close as possible, and the vias between capacitors and device power pins must be avoided.
• It is recommended to bypass the input pin to ground with a 0.1-μF bypass capacitor. The loop area formed by the bypass capacitor connection, the IN pin and the GND pin of the system must be as small as possible.
• It is recommended to use wide and thick copper to minimize I×R drop and heat dissipation.
• Exposed pad must be connected to the PCB ground plane directly, the copper area must be as large as possible. TPL9208-S Series 2-A Output, High-PSRR, Low-Noise LDO Regulator www.3peak.com 24 / 30 DA20221003A3

Order Number Package D1 (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P0 (mm) W0 (mm) Pin1 Quadrant TPL9208AD- DF5R-S DFN2.5X2.5-1 0 180 12.3 2.7 2.7 0.7 4 8 Q2 TPL9208-S Series 2-A Output, High-PSRR, Low-Noise LDO Regulator www.3peak.com 25 / 30 DA20221003A3

Order Number Package D1 (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P0 (mm) W0 (mm) Pin1 Quadrant TPL9208AD- QF7R-S QFN5X5-20 329 16.4 5.3 5.3 1.1 8 12 Q2 TPL9208-S Series 2-A Output, High-PSRR, Low-Noise LDO Regulator www.3peak.com 26 / 30 DA20221003A3

Package Outline Dimensions DFN2.5X2.5-10 TPL9208-S Series 2-A Output, High-PSRR, Low-Noise LDO Regulator www.3peak.com 27 / 30 DA20221003A3

2-A Output, High-PSRR, Low-Noise LDO Regulator www.3peak.com 28 / 30 DA20221003A3

Order Number Operating Temperature Range Package Marking Information MSL Transport Media, Quantity Eco Plan TPL9208AD-DF5R-S −40 to 125°C DFN2.5X2.5-10 L92 MSL3 4,000 Green TPL9208AD-QF7R-S −40 to 125°C QFN5X5-20 L928A MSL3 3,000 Green Green: 3PEAK defines "Green" to mean RoHS compatible and free of halogen substances. TPL9208-S Series 2-A Output, High-PSRR, Low-Noise LDO Regulator www.3peak.com 29 / 30 DA20221003A3

IMPORTANT NOTICE AND DISCLAIMER Copyright© 3PEAK 2012-2024. All rights reserved. Trademarks. Any of the 思瑞浦 or 3PEAK trade names, trademarks, graphic marks, and domain names contained in this document /material are the property of 3PEAK. You may NOT reproduce, modify, publish, transmit or distribute any Trademark without the prior written consent of 3PEAK. Performance Information. Performance tests or performance range contained in this document/material are either results of design simulation or actual tests conducted under designated testing environment. Any variation in testing environment or simulation environment, including but not limited to testing method, testing process or testing temperature, may affect actual performance of the product. Disclaimer. 3PEAK provides technical and reliability data (including data sheets), design resources (including reference designs), application or other design recommendations, networking tools, security information and other resources "As Is". 3PEAK makes no warranty as to the absence of defects, and makes no warranties of any kind, express or implied, including without limitation, implied warranties as to merchantability, fitness for a particular purpose or non-infringement of any third- party’s intellectual property rights. Unless otherwise specified in writing, products supplied by 3PEAK are not designed to be used in any life-threatening scenarios, including critical medical applications, automotive safety-critical systems, aviation, aerospace, or any situations where failure could result in bodily harm, loss of life, or significant property damage. 3PEAK disclaims all liability for any such unauthorized use. TPL9208-S Series 2-A Output, High-PSRR, Low-Noise LDO Regulator www.3peak.com 30 / 30 DA20221003A3