TPL51200

TPL51200 3PEAK | Alldatasheet

Document overview

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Technical content

Features

◼ VIN Voltage: Support 2.5-V, 3.3-V and 5-V Power Rails ◼ VLDOIN Voltage Range: 1.1 V to 3.5 V ◼ Flexible Input Voltage Tracking Directly from REFIN or Through External Resistor Divider ◼ 3-A Sink and Source Current Capability for DDR Termination ◼ Integrated Power MOSFETs ◼ Output Remote Sensing ◼ Fast Load-Transient Response ◼ Open-Drain Power Good to Monitor OUT Regulation ◼ Built in Soft-Start and UVLO, Current Limit and Thermal Shutdown Protection ◼ Support DDR, DDR2, DDR3, DDR3L, Low Power DDR3 and DDR4 VTT Applications ◼ Operating Temperature Range: –40°C to +125°C ◼ Small Package with 3×3 DFN-10 ◼ Pb−Free and are RoHS Compliant

Applications

◼ Memory VTT Regulator for DDR, DDR2, DDR3, DDR3L, Low Power DDR3 and DDR4 ◼ Notebooks, Desktops, and Workstations ◼ Servers, Networking equipment and Datacenters ◼ Telecom and Base Station

Description

With the development of main processors in PCs and servers, more and more source double -data-rate (DDR) memories are required in the mainboard, where the input voltage becomes lower and lower, and space limitation becomes higher and higher. The TPL51200 series devices are 3-A sink and source DDR termination regulator s specifically designed for the DDR applications with heavy space limitation. The TPL51200 series devices implement a fast load-transient response and only requires a minimum output capacitance of 20 μF. The TP L51200 series devices support a remote -sensing function and all power requirements for DDR VTT bus termination. In addition, the TP L51200 series devices provide an open-drain PG signal for VTT regulation indication and an EN signal that can be used to discharge VTT for DDR applications. The TPL51200 series devices are available in the thermally efficient 10-pin 3×3 DFN package with thermal pad, and support the operating temperature range from –40°C to +125°C. Typical Application Schematic TPL51200 REFIN 1 nF 10 kΩ 10 kΩ

2 LDOIN

0.1 μF10 μF

3 OUT

10 μF GND 10 μF10 μF

4 PGND

5 SNS

100 kΩ 9PG 8GND 7EN 6REFOUT 0.1 μF 4.7 μF VDDQ = 1.2 V VLDOIN = VDDQ = 1.2 V VTT = 0.6 V VIN = 3.3 V PG Signal to I/O Enable Signal VTTREF = 0.6 V

www.3peak.com Rev.A.1 TPL51200 Series 3-A Sink and Source DDR Termination Regulator Product Family Table Part Number Output Current Orderable Number Package Transport Media, Quantity MSL Marking information TPL51200 3 A TPL51200-DF8R 3×3 DFN-10 4,000 MSL3 L200

www.3peak.com Rev.A.1 TPL51200 Series 3-A Sink and Source DDR Termination Regulator Table of Contents

www.3peak.com Rev.A.1 TPL51200 Series 3-A Sink and Source DDR Termination Regulator

Revision History

2019/11/30 Rev.Pre Preliminary Version 2020/05/15 Rev.A.0 Initial Released 2020/12/22 Rev.A.1 1. Add Tape and Reel Information 2. Update Package Outline Dimensions

www.3peak.com Rev.A.1 TPL51200 Series 3-A Sink and Source DDR Termination Regulator Pin Configuration and Functions TPL51200 Series Top View REFIN LDOIN OUT PGND SNS 5 6 10 IN PG GND EN REFOUT Exposed PAD Pin Functions NAME PIN NUMBER TYPE DESCRIPTION EN 7 I Regulator enable pin. Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For automatic startup, connect EN to VIN directly. GND 8 − Ground reference pin. Connect GND pin to PCB ground plane directly. IN 10 I Regulator power supply i nput pin. A 1-μF or larger ceramic capacitor from IN to ground (as close as possible to IN pin) is required to reduce the jitter from previous-stage power supply. LDOIN 2 I LDO power supply input pin. OUT 3 O LDO output voltage pin. Total capacitance of 20-μF or larger from OUT to ground (as close as possible to OUT pin) is required to ensure regulator stability. PG 9 O Open-drain power-good output pin. PGND 4 − Power ground pin. Connect PGND pin to PCB ground plane directly. REFIN 1 I Reference input pin. For DDR application, set to VDDQ/2 through resistor divider. REFOUT 6 O Reference output pin. Connect to ground through a 0.1-μF to 1-μF ceramic capacitor. SNS 5 I LDO output voltage sense pin. Connect SNS to the remote DDR termination bypass capacitors to get accurate remote feedback sensing of OUT voltage. (1) Exposed PAD must be connected to a large-area ground plane to maximum the thermal performance.

www.3peak.com Rev.A.1 TPL51200 Series 3-A Sink and Source DDR Termination Regulator Specifications Absolute Maximum Ratings MIN MAX UNIT EN, IN, LDOIN, PG, REFIN, SNS –0.3 6 V PGND to GND –0.3 0.3 V OUT, REFOUT –0.3 3.6 V TJ Junction Temperature Range –40 150 °C TSTG Storage Temperature Range –55 150 °C TL Lead Temperature (Soldering 10 sec) 260 °C (1) Stresses beyond the Absolute Maximum Ratings may permanently damage the device. (2) All voltage values are with respect to GND. ESD Ratings Condition Minimum Level Unit HBM Human Body Model ESD ANSI/ESDA/JEDEC JS-001 ±2000 V CDM Charged Device Model ESD ANSI/ESDA/JEDEC JS-002 ±1500 V Recommended Operating Conditions MIN MAX UNIT IN Regulator input voltage 2.375 5.5 V LDOIN LDO input voltage –0.1 3.5 V EN Regulator enable voltage –0.1 3.5 V OUT LDO output voltage –0.1 3.5 V SNS LDO output sense voltage –0.1 3.5 V REFIN Reference input voltage 0.5 1.8 V REFOUT Reference output voltage –0.1 1.8 V PG Power-good pull-up voltage –0.1 3.5 V PGND Power ground voltage to GND –0.1 0.1 V TJ Junction Temperature Range –40 125 °C Thermal Information PACKAGE θJA θJC UNIT 3×3 DFN-10 77.66 16.33 °C/W

www.3peak.com Rev.A.1 TPL51200 Series 3-A Sink and Source DDR Termination Regulator

Electrical Characteristics

TJ = –40°C to +125°C (typical value at TJ = +25°C), VIN = VEN = 3.3 V; VLDOIN = 1.8 V, VREFIN = 0.9 V, VSNS = 0.9 V, CIN = 10 µF, and COUT = 3 x 10 µF; unless otherwise noted unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Supply Input Voltage and Current VIN Input supply voltage range 2.375 5.5 V VLDOIN LDO input voltage range 3.5 V UVLOIN Input supply UVLO TA = +25°C, VIN rising 2.3 2.375 V Hysteresis 50 mV IIN Input supply current of IN TA = +25°C, VEN = 3.3 V, IOUT = 0 mA 0.8 1 mA IIN_SD Shutdown current of IN TA = +25°C, VEN = 0 V, VREFIN = 0 V, IOUT = 0 mA 65 80 µA TA = +25°C, VEN = 0 V, VREFIN > 0.4 V, IOUT = 0 mA 200 400 µA ILDOIN Input current of LDOIN TA = +25°C, VEN = 3.3 V, IOUT = 0 mA 1 50 µA ILDOIN_SD Shutdown current of LDOIN TA = +25°C, VEN = 0 V, IOUT = 0 mA 1 50 µA Reference Input and Output VREFIN Reference input voltage 0.5 1.8 V UVLOREFIN Reference input UVLO TA = +25°C, VREFIN rising 360 390 420 mV Hysteresis 20 mV IREFIN Input current of REFIN VEN = 3.3 V 1 µA VREFOUT Reference output voltage VREFIN V VREFOUT_TOL Tolerance of REFOUT to REFIN −1 mA ≤ IREFOUT ≤ 1 mA, 0.5 V ≤ VREFIN ≤ 1.8 V −12 12 mV −10 mA ≤ IREFOUT ≤ 10 mA, 0.5 V ≤ VREFIN ≤ 1.8 V −15 15 mV IREFOUT_SRCL Source current limit of REFOUT VREFOUT = 0.5 V 10 60 mA IREFOUT_SNKL Sink current limit of REFOUT VREFOUT = 1.5 V 10 60 mA Regulated Output Voltage and Current VOUT Output voltage VREFOUT = 1.25 V (DDR1), IOUT = 0 A 1.25 V Tolerance −15 15 mV VREFOUT = 0.9 V (DDR2), IOUT = 0 A 0.9 V Tolerance −15 15 mV VREFOUT = 0.75 V (DDR3), IOUT = 0 A 0.75 V Tolerance −15 15 mV VREFOUT = 0.675 V (DDR3L), IOUT = 0 A 0.675 V Tolerance −15 15 mV VREFOUT = 0.6 V (DDR4), IOUT = 0 A 0.6 V Tolerance −15 15 mV ΔVOUT Tolerance of OUT to REFOUT –2A < IOUT < 2A −25 25 mV IOUT_SRCL Source current limit of OUT VSNS = 90% × VREFOUT 3 4.5 A IOUT_SNKL Sink current limit of OUT VSNS = 110% × VREFOUT 3.2 5.5 A RDIS Discharge resistance TA = +25°C, VREFIN = 0 V, VOUT = 0.3 V, VEN = 0 V 12 Ω

www.3peak.com Rev.A.1 TPL51200 Series 3-A Sink and Source DDR Termination Regulator Electrical Characteristics (continued) TJ = –40°C to +125°C (typical value at TJ = +25°C), VIN = VEN = 3.3 V; VLDOIN = 1.8 V, VREFIN = 0.9 V, VSNS = 0.9 V, CIN = 10 µF, and COUT = 3 x 10 µF; unless otherwise noted unless otherwise noted. Enable Control VEN EN High-level input voltage Device enable 1.7 V EN Low-level input voltage of Device disable 0.5 V Hysteresis 0.25 V IEN Leakage current of EN TA = +25°C, VEN = 0 V to 6.5 V –1 1 µA Power Good VPG PG lower threshold With respect to REFOUT –23.5% –20% –17.5% PG upper threshold With respect to REFOUT 17.5 20% 23.5% Hysteresis 5% IPG Leakage current of PG 1 µA VOL(PG) PG low-level output voltage Source 4 mA to PG pin 0.4 V tDLY(PG) PG start-up delay Startup rising edge, VSNS within 15% of VREFOUT 2 ms tDLY(PG_B) PG start-up bad delay VSNS is beyond the ±20% PG trip threshold 10 µs Temperature Range TSD Thermal shutdown threshold Temperature increasing 155 °C Hysteresis 25 °C TJ Operating junction temperature –40 125 °C

www.3peak.com Rev.A.1 TPL51200 Series 3-A Sink and Source DDR Termination Regulator Detailed Description Overview The TPL51200 series devices are 3 -A sink and source DDR termination regulators specifically designed for the DDR applications with heavy space limitation. The TPL51200 series devices implement a fast load -transient response and only requires a minimum output capacitance of 20 μF. The TPL51200 series devices support a remote-sensing function and all power requirements for DDR VTT bus termination. In addition, the TPL51200 series devices provide an open -drain PG signal for VTT regulation indication and an EN signal that can be used to discharge VTT for DDR1 to DDR4 applications. Functional Block Diagram LDOIN Regulation Control OUT AMP Discharge AMP Device Control UVLO ENABLE IN EN REFIN EA SNS REFOUT Discharge PG Power Good ControlGND PGND BUF Figure 19 Functional Block Diagram Feature Description Sink and Source Regulator (OUT and SNS) The TPL51200 series devices are 3 -A sink and source DDR termination regulators specifically designed for the DDR applications with heavy space limitation. The TPL51200 series integrate a high-performance, low-dropout linear regulator with fast-feedback loop that can support fast load transient response with small ceramic capacitors. To get tight regulation tolerance, the remote sensing pin, SNS pin, must be connected to OUT pin through a separate trace from high current path. Voltage Reference (REFIN and REFOUT) The TPL51200 series uses the voltage at the REFIN pin as the reference voltage, and the output voltage at the REFOUT pin exactly follow the REFIN voltage within the tolerance of VREFOUT_TOL. When the TPL51200 series are configured for standard DDR applications, the voltage at the REFIN pin is divided through an external voltage divider from the DDR supply bus, VDDQ. The TPL51200 series support the REFIN input voltage range from 0.5 V to 1.8 V. When the REFIN voltage is higher than rising UVLO threshold of REFIN and IN voltage is ready, there is voltage regulated at the REFOUT pin, which the REFOUT pin is independent with EN status.

www.3peak.com Rev.A.1 TPL51200 Series 3-A Sink and Source DDR Termination Regulator Enable Control (EN) The TPL51200 series integrate the high-active device enable control feature. Connect this pin to the GPIO of an external processor or digital logic control circuit to enable and disable the device. Under-voltage Lockout (IN UVLO) The TPL51200 series use an under -voltage lockout circuit to keep the regulator shut off until IN voltage exceeds the rising UVLO threshold of IN. Power-Good Indicator (PG) The TPL51200 series integrate an open-drain output power good indicator. After regulator startup, the PG pin keeps low impendence until the output voltage enters the power -good window, ±20% of REFOUT voltage. When output voltage enters the power -good window, the PG pin turns to high output impedance, and PG is pulled up to high-voltage level after 2-ms delay to indicate the output voltage is ready. It is recommended to connect a 100-kΩ pull-up resistor between PG pin and the pull-up voltage supply. Over-Current Protection The TPL51200 series integrate a constant over-current protection. When the output voltage exists the power-good window, ±20% of REFOUT voltage, the current -limit level reduces 50% of the full level. After the output voltage enters the power -good window, the current-limit level is released to the full level. Over-Temperature Protection The recommended operating junction temperature range is –40°C to 125°C. When the junction temperature is between 125°C and the thermal shutdown (TSD) threshold, the regulator can still work well, but it will reduce the device lifetime for long-term using. The over-temperature protection works when the junction temperature exceeds the thermal shutdown (TSD) threshold, which turns off the regulator immediately. Until when the device cools down and the junction temperature falls below the thermal shutdown threshold minus thermal shutdown hysteresis, the regulator turns on again.

www.3peak.com Rev.A.1 TPL51200 Series 3-A Sink and Source DDR Termination Regulator Application and Implementation

Application Information

The TPL51200 series devices are 3 -A sink and source DDR termination regulators specifically designed for the DDR applications . The following application schematic shows a typical usage of the TPL51200 series. Typical Application Adjustable Output Operation Figure 20 shows the typical application schematic of the TPL51200 series in DDR4 applications. TPL51200 REFIN 1 nF 10 kΩ 10 kΩ 0.1 μF10 μF 10 μF GND 10 μF10 μF 100 kΩ 9PG 8GND 7EN 6REFOUT 0.1 μF 4.7 μF VDDQ = 1.2 V VLDOIN = VDDQ = 1.2 V VTT = 0.6 V VIN = 3.3 V PG Signal to I/O Enable Signal VTTREF = 0.6 V Figure 20 Typical Application Schematic IN Input Capacitor 3PEAK recommends placing a 1-μF or greater capacitor with a 0.1 -μF bypass capacitor in parallel close to IN pin to keep the input voltage stable. The voltage rating of the capacitors must be greater than the maximum input voltage. LDOIN Input Capacitor 3PEAK recommends placing a 10-μF or greater capacitor with a 0.1-μF bypass capacitor in parallel close to LDOIN pin to keep the voltage stable during transient. More input capacitors are required if there are large output capacitors used at the OUT pin . It is suggested to place input capacitors with a half of the output capacitance value at the LDOIN pin. Output Capacitor To ensure stable operation, the TPL51200 series requires output capacitors of 20 μF or greater. 3PEAK recommends selecting three 10-μF X5R-or X7R -type ceramic capacitor in parallel to minimize the equivalent series resistance (ESR) and equivalent series inductance (ESL). The output capacitors must be placed as close to the OUT pin as possible. Power Dissipation During normal operation, LDO junction temperature should not exceed 125°C. Using below equations to calculate the power dissipation and estimate the junction temperature. NOTE Information in the following applications sections is not part of the 3PEAK’s component specification and 3PEAK does not warrant its accuracy or completeness. 3PEAK’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

www.3peak.com Rev.A.1 TPL51200 Series 3-A Sink and Source DDR Termination Regulator The power dissipation can be calculated using Equation 1. ( )D IN OUT OUT IN GNDP V V I V I= −  +  (1) The junction temperature can be estimated using Equation 2. θJA is the junction-to-ambient thermal resistance. J A D JAT T P = +  (2) Layout Requirements

• Both input capacitors and output capacitors must be placed as close to the device pins as possible.
• Suggest bypass the input pin to ground with a 0.1 μF bypass capacitor. The loop area formed by the bypass capacitor connection, voltage input pin and the ground pin of the system must be as small as possible.
• Suggest use wide trace lengths or thick copper weight to minimize I×R drop and heat dissipation.
• The GND pin and the PGND pin must be connected to the thermal pad with multiple thermal vias as many as possible connected to the internal ground planes.

www.3peak.com Rev.A.1 TPL51200 Series 3-A Sink and Source DDR Termination Regulator Tape and Reel Information Order Number Package (mm) (mm) (mm) (mm) (mm) (mm) (mm) Pin1 Quadrant TPL51200-DF8R 3× 3 DFN-10 330 17.6 3.3 3.3 1.1 8 12 Q2

www.3peak.com Rev.A.1 TPL51200 Series 3-A Sink and Source DDR Termination Regulator Package Outline Dimensions 3× 3 DFN-10 2.00BSCNd 0.400.35 0.45L 2.90 3.00 3.10 2.90 SYMBOL MILLIMETER MIN NOM MAX b 0.203REF D A E 0.50BSCe 3.103.00 0.02 0.05A1 0.300.20 0.25 c R 0.20REF 1.65 2.40 BOTTOM VIEW EXPOSED THERMAL PAD ZONE 2.35 2.45 1.60 1.70 TOP VIEW SIDE VIEW ** 特殊设计：D2和E2尺寸的公差是±0.05； 引脚根部缩小较少； b1 0.23REF R1 0.075REF k 0.35REF 0.800.70 0.75 E D Nd R L b e A c PIN 1(Laser Mark) k

www.3peak.com Rev.A.1 TPL51200 Series 3-A Sink and Source DDR Termination Regulator IMPORTANT NOTICE AND DISCLAIMER Copyright© 3PEAK 2012-2023. All rights reserved. Trademarks. Any of the 思瑞浦 or 3PEAK trade names, trademarks, graphic marks, and domain names contained in this document /material are the property of 3PEAK. You may NOT reproduce, modify, publish, transmit or distribute any Trademark without the prior written consent of 3PEAK. Performance Information. Performance tests or performance range contained in this document/material are either results of design simulation or actual tests conducted under designated testing environment. Any variation in testing environment or simulation environment, including but not limited to testing method, testing process or testing temperature, may affect actual performance of the product. Disclaimer. 3PEAK provides technical and reliability data (including data sheets), design resources (including reference designs), application or other design recommendations, networking tools, security information and other resources "As Is". 3PEAK makes no warranty as to the absence of defects, and makes no warranties of any kind, express or implied, including without limitation, implied warranties as to merchantability, fitness for a particular purpose or non-infringement of any third-party’s intellectual property rights. Unless otherwise specified in writing, products supplied by 3PEAK are not designed to be used in any life-threatening scenarios, including critical medical applications, automotive safety-critical systems, aviation, aerospace, or any sit uations where failure could result in bodily harm, loss of life, or significant property damage. 3PEAK disclaims all liabilit y for any such unauthorized use.