TPF142-TR

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Document overview

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Technical content

Features

 1-SDTV Video Filter Support CVBS  1-HDTV Video Filter Support Y'Pb'Pr'-1080p, R'G'B' or VGA/SVGA/XGA  Optimized 6 th-order Butterworth Video reconstruction filter： CVBS Channel: -3dB at 9MHz HD Channel: -3dB ≥ 72MHz  Support Multiple Input Biasing: - Provide 80-mV Level-Shift when DC-Coupled - Transparent Input Clamping when AC-Coupled - Support External DC Biasing when AC-Coupled  Very Low Quiescent Current: 14.5 mA(at 3.3V, Typical)  6dB Gain(2V/V), Rail TO Rail Output  AC- or DC-Coupled Output Driving Dual Video Loads (75Ω)  Wide Power Supply: +3.0V to +5.5V Single Supply  Robust ESD Protection: - Robust 8kV – HBM and 2kV – CDM ESD Rating  Green Product, MSOP-8 and TSSOP-14 Package

Applications

 Video Signal Amplification  Set-Top Box Video Driver  PVR、DVD Player Video Buffer  Video Buffer for Portable or USB-Powered Video Devices  HDTV

Description

TPF142 is a specially designed for consumer applications, high-performance, low-cost video reconstruction filter, it combine excellent video performance and low power consumption perfectly. It incorporates one standard-definition (CVBS) and one high-definition (HD) filter channels. All filters feature sixth-order Butterworth characteristics that are useful as digital-to-analog converter (DAC) reconstruction filters or as analog-to-digital converter (ADC) anti-aliasing filters. The HD filters can be bypassed to support filters. The HD filters can be bypassed to support 1080p60 video or up to quad extended graphics array (QXGA) RGB video. As part of the TP142 flexibility, the input can be configured for ac- or dc-coupled inputs. The 84-mV output level shift allows for a full sync dynamic range at the output with 0-V input. The ac-coupled modes include a transparent sync-tip clamp option for composite video (CVBS), Y', and G'B'R' signals. AC- coupled biasing for C'/P'B/P'R channels can easily be achieved by adding an external resistor to VS+. The TP142 rail-to-rail output stage with 6-dB gain allows for both ac and dc line driving. The ability to drive two lines, or 75- Ω loads, allows for maximum flexibility as a video line driver. The 14.5-mA total quiescent current at 3.3 V makes it an excellent choice for power-sensitive video applications. TPF142 is available in MSOP-8 package (TPF142-VR) and TSSOP-14 package (TPF142-TR). Its operation temperature range is from −40°C to +85°C. Related Resources AN-1201: Application notes of TPF1x Function Block

One CVBS and One Full-HD Co mposite Video Filter Driver REV 1.1 © 2 0 1 4 3 P E A K I N C O R P O R A T E D ~ 2 ~ w w w . 3 p e a k i c . c o m Order Information Order Number Operating Temperature Range Package Marking Information Transport Media, Quantity TPF142-VR -40 to 85°C 8-Pin MSOP TPF142 Tape and Reel, 3,000 TPF142-TR -40 to 85°C 14-Pin TSSOP TPF142 Tape and Reel, 3,000 Pin configuration (Top View) Absolute Maximum Ratings* Parameters Value Units Power Supply, VDD to GND 6.0 V VIN Input Voltage V DD + 0.3V to GND - 0.3V IO Output Current 65 I O TJ Maximum Junction Temperature 150 T J TA Operating Temperature Range –45 to 85 T A TSTG Storage Temperature Range –65 to 150 T STG TL Lead Temperature (Soldering 10 sec) 300 TL * Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. ESD, Electrostatic Discharge Protection Symbol Parameter Condition Minimum Level Unit HBM Human Body Model ESD MIL-STD-883H Method 3015.8 8 kV CDM Charged Device Model ESD JEDEC-EIA/JESD22-C101E 2 kV Pin Name Function CVBS IN SD video input for CVBS signal, LPF = 9 MHz DIS FHD Disable Full-HD channel. Logic high disables the FHD channel and logic low enables the FHD channel. This pin defaults to logic high if left o pen. FHD IN Full-HD video input, LPF = 72 MHz +VS Positive Power Supply GND Ground FHD OUT Full-HD video output, LPF = 72 MHz DIS CVBS Disable SD channel. Logic high disables the SD channel and logic low enables the SD channel. This pin defaults to logic high if left open. CVBS OUT SD video output for CVBS signal, LPF = 9 MHz NC No Connection

One CVBS and One Full-HD Co mposite Video Filter Driver REV1.1 w w w . 3 p e a k i c . c o m ~ 3 ~ © 2 0 1 4 3 P E A K I N C O R P O R A T E D Electrical Characteristics All test condition is VDD = 3.3V, TA = +25°C, RL = 150Ω to GND, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Input Electrical Specifications +VS Supply Voltage Range 3.0 5.5 V IQ Quiescent current (IQ) +VS = 3.3V, VIN = 500mV, no load, all channels on 14.5 mA +VS = 3.3V, VIN = 500mV, no load, SD channel on, FHD channel off 3.66 mA +VS = 3.3V, VIN = 500mV, no load, SD channel off, FHD channel on 11.24 mA +VS = 3.3V, VIN = 500mV, no load, all channels off 1 μA +VS = 5V, VIN = 500mV, no load, all channels on 14.89 mA +VS = 5V, VIN = 500mV, no load, SD channel on, FHD channel off 3.67 mA +VS = 5V, VIN = 500mV, no load, SD channel off, FHD channel on 11.27 mA +VS = 5V, VIN = 500mV, no load, all channels off 1 μA ICLAMP-DOWN Clamp Discharge Current V IN=300mV, measure current 1.5 2.0 5.1 μA ICLAMP-UP Clamp Charge Current V Y = -0.2V -1.5 -1.7 mA VCLAMP Input Voltage Clamp I Y = -100μA -40 0 +40 mV RIN Input Impedance 0.5V < V Y < 1V 0.5 3 M Ω AV Voltage Gain VIN=0.5V,1V or 2V RL=150Ω to GND 5.9 6.01 6.03 dB ΔAV Channel Mismatch -2 +2 % VOLS Output Level Shift Voltage V IN = 0V, no load, input referred 53 80 124 mV VOL Output Voltage Low Swing V IN = -0.3V, RL =75Ω 0.05 V VOH Output Voltage High Swing V IN = 3V, RL =75Ω to GND (dual load) 3.18 V PSRR Power Supply Rejection Ratio ΔVDD = 3.3V to 3.6V 61 dB ΔVDD = 5.0V to 5.5V, 50Hz 67 dB ISC Short-circuit current VIN = 2V, 10Ω, output to GND 65 mA VIN =0.1V, output short to VDD 65 mA VIH Disable Threshold V DD = 3.0V to 5.5V 1.6 V VIL Enable Threshold V DD = 3.0V to 5.5V 0.4 V tON Enable Time V IN = 500mV, VOUT to 1% 1000 ns tOFF Disable Time V IN = 500mV, VOUT to 1% 1000 ns

One CVBS and One Full-HD Co mposite Video Filter Driver REV 1.1 © 2 0 1 4 3 P E A K I N C O R P O R A T E D ~ 4 ~ w w w . 3 p e a k i c . c o m SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS f-1dB -1dB Bandwidth SD Channel RL=150Ω 7.6 8.2 9.1 MHz FHD Channel 53.1 63.2 72.9 f-3dB -3dB Bandwidth SD Channel RL=150Ω 7.8 9.0 10.5 MHz FHD Channel 63.7 71.5 80.1 Att27MHz Stop Band Attenuation SD Channel f = 27MHz 38.2 57.2 dB FHD Channel f =148MHz 34.0 39.0 dB dG Differential Gain Video input range 1V -0.1 0.4 0.8 % dP Differential Phase Video input range 1V -1.1 0.7 1.1 ° THD Total Harmonic Distortion SD Channel f=1MHz, V OUT=1.4VPP 0.03 0.1 0.2 FHD Channel f=10MHz, V OUT=1.4VPP 0.15 D/DT Group Delay Variation SD Channel f = 100kHz to 5MHz 5.4 ns FHD Channel f = 100kHz t0 60MHz 6.0 XTALK Channel Crosstalk f = 1MHz, V OUT=1.4VPP -68 -74 dB SNR Signal-to-Nois e Ration SD Channel f= 100kHz to 4.43MHz 65 69 dB FHD Channel f= 100kHz to 60MHz 64 ROUT_AC 输出阻抗 f = 10MHz 0.5 Ω CLG Chroma-Luma-Gain (SD Channel) 400kHz to 3.58MHz and 4.43MHz 0.18 0.4 dB CLD Chroma-Luma-Delay (SD Channel) 400kHz to 3.58MHz and 4.43MHz 5 ns

One CVBS and One Full-HD Co mposite Video Filter Driver REV1.1 w w w . 3 p e a k i c . c o m ~ 5 ~ © 2 0 1 4 3 P E A K I N C O R P O R A T E D Typical Performance Characteristics All test condition is VDD = 3.3V, TA = +25°C, RL = 150Ω to GND, unless otherwise noted. Figure1. Small-Scale Frequency Response(SD Channel) Figure2. Small-Scale Frequency Response(FHD Channel) Figure3. Gain Vs. Frequency With CLOAD (SD Channel) Figure4. Gain Vs. Frequency With CLOAD(FHD Channel) Figure5. Group Delay vs Frequency(SD Channel) Figure6. Group Delay vs Frequency(FHD Channel) -0.8 -0.6 -0.4 -0.2 0.2 0.4 0.6 0.8 100k 1M 10M FREQUENCY (Hz) NORMALIZED GAIN (dB) VDD=3.3V RL=150Ω CL=15pF -0.1dB@7MHz -0.8 -0.6 -0.4 -0.2 0.2 0.4 0.6 0.8 100k 1M 10M 100M FREQUENCY (Hz) NORMALIZED GAIN (dB) VDD=3.3V RL=150Ω CL=15pF -0.1dB@50MHz 100k 1M 10M FREQUENCY (Hz) NORMALIZED GAIN (dB)VDD=3.3V RL=150Ω CL=20p CL=5pF CL=15pF 100k 1M 10M 100M FREQUENCY (Hz) NORMALIZED GAIN (dB)VDD=3.3V RL=150Ω CL=5pF CL=20p CL=15pF 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0 100k 1M 10M 100M FREQUENCY (Hz) GROUP DELAY (ns) VDD=3.3V RL=150Ω CL=15pF -10.0 -5.0 0.0 5.0 10.0 15.0 20.0 25.0 30.0 35.0 40.0 1M 10M 100M 1G FREQUENCY (Hz) GROUP DELAY (ns) VDD=3.3V RL=150Ω CL=15pF

One CVBS and One Full-HD Co mposite Video Filter Driver REV 1.1 © 2 0 1 4 3 P E A K I N C O R P O R A T E D ~ 6 ~ w w w . 3 p e a k i c . c o m Figure7. PSRR Vs. Frequency(SD) Figure8. PSRR Vs. Frequency(FHD) Figure9. Large-Signal Pulse Response Vs. Time(SD Channel) Figure10. Small-Signal Pulse Response Vs. Time(SD Channel) Figure11. Large-Signal Pulse Response Vs. Time(FHD Channel) Figure11. Small-Signal Pulse Response Vs. Time(FHD Channel) -80 -70 -60 -50 -40 -30 -20 -10 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) PSSR (dB) VDD=3.3V -80 -70 -60 -50 -40 -30 -20 -10 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) PSSR (dB) VDD=3.3V 0.0 0.5 1.0 1.5 2.0 0 200 400 600 800 1000 1200 TIME (ns) AMPLITUDE (V) VDD=+3.3V RL=100Ω VOUT=1VP-P tRISE=57.1ns tFA LL=48.9ns 0.4 0.5 0.6 0.7 0.8 0.9 0 200 400 600 800 1000 1200 TIME (ns) AMPLITUDE (V) tRISE=35.8ns tFA LL=33.3ns VDD=+3.3V RL=100Ω VOUT=200mVP-P 0.0 0.5 1.0 1.5 2.0 0 20 40 60 80 100 120 140 160 TIME (ns) AMPLITUDE (V) VDD=+3.3V RL=100Ω VOUT=1VP-P tRISE=7.75ns tFA LL=7.41ns 0.4 0.5 0.6 0.7 0.8 0.9 0 20 40 60 80 100 120 140 160 TIME (ns) AMPLITUDE (V) tRISE=3.25ns tFA LL=3.59ns VDD=+3.3V RL=100Ω VOUT=200mVP-P

One CVBS and One Full-HD Composite Video Filter Driver REV1.1 w w w . 3 p e a k i c . c o m ~ 7 ~ © 2 0 1 4 3 P E A K I N C O R P O R A T E D

Application Information

The TPF142 is targeted for systems that require a single standard-definition (CVBS) video output for CVBS video support along with single high-definition (HD) video outputs. Although it can be used for numerous other applications, the needs and requirements of the video signal are the most important design parameters of the TPF142. The TPF142 incorporates many features not typically found in integrated video parts while consuming very low power. Internal Sync Clamp The typical embedded video DAC operates from a ground referenced single s upply. This becomes an issue because the lower level of the sync pulse output may be at a 0V reference level to some positive level. The problem is presenting a 0V input to most single supply driven amplifiers w ill saturate the output stage of the amplifier resulting in a clipped sync tip and degrading the video image. A larger positive reference may offset the input above its positive range. The TPF142 features an in ternal sync clamp and offset function to level shift the entire video signal to the best level before it r eaches the input of the amplifier stage. These feat ures are also helpful to avoid saturation of the output stage of the amplifier by setting the signal closer to the best voltage range. The simplified block diagram of the TPF142 in Page-1. The AC coupled video sync signal is pulled negative by a current source at t he input of the comparator amplifier. When the sync tip goes below the comparator threshold the out put comparator is driven negative, The PMOS device turns on clamping sync tip to near ground level. The network triggers on the sync tip of video signal. Droop Voltage and DC Restoration Selection of the input AC-coupling capacitance is based on the system requireme nts. A typical sync tip width of a 64 μs NTSC line is 4 μs during which clamp circuit restores its DC le vel. In the remaining 60 μs period, the voltage droops because of a small constant 2.0 μA sinking current. If the AC-coupling capacitance is 0.1 μF, the maximum droop voltage is about 1mV which is restored by the clamp circuit. The maximum pull-up current of the clamp circuit is 1.7mA. For a 4 μs sync tip width and 0.1 μF capacitor, the maximum restoration voltage is about 80mV. The line droop voltage will increase if a smaller AC-coupling capacitance is used. For the same reason, if larger capacit ance is used the line droop voltage will decrease. Tabl e 1 is droop voltage and maximum restoration voltage of the clamp for typical capacitance. Table 1. Maximum restoration voltage and droop voltage The Sallen Key is a classic low pass configuration. series with and before the Sallen Key. previously in this document. board space and additional ex pense for capacitors.

One CVBS and One Full-HD Co mposite Video Filter Driver REV 1.1 © 2 0 1 4 3 P E A K I N C O R P O R A T E D ~ 8 ~ w w w . 3 p e a k i c . c o m 1mA, compared to typical 6.6mA used when DC coupling. Output Drive Capability and Power Dissipation With the high output drive capability of the TPF142, it is possible to exceed the +125°C absolute maximum junction temperature under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for an application to determine if load conditions or package types need to be modified to assure operation of the amplifier in a safe operating area. The maximum power dissipation allowed in a package is determined according to Equation: Where： T JMAX = Maximum junction temperature TAMAX = Maximum ambient temperature ΘJA = Thermal resistance of the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the load, or: for sourcing: Where： VS = Supply voltage ISMAX = Maximum quiescent supply current VOUT = Maximum output voltage of the application RLOAD = Load resistance tied to ground By setting the two PDMAX equations equal to each other, we can solve the output current and RLOAD to avoid the device overheat. Power Supply Bypassing Printed Circuit Board Layout As with any modern operat ional amplifier, a good printed circuit board layout is necessary for optimum performance. Lead lengths should be as short as possible. The power supply pin must be well bypassed to reduce the risk of oscillation. For normal single supply operation, a single 4.7μF tantalum capacitor in parallel with a 0.1 μF ceramic capacitor from VS+ to GND will suffice. VIDEO FILTER DRIVER SELECTION GUIDE P/N Product Description Chan nel -3dB Bandwidth Package TPF110 /TPF110L Low power, enable function and SAG correction, 1 channel 6th order 9MHz 1-SD 9MHz SC70-5 SOT23-6 TPF113 Low power 3 channel, 6th-order 9MHz SD video filter 3-SD 9MHz SO-8 TPF114 Low power 4 channel, 6th-order 9MHz SD video filter 4-SD 9MHz MSOP-10 TSSOP-14 TPF116 Low power 4 channel, 6th-order 9MHz SD video filter for CVBS, SVIDEO 6-SD 9MHz TSSOP-14 TPF123 3 channel 6th-order 13.5MHz, 960H/720H-CVBS video filter or Y’Pb’Pr 480P/576P video filter 3-ED 13.5MHz SO-8 TPF133 Low power 3 channel, 6th-order 36MHz HD video filter 3-HD 36MHz SO-8 TPF134 Low power 3 channel, 6th-order 1-SD& 9MHz MSOP-10 = JMAX AMAX MAX JA TTPD  ss=+ OUT MAX SMAX OUT L

One CVBS and One Full-HD Composite Video Filter Driver REV1.1 w w w . 3 p e a k i c . c o m ~ 9 ~ © 2 0 1 4 3 P E A K I N C O R P O R A T E D 36MHz HD video filter and 1 channel SD video filter 3-SD 36MHz TSSOP-14 TPF136 Low power 3 channel, 6th-order 36MHz HD video filter and 3 channel SD video filter 3-SD& 3-HD 9MHz 36MHz TSSOP-20 TPF143 Low power 3 channel, 6th-order 72MHz Full HD video filter 3-FHD 72MHz SO-8 TPF144 Low power 3 channel, 6th-order 72MHz Full HD video filter and 1 channel SD video filter 1-SD& 3-FHD 9MHz 72MHz MSOP-10 TSSOP-14 TPF146 Low power 3 channel, 6th-order 72MHz Full HD video filter and3 channel SD video filter 3-SD& 3-FHD 9MHz 72MHz TSSOP-20 TPF153 Low power 3 channel, 6th-order 220MHz Full HD video filter 3-CH 220MHz SO-8

One CVBS and One Full-HD Co mposite Video Filter Driver REV 1.1 © 2 0 1 4 3 P E A K I N C O R P O R A T E D ~ 10 ~ w w w . 3 p e a k i c . c o m

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision. Revision Change Rev1.0 Initial Release Rev1.1 Delete VIH Max Value data, Add VIH Min Value data 1.6V on page 4 Delete VIL Min Value data, Add VIL Max Value data 0.4V on page 4 Change page header Date from @2013 to @2014

One CVBS and One Full-HD Composite Video Filter Driver REV1.1 w w w . 3 p e a k i c . c o m ~ 11 ~ © 2 0 1 4 3 P E A K I N C O R P O R A T E D Package Outline Dimensions 10 Lead MSOP Package——Main Body 3.00 mm [MSOP_N] Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 0.800 1.200 0.031 0.047 A1 0.000 0.200 0.000 0.008 A2 0.760 0.970 0.030 0.038 b 0.30 TYP 0.012 TYP C 0.15 TYP 0.006 TYP D 2.900 3.100 0.114 0.122 e 0.65 TYP 0.026 E 2.900 3.100 0.114 0.122 E1 4.700 5.100 0.185 0.201 L1 0.410 0.650 0.016 0.026 θ 0° 6° 0° 6° e E D L1 L2 L R θ b

One CVBS and One Full-HD Co mposite Video Filter Driver REV 1.1 © 2 0 1 4 3 P E A K I N C O R P O R A T E D ~ 12 ~ w w w . 3 p e a k i c . c o m Package Outline Dimensions 14 Lead TSSOP Package——Main Body 4.40 mm [TSSOP_N] Symbol Dimensions In Millimeters MIN TYP MAX A - - 1.20 A1 0.05 - 0.15 A2 0.90 1.00 1.05 b 0.20 - 0.28 c 0.10 - 0.19 D 4.86 4.96 5.06 E 6.20 6.40 6.60 E1 4.30 4.40 4.50 e 0.65 BSC L 0.45 0.60 0.75 L1 1.00 REF L2 0.25 BSC R 0.09 - - θ 0° - 8° E e A D L1 L2 L R θ c

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