TPC5120

TPC5120 3PEAK | Alldatasheet

Document overview

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• PDF pages: 32

Technical content

Features

 16 or 8-channel 12-Bit SAR ADC − Supporting Ranges from 0 to 2.5 V and 0 to 5 V − Programmable Out-of-Range Alarms − 1-MHz Sample Rate Serial Devices  General Purpose I/O Ports (GPIOs)  Low-Power SPI-Compatible Serial Interface  Operating Temperature: −40°C to 125°C

Applications

 Wireless Infrastructure  PLC / DCS  Battery Powered Systems  General Purpose Monitor and Control

Description

The TPC5120/TPC5121 products include capacitor- based SAR A/D converters with inherent sample and hold. The TPC5120 has 16 -channel single-ended inputs and the TPC5121 has 8-channel single-ended inputs. The devices accept a wide analog supply range from 2.7 V to 5.25 V. The ultra-low power consumption makes these devices suitable for battery -powered and isolated power-supply applications. A wide 1.7-V to 5.25-V I/O supply range facilitates a glueless interface with the most used digital hosts. The serial interface is controlled by CS̅̅̅̅ and SCLK for easy connection with microprocessors and DSP. The input signal is sampled with the falling edge of CS̅̅̅̅. It uses SCLK for conversion, serial data output, and reading serial data in. The devices allow auto sequencing of preselected channels or manual selection of a channel for the next conversion cycle. There are two software selectable input ranges (0 V to VREF and 0 V to 2 × VREF), individually configurable GPIOs (four in case of the TSSOP and one on the VQFN package devices), and two programmable alarm thresholds per channel. These features make the devices suitable for most data acquisition applications. The devices offer an attractive power -down feature. This is extremely useful for power saving when the device is operated at lower conversion speeds. Functional Block Diagram

www.3peak.com Rev.1.0 TPC512x 12-bit 1 -MHz SAR ADC Table of Contents

www.3peak.com Rev.1.0 TPC512x 12-bit 1 -MHz SAR ADC

Revision History

2022-01-11 Rev.1.0 Version 1.0

www.3peak.com Rev.1.0 TPC512x 12-bit 1 -MHz SAR ADC Pin Configuration and Functions TPC5120 Top View TPC5120 Top View TPC5121 Top View AGND CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 VA AGND CS SCLK SDI SDO BDGND VBD GPIO0 GPIO1 AGND CH8 CH9 CH10 CH11 CH12 CH13 CH14 CH15 AGND AINM AINP M O AGND VA REFP REFM GPIO3 GPIO2 1 AGND 1 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 M O AINP AINM CH15 CH14 CH13 CH12 SCLK AGND VA CH0 CH1 CH2 CH3 CH11 CH10 CH9 CH8 CH7 CH6 CH5 CH4 VA REFP REFM GPIO VBD BDGND SDO SDI CS VA 1 7 8 9 10 11 12 24 23 22 21 20 19 AGND M O AINP AINM CH7 SDI SCLK AGND VA CH0 CH6 CH5 CH4 CH3 CH2 CH1 REFP REFM GPIO VBD BDGND SDO CS

www.3peak.com Rev.1.0 TPC512x 12-bit 1 -MHz SAR ADC Pin Functions TSSOP package TPC5120 I/O Description Pin No. Pin Name

3 REFM Analog input Reference ground

4 REFP Analog input Reference input

8 AINP Analog input ADC input signal

9 AINM Analog input ADC input ground

7 M O Analog output Multiplexer output

28 Ch0 Analog input Analog channel for multiplexer

27 Ch1 Analog input Analog channel for multiplexer

26 Ch2 Analog input Analog channel for multiplexer

25 Ch3 Analog input Analog channel for multiplexer

24 Ch4 Analog input Analog channel for multiplexer

23 Ch5 Analog input Analog channel for multiplexer

22 Ch6 Analog input Analog channel for multiplexer

21 Ch7 Analog input Analog channel for multiplexer

18 Ch8 Analog input Analog channel for multiplexer

17 Ch9 Analog input Analog channel for multiplexer

16 Ch10 Analog input Analog channel for multiplexer

15 Ch11 Analog input Analog channel for multiplexer

14 Ch12 Analog input Analog channel for multiplexer

13 Ch13 Analog input Analog channel for multiplexer

12 Ch14 Analog input Analog channel for multiplexer

11 Ch15 Analog input Analog channel for multiplexer

31 CS̅̅̅̅ Digital input Chip-select input pin; active low

32 SCLK Digital input Serial clock input pin

33 SDI Digital input Serial data input pin

34 SDO Digital output Serial data output pin

GPIO0 Digital I/O General-purpose input or output Alarm Digital output Active high alarm output. GPIO1 Digital I/O General-purpose input or output Low alarm Digital output Active high output indicating low alarm GPIO2 Digital I/O General-purpose input or output Range Digital input Selects ADC input range: High (1) → Range 2 (0 to 2xVREF) / Low (0) → Range 1 (0 to VREF) GPIO3 Digital I/O General-purpose input or output PD Digital input Active low power-down input 5, 29 VA — Analog power supply 6, 10, 19,20,

30 AGND — Analog ground

36 VBD — Digital I/O supply

35 BDGND — Digital ground

— — — Pins internally not connected, do not float these pins, connect these pins to ground

www.3peak.com Rev.1.0 TPC512x 12-bit 1 -MHz SAR ADC Pin Number Pin Name I/O Description TPC5120 TPC5121 31 24 REFP Analog input Reference input 30 23 REFM Analog input Reference ground 3 4 AINP Analog input ADC input signal 4 5 AINM Analog input ADC input ground 2 3 M O Analog output Multiplexer output 20 13 Ch0 Analog input Analog-input channel for multiplexer 19 12 Ch1 Analog input Analog-input channel for multiplexer 18 11 Ch2 Analog input Analog-input channel for multiplexer 17 10 Ch3 Analog input Analog-input channel for multiplexer 16 9 Ch4 Analog input Analog-input channel for multiplexer 15 8 Ch5 Analog input Analog-input channel for multiplexer 14 7 Ch6 Analog input Analog-input channel for multiplexer 13 6 Ch7 Analog input Analog-input channel for multiplexer 12 — Ch8 Analog input Analog-input channel for multiplexer 11 — Ch9 Analog input Analog-input channel for multiplexer 10 — Ch10 Analog input Analog-input channel for multiplexer 9 — Ch11 Analog input Analog-input channel for multiplexer 8 — Ch12 Analog input Analog-input channel for multiplexer 7 — Ch13 Analog input Analog-input channel for multiplexer 6 — Ch14 Analog input Analog-input channel for multiplexer 5 — Ch15 Analog input Analog-input channel for multiplexer 23 16 CS̅̅̅̅ Digital input Chip-select input pin; active low 24 17 SCLK Digital input Serial clock input pin 25 18 SDI Digital input Serial data input pin 26 19 SDO Digital output Serial data output pin 29 22 GPIO0 Digital I/O General purpose input or output Alarm Digital output Active high alarm output. 21, 32 1, 14 VA — Analog power supply 1, 22 2, 15 AGND — Analog ground 28 21 VBD — Digital I/O supply 27 20 BDGND — Digital ground — — — — Pins internally not connected, do not float these pins, connect these pins to ground

www.3peak.com Rev.1.0 TPC512x 12-bit 1 -MHz SAR ADC Specifications Absolute Maximum Ratings (1) Parameters Min Max Unit AINP or CHn to AGND −0.3 VA 0.3 V VA to AGND, VBD to BDGND −0.3 7 V Digital Input Voltage to BDGND −0.3 7 V Digital Output to BDGND −0.3 VA 0.3 V Input Current to any Pin except Supply Pins −10 10 mA Operating Temperature −40 125 °C Junction Temperature (TJ Max) 150 °C Storage Temperature (Tstg) −65 150 °C * (1): Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. The input and output voltage ratings may be exceeded if the input and output diode current ratings are observed. ESD, Electrostatic Discharge Protection Parameter Condition Minimum Level Unit HBM Human Body Model ESD ANSI/ESDA/JEDEC JS-001 ±5 kV CDM Charged Device Model ESD ANSI/ESDA/JEDEC JS-002 ±1.5 kV Recommended Operating Conditions Parameter Min Typ Max Unit VA Analog Power-supply Voltage 2.7 5.25 V VBD Digital I/O-supply Voltage 1.7 3.3 VVA V VREF Reference Voltage 2 2.5 VA V ƒSCLK SCLK Frequency 20 MHz TA Operating Temperature Range −40 125 °C Thermal Information Thermal Metric TSSOP38 Unit RθJA Junction-to-ambient Thermal Resistance 83.6 °C/W RθJC(top) Junction-to-case (top) Thermal Resistance 29.8 °C/W RθJB Junction-to-board Thermal Resistance 44.7 °C/W ψJT Junction-to-top Characterization parameter 2.9 °C/W ψJB Junction-to-board Characterization parameter 44.1 °C/W RθJC(bot) Junction-to-case (bottom) Thermal Resistance N/A °C/W

www.3peak.com Rev.1.0 TPC512x 12-bit 1 -MHz SAR ADC

Electrical Characteristics

= 1 MHz, unless otherwise noted. Parameter Conditions Min. Typ. Max. Unit ANALOG INPUT Full-scale Input Span Range 1 0 VREF V Range 2 while 2VREF ≤ VA 0 2*VREF V Absolute Input Range Range 1 −0.2 VREF 0.2 V Range 2 while 2VREF ≤ VA −0.2 2*VREF 0.2 V Input Capacitance 22 pF Input Leakage Current TA = 25°C 30 nA SYSTEM PERFORMANCE Resolution 12 Bits No Missing Code Resolution 12 Bits Integral linearity Fsample = 750 kHz −1 ±0.4 1 LSB3 Fsample = 1 MHz −1.5 1.5 LSB3 Differential linearity Fsample = 750 kHz −0.99 ±0.5 1 LSB3 Fsample = 1 MHz −0.99 1.5 LSB3 Offset Error −4 ±0.5 4 LSB Total Unadjusted Error (TUE) ±3 LSB Gain Error TPC5120 −2 ±1 2 LSB TPC5121, Gain=1 −2.5 ±1 2.5 LSB TPC5121, Gain=2 −3 ±1 3 LSB SAMPLING DYNAMICS Conversion Time 20 MHz sclk 800 ns Acquisition Time 300 ns Maximum Throughput Rate 20 MHz sclk 1 MHz Aperture Delay 5 ns DYNAMIC CHARACTERISTICS Total Harmonic Distortion 100 kHz, −1 dB input −82 dB Signal-to-noise Ratio 100 kHz, −1 dB input 71 dB Signal-to-noise Distortion 100 kHz, −1 dB input 70 dB Small Signal Bandwidth At −3 dB 47 MHz Channel-to-channel Crosstalk All off-channel with 100 kHz, Full-scale input to the channel being sampled with DC input (isolation crosstalk). −80 From previously sampled to channel with 100 kHz, full-scale input to the channel being sampled with DC input (memory crosstalk). −80

www.3peak.com Rev.1.0 TPC512x 12-bit 1 -MHz SAR ADC Electrical Characteristics (Continued) fsample = 1 MHz, unless otherwise noted. Parameter Conditions Min. Typ. Max. Unit Internal REFERENCE Output (TPC5121) VREF Reference Voltage at REFP 2.48 2.5 2.52 V EXTERNAL REFERENCE INPUT VREF Reference Voltage at REFP 2 2.5 VA V Reference Resistance 16 kΩ ALARM SETTING Higher Threshold Range 0 FFC Hex Lower Threshold Range 0 FFC Hex DIGITAL INPUT/OUTPUT Logic Family CMOS Logic Level VIH 0.7*( VBD) V VIL VBD = 5 V 0.3*VBD V VOH At Isource = 200 μA VBD − 0.2 V VOL At Isink = 200 μA 0.4 V Data Format MSB First MSB First POWER SUPPLY REQUIREMENTS VA Supply Voltage 2.7 3.3 5.5 V VBD Supply Voltage 1.7 3.3 5.5 V Supply Current (Normal Mode) 1-MHz throughput 3.8 mA static state 1.65 mA Power-down State Supply Current 10 μA VBD Supply Current VA = 5.5 V, fs = 1 MHz 10 μA Power-up Time 1 μs Invalid Conversions after Power up or Reset 1 Numbers TEMPERATURE RANGE Specified Performance −40 125 °C

www.3peak.com Rev.1.0 TPC512x 12-bit 1 -MHz SAR ADC Timing Requirements Parameter Conditions Min. Typ Max. Unit tconv Conversion time VBD = 1.8 V 16 SCLK VBD = 3 V 16 VBD = 5 V 16 tq Minimum quiet sampling time needed from bus 3-state to start of next conversion VBD = 1.8 V 40 ns VBD = 3 V 40 VBD = 5 V 40 td1 Delay time, CS̅̅̅̅ low to first data (DO– 15) out VBD = 1.8 V 38 ns VBD = 3 V 27 VBD = 5 V 17 tsu1 Setup time, CS̅̅̅̅ low to first rising edge of SCLK VBD = 1.8 V 8 ns VBD = 3 V 6 VBD = 5 V 4 td2 Delay time, SCLK falling to SDO next data bit valid VBD = 1.8 V 35 ns VBD = 3 V 27 VBD = 5 V 17 th1 Hold time, SCLK falling to SDO data bit valid VBD = 1.8 V 7 ns VBD = 3 V 5 VBD = 5 V 3 td3 Delay time, 16th SCLK falling edge to SDO 3-state VBD = 1.8 V 26 ns VBD = 3 V 22 VBD = 5 V 13 tsu2 Setup time, SDI valid to the rising edge of SCLK VBD = 1.8 V 2 ns VBD = 3 V 3 VBD = 5 V 4 th2 Hold time, the rising edge of SCLK to SDI valid VBD = 1.8 V 12 ns VBD = 3 V 10 VBD = 5 V 6 tw1 Pulse duration CS̅̅̅̅ high VBD = 1.8 V 20 ns VBD = 3 V 20 VBD = 5 V 20 td4 Delay time CS̅̅̅̅ high to SDO 3-state VBD = 1.8 V 24 ns VBD = 3 V 21 VBD = 5 V 12 twh Pulse duration SCLK high VBD = 1.8 V 20 ns VBD = 3 V 20 VBD = 5 V 20 twl Pulse duration SCLK low VBD = 1.8 V 20 ns VBD = 3 V 20 VBD = 5 V 20 Frequency SCLK VBD = 1.8 V 20 MHz VBD = 3 V 20 VBD = 5 V 20

www.3peak.com Rev.1.0 TPC512x 12-bit 1 -MHz SAR ADC Detail description Overview The TPC512 x series of products are 12-bit multichannel, high -speed, low -power, real -time-converting, capacitor-based, and successive approximation register (SAR) analog-to-digital converters (ADC) that use external references. The architecture is based on capacitor charge redistribution, which inherently includes a sample/hold function. The sampling point can be controlled with great precision in time by CSN’s falling edge. The analog inputs to the TPC512x are provided to CHx input channels, all input channels share a common reference ground (AINM). The TPC512x has a multiplexer breakout feature which allows to connect the signal conditioning circuit between the multiplexer output (M O) and the ADC input (AINP). This feature enables the use of common signal conditioning block for the input signal which exhibits similar performance characteristics. Figure 7 The TPC512x can be programmed to select a channel manually or can be programmed into the auto channel select mode to sweep through the input channels automatically. Each frame begins with the falling edge of CSN. With the falling edge of CSN, the input signal from the selected channel is sampled, and the conversion process is initialed. While the conversion is in progress, the device outputs data at the same time. The 16-bit data word contains a 4-bit head data (which could be configured as channel address or GPIO status), followed by a 12-bit conversion result in MSB first format. The device outputs DO15 (first bit of 4-bit head data) on the falling edge of CSN, and outputs DO14~DO0 on the subsequent falling edge of SCLK. If the user configures the input channel to CHx in [N-2]th frame. The device selects CHx on the 2nd SCLK falling edge in the [N-1]th frame. The device starts the acquisition phase of CHx on the 14th SCLK rising edge in the [N-1]th frame. The device ends the acquisition phase and samples the CHx signal on the CSN falling edge in the [N]th frame. And the device outputs the conversion result on the subsequent SCLK falling edge in the [N]th frame. The device offers a 1 /2 input range feature. There are two ways to change the input range. The input range can be changed to 2 by writing DI06 = 1 in the mode control register; in this case, the register is written in on the 16th SCLK rising edge of this frame. And because the input range change is implemented by changing the sampling capacitor. The register takes effect in the acquisition phase in the next frame and affects the output conversion data in the third frame. Another way to change the input range is through GPIO in the case of the TSSOP packaged devices. GPIO2 can act as the RangeSel input. The RangeSel signal takes effect in the next acquisition phase.

www.3peak.com Rev.1.0 TPC512x 12-bit 1 -MHz SAR ADC The TSSOP packaged devices have four General Purpose IO(GPIO) pins while QFN versions have only one GPIO. These four pins can be individually programmed as GPO or GPI. It is also possible to use them for pre - assigned functions. GPO data can be written into the device through the SDI line. The device refreshes the GPO data on the CSN falling edge as per the SDI data written in the previous frame. Similarly, the device latches the GPI status on the CSN falling edge and outputs the GPI data on the SDO line in the same frame starting with the CSN falling edge. The device has two (high and low) programmable alarm thresholds per channel. If the input crosses these limits, the device flags out an alarm on GPIO0/GPIO1 depending on the GPIO program register setting. The alarm is asserted (under the alarm conditions) on the 12th SCLK falling edge in the same frame when data conversion is in progress. The alarm outputs are reset on the 10th falling edge of SCLK in the next frame. The device offers a power-down feature to save power when not in use. There are two ways to power down the device. It can be powered down by writing DI05 = 1 in the mode control register; in this case the device powers down on the 16th falling edge of SCLK in the next frame. The device will power up again with DI05 = 0 in the mode control register. E.g. if the user configures mode control register DI05 = 1 in the [N-2]th frame. The register writes in on the 16th SCLK rising edge in the [N-2]th frame. ADC works properly in the [N-1]th frame. The device powers down ADC on the 16th SCLK falling edge in the [N-1] th frame. The device goes into power-down mode in the [N]th frame. And if the user configures mode control register DI05 = 0 in the [N 1]th frame. The register writes in on the 16th SCLK rising edge in the [N 1] th frame, and the device powers on in the [N 1]th frame. After 1 frame analog settling time, the ADC works properly in the [N 2]th frame. Another way to power down the device is through GPIO in the case of the TSSOP packaged devices. GPIO3 can act as the PDN input. This is an asynchronous and active low input. The device powers down instantaneously after GPIO3(PDN) = 0. Functional block diagram Figure 8 Functional Block Diagram

www.3peak.com Rev.1.0 TPC512x 12-bit 1 -MHz SAR ADC Feature description Device Functional Modes Channel Sequencing Modes Figure 9 Example Manual Mode Timing Diagram Table 1 Mode Control Register Settings for Manual Mode Bits Reset State Logic State Function DI15-12 0001 0001 Selects Manual Mode DI11 0 1 Enables programming of bits DI06-00. 0 Device retains values of DI06-00 from the previous frame. DI10-07 0000 This four-bit data represents the address of the next channel to be selected in the next frame. DI10: MSB and DI07: LSB. For example, 0000 represents channel- 0, 0001 represents channel-1 and so forth. DI06 0

0 Selects 0 to VREF input range (Range 1)

1 Selects 0 to 2xVREF input range (Range 2)

0 Device normal operation (no power-down)

1 Device powers down on 16th SCLK falling edge

0 SDO outputs the current channel address of the channel on

GPIO3-GPIO0 data (both input and output) is mapped onto DO15-DO12 in the order shown below. Lower data bits DO11-DO00 represent the 12-bit conversion result of the current channel. DOI5 DOI4 DOI3 DOI2 GPIO3 (1) GPIO2 (1) GPIO1 (1) GPIO0 (1) DI03-00 0000 GPIO data for the channels configured as output. Device will ignore the data for the channel which is configured as input. SDI bit and corresponding GPIO information is given below DI03 DI02 DI01 DI00 GPIO3 (1) GPIO2 (1) GPIO1 (1) GPIO0 (1) Note: (1) GPIO 1 to 3 are available only in TSSOP packaged devices. QFN device offers GPIO 0 only.

www.3peak.com Rev.1.0 TPC512x 12-bit 1 -MHz SAR ADC Figure 10 Example Auto-1 Mode Timing Diagram Table 2 Mode Control Register Settings for Auto-1 Mode Bits Reset State Logic State Function DI15-12 0001 0010 Selects Auto-1 Mode DI11 0 1 Enables programming of bits DI10-00. 0 Device retains values of DI10-00 from the previous frame. DI10 0

1 The channel counter is reset to the lowest programmed channel in the Auto-1

0 The channel counter increments every conversion (No reset)

DI09-07 000 xxx Do not care DI06 0

1 Device powers down on the 16th SCLK falling edge

0 SDO outputs current channel address of the channel on DO15..12 followed by 12-bit conversion result on DO11..00. GPIO3-GPIO0 data (both input and output) is mapped onto DO15-DO12 in the order shown below. Lower data bits DO11-DO00 represent the 12-bit conversion result of the current channel. DO15 DO14 DO13 DO12 GPIO3 (1) GPIO2 (1) GPIO1 (1) GPIO0 (1) DI03-00 0000 GPIO data for the channels configured as output. Device will ignore the data for the channel which is configured as input. SDI bit and corresponding GPIO information is given below DI03 DI02 DI01 DI00 GPIO3 (1) GPIO2 (1) GPIO1 (1) GPIO0 (1) Note: (1) GPIO 1 to 3 are available only in TSSOP packaged devices. QFN device offers GPIO 0 only.

www.3peak.com Rev.1.0 TPC512x 12-bit 1 -MHz SAR ADC Table 3 Program Register Settings for Auto-1 Mode Bits Reset State Logic State Function FRAME 1 DI15-12 NA 1000 Device enters the Auto-1 program sequence. Device programming is done in the next frame. DI11-00 NA Do not care FRAME 2 DI15-00 All 1s (individual bit) A particular channel is programmed to be selected in the channel scanning sequence. The channel numbers are mapped one-to-one with respect to the SDI bits, for example, DI15 → Ch15, DI14 → Ch14 … DI00 → Ch00 (individual bit) A particular channel is programmed to be skipped in the channel scanning sequence. The channel numbers are mapped one-to-one with respect to the SDI bits, for example DI15 → Ch15, DI14 → Ch14 … DI00 → Ch00

www.3peak.com Rev.1.0 TPC512x 12-bit 1 -MHz SAR ADC Table 4 Mapping of Channels to SDI Bits for 16, 12, 8, 4 Channel Devices Device SDI Bits DI1 DI1 DI1 DI1 DI1 DI1 DI0 DI0 DI0 DI0 DI0 DI0 DI0 DI0 DI0 DI0 Chan 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 Chan 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0

8 Chan 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0

4 Chan 1/0 1/0 1/0 1/0

Note:* When operating in Auto-1 mode, the device only scans the channels programmed to be selected. Table 5 Mode Control Register Settings for Auto-2 Mode Bits Reset State Logic State Function DI15-12 0001 0011 Selects Auto-2 Mode DI11 0 1 Enables programming of bits DI10-00. 0 Device retains values of DI10-00 from the previous frame. DI10 0 1 Channel number is reset to Ch-00. 0 Channel counter increments every conversion. (No reset). DI09-07 000 xxx Do not care DI06 0 0 Selects VREF i/p range (Range 1)

1 Selects 2xVREF i/p range (Range 2)

DI05 0 0 Device normal operation (no power-down) DI04 0 0 SDO outputs the current channel address of the channel on DO15..12 followed by the 12-bit conversion result on DO11..00. GPIO3-GPIO0 data (both input and output) is mapped onto DO15-DO12 in the order shown below. Lower data bits DO11-DO00 represent the 12-bit conversion result of the current channel. DO15 DO14 DO13 DO12 GPIO3 (1) GPIO2 (1) GPIO1 (1) GPIO0 (1) DI03-00 0000 GPIO data for the channels configured as output. Device ignores data for the channel which is configured as input. SDI bit and corresponding GPIO information is given below: DI03 DI02 DI01 DI00 GPIO3 (1) GPIO2 (1) GPIO1 (1) GPIO0 (1) Note: (1) GPIO 1 to 3 are available only in TSSOP packaged devices. QFN device offers GPIO 0 only. Table 6 Program Register Settings for Auto-2 Mode Bits Reset State Logic State Function DI15-12 NA 1001 Auto-2 program register is selected for programming DI11-10 NA Do not care DI09-06 NA aaaa This 4-bit data represents the address of the last channel in the scanning sequence. During device operation in Auto-2 mode, the channel counter starts at CH-00 and increments every frame until it equals “aaaa”. The channel counter roles over to CH-00 in the next frame. DI05-00 NA Do not care

www.3peak.com Rev.1.0 TPC512x 12-bit 1 -MHz SAR ADC Table 7 Continued Operation in a Selected Mode Bits Reset State Logic State Function DI15-12 0001 0000 The device continues to operate in the selected mode. In Auto-1 and Auto- 2 modes the channel counter increments normally, whereas in the Manual mode it continues with the last selected channel. The device ignores data on DI11-DI00 and continues operating as per the previous settings. This feature is provided so that SDI can be held low when no changes are required in the Mode Control Register settings. DI11-00 All '0' Device ignores these bits when DI15-12 is set to 0000 logic state

www.3peak.com Rev.1.0 TPC512x 12-bit 1 -MHz SAR ADC Programming Digital Output As described previously in Overview, the digital output of the devices is SPI compatible. The following tables list the output codes corresponding to various analog input voltages. Table 8 Ideal Input Voltages and Output Codes Description Analog Value Digital Output Straight Binary Full-scale range Range 1 → VREF Range 2 → 2×VREF Least significant bit (LSB) VREF / 4096 2VREF / 4096 BINARY CODE HEX CODE Full scale VREF – 1 LSB 2VREF – 1 LSB 1111 1111 1111 FFF Midscale VREF / 2 VREF 1000 0000 0000 800 Midscale – 1 LSB VREF / 2 – 1 LSB VREF – 1 LSB 0111 1111 1111 7FF Zero 0 V 0 V 0000 0000 0000 000 Table 9 GPIO Program Register Settings Bits Reset State Logic State Function DI15-12 NA 0100 Device selects GPIO Program Registers for programming. DI11-10 00 00 Do not program these bits to any logic state other than ‘00’ DI09 0

1 Device resets all registers in the next CS̅̅̅̅ frame to the reset state shown in the

corresponding tables (it also resets itself).

0 Device normal operation

1 Device configures GPIO3 as the device power-down input. 0 GPIO3 remains general purpose I or O. Program 0 for QFN packaged devices. DI07 0 1 Device configures GPIO2 as device range input. 0 GPIO2 remains general purpose I or O. Program 0 for QFN packaged devices. DI06-04 000 000 GPIO1 and GPIO0 remain general purpose I or O. Valid setting for QFN packaged devices. xx1 Device configures GPIO0 as a ‘high or low’ alarm output. This is an active high output. GPIO1 remains general purpose I or O. Valid setting for QFN packaged devices. 010 Device configures GPIO0 as a high alarm output. This is an active high output. GPIO1 remains general purpose I or O. Valid setting for QFN packaged devices. 100 Device configures GPIO1 as a low alarm output. This is an active high output. GPIO0 remains general purpose I or O. Setting is not allowed for QFN packaged devices. 110 Device configures GPIO1 as a low alarm output and GPIO0 as a high alarm output. These are active high outputs. Setting is not allowed for QFN-packaged devices. Note: The following settings are valid for GPIO which are not assigned a specific function through bits DI08..04 DI03 0 1 GPIO3 pin is configured as a general-purpose output. Program 1 for QFN- packaged devices. 0 GPIO3 pin is configured as a general-purpose input. The setting is not allowed for QFN packaged devices. DI02 0 1 GPIO2 pin is configured as a general-purpose output. Program 1 for QFN- packaged devices. 0 GPIO2 pin is configured as a general-purpose input. The setting is not allowed for QFN-packaged devices. DI01 0 1 GPIO1 pin is configured as a general-purpose output. Program 1 for QFN packaged devices.

www.3peak.com Rev.1.0 TPC512x 12-bit 1 -MHz SAR ADC 0 GPIO1 pin is configured as a general-purpose input. The setting is not allowed for QFN packaged devices. DI00 0 1 GPIO0 pin is configured as a general-purpose output. Valid setting for QFN packaged devices. 0 GPIO0 pin is configured as a general-purpose input. Valid setting for QFN packaged devices. Table 10 Grouping of Alarm Program Registers Group No. Registers Applicable for Device

0 High and low alarms for channels 0, 1, 2, and 3 TPC5120

1 High and low alarms for channels 4, 5, 6, and 7 TPC5120, TPC5121

2 High and low alarms for channels 8, 9, 10, and 11 TPC5120

3 High and low alarms for channels 12, 13, 14, and 15 TPC5120

Table 11 Alarm Program Register Settings Bits Reset State Logic State Function FRAME 1 DI15-12 NA

1100 Device enters ‘alarm programming sequence’ for group 0

1101 Device enters ‘alarm programming sequence’ for group 1

1110 Device enters ‘alarm programming sequence’ for group 2

1111 Device enters ‘alarm programming sequence’ for group 3

Note: DI15-12 = 11bb is the alarm programming request for group bb. Here ‘bb’ represents the alarm programming group number in binary format. DI11-14 NA Do not care FRAME 2 AND ONWARDS DI15-14 NA cc Where “cc” represents the lower two bits of the channel number in binary format. The device programs the alarm for the channel represented by the binary number “bbcc”. “bb” is programmed in the first frame. DI13 NA

1 High alarm register selection

0 Low alarm register selection

0 Continue the alarm programming sequence in the next frame

Exit Alarm Programming in the next frame. Note: If the alarm programming sequence is not terminated using this feature, then the device will remain in the alarm programming sequence state and all SDI data will be treated as alarm thresholds. DI11-10 NA xx Do not care DI09-00 All ones for high alarm register and all zeros for low alarm register This 10-bit data represents the alarm threshold. The 10-bit alarm threshold is compared with the upper 10-bit word of the 12-bit conversion result. The device sets off an alarm when the conversion result is higher (High Alarm) or lower (Low Alarm) than this number. For 10-bit devices, all 10 bits of the conversion result are compared with the set threshold. For 8-bit devices, all 8 bits of the conversion result are compared with DI09 to DI02 and DI00, and 01 are 'do not care'.

www.3peak.com Rev.1.0 TPC512x 12-bit 1 -MHz SAR ADC Register Maps Address Type Default Register Name 4'b0000 W 12'h000 Continued Operation in a Selected Mode 4'b0001 R/W 12'h000 Manual Mode Control Register 4'b0010 R/W 12'h000 Auto-1 Mode Control Register 4'b0011 R/W 12'h000 Auto-2 Mode Control Register 4'b0100 R/W 12'h000 GPIO Program Register 4'b0101 / 12'h000 Reserved and forbidden to read/write. 4'b0110 / 12'h000 Reserved and forbidden to read/write. 4'b0111 R/W 12'h000 Reference enable. This register is only for TPC5121. Reserved for TPC5120. 4'b1000 R/W 16'hffff Auto-1 Mode Program Register 4'b1001 R/W 12'h3c0 Auto-2 Mode Program Register 4'b1100 W Group 0 Alarm Program Register 2'b00 R/W 10'h3ff Channel 0 High Alarm Register R/W 10'h000 Channel 0 Low Alarm Register 2'b01 R/W 10'h3ff Channel 1 High Alarm Register R/W 10'h000 Channel 1 Low Alarm Register 2'b10 R/W 10'h3ff Channel 2 High Alarm Register R/W 10'h000 Channel 2 Low Alarm Register 2'b11 R/W 10'h3ff Channel 3 High Alarm Register R/W 10'h000 Channel 3 Low Alarm Register 4'b1101 W Group 1 Alarm Program Register 2'b00 R/W 10'h3ff Channel 4 High Alarm Register R/W 10'h000 Channel 4 Low Alarm Register 2'b01 R/W 10'h3ff Channel 5 High Alarm Register R/W 10'h000 Channel 5 Low Alarm Register 2'b10 R/W 10'h3ff Channel 6 High Alarm Register R/W 10'h000 Channel 6 Low Alarm Register 2'b11 R/W 10'h3ff Channel 7 High Alarm Register R/W 10'h000 Channel 7 Low Alarm Register 4'b1110 W Group 2 Alarm Program Register 2'b00 R/W 10'h3ff Channel 8 High Alarm Register R/W 10'h000 Channel 8 Low Alarm Register 2'b01 R/W 10'h3ff Channel 9 High Alarm Register R/W 10'h000 Channel 9 Low Alarm Register 2'b10 R/W 10'h3ff Channel 10 High Alarm Register R/W 10'h000 Channel 10 Low Alarm Register 2'b11 R/W 10'h3ff Channel 11 High Alarm Register R/W 10'h000 Channel 11 Low Alarm Register 4'b1111 W Group 3 Alarm Program Register 2'b00 R/W 10'h3ff Channel 12 High Alarm Register R/W 10'h000 Channel 12 Low Alarm Register 2'b01 R/W 10'h3ff Channel 13 High Alarm Register R/W 10'h000 Channel 13 Low Alarm Register

www.3peak.com Rev.1.0 TPC512x 12-bit 1 -MHz SAR ADC 2'b10 R/W 10'h3ff Channel 14 High Alarm Register R/W 10'h000 Channel 14 Low Alarm Register 2'b11 R/W 10'h3ff Channel 15 High Alarm Register R/W 10'h000 Channel 15 Low Alarm Register Register Identification Table 12 Manual Mode Control Register (4'b0001) Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 NA NA NA NA ManuLSBEn ManuChnl[3] ManuChnl[2] ManuChnl[1] 1'b0 1’b0 1’b0 1’b0 1'b0 1’b0 1’b0 1’b0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ManuChnl[0] ManuRangSe l ManuP d ManuGPIOE n ManuGPIOData[3 ManuGPIOData[2 ManuGPIOData[1 ManuGPIOData[0 1’b0 1’b0 1’b0 1’b0 1’b0 1’b0 1’b0 1’b0 Table 13 Auto-1 Mode Control Register (4'b0010) Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 NA NA NA NA Auto1LSBEn Auto1ChnlRst NA NA 1'b0 1’b0 1’b0 1’b0 1'b0 1’b0 1’b0 1’b0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 NA Auto1RangSel Auto1Pd Auto1GPIOEn Auto1GPIOData[3] Auto1GPIOData[2] Auto1GPIOData[1] Auto1GPIOData[0] 1’b0 1’b0 1’b0 1’b0 1’b0 1’b0 1’b0 1’b0 Table 14 Auto-2 Mode Control Register (4'b0011) Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 NA NA NA NA Auto2LSBEn Auto2ChnlRst NA NA 1'b0 1’b0 1’b0 1’b0 1'b0 1’b0 1’b0 1’b0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 NA Auto2RangSel Auto2Pd Auto2GPIOEn Auto2GPIOData[3] Auto2GPIOData[2] Auto2GPIOData[1] Auto2GPIOData[0] 1’b0 1’b0 1’b0 1’b0 1’b0 1’b0 1’b0 1’b0 Table 15 RefEn Register (4'b0111) Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 NA NA NA NA NA NA NA NA 1'b0 1’b0 1’b0 1’b0 1’b0 1’b0 1’b0 1’b0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 NA NA NA NA NA NA RefEn NA 1’b0 1’b0 1’b0 1’b0 1’b0 1’b0 1’b0 1’b1 Note: This register is only for TPC5121. Table 16 GPIO Program Register (4'b0100) Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 NA NA NA NA 1'b0 1'b0 GPIORegRst GPIO3PdIn

www.3peak.com Rev.1.0 TPC512x 12-bit 1 -MHz SAR ADC 1'b0 1’b0 1’b0 1’b0 1'b0 1’b0 1’b0 1’b0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 GPIO2RangeIn GPIO10Cfg[2] GPIO10Cfg[1] GPIO10Cfg[0] GPIO3Cfg GPIO2Cfg GPIO1Cfg GPIO0Cfg 1’b0 1’b0 1’b0 1’b0 1’b0 1’b0 1’b0 1’b0 Table 17 Auto-1 Mode Program Register (4'b1000) Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Auto1Chnl[15] Auto1Chnl[14] Auto1Chnl[13] Auto1Chnl[12] Auto1Chnl[11] Auto1Chnl[10] Auto1Chnl[9] Auto1Chnl[8] 1'b1 1’b1 1'b1 1’b1 1'b1 1’b1 1'b1 1’b1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Auto1Chnl[7] Auto1Chnl[6] Auto1Chnl[5] Auto1Chnl[4] Auto1Chnl[3] Auto1Chnl[2] Auto1Chnl[1] Auto1Chnl[0] 1'b1 1’b1 1'b1 1’b1 1'b1 1’b1 1'b1 1’b1

www.3peak.com Rev.1.0 TPC512x 12-bit 1 -MHz SAR ADC Table 18 Auto-2 Program Register (4'b1001) Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 NA NA NA NA NA NA Auto2Chnl[3] Auto2Chnl[2] 1'b0 1’b0 1’b0 1’b0 1’b0 1’b0 1'b1 1’b1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Auto2Chnl[1] Auto2Chnl[0] NA NA NA NA NA NA 1'b1 1’b1 1’b0 1’b0 1’b0 1’b0 1’b0 1’b0 Table 19 Group0 Alarm Program Register (4'b1100) Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 ChnlNumLSB[1] ChnlNumLSB[0] HiAlarmRegSel AlarmPgCont NA NA AlarmTh[9] AlarmTh[8] 1'b0 1’b0 1’b0 1’b0 1’b0 1’b0 1’b0 1’b0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 AlarmTh[7] AlarmTh[6] AlarmTh[5] AlarmTh[4] AlarmTh[3] AlarmTh[2] AlarmTh[1] AlarmTh[0] 1’b0 1’b0 1’b0 1’b0 1’b0 1’b0 1’b0 1’b0 Table 20 Group1 Alarm Program Register (4'b1101) Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 ChnlNumLSB[1] ChnlNumLSB[0] HiAlarmRegSel AlarmPgCont NA NA AlarmTh[9] AlarmTh[8] 1'b0 1’b0 1’b0 1’b0 1’b0 1’b0 1’b0 1’b0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 AlarmTh[7] AlarmTh[6] AlarmTh[5] AlarmTh[4] AlarmTh[3] AlarmTh[2] AlarmTh[1] AlarmTh[0] 1’b0 1’b0 1’b0 1’b0 1’b0 1’b0 1’b0 1’b0 Table 21 Group2 Alarm Program Register (4'b1110) Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 ChnlNumLSB[1] ChnlNumLSB[0] HiAlarmRegSel AlarmPgCont NA NA AlarmTh[9] AlarmTh[8] 1'b0 1’b0 1’b0 1’b0 1’b0 1’b0 1’b0 1’b0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 AlarmTh[7] AlarmTh[6] AlarmTh[5] AlarmTh[4] AlarmTh[3] AlarmTh[2] AlarmTh[1] AlarmTh[0] 1’b0 1’b0 1’b0 1’b0 1’b0 1’b0 1’b0 1’b0 Table 22 Group3 Alarm Program Register (4'b1111) Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 ChnlNumLSB[1] ChnlNumLSB[0] HiAlarmRegSel AlarmPgCont NA NA AlarmTh[9] AlarmTh[8] 1'b0 1’b0 1’b0 1’b0 1’b0 1’b0 1’b0 1’b0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 AlarmTh[7] AlarmTh[6] AlarmTh[5] AlarmTh[4] AlarmTh[3] AlarmTh[2] AlarmTh[1] AlarmTh[0] 1’b0 1’b0 1’b0 1’b0 1’b0 1’b0 1’b0 1’b0

www.3peak.com Rev.1.0 TPC512x 12-bit 1 -MHz SAR ADC Table 23 RefEn & FullDifEn Register (4'b0111) Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 NA NA NA NA NA NA NA NA 1'b0 1’b0 1’b0 1’b0 1’b0 1’b0 1’b0 1’b0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 NA NA NA NA NA NA RefEn Reserved 1’b0 1’b0 1’b0 1’b0 1’b0 1’b0 1’b0 1’b1

Application Information

………… CH0 4pF CH1 4pF CHn 4pF 4pF 4pF110Ω MXO AINP AIN M 4pF 25Ω 45Ω 9pF 9pF In general application, the converting process is as below: 1. Multiplexer switch is close (meanwhile, the sampling switch is open, and ADC is in the conversion phase), channel input source charges the parasitic capacitor of M O/AINP. 2. The sampling switch is close, and the 12-pF sampling capacitor, which is charged to the previously converted channel, is recharged to the current converting channel. 3. The sampling switch opens again. The sampling capacitor holds the signal, and the device goes into the conversion phase. 4. While the conversion is in progress, the device outputs data at the same time. And because the sampling switch is open, the multiplexer switch can switch to another channel freely on the 2nd SCLK rising edge in this phase. 5. Repeat 1~4. Analog Input There are about 22 -pF internal capacitors in total. These capacitors consist of pin parasitic capacitors and sampling capacitors. Before the multiplexer switch of the current converting channel close, these capacitors are charged to the previous channel signal. And these capacitors must settle to the current converting channel

www.3peak.com Rev.1.0 TPC512x 12-bit 1 -MHz SAR ADC signal before the sampling switch opens. Several methods can be adopted to achieve enough performance. 1. Low impedance input source. 2. Large enough CHx decouple capacitor. Users can tradeoff between source character, performance, and sampling rate. E.g. Assume source signal voltage 2 V, current saturation less than 1.5 V, source equivalent impedance 1 Kohms, 12-bit resolution requirement. If the previous channel is 0 V, and the 22-pF capacitor should be charged from 0 V to 1.5 V, and step should be higher than 1 V. Then 𝐶𝐶𝐻𝑥 × 2 𝑉 + 22 𝑝𝐹 × 0 𝑉 > (𝐶𝐶𝐻𝑥 + 22 𝑝𝐹) × 1.5 𝑉, 𝐶𝐶𝐻𝑥 > 66 𝑝𝐹, leave some guard band, 150-pF decouple capacitor should be added to CHx. In order to calculate easily, all internal capacitor is charged in the Acquisition phase. At the beginning of the Acquisition phase, charge balance between channel decouple capacitor and internal capacitor, the initial voltage is (𝐶𝐶𝐻𝑥 × 2 𝑉 + 𝐶𝑖𝑛𝑡 × 2 𝑉) ÷ (𝐶𝐶𝐻𝑥 + 𝐶𝑖𝑛𝑡) = 1.7 𝑉 , and the final voltage is 2 V, 𝜏 = 1 𝑘𝛺 × (150 𝑝𝐹 + 22 𝑝𝐹) = 172 𝑛𝑠 , and settle err is less than 1LSB=610 μV, the Acquisition time should be longer than 𝜏 × 𝑙𝑛((2 𝑉 − 1.7 𝑉)/610 μ𝑉) = 1.06 μ𝑠. Reference The TPC512x can operate with an external 2 V ~ VA reference. A clean, low-noise, low-output impedance, and well-decoupled reference voltage on the REFP pin is required to ensure the good performance of the converter. A 10-uf ceramic decoupling capacitor is required between the REFP and REFM pins of the converter. The capacitor should be placed as close as possible to the pins of the device. The connection between REFM and ground should be solid and should be avoided sharing any common path with other devices. Because the reference input resistance of this device is about 16 Kohms, the sum of reference output resistance and total parasitic resistance of REFP and REFM should be less than 4 ohms (which is easy to achieve with careful layout). SPI Interface The device converts input and outputs conversion results simultaneously. In order to reduce the effect of SPI output flipping, the drive capability of this device is weaker than other parts. So lighter SDO capacitive loading is required (less than 20 pF) in the high-speed application.

www.3peak.com Rev.1.0 TPC512x 12-bit 1 -MHz SAR ADC Tape and Reel Information Order Number Package D1 (mm) (mm) (mm) (mm) (mm) (mm) (mm) Pin1 Quadrant TPC5120S16-TS7R-S TSSOP38 329 16.4 6.8 10.25 1.6 8 16 Q1 TPC5120S16-QFBR QFN5 5-32 330 16 5.2 5.2 1.1 8 12 Q1 TPC5121S08-QF8R QFN4 4-24 330 16 4.35 4.35 1.1 8 12 Q1

www.3peak.com Rev.1.0 TPC512x 12-bit 1 -MHz SAR ADC

Package Information

www.3peak.com Rev.1.0 TPC512x 12-bit 1 -MHz SAR ADC QFN5X5-32

www.3peak.com Rev.1.0 TPC512x 12-bit 1 -MHz SAR ADC QFN4X4-24

www.3peak.com Rev.1.0 TPC512x 12-bit 1 -MHz SAR ADC Order Information Order Number Operating Temperature Range Package Marking Information MSL Transport Media, Quantity Eco Plan TPC5120S16-TS7R-S −40 to 125°C TSSOP38 5120 MSL3 Tape reel, 3000 Green TPC5120S16-QFBR −40 to 125°C QFN5 5-32 5120 MSL3 Tape reel, 3000 Green TPC5121S08-QF8R −40 to 125°C QFN4 4-24 5121 MSL3 Tape reel, 3000 Green Green: 3PEAK defines "Green" to mean RoHS compatible and free of halogen substances.

www.3peak.com Rev.1.0 TPC512x 12-bit 1 -MHz SAR ADC IMPORTANT NOTICE AND DISCLAIMER Copyright© 3PEAK 2012-2023. All rights reserved. Trademarks. Any of the 思瑞浦 or 3PEAK trade names, trademarks, graphic marks, and domain names contained in this document /material are the property of 3PEAK. You may NOT reproduce, modify, publish, transmit or distribute any Trademark without the prior written consent of 3PEAK. Performance Information. Performance tests or performance range contained in this document/material are either results of design simulation or actual tests conducted under designated testing environment. Any variation in testing environment or simulation environment, including but not limited to testing method, testing process or testing temperature, may affect actual performance of the product. Disclaimer. 3PEAK provides technical and reliability data (including data sheets), design resources (including reference designs), application or other design recommendations, networking tools, security information and other resources "As Is". 3PEAK makes no warranty as to the absence of defects, and makes no warranties of any kind, express or implied, including without limitation, implied warranties as to merchantability, fitness for a particular purpose or non-infringement of any third- party’s intellectual property rights. Unless otherwise specified in writing, products supplied by 3PEAK are not designed to be used in any life-threatening scenarios, including critical medical applications, automotive safety-critical systems, aviation, aerospace, or any situations where failure could result in bodily harm, loss of life, or significant property damage. 3PEAK disclaims all liability for any such unauthorized use.