TPC219

TPC219 3PEAK | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 30

Technical content

Features

• High accuraccy – INL: typical ±1LSB at 16-bit Resolution
• Integrated 2.5V Internal Reference – Low Drift: 5ppm/℃
• Flexible output configuration – User selectable Gain: 1/2, 1, 2 – Reset to Zero Scale or Midscale
• High output current capability: 20mA
• Serial Interfaces – 4 Wire SPI Compatible Serial Interface – Daisy Chain Operation – CRC Error Check
• Temperature Range: −40°C to +125°C
• Package: QFN 3X3-16, WLCSP 2.4X2.4-16

Applications

• Industrial automation
• Optical networking
• Data Acquisition Systems

Description

The TPC219 is faimily of high accuracy DACs with 16, 14 and 12bit resolution which are all pin-compatible. The device includes a 2.5V internal reference, which can be used to reduce system complexity Several gain options could be selected to provide different full scale output voltages, 1.25V, 2.5V and 5V. The device operates under a single analog supply, and has seperate VIO supply for digital communication. The communication is performed through a serial interface, and can operate under wide range VIO supply voltage. A power on reset circuit is intergraged to maintain the DAC output at zero scale or midscale. The device is characterized for temeprature range of -40 ℃ to 125 ℃. And is available in small package of QFN and WLCSP. Typical Application Circuit Divided by 1 or 2 Internal Reference Power On Reset Level DAC Buffer DAC registerDAC Gain x1 or x2 BUF Power down logicChannel 0 Channel 1 Channel 7 Serial Interface and Digital SCLK SDI SDO/ALARM or CLR CS VIO VDD REF GND OUT0 OUT1 OUT2~6 OUT7 TPC219 8-Channel high precision Voltage output DAC with internal Reference www.3peak.com 1 / 30 Rev.A.0

8-Channel high precision Voltage output DAC with internal Reference www.3peak.com 2 / 30 Rev.A.0

Order Number Resolution Reference RESET SDO or CLR Operation Package TPC2190-QFNR 16 Internal/External 0 SDO QFN3X3-16 TPC2190-WLPR 16 Internal/External 0 SDO WLCSP2.4X2.4-16 TPC2190M-QFNR 16 Internal/External Midscal SDO QFN3X3-16 TPC2192-QFNR (1) 12 Internal/External 0 SDO QFN3X3-16 TPC2192-WLPR 12 Internal/External 0 SDO WLCSP2.4X2.4-16 Note: (1) Could provide samples in 2 months.

Revision History

2023/6/5 Rev.A.0 Released Version. TPC219 8-Channel high precision Voltage output DAC with internal Reference www.3peak.com 3 / 30 Rev.A.0

Pin Configuration and Functions TPC219 Top View TPC219 Top View REF 1 OUT3 5 6 7 8 16 15 14 13 OUT0 OUT1 OUT2 OUT5 OUT6 OUT7 CS OUT4 VDD GND VIO SCLK SDI SDO/ALARM Thermal Pad OUT3 GND VDD OUT6OUT2OUT1 REF OUT0 OUT7 1 2 3 B A C OUT4 OUT5 CS VIO SDO/ALARM SDI SCLKD Table 1. Pin Functions NO. WQFN NO. WLCSP NAME TYPE 1 C1 REF I/O Reference output pin(default). Can be used as reference inpput pin when using external reference. 2 C2 OUT0 O DAC channel 0 output. 3 B1 OUT1 O DAC channel 1 output. 4 B2 OUT2 O DAC channel 2 output. 5 A1 OUT3 O DAC channel 3 output. 6 A2 GND GND Ground pin. 7 A3 VDD PWR Analog supply pin. 8 A4 OUT4 O DAC channel 4 output. 9 B4 OUT5 O DAC channel 5 output. 10 B3 OUT6 O DAC channel 6 output. 11 C3 OUT7 O DAC channel 7 output. 12 C4 CS I Frame synchronization signal for SPI interface. 13 D4 SCLK I Clock input for SPI interface. 14 D3 SDI I Data input for SPI interface.

15 D2 SDO/ALARM O

TPC216X: Data output for SPI interface. It is in high impedance when /CS is high. And the pin can also be configured as /Alarm pin, which is open-drain output to indicate a CRC or reference alarm event. TPC219 8-Channel high precision Voltage output DAC with internal Reference www.3peak.com 4 / 30 Rev.A.0

NO. WQFN NO. WLCSP NAME TYPE LR I TPC216XC: A low value on /CLR pin clears DAC registers and output to the reset value. A high value on /CLR pin causes the device to exit clear mode. 16 D1 VIO PWR IO supply pin. - - Thermal Pad - Thermal pad should be connected to PCB ground plane. TPC219 8-Channel high precision Voltage output DAC with internal Reference www.3peak.com 5 / 30 Rev.A.0

Absolute Maximum Ratings (1) MIN MAX UNIT Supply Voltage VDD to GND –0.3 6 V VIO to GND –0.3 6 V Pin voltage DAC outputs to GND –0.3 VDD + 0.3 V REF to GND –0.3 VDD + 0.3 V Digital pins to GND –0.3 VIO + 0.3 V Input current Input current to any pin excep supply pins -10 10 mA Temperature Junction, TJ -40 150 ℃ Storage, Tstg -60 150 ℃ (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. ESD, Electrostatic Discharge Protection Symbol Parameter Condition Minimum Level Unit HBM Human Body Model ESD ANSI/ESDA/JEDEC JS-001 (1) 4 kV CDM Charged Device Model ESD ANSI/ESDA/JEDEC JS-002 (2) 1.5 kV (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Recommended Operating Conditions MIN NOM MAX UNIT VDD Analog supply voltage 2.7 5.5 V VIO Digital IO supply voltage 1.7 5.5 V Digital input voltage Digital input voltage 0 VIO V VREFIN Reference divider disabled 1.2 (VDD-0.2)/2 V Reference divider enabled 2.4 VDD-0.2 V Reference divider disabled 1.2 VDD/2 V TPC219 8-Channel high precision Voltage output DAC with internal Reference www.3peak.com 6 / 30 Rev.A.0

enabled 2.4 VDD V TJ Operating Junction temperature –40 125 °C Thermal Information Package Type θJA θJC Unit QFN3X3-16 33 29.5 °C/W WLCSP 68 0.3 °C/W TPC219 8-Channel high precision Voltage output DAC with internal Reference www.3peak.com 7 / 30 Rev.A.0

Electrical Characteristics

GND,CLOAD=200pF to GND,digital inputs at VIO or GND,TJ = –40℃ to +125℃ and all typical specifications at TJJ = 25℃. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STATIC PERFORMANCE Note:Static performance specified with DAC outputs unloaded for all gain options, unless otherwise noted. End point fit between codes. 16-bit: Code 256 to 65280 Resolution 16 Bits DNL (TPC2190) Differential nonlinearity -1 ±0.5 1.5 LSB DNL (TPC2192) Differential nonlinearity -1 ±0.5 1 LSB INL (TPC2190) INL (TPC2192) Integral nonlinearity -1 ±0.5 1 LSB TUE Total unadjusted error REF-DIV=0 ±0.05 ±0.2 %FSR REF-DIV=1 ±0.05 ±0.3 %FSR OE Offset error All Gians ±0.75 ±2.5 mV Offset error temperature drift ±1.5 uV/°C GE Gain error REF-DIV=0 ±0.05 ±0.1 %FSR REF-DIV=1 ±0.05 ±0.2 %FSR Gain error temperature drift ±1.2 ppm of FSR/°C ZSE Zero-scale error DAC code = zero scale 0.5 2.5 mV Zero-scale error temperature drift ±1.5 uV/°C FSE Full-scale error REF-DIV=0 ±0.05 ±0.15 %FSR REF-DIV=1 ±0.05 ±0.25 %FSR Full-scale error temperature drift ±2 ppm of FSR/°C OUTPUT CHARACTERISTICS Voltage range Gain = 2 (BUFF-GAIN = 1, REF-DIV = 0) 0 2 x V REF V Gain = 1 (BUFF-GAIN = 1, REF-DIV = 1) 0 V REF V Gain =1/2 (BUFF-GAIN = 0, REF-DIV = 1) 0 1/2 x V REF V Output voltage headroom to GND or VDD (unloaded) 0.004 V to GND or VDD (-10 mA ≤ IOUT ≤ 10 mA) 0.3 V TPC219 8-Channel high precision Voltage output DAC with internal Reference www.3peak.com 8 / 30 Rev.A.0

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Short circuit current (1) DAC code = full scale. Output shorted to GND 28 mA DAC code = zero scale. Output shorted to VDD 25 mA CL Capacitive load stability (2) RLOAD=∞ 0 2 nF RLOAD=2kΩ 0 10 RL Clamp resistance 1 kΩ Load regulation DAC code = midscale, -10 mA <= IOUT<= 10 mA 85 µV/mA DC output impedance DAC code = midscale 0.085 Ω DYNAMIC PERFORMANCE Tst Output voltage settling time 1/4 to 3/4 scale and 3/4 to 1/4 scale settling to ±2 LSB V DD =5.5V,V REFIN =2.5V,GAIN=2 6 µs Slew rate V DD =5.5V,V REFIN =2.5V,GAIN=2 , 10% to 90%

0.8 V/µs

0.1 Hz to 10 Hz, midscale

code,V DD =5.5V,V REFIN =2.5V,GAIN=2 17 µVpp Output noise density 1kHz, midscale code,V DD =5.5V,V REFIN =2.5V,GAIN=2 nV/√Hz 10kHz, midscale code,V DD =5.5V,V TPC219 8-Channel high precision Voltage output DAC with internal Reference www.3peak.com 9 / 30 Rev.A.0

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT REFIN =2.5V,GAIN=2 1kHz, midscale code,V DD =5.5V,V REFIN =2.5V,GAIN=1 10kHz, midscale code,V DD =5.5V,V REFIN =2.5V,GAIN=1 PSRRac AC PSRR Midscale code, frequency =60 Hz, amplitude = 200 mVPP superimposed on V DD 76 dB PSRRdc DC PSRR Midscale code,VDD= 5V±10% 20 uV/V Code change glitch impulse 1 LSB change around major carrier 2.5 nV-s Power-up time DACx-PWDWN 1 to 0 transition. DAC code = full scale. VDD = 5.5 V, VREFIN = 2.5 V, Gain = 2 (3) 14.2 µs Power-down glitch amplitude DAC code = zero scale. VDD = 5.5 V, VREFIN = 2.5 V, Gain = 2. CLOAD = 50 pF 25 mV Overshot/Downshot 1/4 to 3/4 scale and 3/4 to 1/4 scale VDD=5.5V,VREFIN=2.5V,GAI N=2 Channel-to-channel AC crosstalk Measured DAC output at midscale, Code 32 to full- scale swing on asjacent channel nV-s Channel-to-channel DC crosstalk Measured DAC output at midscale, all other DAC outputs at full-scale, Gain=1 1 µV TPC219 8-Channel high precision Voltage output DAC with internal Reference www.3peak.com 10 / 30 Rev.A.0

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Measured DAC output at midscale, all other DAC outputs at full-scale, Gain=2 10 µV INTERNAL REFERENCE CHARACTERISTICS VREFOUT Internal referencel voltage TA = 25°C 2.494 2.5 2.506 V TC Internal reference temperature coefficient TJ = -40°C to 125°C 8 ppm/°C Internal reference impedance 0.1 Ω Internal reference output noise 0.1 Hz to 10 Hz 15 µVPP Internal reference noise density 10 kHz, REFLOAD = 10 nF 370 nV/ sqrtHz Internal reference load current ±5 mA refierence Load regulation source and sink 100 uV/mA Internal reference load cap actual capacitance 300 2200 nF EXTERNAL REFERENCE CHARACTERISTICS Referencel input current V REFIN =2.5V 25 uA Referencel input impedance 100 kΩ Referencel input capacitance 5 pF DIGITAL INPUT CHARACTERISTICS VIH High-level input voltage 0.7 × VIO V VIL Low-level input voltage 0.3 × VIO V Input current ±2 µA Input pin capacitance 2 pF DIGITAL OUTPUT CHARACTERISTICS VOH High-level output voltage ILOAD = 0.2 mA VIO – 0.4 V VOL Low-level output voltage ILOAD = 0.2 mA 0.4 V Output pin capacitance 4 pF POWER CONSUMPTION CHARACTERISTICS IVDD VDD supply current Active mode. Internal reference enabled. Gain = 1. DAC code = full scale. Outputs unloaded. SPI static 5 6 mA TPC219 8-Channel high precision Voltage output DAC with internal Reference www.3peak.com 11 / 30 Rev.A.0

reference disabled. Gain = 1. GND,CLOAD=200pF to GND,digital inputs at VIO or GND,TJ = –40℃ to +125℃ and all typical specifications at TJJ = 25℃. Figure 1. SPI Write Timing Diagram

Figure 2. SPI ReadTiming Diagram

Figure 11. Functional Block Diagram CODE = decimal value of the binary code in the DAC register. VREF = DAC reference voltage. DIV: 1 or 2 as set by REF-DIV bit. Gain: 1 or 2 as set bu BUFF-GAIN bit.

Data written to the DAC data registers is initially stored in the DAC buffer registers. And then transfer of data from the DAC buffer registers to the active DAC registers, can be selected to happen immediately (asynchronous mode) or initiated by an LDAC trigger (synchronous mode). Once the DAC active registers are updated, the DAC outputs change to the new values. When a DAC Data register is read, the value held in the DAC buffer register is returned (not the value in the DAC active register). The SYNC-EN bit controls the update mode for each DAC channel. In asynchronous mode, writing to the DAC data register results in an immediate update of the DAC active register and DAC output on the CS rising edge. In synchronous mode, writing to the DAC data register does not update the DAC output, but the update happens when an LDAC trigger event is generated through the LDAC bit. The synchronous update mode can update multiple DAC outputss imultaneously. A DAC broadcast register is proved to simultaneously update multiple DAC outputs with the same value by a single register write. Each DAC channel can be configured to be updated or not by a broadcast command, through the corresponding DAC-BRDCAST-EN bit. A register write to the BRDCAST-DATA register forces selected DAC channels that have been configured for broadcast operation to update their outputs. The DAC ouputs update to the broadcast value on CS rising edge independently of their synchronous mode configuration. CLEAR Operation The CLRpin can update multiple DAC outputs to the clear value simultaneously: zero code or midscale code (for different parts). Channels can be independently configured to update or remain unaffected by theCLRpin Reference The device provides a internal 2.5V reference, which is enabled by default after power up. The internal reference is available on the REF pin. And External reference is supported by disabling the enable reference by CONFIG register. The reference voltage from the internal reference or an external one can be divided by a factor of two by setting the REF-DIV bit. Reset Options After power up, and the V DDand V IO supplies have settled, the Power On Reset (POR) function causes all registers to initialize to their default values. And DAC output remains at the power-up voltage. A software reset is provided by writing the reserved code 0x1010 to SOFT-RESET bits. Functional Modes Stand Alone Operation A serial interface access cycle can be initiated by asserting the ovCS pin low. SDI data are clocked on SCLK falling edges. A regular serial interface access cycle is 24 bits long with error checking disabled and 32 bits long with error checking enabled. If the access cycle contains more than the minimum clock edges, only the last 24 or 32 bits are used by the device. Daisy Chain Operation For systems that contain more than one devices, the SDO pin can be used to daisy-chain them together. Daisy-chain operation is useful in reducing the number of serial interface lines. By connecting the SDO output of the first device to the SDI input of the next device in the chain, a multiple-device interface is constructed. Each device in the system requires 24 clock pulses. As a result the total number of clock cycles must be equal to 24 × N, where N is the total number of devices in the daisy chain. TPC219 8-Channel high precision Voltage output DAC with internal Reference www.3peak.com 17 / 30 Rev.A.0

SCLK according to the FSDO bit. The error checking scheme is based on the CRC-8-ATM (HEC) polynomial x8 + x2 + x + 1 (that is, 100000111). with an 8-bit CRC polynomial by the host processor before feeding it to the device. Table 2. Error Checking Serial Interface Access Cycle register. R/W = 0 sets a write operation. R/W = 1 sets a read operation. 30 CRC-ERROR Reserved bit. Set to zero. 29:28 Reserved Reserved bits. Must be filled with zeros. cycle bits are don’t care values. 7:0 CRC 8-bit CRC polynomial. remainder is zero and data are accepted by the device. Table 3. Write Operation Error Checking Cycle

31 RW Echo RW from previous access cycle

30 CRC-ERROR Returns a 1 when a CRC error is

23:8 DO[15:0] Echo data from previous access cycle.

7:0 CRC Calculated CRC value of bits 31:8. result (CRC-ERROR bit) from the read command is output on the SDO pin. Table 4. Read Operation Error Checking Cycle 7:0 CRC Calculated CRC value of bits 31:8. mode is connected internally to GND through a 1 kΩ resistor. The TPC219 family supports SPI-compatible interface.

0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

W 16'h0000 16'h00F F 7'h04 Reserved CL R-4 TO MS K CL TO MS K RE F DIV EN BUFFx-GAIN TRIGGE R W 16'h0000 7'h05 Reserved LD AC SOFT-RESET[3:0] BRDCA ST W 16'h0000 7'h06 BRDCAST-DATA[15:0] STATUS R/ W 16'h0000 7'h07 Reserved RE FA LM DAC0 R/ W 16'h0000 16'h8000 7'h08 DAC0-DATA[15：0] DAC1 R/ W 16'h0000 16'h8000 7'h09 DAC1-DATA[15：0] DAC2 R/ W 16'h0000 16'h8000 7'h0a DAC2-DATA[15：0] DAC3 R/ W 16'h0000 16'h8000 7'h0b DAC3-DATA[15：0] DAC4 R/ W 16'h0000 16'h8000 7'h0c DAC4-DATA[15：0] DAC5 R/ W 16'h0000 16'h8000 7'h0d DAC5-DATA[15：0] DAC6 R/ W 16'h0000 16'h8000 7'h0e DAC6-DATA[15：0] DAC7 R/ W 16'h0000 16'h8000 7'h0f DAC7-DATA[15：0] NOP Register Bit Field Type Reset Description 15:0 NOP W 0x0000 No operation. Write 0000h for proper no-operation command Device ID Register Bit Field Type Reset Description 15:2 DEVICEID R ---- Device ID: D15 Reserved - 0 D14:12 Resolution - 000 (16-bit); 001 (14-bit); 010 (12-bit) TPC219 8-Channel high precision Voltage output DAC with internal Reference www.3peak.com 20 / 30 Rev.A.0

Bit Field Type Reset Description D11:8 Channels - 1000 (8 channels) D7 Reset - 0 ; 1 reset- to-midscale) D6:2 Reserved - 00101 1:0 VERSIONID R 10 Version ID. Subject to change Sync Register Bit Field Type Reset Description

15 DAC7-BRDCAST-EN R/W 1

When set to 1 the corresponding DAC is set to update its output after a serial interface write to the BRDCAST register. When cleared to 0 the corresponding DAC output remains unaffected after a serial interface write to the BRDCAST register.

14 DAC6-BRDCAST-EN R/W 1

13 DAC5-BRDCAST-EN R/W 1

12 DAC4-BRDCAST-EN R/W 1

11 DAC3-BRDCAST-EN R/W 1

10 DAC2-BRDCAST-EN R/W 1

9 DAC1-BRDCAST-EN R/W 1

8 DAC0-BRDCAST-EN R/W 1

7 DAC7-SYNC-EN R/W 0

When set to 1 the corresponding DAC output is set to update in response to an LDAC trigger (synchronous mode). When cleared to 0 the corresponding DAC output is set to update immediately on a CS rising edge (asynchronous mode).

6 DAC6-SYNC-EN R/W 0

5 DAC5-SYNC-EN R/W 0

4 DAC4-SYNC-EN R/W 0

3 DAC3-SYNC-EN R/W 0

2 DAC2-SYNC-EN R/W 0

1 DAC1-SYNC-EN R/W 0

0 DAC0-SYNC-EN R/W 0

Bit Field Type Reset Description 15:14 Reserved — 00 Reserved for factory use

13 ALM-SEL R/W 0

0:ALARMpin is CRC-ERROR 1: ALARM pin is REF-ALARM

12 ALM-EN R/W 0

Configure SDO/ALARM pin. When 1: SDO/ALARM pin is an active-low, open-drain, alarm pin. An external 10 kΩ pullup resistor to VIOrequired. FSDO and DSDO bits are ignored. When 0: SDO/ALARM pin is a serial interface, push-pull, SDO pin 11 CRC-EN R/W 0 CRC enable bit. Set to 1 to enable CRC. Set to 0 to disable

10 FSDO R/W 0

Fast SDO bit (half-cycle speedup). When 0, SDO updates on an SCLK rising edge. When 1, SDO updates a half-cycle earlier, during an SCLK falling edge. TPC219 8-Channel high precision Voltage output DAC with internal Reference www.3peak.com 21 / 30 Rev.A.0

Bit Field Type Reset Description

9 DSDO R/W 0

Disable SDO bit. When1, SDO is always tri-stated. When 0, SDO is driven while CS is low, and tri-stated while CS is high

8 REF-PWDWN R/W 0 When set to 1 disables the device internal reference

7 DAC7-PWDWN R/W 0

When set to 1 the corresponding DAC is set in power- down mode and its output is connected to GND through a 1 kΩ internal resistor.

6 DAC6-PWDWN R/W 0

5 DAC5-PWDWN R/W 0

4 DAC4-PWDWN R/W 0

3 DAC3-PWDWN R/W 0

2 DAC2-PWDWN R/W 0

1 DAC1-PWDWN R/W 0

0 DAC0-PWDWN R/W 0

Bit Field Type Reset Description 15:11 Reserved — 0 Reserved for factory use.

10 Reserved / CLR-4TO7-

MSK R/W 0 For non-clear pin device: Reserved for factory use. For clear pin device. When cleared to 0 the corresponding DAC group is set to clear in response to a logic-low value on the CLR pin. When set to 1 the corresponding DAC group remains unaffected by the CLR pin.

9 Reserved / CLR-0TO3-

8 REFDIV-EN R/W 0/1

When set to 1 the reference voltage is internally divided by a factor of 2. When cleared to 0 the reference voltage is unaffected.

7 BUFF7-GAIN R/W 0/1

When set to 1 the buffer amplifier for corresponding DAC has a gain of 2. Default value for the default middle scale output devices. When cleared to 0 the buffer amplifier for corresponding DAC has a gain of 1. Default value for the default zero scale output devices.

6 BUFF6-GAIN R/W 0/1

5 BUFF5-GAIN R/W 0/1

4 BUFF4-GAIN R/W 0/1

3 BUFF3-GAIN R/W 0/1

2 BUFF2-GAIN R/W 0/1

1 BUFF1-GAIN R/W 0/1

0 BUFF0-GAIN R/W 0/1

Bit Field Type Reset Description 15:5 Reserved — 0 Reserved for factory use.

4 LDAC W 0

Set this bit to 1 to synchronously load those DACs that have been set in synchronous mode in the SYNC register. TPC219 8-Channel high precision Voltage output DAC with internal Reference www.3peak.com 22 / 30 Rev.A.0

Bit Field Type Reset Description 3:0 SOFT-RESET[3:0] W 0x0 When set to the reserved code 1010 resets the device to its default state. Broadcast Register Bit Field Type Reset Description 15:0 BRDCAST-DATA[15:0] R/W 0x0000 Writing to the BRDCAST register forces those DAC channels that have been set to broadcast in the SYNC register to update their active data register with the BRDCAST-DATA value. Data are MSB aligned in straight binary format and follows the format below: 16bit version: { DATA[15:0] } 14bit version: { DATA[13:0], x, x } 12bit version: { DATA[11:0], x, x, x, x } x – Don’t care bits Status Register Bit Field Type Reset Description 15:1 Reserved — 0 Reserved for factory use.

0 REF-ALM R 0

Reference alarm bit. Reads 1 when the difference between VREF/DIV and VDD is below the required minimum analog threshold. Reads 0 otherwise. DAC Register (Address = 0x8 to 0xF) Bit Field Type Reset Description 15:0 DACx-DATA[15:0] R/W 0x0000 or 0x8000 Stores the 16-, 14- or 12-bit data to be loaded to DACx in MSB aligned straight binary format. The default value is zero-code for default zero scale output version, midscale-code for the default middle scale output version. Data follows the format below: 16bit version: { DATA[15:0] } 14bit version: { DATA[13:0], x, x } 12 bit version: { DATA[11:0], x, x, x, x } x – Don’t care bits TPC219 8-Channel high precision Voltage output DAC with internal Reference www.3peak.com 23 / 30 Rev.A.0

Application and Implementation Note Information in the following application sections is not part of the 3PEAK’s component specification and 3PEAK does not warrant its accuracy or completeness. 3PEAK’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

Application Information

The TPC219 seris has high linearity, small package size and internal reference, which are suitable for applications such as optical networking, Test equipment, industrial automation and data acquisition systems. Typical Application TPC219 8-Channel high precision Voltage output DAC with internal Reference www.3peak.com 24 / 30 Rev.A.0

• Both input capacitors and output capacitors must be placed to the device pins as close as possible.
• It is recommended to bypass the input pin to ground with a 0.1 μF bypass capacitor.
• It is recommended to use wide trace lengths or thick copper weight to minimize I×R drop and heat dissipation.
• Exposed pad must be connected to the PCB ground plane directly, the copper area must be as large as possible. TPC219 8-Channel high precision Voltage output DAC with internal Reference www.3peak.com 25 / 30 Rev.A.0

Order Number Package D1 (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P0 (mm) W0 (mm) Pin1 Quadrant TPC2190- QFNR QFN3X3-16 330 17.6 3.3 3.3 1 8 12 Q1 TPC2190M- QFNR QFN3X3-16 330 17.6 3.3 3.3 1 8 12 Q1 TPC2190- TPC2192- TPC219 8-Channel high precision Voltage output DAC with internal Reference www.3peak.com 26 / 30 Rev.A.0

Package Outline Dimensions QFN3X3-16 TPC219 8-Channel high precision Voltage output DAC with internal Reference www.3peak.com 27 / 30 Rev.A.0

8-Channel high precision Voltage output DAC with internal Reference www.3peak.com 28 / 30 Rev.A.0

Order Number Operating Temperature Range Package Marking Information MSL Transport Media, Quantity Eco Plan TPC2190-QFNR −40 to 125°C QFN3X3-16 2190 1 Tape and Reel, 4000 Green TPC2190M-QFNR −40 to 125°C QFN3X3-16 2190M 1 Tape and Reel, 4000 Green TPC2190-WLPR −40 to 125°C WLCSP 190 1 Tape and Reel, 3000 Green TPC2192-WLPR −40 to 125°C WLCSP 192 1 Tape and Reel, 3000 Green (1) For future products, contact the 3PEAK factory for more information and sample. 3PEAK defines "Green" to mean RoHS compatible and free of halogen substances. Green: 3PEAK defines "Green" to mean RoHS compatible and free of halogen substances. Trademarks. Any of the 思瑞浦 or 3PEAK trade names, trademarks, graphic marks, and domain names(“Trademarks”) contained in this document/material are the property of 3PEAK. You may NOT reproduce, modify, publish, transmit or distribute any Trademark without the prior written consent of 3PEAK. TPC219 8-Channel high precision Voltage output DAC with internal Reference www.3peak.com 29 / 30 Rev.A.0

Performance Information. Performance tests or performance range contained in this document/material are results of design simulation or actual tests conducted under designated testing environment. Any differences in testing environment or simulation environment, including but not limited to testing method, testing process or testing temperature, may affect actual performance of the product. Forward-Looking Statements. The information in this document/material may contain forward-looking statements, except for statements or descriptions of historical facts. These forward-looking statements are based upon our current understanding of our industry, management philosophy and certain assumptions and speculative calculations. These forward-looking statements are subject to risks and uncertainties and our actual results may differ. Please do not rely solely on the above information to make your business decisions. Disclaimer. 3PEAK provides technical and reliability data (including data sheets), design resources (including reference designs), application or other design recommendations, networking tools, security information and other resources "As Is". 3PEAK makes no warranty as to the absence of defects, and makes no warranties of any kind, express or implied, including, without limitation, implied warranties as to merchantability, fitness for a particular purpose or non-infringement of any third-party’s intellectual property rights. TPC219 8-Channel high precision Voltage output DAC with internal Reference www.3peak.com 30 / 30 Rev.A.0