IA82050_11 INNOVASIC | Alldatasheet
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Asynchronous Serial Controller February 25, 2011 IA211030617-08 http://www.Innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 1 of 22 1-888-824-4184 IA82050 Asynchronous Serial Controller Data Sheet
Asynchronous Serial Controller February 25, 2011 IA211030617-08 http://www.Innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 2 of 22 1-888-824-4184 Copyright 2008 by Innovasic Semiconductor, Inc. Published by Innovasic Semiconductor, Inc.
3737 Princeton Drive NE, Suite 130, Albuquerque, NM 87107
is a registered trademark of Intel Corporation MILES™ is a trademark of Innovasic Semiconductor, Inc.
Asynchronous Serial Controller February 25, 2011 IA211030617-08 http://www.Innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 3 of 22 1-888-824-4184 TABLE OF CONTENTS
Asynchronous Serial Controller February 25, 2011 IA211030617-08 http://www.Innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 5 of 22 1-888-824-4184 1. Features
- Form, Fit and Function Compatible with the Intel 82050
- Packaging options available: 28-Pin Plastic DIP and 28-Lead Plastic Leaded Chip Carrier (see Figure 1, Package Pinout)
- Asynchronous Serial Channel Operation
- Separate Transmit and Receive FIFOs with Programmable Threshold
- Programmable Baud Rate Generator up to 288K Baud
- Special Protocol Features – Loopback Modes – 5- to 8-Bit Character Format The IA82050 is a "plug-and-play" drop-in replacement for the original IC. Innovasic produces replacement ICs using its MILESTM, or Managed IC Lifetime Extension System, cloning technology. This technology produces replacement ICs far more complex than "emulation" while ensuring they are compatible with the original IC. MILESTM captures the design of a clone so it can be produced even as silicon technology advances. MILESTM also verifies the clone against the original IC so that even the "undocumented features" are duplicated. This data sheet documents all necessary engineering information about the IA82050 including functional and I/O descriptions, electrical characteristics and applicable timing.
Figure 1. Package Pinout
Asynchronous Serial Controller February 25, 2011 IA211030617-08 http://www.Innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 7 of 22 1-888-824-4184 2. Description The IA82050 is an asynchronous serial controller that provides a CPU interface to one transmit and one receive channel. It is form, fit, and function compatible with the Intel® 82050 and 82510. Configuration registers are used to control the serial channel, interrupts, and modes of operation. The CPU controls this device via address and data lines with read/write control. The CPU also uses this interface to read and write data to receive and transmit data through the serial channel. FIFOs and various serial modes can be used to help off-load the CPU from transmitting and receiving data. An interrupt line provides an indication to the CPU that the device requires servicing. The device can be configured for 8250A/16450 compatibility. See Figure 2, Functional Block Diagram.
Figure 2. Functional Block Diagram
Asynchronous Serial Controller February 25, 2011 IA211030617-08 http://www.Innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 9 of 22 1-888-824-4184 3. Functional Overview
3.1 Transmitter
The Transmit function consists of a one-character FIFO, and a Transmit Engine. The transmit engine is responsible for reading the data out of the FIFO and placing it in the proper order on the TXD pin. The transmit engine is highly configurable to be compatible with numerous formats, including 16450 and 8250 modes of communication. Transmit Communication parameters that can be programmed include:
- Parity modes
- Stop Bits
- Character Length For more details, see Chapter 5, Register Descriptions.
3.2 Receiver
The Receiver function consists of a one-character FIFO and a receive engine. The receive engine is responsible for sampling the data on the RXD input pin, formatting the data, and placing the data in the FIFO. The receive engine is highly configurable with parameters that include:
- Parity modes
- Stop Bits
- Character Length For more details, see Chapter 5, Register Descriptions.
3.3 Bus Interface
The Bus Interface is a simple interface that allows a micro-processor or micro-controller to read and write the IA82050 Registers. It consists of the following I/O lines:
- A0, A1, A2 : 3-Bit Address
- D0-D7 : 8-Bit Data
- RDn: Active Low Read Enable
- WRn: Active Low Write Enable
- CSn: Active Low Chip Select
- INT: Interrupt Output
- RESET: Chip Reset
3.4 Register Description
Table 1 presents the register summary. Table 1. Register Summary
4.1 Baud Rate Generator A Divide Count, MSB and LSB (BAH/BAL)
4.2 General Interrupt Enable Register (GER)
Table 2. General Interrupt Enable Register
4.3 General Interrupt Register (GIR)
Table 3. General Interrupt Register
0 BANK1 BANK0 0 0 BI1 BI0 IPN
4.4 Line Configure Register (LCR)
Defines configuration of serial message (ADDR 011, Mode R/W, Default 00000000).
Table 4. Line Configure Register
4.5 Line Status Register (LSR)
Table 5. Line Status Register
0 TXST TFST BKD FE PE OE RFIR
4.6 Modem Control Register (MCR)
Table 6. Modem Control Register
4.7 Modem Status Register (MSR)
Table 7. Modem Status Register
4.8 Receive Data Register (RXDATA)
character length (LCR_CL) is less than eight, the unused RXDATA bits will be zero. A read from RXDATA will be directly from the RX FIFO.
4.9 Scratch Register (SCR)
Asynchronous Serial Controller February 25, 2011 IA211030617-08 http://www.Innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 14 of 22 1-888-824-4184 General purpose scratch pad register to be defined by user.
4.10 Transmit Data Register (TXDATA)
(ADDR 000, Mode W, Default N/A) Transmit Data - A write to this location adds a data byte to the TX FIFO, and initiates the transmit sequence.
Table 8. AC/DC Parameters Lead temperature +300°C, 10 sec. adversely affect device reliability. Innovasic’s guarantee of part performance.
Table 9. DC Characteristics
- Does not apply to CLK/X1 pin, when configured as crystal oscillator input (X1).
- Does not apply to OUT2/X2 pin, when configured as crystal oscillator output (X2).
- Freq. = 1 MHz, but input clock not running. Static IDD current is exclusive of input/output drive
- Applies only during hardware reset for clock configuration options. Strapping current for logic HIGH.
- Applies only during hardware reset for clock configuration options. Strapping current for logic LOW.
- Inputs (RTSn, DTRn, TB) with Pullups tested @ Vin = 0.0V, VDD = 5.5V
Table 10. AC Characteristics
8.1 PDIP Package
Figure 3. PDW Physical Package Dimensions
2 PLCS
8.2 PLCC Package
Figure 4. PLCC Physical Package Dimensions
- Innovasic Part Number Cross-Reference
Table 11. Innovasic Part Number Cross-Reference for the PDIP Table 12. Innovasic Part Number Cross-Reference for the PLCC
Asynchronous Serial Controller February 25, 2011 IA211030617-08 http://www.Innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 21 of 22 1-888-824-4184 10. Revision History The table below presents the sequence of revisions to document IA211030617. Date Revision Description Page(s) August 19, 2008 06 Corrected control number and reformatted some elements to meet publication standards. NA October 15, 2008 07 Corrected part number on cover page, enlarged package pinout and functional block diagram figures, corrected trademark references (p. 2), changed “pin” to “lead” in LCC package pinout figure, changed “lead” to “pin” in PDIP physical page dimensions figure and part number table, formatted part cross-reference table to meet publication standards, added “For Additional Information” chapter. 1, 5, 6, 17, 18, February 25, 2011 08 Removed packaging options to support the elimination of SnPb lead plating options.
Asynchronous Serial Controller February 25, 2011 IA211030617-08 http://www.Innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 22 of 22 1-888-824-4184 11. For Additional Information The IA82050 is a "plug-and-play" drop-in replacement for the original IC. This data sheet documents all necessary engineering information about the IA82050 including functional and I/O descriptions, electrical characteristics and applicable timing. The Innovasic Support Team wants our information to be complete, accurate, useful, and easy to understand. Please feel free to contact our experts at Innovasic at any time with suggestions, comments, or questions. Innovasic Support Team
3737 Princeton NE
Albuquerque, NM 87107 (505) 883-5263 Fax: (505) 883-5477 Toll Free: (888) 824-4184 E-mail: support@innovasic.com Website: www.Innovasic.com