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SDLC Communications Controller March 30, 2010 IA211010112-04 http://www.Innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 1 of 65 1-888-824-4184 IA8044/IA8344 SDLC Communications Controller Data Sheet
SDLC Communications Controller March 30, 2010 IA211010112-04 http://www.Innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 2 of 65 1-888-824-4184 Copyright 2010 by Innovasic Semiconductor, Inc. Published by Innovasic Semiconductor, Inc.
3737 Princeton Drive NE, Suite 130, Albuquerque, NM 87107
is a registered trademark of Intel Corporation. MILES™ is a trademark of Innovasic Semiconductor, Inc.
SDLC Communications Controller March 30, 2010 IA211010112-04 http://www.Innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 3 of 65 1-888-824-4184 TABLE OF CONTENTS
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SDLC Communications Controller March 30, 2010 IA211010112-04 http://www.Innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 9 of 65 1-888-824-4184 1. Introduction The Innovasic Semiconductor IA8044 and IA8344 are ―plug-and-play‖ drop-in replacements and are form, fit, and function compatible parts to the Intel 8044 and 8344 (see Chapter 4, Innovasic/Intel Part Number Cross-Reference Tables). These devices are produced using Innovasic’s Managed IC Lifetime Extension System (MILES™). This cloning technology, which produces replacement ICs beyond simple emulations, ensures complete compatibility with the original device, including any ―undocumented features.‖ Additionally, the MILES™ process captures the clone design in such a way that production of the clone can continue even as silicon technology advances. The IA8044 and IA8344 replace the obsolete Intel 8044 and 8344, allowing users to retain existing board designs, software compilers/assemblers, and emulation tools—thus avoiding expensive redesign efforts. The IA8044 and IA8344 are Fast Single-Chip 8-Bit Microcontrollers with an integrated SDLC/HDLC serial interface controller. They are fully functional 8-Bit Embedded Controllers that execute all ASM51 instructions and have the same instruction set as the Intel 80C51. The IA8044 and IA8344 can access the instructions from two types of program memory, serve software and hardware interrupts, and provide interface for serial communications and a timer system. The IA8044 and IA8344 are fully compatible with the Intel 8X44 series. This data sheet documents all necessary engineering information about the IA8044 and IA8344 including functional and I/O descriptions, electrical characteristics, and applicable timing.
1.1 Features
Form, fit, and function compatible with the Intel 8044 and 8344 Packaging options available in both leaded and RoHS versions: – 40-Pin Plastic Dual In-Line Package (PDIP) (see IA8044 40-Lead PDIP Package Diagram) – 44-Pin Plastic Leaded Chip Carrier (PLCC) (see IA8344 44-Pin PLCC Package Diagram) 8-bit control unit (see Functional Block Diagram) 8-bit arithmetic-logic unit with 16-bit multiplication and division 12-MHz clock Four 8-bit input/output ports Two 16-bit timer/counters Serial interface unit with SDLC/HDLC compatibility 2.4-Mbps maximum serial data rate Two-level priority interrupt system 5 interrupt sources Internal clock prescaler and phase generator 192 bytes of read/write data memory space 64-Kbyte external program memory space
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1.2 Variants
– 4-Kbyte internal ROM with R0117 version 2.3 firmware – 192-byte internal RAM – 64-Kbyte external program and data space IA8344 – 192-byte internal RAM – 64-Kbyte external program and data space 2. Packaging, Pin Descriptions, and Physical Dimensions The Innovasic Semiconductor IA8044 and IA8344 serial controllers are available in the following packages: 40-Pin Plastic Dual In-Line Package (PDIP), equivalent to original PDIP package (see Physical Package Dimensions) 44-Lead Plastic Leaded Chip Carrier (PLCC), equivalent to original PLCC package (see Physical Package Dimensions)
2.1 PDIP Package
Figure 1. IA8044 and IA8344 40-Lead PDIP Package Diagram
Table 1. IA8044 and IA8344 40-Lead PDIP Pin Listing
2.2 PDIP Physical Dimensions
The physical dimensions for the 40 PDIP are as shown in Figure 2. Figure 2. PDIP Physical Package Dimensions
2.3 PLCC Package
Figure 3. IA8044 and IA8344 44-Pin PLCC Package Diagram
Table 2. IA8044 and IA8344 44-Pin PLCC Pin Listing
2.4 PLCC Physical Dimensions
The physical dimensions for the 44 PLCC are as shown in Figure 4. Figure 4. PLCC Physical Package Dimensions
- Maximum Ratings and DC Characteristics
Table 3. IA8044 and IA8344 Absolute Maximum Ratings adhered to especially for input pin EA, which is used as the programming voltage pin in the Intel device. Exceeding the listed maximum voltage will cause damage to the device. Table 4. IA8044 and IA8344 DC Characteristics
4.1 Functional Block Diagram
functional modules are provided in the following subsections.
Figure 5. Functional Block Diagram
4.2 Input/Output Characteristics
Table 5. Input/Output Characteristics of IC Signals cycles while the oscillator is running. instructions from external memory. dependent upon data link configuration. upon data link configuration. Also enables diagnostic mode when cleared. P3.2 (INT0)—Interrupt 0 input or gate control input for Counter 0. P3.3 (INT1)—Interrupt 1 input or gate control input for Counter 1. P3.4 (T0)—Input to Counter 0. P3.5 (SCLK/T1)—SCLK input to SIU or input to Counter 1. P3.6 (WR)—External memory write signal. P3.7 (RD)—External memory read signal. XTAL1 I Crystal Input 1—Connects to VSS when external clock is used on XTAL2. clock source (XTAL2 not connected). directly with an inverted clock source (XTAL1 tied to ground).
4.3 Memory Organization
4.3.1 Program Memory
intervals, starting from 0003H for External Interrupt 0. Table 6. Reset Vectors
4.3.2 External Data Memory
4.3.3 Internal Data Memory
accessible by indirect addressing.
Figure 6. Internal Data Memory Addresses 00h to FFh
4.3.4 Bit Addressable Memory
addressable locations (see Tables 7 and 8). Table 7. SFR Bit Addressable Locations Table 8. Internal RAM Bit Addressable Locations
4.4 Special Function Registers
Table 9 presents the SFRs of the IA8044 and IA8344. Table 9. Special Function Registers
4.5 Ports
(VCC), and writing a ―0‖ causes the corresponding pin to be held at low level (GND). they are not used for alternate purposes. address. Keeping ―ea‖ pin low (tied to GND) activates this alternate function for Ports P0 and P2. Port P3 and P1 can perform some alternate functions. The pins of Port P3 are multifunctional. They can perform the additional functions described in Table 10. Table 10. Additional Functions of Port P3 diagnostic mode this pin is RxD, Receive Data input. data, TxD pin. Writing a ―0‖ to this port buffer bit enables the diagnostic mode. P3.2 INT0 External Interrupt 0 input. Also gate control input for Counter 0. P3.3 INT1 External Interrupt 1 input. Also gate control input for Counter 1. Function Registers TCON and TMOD activates this function. CPU write access to External Data Memory (i.e., MOVX @DPTR, A). CPU read access from External Data Memory (i.e., MOVX A, @DPTR). P1.6 RTS Request To Send output, active low. P1.7 CTS Clear To Send input, active low.
4.6 Port Registers
4.6.1 Port 0 (P0)
order address and data bus with open-drain output buffers.
Table 11. Port 0 Register
4.6.2 Port 1 (P1)
Table 12. Port 1 Register
4.6.3 Port 2 (P2)
Table 13. Port 2 Register
4.6.4 Port 3 (P3)
inputs, timer inputs and the read and write strobes for external memory accesses.
Table 14. Port 3 Register
4.7 Timers/Counters
4.7.1 Timers 0 and 1
are used to select the appropriate mode.
4.7.2 Mode 0
In Mode 0 the timers operate as an 8-bit timer (TH0/1) with a divide by 32-bit prescalar (TL0/1). rolls over from all 1s to all 0s it will set the interrupt flag TF0/1.
4.7.3 Mode 1
4.7.4 Mode 2
Mode 2 configures TL0/1 as an 8-bit counter with automatic reload from the contents of TH0/1. TH0/1 are not affected by the reload.
4.7.5 Mode 3
will stop and hold its count.
4.7.6 Timer Mode (TMOD)
controls Timer 1. Table 16 presents the timer mode select bits. Table 15. Timer Mode Register counter is incremented every falling edge on T1 input pin. counter operation is performed. When cleared to 0, the register will function as a timer. Bit [5]—M1 → (TMOD.5) Timer 1 mode selector bit. Bit [4]—M0 → (TMOD.4) Timer 1 mode selector bit. counter is incremented every falling edge on T0 input pin.
counter operation is performed. When cleared to 0, the register will function as a timer. Bit [1]—M1 → (TMOD.1) Timer 0 mode selector bit. Bit [0]—M0 → (TMOD.0) Timer 0 mode selector bit. Table 16. Timer Mode Select Bits 8-bit timer function only, controlled by Timer 1 control bits.
4.7.7 Timer Control (TCON)
counters. It also contains bits to select the type of external interrupt desired, edge or level. Table 17. Timer Control Register overflows. This flag should be cleared by software. Bit [4]—TR0 → (TCON.4) Timer 0 run control bit. If cleared, Timer 0 stops. external pin INT1 is detected cleared when interrupt is processed.
input pin to cause interrupt. external pin INT1 is observed. Cleared when interrupt is processed. input pin to cause interrupt.
4.7.8 Timer 0 High Byte (TH0)
Table 18 presents the high-order byte of Timer/Counter 0. Table 18. Timer 0 High Byte Register
4.7.9 Timer 0 Low Byte (TL0)
Table 19 presents the low-order byte of Timer/Counter 0. Table 19. Timer 0 Low Byte Register
4.7.10 Timer 1 High Byte (TH1)
Table 20 presents the high-order byte of Timer/Counter 1. Table 20. Timer 1 High Byte Register
4.7.11 Timer 1 Low Byte (TL1)
Table 21 presents the low order byte of Timer/Counter 1. Table 21. Timer 1 Low Byte Register
4.7.12 Timer/Counter Configuration
Mode 2, and Timer 0 Mode 3, respectively. Figure 7. Timer 0 Mode 0 Figure 8. Timer 0 Mode 1
4.8 General CPU Registers
4.8.1 Accumulator (ACC)
Table 22. Accumulator Register
4.8.2 B Register (B)
be used as a scratch-pad register to hold temporary data. Table 23. B Register
4.8.3 Program Status Word (PSW)
Table 24. Program Status Word Register
The state of Bits RS1 and RS0 selects the working registers bank as presented in Table 25. Table 25. RS1/RS0 Bank Selections by State
00 Bank 0 (00H–07H)
01 Bank 1 (08H–0FH)
10 Bank 2 (10H–17H)
11 Bank 3 (18H–1FH)
4.8.4 Stack Pointer (SP)
08H. The stack pointer points to a location in internal RAM. Table 26. Stack Pointer
4.8.5 Data Pointer (DPTR)
The data pointer (DPTR) is two bytes wide. Table 27 presents the highest, which is DPH. external code (MOVC A,@A+DPTR each) or data space (MOV A,@DPTR). Table 27. Data Pointer (High) Register Table 28. Data Pointer (Low) Register
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4.9 Interrupts
The IA8044/IA8344 provides five interrupt sources. There are two external interrupts accessible through pins INT0 and INT1, edge or level sensitive (falling edge or low level). There are also internal interrupts associated with Timer 0 and Timer 1 and an internal interrupt from the SIU.
4.9.1 External Interrupts
The choice between external interrupt level or transition activity is made by setting IT1 and IT0 bits in the SFR TCON. When the interrupt event happens, a corresponding Interrupt Control Bit is set (IT0 or IT1). This control bit triggers an interrupt if the appropriate interrupt bit is enabled. When the interrupt service routine is vectored, the corresponding control bit (IT0 or IT1) is cleared, provided that the edge triggered mode was selected. If level mode is active, the external requesting source controls flags IT0 or IT1 by the logic level on pins INT0 or INT1 (0 or 1).
4.9.2 Timer 0 and Timer 1 Interrupts
Timer 0 and 1 interrupts are generated by TF0 and TF1 flags, which are set by the rollover of Timers 0 and 1, respectively. When an interrupt is generated, the flag that caused this interrupt is cleared by the hardware if the CPU accessed the corresponding interrupt service vector. This can be done only if this interrupt is enabled in the IE register.
4.9.3 Serial Interface Unit Interrupt
The SIU generates an interrupt when a frame is received or transmitted. No interrupts are generated for a received frame with errors.
4.9.4 Interrupt Priority Level Structure
There are two priority levels in the IA8044/IA8344—any interrupt can be individually programmed to a high or low priority level. Modifying the appropriate bits in the SFR IP can accomplish this. A low-priority interrupt service routine will be interrupted by a high-priority interrupt. However, the high-priority interrupt cannot be interrupted. If two interrupts of the same priority level occur, an internal polling sequence determines which will be processed first. This polling sequence is a second priority structure defined as follows: IE0 1—highest TF0 2 IE1 3 TF1 4 SIU—lowest
4.9.5 Interrupt Handling
An interrupt of the same or higher priority is processed. The instruction in progress is RETI or any write to IE or IP registers. the interrupt condition is not remembered; every polling cycle is new.
4.9.6 Interrupt Priority Register (IP)
Table 29. Interrupt Priority Register
4.9.7 Interrupt Enable Register (IE)
individual interrupt enable bits. Setting a bit enables the corresponding interrupt. Table 30. Interrupt Enable Register
4.10 SIU—Serial Interface Unit
4.10.1 SIU Special Function Registers
Unit Control Registers are detailed in the sections that follow.
4.10.2 Serial Mode Register (SMD)
both zero. SMD is normally only accessed during initialization. This register is byte addressable. Table 32 presents the serial mode select clock mode bits. Table 31. Serial Mode Register Bit [7]—SCM2 → (SMD.7) Select clock mode—Bit [2]. Bit [6]—SCM1 → (SMD.6) Select clock mode—Bit [1]. Bit [5]—SCM0 → (SMD.5) Select clock mode—Bit [0]. Bit [4]—NRZI → (SMD.4) When set selects NRZI encoding otherwise NRZ. Bit [1]—NB → (SMD.1) Non-buffered mode. No control field contained in SDLC frame. Bit [0]—NFCS → (SMD.0) When set, selects No FCS field contained in the SDLC frame.
Table 32. Serial Mode Select Clock Mode Bits aBased on a12-MHz crystal frequency. b0–1 Mbps in loop configuration.
4.10.3 Status/Command Register (STS)
MOV bit,C—should not be used. STS is bit addressable. Table 33. Status/Command Register transmit buffer is ready and TBF is cleared by the SIU. been received. Can be thought of as a Receive Enable. external pin in non-loop mode. Can be thought of as a Transmit Enable. Note: RTS signal at the pin (P1.6) is the inverted version of this bit. the CPU before returning from the interrupt routine. Bit [3]—BOV → (STS.3) Receive buffer overrun. The SIU can set or clear BOV .
optional poll (UP with P=0). The SIU can set or clear the OPB. mode when clear. The SIU can clear AM. the receive buffer. Causes RNR response instead of RR in AUTO mode.
4.10.4 Send/Receive Count Register (NSNR)
sequence numbers in addition to the tally error indications. The CPU can read and write the STS. non-AUTO mode. NSNR is bit addressable. Table 34. Send/Receive Count Register Bit [7]—NS2 → (NSNR.7) Send sequence counter, Bit [2]. Bit [6]—NS1 → (NSNR.6) Send sequence counter, Bit [1]. Bit [5]—NS0 → (NSNR.5) Send sequence counter, Bit [0]. Bit [3]—NR2 → (NSNR.3) Receive sequence counter, Bit [2]. Bit [2]—NR1 → (NSNR.2) Receive sequence counter, Bit [1]. Bit [1]—NR0 → (NSNR.1) Receive sequence counter, Bit [0]. Bit [0]—SER → (NSNR.0) Sequence error receive. NS (P) ≠ NR (S).
4.10.5 Station Address Register (STAD)
RBE = 0. Normally STAD is accessed only during initialization. STAD is byte addressable. Table 35. Station Address Register
4.10.6 Transmit Buffer Start Address Register (TBS)
Table 36. Transmit Buffer Start Address Register
4.10.7 Transmit Buffer Length Register (TBL)
after address 191 (BFH). A buffer end is automatically generated when address 191 is reached. Table 37. Transmit Buffer Length Register
4.10.8 Transmit Control Byte Register (TCB)
access TCB only when the SIU is not transmitting a frame, TBF = 0. TCB is byte addressable.
Table 38. Transmit Control Byte Register
4.10.9 Receive Buffer Start Address Register (RBS)
should write RBS only when the SIU is not receiving a frame, RBE = 0. RBS is byte addressable. Table 39. Receive Buffer Start Address Register
4.10.10 Receive Buffer Length Register (RBL)
reached. RBL is byte addressable. Table 40. Receive Buffer Length Register
4.10.11 Receive Field Length Register (RFL)
is loaded by the SIU. RFL is byte addressable. Table 41. Receive Field Length Register
4.10.12 Receive Control Byte Register (RCB)
access RCB only when the SIU is not receiving a frame, RBE = 0. RCB is loaded by the SIU.
Table 42. Receive Control Byte Register
4.10.13 DMA Count Register (DMA CNT)
remaining for the information field currently being used. This register is an ICE support register. DMA CNT is byte addressable. Table 43. DMA Count Register (DMA CNT)
4.10.14 DMA Count Register (FIFO)
receive buffer when an information field is received. This register is an ICE support register. Table 44. DMA Count Register (FIFO) a1, 2, or 3 for FIFO1, FIFO2, or FIFO3, respectively.
4.10.15 SIU State Counter (SIUST)
register. SIUST is byte addressable. Table 45. SIU State Counter
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4.11 Data Clocking Options
The SIU may be clocked in one of two ways, with an external clock or in a self-clocked mode. In the external clocked mode, a serial clock must be provided on SCLK. This clock must be synchronized to the serial data. Incoming data is sampled at the rising edge of SCLK. Outgoing data is shifted out at the falling edge of SCLK. In the self-clocked mode, the SIU uses a reference clock and the serial data to reproduce the serial data clock. The reference clock can be an external source applied to SCLK, the IA8044/IA8344’s internal clock or the Timer 1 overflow. The reference clock must be 16 or 32 the data rate. A DPLL uses the reference clock and the serial data to adjust the sample time to the center of the serial bit. It does this by adjusting from a serial data transition in increments of 1/16 of a bit time. The maximum data rate in the externally clocked mode is 2.4 Mbps in a point-to-point configuration and 1.0 Mbps in a loop configuration. With a 12-MHz CPU clock, the maximum data rate in the self-clocked mode with an external clock is 375 Kbps. The maximum data rate in the self-clocked mode with an internal clock will depend on the frequency of the IA8044/IA8344’s input clock. An IA8044/IA8344 using a 12-MHz input clock can operate at a maximum data rate of 375 Kbps. The Serial mode register Bits [5], [6], and [7] select the clocking option for the SIU (see SMD register description).
4.12 Operational Modes
The SIU operates in one of two modes, AUTO or FLEXIBLE. The mode selected determines how much intervention is required by the CPU when receiving and transmitting frames. In both modes, short frames, aborted frames, and frames with CRC errors will be ignored. AUTO mode allows the SIU to recognize and respond to specific SDLC frames without the CPU’s intervention. This provides for a faster turnaround time but restricts the operation of the SIU. When in AUTO mode, the SIU can only act as a normal response secondary station and responses will adhere to IBM’s SDLC definitions. When receiving in the AUTO mode, the SIU receives the frame and examines the control byte. It will then take the appropriate action for that frame. If the frame is an information frame, the SIU will load the receive buffer, interrupt the CPU and make the required response to the primary station. The SIU in AUTO mode can also respond to the following commands from the primary station: RR (Receive ready) RNR (Receive Not Ready) REJ (Reject)
The FLEXIBLE mode requires the CPU to control the SIU for both transmitting and receiving. receiving station (see Table 46). Table 46. Basic SDLC Frame
4.13 Frame Format Options
the address, control, and information fields. The address and control fields may not be extended. format is supported by both AUTO and FLEXIBLE modes.
field may still be used in the frame but the SIU will treat it as a byte of the information field. it as a byte of the information field. Table 47. Frame Format Options
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4.14 HDLC Restrictions
The IA8044/IA8344 supports a subset of the HDLC protocol. The differences include the restriction by the IA8044/IA8344 of the serial data to be in 8-bit increments. In contrast, HDLC allows for any number of bits in the information field. HDLC provides an unlimited address field and an extended frame number sequencing. HDLC does not support loop configuration.
4.15 SIU Details
The SIU is composed of two functional blocks with each having several sub blocks. The two blocks are called the bit processor (BIP) and the byte processor (BYP) (see Figure 11).
4.15.1 BIP
The BIP consists of the DPLL, NRZI encoder/decoder, serial/parallel shifter, zero insertion/deletion, shutoff logic, and FCS generation/checking. The NRZI logic compares the current bit to the previous bit to determine if the bit should be inverted. The serial shifter converts the outgoing byte data to bit data and incoming bit data to byte data. The zero insert/delete circuitry inserts and deletes zeros and also detects flags (01111110), go-aheads (GA) (01111111), and aborts (1111111). The pattern 1111110 is detected as an early go-ahead that can be turned into a flag in loop configurations. The shutoff detector is a three-bit counter that is used to detect a sequence of eight zeros, which is the shutoff command in loop-mode transmissions. It is cleared whenever a ―1‖ is detected. The FCS logic performs the generation and checking of the FCS value according to the polynomial described above. The FCS register is set to all 1s prior to each calculation. If a CRC error is generated on a receive frame, the SIU will not interrupt the CPU and the error will be cleared upon receiving an opening flag.
Figure 11. Bit and Byte Processors
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4.15.2 BYP
The BYP contains registers and controllers used to perform the manipulations required for SDLC communications. The BYP registers may be accessed by the CPU (see Table 7, SFR Bit Addressable Locations). The BYP contains the SIU state machine that controls transmission and reception of frames.
4.16 Diagnostics
A diagnostic mode is included with the IA8044/IA8344 to allow testing of the SIU. Diagnostics cleared, writing data to P3.0 has the effect of writing a serial data stream to the SIU. P3.0 is the serial data and any write to Port 3 will clock SCLK. The transmit data may be monitored on P3.1 with any write to Port 3, again clocking SCLK. In the test mode P3.0 and P3.1 pins are placed in the high impedance state (see Figure 12).
Figure 12. Diagnostic Signal Routing
external clock drive characteristics are provided in Tables 48 through 51, respectively. Table 48. External Program Memory Characteristics
12 MHz Osc
Table 49. External Data Memory Characteristics
Table 50. Serial Interface Characteristics Table 51. External Clock Drive Characteristics
5.1 Memory Access Waveforms
write cycle are presented in Figures 13 through 15, respectively.
Figure 13. Program Memory Read Cycle
Figure 14. Data Memory Read Cycle
Figure 15. Data Memory Write Cycle
5.2 Serial I/O Waveforms
presented in Figures 16 and 17, respectively. Figure 16. Synchronous Data Transmission Figure 17. Synchronous Data Reception
reset, which is executed during the second cycle in which RST is high. does not affect the contents of internal RAM. Table 52. Reset Values Register
The IA8044 and IA8344 architecture and instruction set are identical to the Intel 8051’s. Tables 53 through 57 present the instruction set of the IA8044/IA8344 microcontroller core. Table 53. Arithmetic Operations
Table 54. Logic Operations
Table 55. Data Transfer
Table 56. Boolean Manipulation Table 57. Program Branches
- Innovasic/Intel Part Number Cross-Reference Tables
number for the PDIP and PLCC, respectively. Table 58. Innovasic/Intel Part Number Cross-Reference for the PDIP Table 59. Innovasic/Intel Part Number Cross-Reference for the PLCC
9.1 Summary
Table 60 presents a summary of errata in the IA8044/IA8344 controller. Table 60. Summary of Errata
4 Under certain conditions the SIU will overwrite the RCB register when starting a
9.2 Detail
Problem: Cannot read internal ROM with EPROM verification method. support the EPROM read feature. Workaround: Must use alternate method to read internal ROM. Problem: The device has a different pullup value than the Intel version. Description: The Intel version can source more current than the IA8044/IA8344. Workaround: Adjust external circuits if necessary.
SDLC Communications Controller March 30, 2010 IA211010112-04 http://www.Innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 63 of 65 1-888-824-4184 Errata No. 3 Problem: The device responds to an idle flag one bit time too early. Description: This causes problems in a loop-mode network. It only occurs in loop mode when using an external SIU clock source and idle flags. Workaround: None. Errata No. 4 Problem: Under certain conditions the SIU will overwrite the RCB register when starting a transmission. Description: The conditions are: The SIU is externally clocked. The SIU is in flexible mode. The CPU has not already read the RCB from a previous reception before the transmission takes place. Workaround: Read the RCB before initiating a transmit.
Table 61 presents the sequence of revisions to document IA211010112. Table 61. Revision History updated. ―Summary of Errata‖ table added.
SDLC Communications Controller March 30, 2010 IA211010112-04 http://www.Innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 65 of 65 1-888-824-4184 11. For Additional Information The Innovasic Semiconductor IA8044 and IA8344 are ―plug-and-play‖ drop-in replacements and are form, fit, and function compatible parts to the Intel 8044 and 8344. The IA8044 and IA8344 replace the obsolete Intel 8044 and 8344, allowing users to retain existing board designs, software compilers/assemblers, and emulation tools—thus avoiding expensive redesign efforts. The Innovasic Support Team is continually planning and creating tools for your use. Visit http://www.Innovasic.com for up-to-date documentation and software. Our goal is to provide timely, complete, accurate, useful, and easy-to-understand information. Please feel free to contact our experts at Innovasic at any time with suggestions, comments, or questions. Innovasic Support Team
3737 Princeton NE
Albuquerque, NM 87107 (505) 883-5263 Fax: (505) 883-5477 Toll Free: (888) 824-4184 E-mail: support@innovasic.com Website: http://www.Innovasic.com