TP3465V

TP3465 NSC | Alldatasheet

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Features

Y Multiplexed and Non-multiplexed microprocessor bus compatible Y National/Intel and Motorola microprocessor bus compatible Y Microprocessor Clock (CKIN) up to 20 MHz Y MICROWIRE clock speeds up to5 MHz Y Directly compatible with 8- and 16-bit MICROWIRE peripherals Y Commercial temperature range 0C to +70C Y TP3465 for8 Chip Select output Y Memory mapped peripherals Y Programmable MICROWIRE Clock to communicate with devices of different speeds Y Operates as MICROWIRE bus master or slave Y 28-pin PLCC Package Y CMOS, Low Power Block Diagram TL/H/10803– 1 FIGURE 1. MICROWIRE Interface Device MID COMBOÉ, Series 32000É and TRI-STATEÉ are registered trademarks of National Semiconductor Corporation. MICROWIRETM isa trademark of National Semiconductor Corporation.

FIGURE 2. MICROWIRE Interface Device MID TP3465 Pinouts Name Pin No. Type Function 28 Pkg. The MICROWIRE Interface consists of SK (clock out), SO (data out), SI (data in) and up to8 chip select output lines. Name Pin No. Type Function 28 Pkg. SK 13 O MICROWIRE clock output. devices. See application section. SI 16 I MICROWIRE data input. 23 when using the Multiplexed bus mode.

MultiplexedMicroprocessorBus Interface The MULT/INT pin is sampled on power-up and, if LOW, the microprocessor bus format is assumed to be Multiplexed and the pin is considered an input pin to indicate Multiplexed bus format. The pin has an internal pull-up and thus if pin is left floating, it will be considered as in Non-multiplexed mode. The interface consists of an eight bit multiplexed Address/Data microprocessor bus (only the A0, A1, A2 and A3 address lines are decoded), and six control lines (CE, RST, AS/MI, RD/DS, WR/(R/W) and the MULT input) which should be tied LOW. Name Pin No. Type Function 28 Pkg. AD0- AD7 1, 2, 3, 4, I/O Address/Data bus. Transfers addresses and data 5, 7, 8, 10 between the microprocessor and the MID. CE 19 I Chip Enable.A LOW on this signal selects the MID for a Read/Write operation. WR/ 11 I Write or Read-Write direction. This signal indicates a Write R/W operation or Read/Write direction signal. RD/DS 12 I Read or Data Strobe. With an Intel mP this signal indicates a Read operation (active low polarity signal) or with a Motorola mP, a Data strobe (active high polarity signal). AS/MI 21 I Address Latch Enable or Address Strobe. A HIGH on this line indicates an address on the external A/D bus. When MULT e 1 (non-multiplexed bus), the pin indicates the type of bus, MI e 1 for NSC/Intel format and MI e 0, for Motorola format. RST 22 I The RST is the master Reset input, when LOW forces the device in the RESET condition (same as Power-on- Reset). MULT/ 18 I Multiplexed Bus input or INTerrupt output. It is internally INT pulled HIGH to indicate a Non-Multiplexed bus format and needs to be pulled LOW externally to indicate the Multiplexed bus format. Non-Multiplexed Microprocessor Interface The MULT/INT pin is sampled on power-up and, if not LOW, the microprocessor bus format is assumed to be Non-multiplexed. This interface consists ofa four-bit Address bus, an eight-bit Data bus and six control lines (CE RST, AS/MI, RD/DS, WR/(R/WR) and the INT signal if enabled). Name Pin No. Type Function28 Pkg. A0– A3 6, 9, I Address bus. These4 pins (accessible in the 28-pin package) 20, 23 are used to address the 16 registers. D0– D7 1, 2, 3, 4, I/O Data bus for data transfer between the microprocessor and the 5, 7, 8, 10 MID. CE 19 I Chip Enable.A LOW on this signal selects the MID for a Read/Write operation. WR/ 11 I Write or Read-Write direction. This signal indicates a Write (R/W) operation or Read/Write direction signal. RD/DS 12 I Read or Data Strobe. With an Intel mP this signal indicates a Read operation (active low polarity signal) or witha Motorola mP, a Data Strobe (active high polarity signal). AS/MI 21 I Address Latch Enable or Address Strobe. A HIGH on this line indicates an address on the external A/D bus. When MULTe1 (non-multiplexed bus), the pin indicates the type of bus, MIe1 for NSC/Intel format and MIe0 for Motorola format.

Non-Multiplexed Microprocessor Interface (Continued) The MULT/INT pin is sampled on power-up and, if not LOW, the microprocessor bus format is assumed to be Non-multiplexed. This interface consists ofa four-bit Address bus, an eight-bit Data bus and six control lines (CE RST, AS/MI, RD/DS, WR/(R/WR) and the INT signal if enabled). Name Pin No. Type Function28 Pkg. RST 22 I The RST is the master Reset input; when LOW, it forces the device in the RESET condition (same as Power-on-Reset). MULT/ 18 I Multiplexed Bus input or INTerrupt output. It is internally pulled INT O HIGH to indicate a Non-multiplexed bus format and the pin can be an INT output pin if enabled by setting the Inten bit in the CKR register. INT pulls low to indicate the completion of a MICROWIRE transfer operation. Functional Description The block diagram of the MICROWIRE Interface Device (MID) is shown in Figure 1 . It essentially consists of a very flexible microprocessor bus interface,a serial MICROWIRE interface and a Chip Select (output) port. Internally it con- tainsa programmable clock divider to derive the MICRO- WIRE clock speed froma system clock. MICROPROCESSOR INTERFACE The Microprocessor bus interface supports both National/ Intel and Motorola bus formats in the Multiplexed and Non- multiplexed bus modes. The MULT/INT pin is sampled on power-up and, if LOW, the microprocessor bus format is assumed to be Multiplexed and the pin is considered an input pin to indicate Multi- plexed bus format. The pin is internally pulled HIGH. Upon sampling, if the pin is not LOW, the bus format is assumed to be Non-multiplexed. The microprocessor interface supports multiplexed Ad- dress/Data Formats for the Intel 8088/80188 and Motorola 6803 families to work in 8-bit mode. Non-multiplexed busses of the National 32000, Intel 80286 and Motorola 68000, se- ries processors and similar are supported in the TP3465 28- pin part. Four address lines allow access to all MID regis- ters. The MID incorporatesa flexible bus interface logic to sup- port the different address and data strobes required by the different bus formats. The timing specifications are shown in a later section. The following table shows microprocessor bus control pin functions: MID Pin NSC/Intel Bus Motorola Bus MUXed Non-MUXed MUXed Non-MUXed AS/MI ALE MI e 1 AS MI e 0 RD/DS RD RD DS DS WR/(R/W) WR WR (R/W) (R/W) See Figure 7 for connection of the AS and DS signals to Motorola mPs. MICROWIRE COMMUNICATION MODES The MID provides a MICROWIRE port to the main proces- sor having two modes of operation with the MICROWIRE peripherals; software-controlled chip select and hard- ware-generated chip select modes. In the first scheme, besides the2 data byte registers, there isa third register which maps directly with the output CS Chip Selects pins, which there eight pins for this function in the TP3465 28-pin package . The software in the microproc- essor then writes to the CS register to select and deselect individual bits (corresponding to pins). In the second scheme, the CS pins are activated bya hard- ware state machine when triggered, by accessing the data registers through other address locations (see section on Register description). In this case the hardware will activate the chip select pin, send the appropriate number of MICRO- WIRE data bits (8 or 16 ) and then deselect the pin. This enhanced mode of communication allows the MICROWIRE peripheral devices to appear as if I/O mapped in the micro- processor’s memory space. CONTROL AND DATA REGISTERS There are6 control registers (PD, MWM, SKP, SKR, ST and CS), and 1 set of Data registers (First MICROWIRE Byte FMB and Second MICROWIRE Byte SMB) for data com- munication to MICROWIRE devices. In normal mode, the Chip select pins CS0– C7 are controlled (via the CS register) by software and data is transferred via the FMB and SMB registers located at address 01h and 00h (see Table I). Eight additional addresses (FMBD0– 7) access the same data register (FMB) but provide additional information to an internal state machine which drives appropriate chip se- lect pins (e.g., FMBD0 at address 02h controls CS0 pin, FMBD1 at address 03h controls CS1 pin etc.). There is only 1 set of Data registers (FMB and SMB) which han- dle the MICROWIRE communication. This latter method of allocating special addresses to provide pin-select infor- mation facilitates an enhanced MICROWIRE interface to the host processor. Table I summarizes the Control and Data Registers and the addresses at which they are accessed.

pd0–7 bits configure the CS0–7 pins as inputs or outputs. (i.e., SO data output on the positive edge of SK clock).

000 S K e CKIN SK e 5 MHz

TABLE 2. SK Clock Rate Control

Functional Description (Continued) The uwdone bit in the ST register can be connected to the INT pin of the MID to alert the host processor when MICROWIRE transmission is completed by setting the inten bit in this SKR register. The INT pin will only be functional as an interrupt in the Non-multiplexed bus mode in the 28-pin TP3465 device. The soi bit configures the SO pin to be output (soi e 0) or input (soi e 1). This bit function is used to performa Read operation ona device such as NSC TP3071 COMBO II be- cause the TP3071 sends data back on the SO pin. When soi e 1, the SO pin functions as the SI input pin, internally, and feeds the data registers. See applications diagrams and software procedures for more details. The ms bit configures the MID device asa Master of MI- CROWIRE (ms e 0) or Slave of MICROWIRE (ms e 1). MICROWIRE Slave mode is described and illustrated in the applications section. CSÐChip Select Port Register: R/W Register RESET condition, CS pins are inputs and the register con- tains the state of these pins. Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 cs7 cs6 cs5 cs4 cs3 cs2 cs1 cs0 The cs0- 7 bits control the 8, CS input/output port pins. However, only the cs0- 3 control bits are available in the TP3465 device when used in the non-multiplexed bus for- mat. In the multiplexed bus format in TP3465, all 8 CS pins are accessible. Writing to this register will affect the pins (configured as outputs in PD register) directly. Similarly, the state of the pins which are configured as inputs in the PD registers can be Read via the same (CS) register. When reading the pins designated as outputs, the bits will havea ‘‘1’’ condition. Writing to bits corresponding to input pins will have no effect on the pins. The state of an output chip select pin may also be con- trolled by the chip hardware state machine if the user writes to the FMBD0–7 registers. The hardware can only bring the appropriate pin LOW for the duration of the MICROWIRE transfer and will attempt to set it HIGH at the end of the transfer. If the user has, however, set this pin to be LOW by writing to this register, it will over-ride the action of the hard- ware and the pin will remain LOW. Thus the user must write a ‘‘1’’ in the bits that will be controlled by hardware, and the pins must be set as outputs in the PD register. STÐMICROWIRE Status Register: R Register RESET Condition, Read 80 Hex Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 uwdone 0 0 0 0 0 0 0 The uwdone bit (read only) in the ST register can be polled by the software to determine the end of the MICROWIRE transmission (uwdone e 1). uwdone e 0 during transmis- sion. FMBÐFirst MICROWIRE Byte: R/W Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 d7 d6 d5 d4 d3 d2 d1 d0 SMBÐSecond MICROWIRE Byte: R/W Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 d7 d6 d5 d4 d3 d2 d1 d0 The SMB and the FMB data registers are used to communi- cate to any MICROWIRE device 0–7 (connected to pins CS0– 7) when controlling the chip select lines via CS regis- ter (using software). The MICROWIRE parameters for this mode of operation are defined by the parameters for device 7, i.e., skp7 in SKP register, and mwm7 in MWM register. So when communicating with peripherals requiring different formats, the skp7 and mwm7 bits may need to be re-config- ured before sending data to each of these devices. Example of communication to 8-bit and 16-bit peripherals are de- scribed below: Example 1: Communicating with an 8-bit MICROWIRE pe- ripheral at CS1: Set the skp7 bit to0 (normal MICROWIRE polarity), and set the mwm7 to 0 for 1 byte operation. Set cs1 bit to 0 to select the device. Write the data into the FMB byte location so it will be shifted out after the trailing edge of the Write strobe signal. At the end of the MICROWIRE transmission set the cs1 bit to1 to de-select the device. The 8-bit STATUS from the peripheral is read from the FMByte loca- tion. Example 2: Communicating witha 16-bit MICROWIRE pe- ripheral at CS3: MICROWIRE protocol specifies that the Most Significant Bit is transmitted first. Thus the HIGH byte of data becomes the First MICROWIRE Byte to be sent out. Set the skp7 bit to0 (normal MICROWIRE polarity), and set the mwm7 to 1 for 2 byte operation. Set cs3 bit to 0 to select the device. Write the LOW data byte in the SMB reg- ister and then write the HIGH data byte into the FMB byte location. All 16 data bits are shifted out after the trailing edge of the Write strobe for the FMB register. At the end of the MICROWIRE transmission set the cs3 bit to 1 to de- select the device. The 16-bit STATUS from the peripheral is read from the FMB (HIGH data byte) and the SMB (LOW data byte) locations. FMBD0ÐFirst MICROWIRE Byte Dev0: R/W Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 d7 d6 d5 d4 d3 d2 d1 d0 There is only one set of data registers (FMB and SMB) which handle the MICROWIRE data communication. The FMBD0 address accesses the data register FMB but also provides information for the internal state machine to con- trol the CS0 pin. The MICROWIRE parameters for device 0 are indicated by the state of bits skp0 and mwm0, etc.

Functional Description (Continued) Example 1: Communicating with 8-bit peripheralÐdevice 0: The mwm0 bit must be set to 0. Write the MICROWIRE data in to the FMBD0 address. The 8-bit data is then shifted out after the trailing edge of the write pulse. The Chip Select (CS0) is automatically activated (LOW) and deactivated (HIGH) by hardware before and after the data transfer (see timing diagrams). The 8-bit STATUS from the peripheral is read from the FMBD0 byte location. Example 2: Communicating with 16-bit peripheralÐdevice The mwm0 bit must be set to 1. Write the LOW byte of MICROWIRE data into the SMB data register and then write the HIGH byte in to the FMBD0 address. The 16-bit data is then shifted out after the trailing edge of the write strobe signal for this FMBD0 address. The Chip Select 0 (CS0) pin is automatically activated (LOW) and deactivated (HIGH) by hardware before and after the data transfer (see timing dia- grams). The 16-bit STATUS from the peripheral is read from the FMBD0 (HIGH data byte) and the SMB (LOW data byte) locations. FMBD1ÐFirst MICROWIRE Byte Dev1: R/W Register Same function as FMBD0 except this refers to Device 1 and Chip Select 1 (CS1). FMBD2ÐFirst MICROWIRE Byte Dev2: R/W Register Same function as FMBD0 except this refers to Device 2 and Chip Select 2 (CS2). FMBD3ÐFirst MICROWIRE Byte Dev3: R/W Register Same function as FMBD0 except this refers to Device 3 and Chip Select 3 (CS3). FMBD4ÐFirst MICROWIRE Byte Dev4: R/W Register Same function as FMBD0 except this refers to Device 4 and Chip Select 4 (CS4). FMBD5ÐFirst MICROWIRE Byte Dev5: R/W Register Same function as FMBD0 except this refers to Device 5 and Chip Select 5 (CS5). FMBD6ÐFirst MICROWIRE Byte Dev6: R/W Register Same function as FMBD0 except this refers to Device 6 and Chip Select 6 (CS6). FMBD7ÐFirst MICROWIRE Byte Dev7: R/W Register Same function as FMBD0 except this refers to Device 7 and Chip Select 7 (CS7). MICROWIRE Master/Slave Modes MICROWIRE MASTER MODE The primary application for MID is as a master of MICRO- WIRE bus ( ms bit in CKR register set to 0), and as such it provides the SK clock out to the peripheral devices. It trans- mits data on the SO pin and receives data on the SI pin. The CS0–7 pins are used as chip select pins for the peripherals and have a predefined relationship with the SK clock output. Writing to the FMB pin causes the most significant bit to be output immediately to the SO pin, and the uwdone bit is automatically reset to 0. Upon completion of transfer of ei- ther 8 bits ( mwm7 e 0) or 16 bits ( mwm7 e 1), the uwdone bit is set to 1. The SO pin is then set to the TRI- STATEÉ condition. Note that when using the FMB and SMB registers, the communication mode is determined by the pa- rameters for channel 7 (mwm7 and skp7). MICROWIRE SLAVE MODE The MID can be set to work in MICROWIRE Slave mode by setting the ms bit to 1. The MICROWIRE clock from the master is connected to the CKIN pin of this MID device. The SK output is ignored. Normally the SO pin is in TRI-STATE condition and, while the uwdone bit is 1, any CKIN clock inputs are ignored. Writing to the FMB register causes the most significant bit to be output immediately to the SO pin and the uwdone bit is reset to 0 by hardware. The SK clock input is then enabled to clock data into SI and out of SO. After receiving SK clock pulses; either 8 ( mwm7 e 0) or 16 bits ( mwm7 e 1), the uwdone bit is set to 1 by hardware. The SO pin is then set to TRI-STATE condition. Note that when using the FMB and SMB registers, the communication mode is determined by the parameters of channel 7 (mwm7 and skp7). FMBD0–7 addresses are not used in the slave mode. The CS register, however, can be used as a general I/O port control register. See applications section for an example of the Slave opera- tion (Figure 6) . MICROWIRE BUS FORMATS MID supports devices which implement either of the two MICROWIRE bus formats; a 3-pin format and a 4-pin format. Figure 3 shows a MID connected to devices supporting each of these formats. The standard 4-pin format consists of the CCLK clock pin, CO and CI as the data out and data in pins, and CS to select the MICROWIRE peripheral. ISDN transceivers and other intelligent peripherals also have an INTerrupt signal from the peripheral to the local microprocessor. NSC MICRO- WIRE devices with this 4-pin format include ISDN transceiv- ers, COMBO II, LCD display drivers and EEPROMs. There are, however, some MICROWIRE peripherals (e.g., TP3071 COMBO II, and some EEPROMs) which support a 3-pin bus format because of package pin limitations. The format consists of the CCLK clock signal, a bi-directional data signal CO/CI, and a CS chip select signal. The direc- tion of the data transferred on the CO/CI pin is determined by a protocol between the Master and the Slave of the MI- CROWIRE bus. For example, the TP3071 implements a two-byte protocol. The first byte into the TP3071 indicates a Read or a Write operation and thus defines the direction of the next byte to the device. Software Driver Procedures This section describes the steps for software driver routines to communicate with different MICROWIRE devices (8-bit, 16-bit, or more) and those supporting the 3-pin or 4-pin MICROWIRE bus formats. INITIALIZATION 1. Write to PD (Pin Definition) register to set the desired chip select control pins (CS0–7) as outputs. (All CS pins are set to inputs on chip RESET.) 2. Write to SKP (SK polarity), to select the polarity of the SK clock for each of the MICROWIRE devices connected to CS0–7 pins. 3. Write to MWM (MICROWIRE Mode) register to select whether 8- or 16-bit devices are attached to the CS0–7 pins. Devices needing more than 16-bits may still be con- figured as 8-bit mode (if multiple of 8) or 16-bit mode (if multiple of 16 bits).

Software Driver Procedures (Continued) 4. Write to SKR to set the div bits to support the fastest SK clock rate supported by the peripherals. Set inten e 1 if the uwdone status is to set an INTerrupt to the host processor (available only in the Non-multiplexed bus im- plementation of TP3465, 28-pin package). The ms and the soi bit are set to 0 upon power up and indicate that the MID is in MICROWIRE Master mode, with SO as an output pin as normal. SENDING DATA TO PERIPHERALS (Normal Mode) Assume sending 16-bit data toa MICROWIRE based device connected to any one of CS0 to CS7. 1. Write to CS (Chip Select) register and reset the appropri- ate bit and thus activate the corresponding CS pin. 2. Write LOW byte data to SMB (Second MICROWIRE Byte) register and then HIGH byte data to FMB (First MICRO- WIRE Byte) register. 3. Read the ST (Status) register and stay in a loop until uwdone bit is set. 4. Write to CS register and set the bit to deactivate the ap- propriate chip select pin. SENDING DATA TO PERIPHERALS (Hardware Assisted Chip Select) Assuming sending 16-bit data to dev3 connected to CS3 pin. 1. Write LOW byte data to address SMB and then HIGH byte data to FMBD3. 2. Read the ST register and stay ina loop until uwdone bit is set. Communicating with an NSC TP3071 COMBO II Type Device The NSC TP3071 COMBO II device hasa modified MICRO- WIRE port. It shares a single pin (called CO/CI) for incoming and outgoing data. The MID’s SO pin may be tied to this pin, as shown in Figure 3 , and the following steps are followed to Read from and Write to this device. Assume that the chip select for TP3071 is connected to CS1 pin. TP3071 Write Operation: a. Initialization states: skp1 e 1, mwm1 e 1, and soi e 0 b. Data transfer options: i. Set cs1 bit to 0, write LOW byte to SMB, and HIGH byte to FMB and then set cs1 bit to1 after uwdone bit is set to 1. OR ii. Write LOW byte to SMB, and HIGH byte to FMBD1. TP3071 Read Operation: a. Initialization states: skp1 e 1, mwm1 e 0, and soi e 0. b. Data transfer options: i. Set cs1 bit to 0, write HIGH byte to FMB, wait until uwdone bit is set to1 by hardware. Set soi bit to 1. Write dummy LOW byte (e.g., 00h) to FMB, wait until uwdone bit is set to 1 by hardware. Read STATUS from FMB address. Set soi to 0 and cs1 to 1. OR ii. Write HIGH byte to FMBD1, wait until uwdone bit is set to1 by hardware. Set soi bit to 1. Write a dummy LOW byte (e.g., 00h) to FMBD1 and wait until uwdone bit is set to 1 by hardware. Read STATUS from FMBD1 ad- dress. Set soi bit to 0.

Applications

The versatile TP3465 MICROWIRE Interface Device can be used in a number of applications involving MICROWIRE pe- ripheral devices that need to be controlled usinga standard microprocessor which only hasa parallel bus structure. ISDN TERMINAL ADAPTER The MID can be used in ISDN terminal adapters (see Figure 4 ) interfacing to ISDN components such as TP3420 SID, as well as non-ISDN components such as LCD display drivers (e.g., COP470) and serial EEPROMs (COP494). In this ap- plication the MID signals SK, SO and SI are bussed to all peripheral devices. The device chip selects control lines a total of 8 in the 28-pin package are individually connected to each of the devices. Status Interrupt from the peripherals such as SID are connected directly to the main processor. ANALOG OR DIGITAL LINECARDS The MID can also be used in analog and digital (ISDN and Non-ISDN) linecard applications (see Figure 5 ). Up to 8 MICROWIRE peripheral devices (TP3070 COMBO II, or TP3420 SIDs, TP3410 UIDs or TP3401 DASLs) can be con- nected to one MID device. The Interrupts from the trans- ceivers may be wire-ORed and fed into one interrupt line of the main processor, in which case all the devices will need to be polled after an interrupt. The efficient interface be- tween the MID and microprocessor allows this process to be accomplished with minimum overhead. In a given application, if any of the chip select pins are not used to perform chip select for peripherals, then it may be used asa general purpose input/output pin under software control. MID SUPPORTING MASTER AND SLAVE MICROWIRE OPERATION The MICROWIRE serial data bus is often used asa means of inter-processor communication. The MID may be used either as the Master of the MICROWIRE clock SK or as a Slave to the SK clock fed via CKIN pin. Figure 6 shows an application in which two general microprocessors communi- cate with each other over the MICROWIRE bus. At the same time other peripherals are also connected to the serial bus. External handshaking between the two processors is required before the MICROWIRE Byte data transfer is exe- cuted by the master of the MICROWIRE bus.

FIGURE 5. MID, LINECARD ApplicationÐDigital (ISDN/Non-ISDN) or Analog

Device Electrical Characteristics Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. V CC to GND 7V Input Voltage b0.3V to V CC a 0.3V DC Input Current I I g 50 mA Storage Temperature Range b65§Ct o a150§C Lead Temperature (Soldering, 10 Sec.) 300 §C ESD Rating t 1500V

Electrical Characteristics

Unless otherwise noted, limits in BOLD characters are electrical testing limits at V CC e 5.0V and T A ea 25§C. All other limits are assured by correlation with other production tests and/or product design and characterization for V CC e 5.0V g5% and TA e 0§Ct o a70§C. All signals are referenced to GND. Symbol Parameter Conditions Limits Units Min Max VIL Input Low Voltage All Inputs 0.8 V VIH Input High Voltage All Inputs 2.0 V VOL Output Low Voltage CS0–7: I OL e 1m A SK, SO: I OL e 4m A 0.4 V AD(7:0): I OL e 2m A VOH Output High Voltage CS0–7: I OH e 1m A SK, SO: I OH e 4m A 2.4 V AD(7:0): I OH e 2m A IIH High Level Input Current All Inputs, b10 mAGND k VIN k VCC IIL Low Level Input Current All Inputs a10 mA IOZ Output Current in High-Z AD(7:0), SO g20 mA ICC Dynamic Supply Current CKIN e SK e 1 MHz 0.7 mACKIN e SK e 20 MHz 4

This section contains timing diagrams for the microprocessor bus interface, MICROWIRE port interface and the Control and Clock timings relationships. Timing characteristics are derived from worst-case simulations plus guardbanding. Production testing is limited to device func- tionality. NSC/Intel Bus Format MULTIPLEXED MICROPROCESSOR BUS TL/H/10803–7 NON-MULTIPLEXED MICROPROCESSOR BUS TL/H/10803–8 Symbol Parameter Conditions Min Max Units tWASH Width, Address Strobe High 20 ns tSAAS Setup, Address to Address Strobe 10 ns tHASA Hold, Address Strobe Low to Address 10 ns tHASR Hold, Address Strobe to Read Strobe 10 ns tDRD Delay, Read Low to Data 100 pF Load 70 ns tHRD Hold, Read High to Data 5 40 ns tWRL Width, Read Strobe Low 20 ns tSDW Setup, Data to Write High 30 ns tHWD Hold, Write High to Data 10 ns tWWL Width, Write Strobe Low 20 ns tSAR Setup, Address to Read Low Non-Muxed, MI e 11 0 n s tHRA Hold, Read High to Address Non-Muxed, MI e 11 0 n s tSAW Setup, Address to Write Low Non-Muxed, MI e 11 0 n s tHWA Hold, Write High to Address Non-Muxed, MI e 11 0 n s

MULTIPLEXED MICROPROCESSOR BUS TL/H/10803–9 NON-MULTIPLEXED MICROPROCESSOR BUS TL/H/10803–10 Note: For TP3465 MID, the AS (Address Strobe) and DS (Data Strobe) are active high polarity signals. For Non-multiplexed busses AS= 0. SeeFigure7 for connection diagram. Symbol Parameter Conditions Min Max Units tWASH Width, Address Strobe High 20 ns tSAAS Setup, Address to Address Strobe 10 ns tHASA Hold, Address Strobe Low to Address 10 ns tHASDS Hold, Address Strobe to Data Strobe 10 ns tDDSD Delay, Data Strobe Low to Data (Read) 100 pF Load 70 ns tHDSD Hold, Data Strobe High to Data 5 40 ns tWDSL Width, Data Strobe Low 20 ns tSDDS Setup, Data to Data Strobe High (Write) 30 ns tSRWDS Setup, R/W Strobe to Data Strobe 10 ns tHDSRW Hold, Data Strobe to R/W 10 ns tSADS Setup, Address to Data Strobe Low Non-Muxed, MI e 0 10 ns tHDSA Hold, Data Strobe High to Address Non-Muxed, MI e 0 10 ns

Symbol Parameter Conditions Min Max Units fCKIN CKin Frequency 20 MHz fSK SK Frequency 5 MHz tSKD SK Clock Duration 200 ns tSKH SK High Duration 70 ns tSKL SK Low Duration 70 ns tRSK Rise Time, SK 100 pF Load 30 ns tFSK Fall Time, SK 100 pF Load 30 ns tSISK Setup Time, SI Valid to SK Edge 20 ns tHSKI Hold Time, SK High to SI Invalid 20 ns tDSKO Delay, SK Edge to SO Data Valid Output 20 ns tDSKZ Delay, Last SK to SO TRI-STATE 30 ns tDWOV Delay, WR to SO Valid FMB or 50 nsFMBD0–7 MICROWIRE Timing for 1 Byte Transfer TL/H/10803–11 MICROWIRE Timing for 2 Byte Transfers TL/H/10803–12

Control Interface Timing Relationships Symbol Parameter Conditions Min Max Units tDWCSA Delay, Write Strobe to CS Asserted Auto Mode 2 SK Cycle tDCSSKA Delay, CS Active to first SK Edge Auto Mode 0.5 SK 0.5 SK nsb 50 ns tDSKCSA Delay, Last SK Edge to CS Inactive Auto Mode 2.8 7.3 nsCS Load e 10 pF; SK Load e 50 pF tDWCSS Delay, Write Strobe (CS Register) Software 30 nsto CS Asserted tDCSN Delay, CS High to INT Low 50 ns tDRDN Delay, RD Low to INT High ST Register 80 ns TL/H/10803–13

TP3465 MICROWIRE Interface Device (MID) PhysicalDimensionsinches(millimeters)(Continued) PlasticChipCarrier(V) OrderNumberTP3465V NSPackageNumberV28A LIFESUPPORTPOLICY NATIONAL’SPRODUCTSARENOTAUTHORIZEDFORUSEASCRITICALCOMPONENTSINLIFESUPPORT DEVICESORSYSTEMSWITHOUTTHEEXPRESSWRITTENAPPROVALOFTHEPRESIDENTOFNATIONAL SEMICONDUCTORCORPORATION.Asusedherein: 1.Lifesupportdevicesorsystemsaredevicesor2.Acriticalcomponentisanycomponentofalife systemswhich,(a)areintendedforsurgicalimplantsupportdeviceorsystemwhosefailuretoperformcan intothebody,or(b)supportorsustainlife,andwhosebereasonablyexpectedtocausethefailureofthelife failuretoperform,whenproperlyusedinaccordancesupportdeviceorsystem,ortoaffectitssafetyor withinstructionsforuseprovidedinthelabeling,caneffectiveness. bereasonablyexpectedtoresultinasignificantinjury totheuser. NationalSemiconductorNationalSemiconductorNationalSemiconductorNationalSemiconductor CorporationEuropeHongKongLtd.JapanLtd. 1111WestBardinRoadFax:(a49)0-180-530858613thFloor,StraightBlock,Tel:81-043-299-2309 Arlington,TX76017Email:cnjwge@tevm2.nsc.comOceanCentre,5CantonRd.Fax:81-043-299-2408 Tel:1(800)272-9959DeutschTel:(a49)0-180-5308585Tsimshatsui,Kowloon Fax:1(800)737-7018EnglishTel:(a49)0-180-5327832HongKong Fran3aisTel:(a49)0-180-5329358Tel:(852)2737-1600 ItalianoTel:(a49)0-180-5341680Fax:(852)2736-9960 Nationaldoesnotassumeanyresponsibilityforuseofanycircuitrydescribed,nocircuitpatentlicensesareimpliedandNationalreservestherightatanytimewithoutnoticetochangesaidcircuitryandspecifications.