TP2411

TP2411 3PEAK | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 17

Technical content

Features

 Gain-bandwidth Product: 10 MHz  Low Noise: 8.2 nV/√Hz(f= 1kHz)  Slew Rate: 7 V/μs  Offset Voltage: 1 mV (max)  EMIRR IN+: 88 dB( under 2.4GHz)  Low THD+N: 0.0005%  Supply Range: 2.2 V to 5.5 V  Supply Current: 1.4 mA/ch  Low Input Bias Current: 0.3pA Typical  Rail-to-Rail I/O  High Output Current: 70 mA (1.0V Drop)  –40° C to 125° C Operation Range

Applications

 Sensor Signal Conditioning  Consumer Audio  Multi-Pole Active Filters  Control-Loop Amplifiers  Communications  Security  Scanners Pin Configuration (Top View) TP2412 8-Pin SOP/MSOP/SOT/TSSOP (-S ,-V, -T, -TS Suffixes) Out A ﹢In A ﹣In A ﹢In B ﹣In B Out BA B ﹣Vs ﹢Vs TP2414 14-Pin SOP/TSSOP (-S and -T Suffixes) Out A ﹢In A ﹣In A DA CB Out D ﹢In D ﹣In D Out B ﹢In B ﹣In B Out C ﹢In C ﹣In C ﹣Vs﹢Vs TP2411 8-Pin SOP (-S Suffix) Out TP2411 5-Pin SOT23 (-T Suffix) NC ﹢In ﹣In ﹣Vs ﹢Vs NC NC 1Out +In -In ﹣Vs ﹢Vs

Description

The TP2411, TP2412, and TP2414 are low cost, single, dual, and quad rail-to-rail output, single-supply amplifiers featuring low offset and input voltages, low current noise, and wide signal bandwidth. The combination of low offset, low noise, very low input bias currents, and high speed make these amplifiers useful in a wide variety of applications. Filters, integrators, photodiode amplifiers, and high impedance sensors all benefit from this combination of performance features. Audio and other ac applications benefit from the wide bandwidth and low distortion of these devices. Applications for these amplifiers include power amplifier (PA) controls, laser diode control loops, portable and loop -powered instrumentation, audio amplification for portable devices, and ASIC input and output amplifiers. The TP2411 is single channel version available in 8-pin SOP and 5-pin SOT23 packages. The TP2412 is dual channel version available in 8 -pin SOP, SOT, TSSOP and MSOP packages. The TP2414 is quad channel version available in 14-pin SOP and TSSOP packages. 3PEAK and the 3PEAK logo are registered trademarks of 3PEAK INCORPORATED . All other trademarks are the property of their respective owners. Input Voltage Noise Spectral Density 100 1000 1 10 100 1k 10k 100k 1M Noise(nV/√Hz) Frequency(Hz) VCC= +5V RL= 1kΩ

Low Cost, Low Noise CMOS RRIO Op-amps Order Information Model Name Order Number Package Transport Media, Quantity Marking Information TP2411 TP2411-SR 8-Pin SOP Tape and Reel, 4,000 TP2411 TP2411-TR 5-Pin SOT23 Tape and Reel, 3,000 411 TP2412 TP2412-SR 8-Pin SOP Tape and Reel, 4,000 TP2412 TP2412-VR 8-Pin MSOP Tape and Reel, 3,000 TP2412 TP2412-TSR 8-Pin TSSOP Tape and Reel, 3,000 TP2412 TP2412-TR 8-Pin SOT23 Tape and Reel, 3,000 S12 TP2414 TP2414-SR 14-Pin SOP Tape and Reel, 2,500 TP2414 TP2414-TR 14-Pin TSSOP Tape and Reel, 3,000 TP2414 Absolute Maximum Ratings Note 1 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The op amp supplies must be established simultaneously, with, or before, the application of any input signals. Note 3: The inputs are protected by ESD protection diodes to each power supply. If the input extends more than 500mV beyond the power supply, the input current should be limited to less than 10mA. Note 4: A heat sink may be required to keep the junction temperature below the absolute maximum. This depends on the power supply voltage and how many amplifiers are shorted. Thermal resistance varies with the amount of PC board metal connected to the package. The specified values are for short traces connected to the leads. ESD, Electrostatic Discharge Protection Symbol Parameter Condition Minimum Level Unit HBM Human Body Model ESD ANSI/ESDA/JEDEC JS-001 2 kV CDM Charged Device Model ESD ANSI/ESDA/JEDEC JS-002 1 kV Thermal Resistance Package Type θJA θJC Unit 5-Pin SOT23 250 81 °C /W 8-Pin SOP 158 43 °C /W 8-Pin MSOP 210 45 °C /W 8-Pin TSSOP 191 °C /W 8-Pin SOT23 196 70 °C /W 14-Pin SOP 120 36 °C /W 14-Pin TSSOP 180 35 °C /W

Low Cost, Low Noise CMOS RRIO Op-amps

Electrical Characteristics

The specifications are at TA = 27° C. VS = 5V, RL = 2kΩ, CL =100pF.Unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VOS Input Offset Voltage VCM = VS/2 -1 ± 0.25 +1 mV VCM = 0V -1 ± 0.25 +1 mV VOS TC Input Offset Voltage Drift -40°C to 125°C 1 μV/° C IB Input Bias Current TA = 27 °C 0.3 pA TA = 85 °C 150 pA TA = 125 °C 300 pA IOS Input Offset Current 0.3 pA Vn Input Voltage Noise f = 0.1Hz to 10Hz 3.14 μVPP en Input Voltage Noise Density f = 1kHz 8.2 nV/√Hz in Input Current Noise f = 1kHz 2 fA/√Hz CIN Input Capacitance Differential Common Mode 8 7 pF CMRR Common Mode Rejection Ratio VCM = 2.5V 90 106 dB VCM = 0V to 3V 80 106 dB VCM = 0V to 5V 55 72 dB VCM Common-mode Input Voltage Range V– -0.1 V+-0.1 V PSRR Power Supply Rejection Ratio VS = 2.2V to 5.5V, VCM = 0V 82 100 dB AVOL Open-Loop Large Signal Gain RLOAD = 2kΩ, VOUT = -2V to 2V 100 120 dB VOL, VOH Output Swing from Supply Rail RLOAD = 2kΩ 20 50 mV ROUT Closed-Loop Output Impedance G = 1, f =1MHz, IOUT = 0 0.2 Ω RO Open-Loop Output Impedance f = 1kHz, IOUT = 0 125 Ω ISC Output Short-Circuit Current Sink or source current 100 130 mA VS Supply Voltage 2.2 5.5 V IQ Quiescent Current per Amplifier VS = 5V 1.4 1.95 mA PM Phase Margin RLOAD = 1kΩ, CLOAD = 60pF 60 ° GM Gain Margin RLOAD = 1kΩ, CLOAD = 60pF 8 dB GBWP Gain-Bandwidth Product f = 1kHz 10 MHz SR Slew Rate AV = 1, VOUT = 0V to 10V, CLOAD = 100pF, RLOAD = 2kΩ 3.0 7 V/μs FPBW Full Power Bandwidth Note 1 414 kHz tS Settling Time, 0.1% Settling Time, 0.01% AV = –1, 1V Step 0.75 0.85 μs THD+N Total Harmonic Distortion and Noise f = 1kHz, AV =1, RL = 2kΩ, VOUT = 1Vp-p 0.0005 % Xtalk Channel Separation f = 1kHz, RL = 2kΩ 110 dB Note 1: Full power bandwidth is calculated from the slew rate FPBW = SR/π • VP-P

Low Cost, Low Noise CMOS RRIO Op-amps Typical Performance Characteristics VS = ±2.75V, VCM = 0V, RL = Open, unless otherwise specified. Offset Voltage Production Distribution Unity Gain Bandwidth vs. Temperature Open-Loop Gain and Phase Input Voltage Noise Spectral Density Input Bias Current vs. Temperature Input Bias Current vs. Input Common Mode Voltage 100 200 300 400 500 600 700 800 900 1000 -990 -890 -790 -690 -590 -490 -390 -290 -190 -90 110 210 310 410 510 610 710 810 910 Population Offset Voltage(uV) Number = 38300 pcs 14.1 14.2 14.3 14.4 14.5 14.6 14.7 14.8 14.9 -40 -20 0 20 40 60 80 100 120 GBW(MHz) Temperature(℃) -270 -170 -70 130 230 330 -60 -40 -20 100 120 140 0.1 10 1k 100k 10M 1000M Phase (°) Gain(dB) Frequency (Hz) 100 1000 1 10 100 1k 10k 100k 1M Noise(nV/√Hz) Frequency(Hz) VCC= +5V RL= 1kΩ 1.00E-21 1.00E-19 1.00E-17 1.00E-15 1.00E-13 1.00E-11 -10 10 30 50 70 90 110 130 150 Input Bias Current(A) Temperature(℃) 5.00E-18 5.00E-17 5.00E-16 0 1 2 3 4 5 6 Input Bias Current(A) Common Mode Voltage(V)

Low Cost, Low Noise CMOS RRIO Op-amps Typical Performance Characteristics VS = ±2.75V, VCM = 0V, RL = Open, unless otherwise specified. (Continued) Common Mode Rejection Ratio CMRR vs. Frequency Quiescent Current vs. Temperature Short Circuit Current vs. Temperature Power-Supply Rejection Ratio Quiescent Current vs. Supply Voltage 100 120 140 0 1 2 3 4 CMRR(dB) Common Mode Voltage(V) 100 120 140 160 180 1 100 10k 1M 100M CMRR(dB) Frequency(Hz) 1.3 1.32 1.34 1.36 1.38 1.4 1.42 1.44 1.46 1.48 -40 -15 10 35 60 85 110 Supply current(mA) Temperature(℃) 100 120 140 160 180 200 -50 0 50 100 150 Ishort(mA) Temperature(℃) ISINK ISOURCE 100 120 140 1 100 10k 1M PSRR(dB) Frequency(Hz) PSRR+ PSRR- 0.2 0.4 0.6 0.8 1.2 1.4 1.6 1.8 Supply current (mA) Supply Voltage (V)

Low Cost, Low Noise CMOS RRIO Op-amps Typical Performance Characteristics VS = ±2.75V, VCM = 0V, RL = Open, unless otherwise specified. (Continued) Power-Supply Rejection Ratio vs. Temperature CMRR vs. Temperature EMIRR IN+ vs. Frequency Large-Scale Step Response Negative Over-Voltage Recovery Positive Over-Voltage Recovery 100 120 140 -50 0 50 100 150 PSRR(-dB) Temperature(℃) 100 120 -50 0 50 100 150 CMRR(-dB) Temperature(℃) 100 40 400 4000 EMIRR IN+ (dB) Frequency (MHz) Output Voltage (2V/div) Time (20μs/div) Gain= +1 RL= 10kΩ 1V/div 2V/div Time (500ns/div) Gain= +10 ±V= ±2.5V Time (500ns/div) 1V/div 2V/div Gain= +10 ±V= ±2.5V

Low Cost, Low Noise CMOS RRIO Op-amps Typical Performance Characteristics VS = ±2.75V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)

0.1 Hz TO 10 Hz Input Voltage Noise Offset Voltage vs Common-Mode Voltage

Positive Output Swing vs. Load Current Negative Output Swing vs. Load Current 5s/div 2μV/div -3000 -2500 -2000 -1500 -1000 -500 500 Offset voltage(μV) Common-mode voltage(V) Vcc=±2.5V 100 120 140 0 1 2 3 4 5 Iout(mA) Vout Dropout (V) 25℃-40℃ +125℃ -200 -180 -160 -140 -120 -100 -80 -60 -40 -20 0 1 2 3 4 5 Iout(mA) Vout Dropout (V) 25℃ -40℃ +125℃

Low Cost, Low Noise CMOS RRIO Op-amps Pin Functions -IN: Inverting Input of the Amplifier. +IN: Non-Inverting Input of Amplifier. OUT: Amplifier Output. The voltage range extends to within mV of each supply rail. V+ or +Vs: Positive Power Supply. Typically the voltage is from 2.2V to 5.5V. Split supplies are possible as long as the voltage between V+ and V– is between 2.2V and 5.5V. A bypass capacitor of 0.1μF as close to the part as possible should be used between power supply pins or between supply pins and ground. V- or -Vs: Negative Power Supply. It is normally tied to ground. It can also be tied to a voltage other than ground as long as the voltage between V+ and V– is from 2.2V to 5.5V. If it is not connected to ground, bypass it with a capacitor of 0.1μF as close to the part as possible. Operation The TP2411 series op amps can operate on a single-supply voltage (2.2 V to 5.5 V), or a split-supply voltage (±1.1 V to ± 2.75 V), making them highly versatile and easy to use. The power -supply pins should have local bypass ceramic extended temperature range of –40° C to +125° C. Parameters that can exhibit variance with regard to operating voltage or temperature are presented in the Typical Characteristics. Applications Information Input ESD Diode Protection The TP2411 incorporates internal electrostatic discharge (ESD) protection circuits on all pins. In the case of input and output pins, this protection primarily consists of current-steering diodes connected between the input and power-supply pins. These ESD protection diodes also provide in-circuit input overdrive protection, as long as the current is limited to 10 mA as stated in the Absolute Maximum Ratings table. Many input signals are inherently current-limited to less than 10 mA; therefore, a limiting resistor is not required. Figure 1 shows how a series input resistor (RS) may be added to the driven input to limit the input current. The added resistor contributes thermal noise at the amplifier input and the value should be kept to the minimum in noise-sensitive applications. IN+ IN- 500Ω 500Ω INPUT ESD DIODE CURRENT LIMITING- UNITY GAIN Figure1. Input ESD Diode Ioverload 10mA max VIN Current-limiting resistor required if input voltage exceeds supply rails by >0.5V. TP2411 Vout +2.5V -2.5V 5kΩ

Low Cost, Low Noise CMOS RRIO Op-amps PCB Surface Leakage In applications where low input bias current is critical, Printed Circuit Board (PCB) surface leakage effects need to be considered. Surface leakage is caused by humidity, dust or other contamination on the board. Under low humidity conditions, a typical resistance between nearby traces is 1012Ω. A 5V difference would cause 5pA of current to flow, which is greater than the TP2411/2412/2414 OPA’s input bias current at +27°C (± 3pA, typical). It is recommended to use multi-layer PCB layout and route the OPA’s -IN and +IN signal under the PCB surface. The effective way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin. An example of this type of layout is shown in Figure 1 for Inverting Gain application. 1. For Non-Inverting Gain and Unity-Gain Buffer: a) Connect the non-inverting pin (VIN+) to the input with a wire that does not touch the PCB surface. b) Connect the guard ring to the inverting input pin (VIN–). This biases the guard ring to the Common Mode input voltage. 2. For Inverting Gain and Trans-impedance Gain Amplifiers (convert current to voltage, such as photo detectors): a) Connect the guard ring to the non-inverting input pin (VIN+). This biases the guard ring to the same reference voltage as the op-amp (e.g., VDD/2 or ground). b) Connect the inverting pin (VIN–) to the input with a wire that does not touch the PCB surface. VIN+ VIN- +VSGuard Ring Figure 4 The Layout of Guard Ring Power Supply Layout and Bypass The TP2411/2412/2412 OPA’s power supply pin (V DD for single-supply) should have a local bypass capacitor (i.e., within 100mm to provide large, slow currents. This bulk capacitor can be shared with other analog parts. Ground layout improves performance by decreasing the amount of stray capacitance and noise at the OPA’s inputs and outputs. To decrease stray capacitance, minimize PC board lengths and resistor leads, and place external components as close to the op amps’ pins as possible. Proper Board Layout To ensure optimum performance at the PCB level, care must be taken in the design of the board layout. To avoid leakage currents, the surface of the board sh ould be kept clean and free of moisture. Coating the surface creates a barrier to moisture accumulation and helps reduce parasitic resistance on the board. Keeping supply traces short and properly bypassing the power supplies minimizes power supply disturb ances due to output current variation, such as when driving an ac signal into a heavy load. Bypass capacitors should be connected as closely as possible to the device supply pins. Stray capacitances are a concern at the outputs and the inputs of the amplifier. It is recommended that signal traces be kept at least 5mm from supply lines to minimize coupling. A variation in temperature across the PCB can cause a mismatch in the Seebeck voltages at solder joints and other points where dissimilar metals are in c ontact, resulting in thermal voltage errors. To minimize these thermocouple effects, orient resistors so heat sources warm both ends equally. Input signal paths should contain matching numbers and types of components, where possible to match the number and type of thermocouple junctions. For example, dummy components such as zero value resistors can be used to match real resistors in the opposite input path. Matching components should be located in close proximity and should be oriented in the same manner. Ensure leads are of equal length so that thermal conduction is in equilibrium. Keep heat sources on the PCB as far away from amplifier input circuitry as is practical. The use of a ground plane is highly recommended. A ground plane reduces EMI noise and al so helps to maintain a constant temperature across the circuit board.

Low Cost, Low Noise CMOS RRIO Op-amps D e E b θ Package Outline Dimensions SOT23-5 Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A1 0.000 0.100 0.000 0.004 A2 1.050 1.150 0.041 0.045 b 0.300 0.400 0.012 0.016 D 2.820 3.020 0.111 0.119 E 1.500 1.700 0.059 0.067 E1 2.650 2.950 0.104 0.116 e 0.950TYP 0.037TYP e1 1.800 2.000 0.071 0.079 L1 0.300 0.460 0.012 0.024 θ 0° 8° 0° 8°

Low Cost, Low Noise CMOS RRIO Op-amps Package Outline Dimensions SOT-23-8 Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 1.050 1.250 0.041 0.049 A1 0.000 0.100 0.000 0.004 A2 1.050 1.150 0.041 0.045 b 0.300 0.500 0.012 0.020 c 0.100 0.200 0.004 0.008 D 2.820 3.020 0.111 0.119 E 1.500 1.700 0.059 0.067 E1 2.600 3.000 0.102 0.118 e 0.65（BSC） 0.026(BSC) e1 0.975（BSC） 0.038(BSC) L 0.300 0.600 0.012 0.024 θ 0° 8° 0° 8°

Low Cost, Low Noise CMOS RRIO Op-amps D b E e θ C Package Outline Dimensions SOP-8 Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A1 0.100 0.250 0.004 0.010 A2 1.350 1.550 0.053 0.061 b 0.330 0.510 0.013 0.020 C 0.190 0.250 0.007 0.010 D 4.780 5.000 0.188 0.197 E 3.800 4.000 0.150 0.157 E1 5.800 6.300 0.228 0.248 e 1.270 TYP 0.050 TYP L1 0.400 1.270 0.016 0.050 θ 0° 8° 0° 8°

Low Cost, Low Noise CMOS RRIO Op-amps Package Outline Dimensions MSOP-8 Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 0.800 1.200 0.031 0.047 A1 0.000 0.200 0.000 0.008 A2 0.760 0.970 0.030 0.038 b 0.30 TYP 0.012 TYP C 0.15 TYP 0.006 TYP D 2.900 3.100 0.114 0.122 e 0.65 TYP 0.026 E 2.900 3.100 0.114 0.122 E1 4.700 5.100 0.185 0.201 L1 0.410 0.650 0.016 0.026 θ 0° 6° 0° 6° e E A D L1 L2 L R θ b

Low Cost, Low Noise CMOS RRIO Op-amps Package Outline Dimensions TSSOP-8 Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max D 2.900 3.100 0.114 0.122 E 4.300 4.500 0.169 0.177 b 0.190 0.300 0.007 0.012 c 0.090 0.200 0.004 0.008 E1 6.250 6.550 0.246 0.258 A 1.200 0.047 A2 0.800 1.000 0.031 0.039 A1 0.050 0.150 0.002 0.006 e 0.65(BSC) 0.026（BSC） L 0.500 0.700 0.020 0.028 H 0.25(BSC) 0.01（BSC） θ 1° 7° 1° 7°

Low Cost, Low Noise CMOS RRIO Op-amps Package Outline Dimensions TSSOP-14 Symbol Dimensions In Millimeters MIN TYP MAX A - - 1.20 A1 0.05 - 0.15 A2 0.90 1.00 1.05 b 0.20 - 0.28 c 0.10 - 0.19 D 4.86 4.96 5.06 E 6.20 6.40 6.60 E1 4.30 4.40 4.50 e 0.65 BSC L 0.45 0.60 0.75 L1 1.00 REF L2 0.25 BSC R 0.09 - - θ 0° - 8° E e A D L1 L2 L R θ c

Low Cost, Low Noise CMOS RRIO Op-amps θ e b E1 E D A A2 L Package Outline Dimensions SOP-14 Symbol Dimensions In Millimeters MIN TYP MAX A 1.35 1.60 1.75 A1 0.10 0.15 0.25 A2 1.25 1.45 1.65 b 0.36 0.49 D 8.53 8.63 8.73 E 5.80 6.00 6.20 E1 3.80 3.90 4.00 e 1.27 BSC L 0.45 0.60 0.80 L1 1.04 REF L2 0.25 BSC θ 0° 8°