TMXF28155

TMXF28155 AGERE | Alldatasheet

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155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

1 Features

I Versatile IC supports 155/51 Mbits/s SONET/SDH interface solutions for T3/E3, DS2, T1/E1/J1, and DS0/E0/J0 applications. I Implementation supports both linear (1 + 1, unpro- tected) and ring (UPSR) network topologies. I Provides full termination of up to 21 E1, 28 T1, or 28 J1. I Low power 3.3 V supply. I –40 °C to +85 °C industrial temperature range. I 456-pin ball grid array (PBGA) package. I Complies with Bellcore*, ITU, ANSI †, ETSI and Jap- anese TTC standards: GR-253-CORE, GR-499, (ATT) TR-62411, ITU-T G.707, G.704, G.706, G.783, JT-G706, JT-G707, JT -I431-a, ETS 300 417-1-1, ETS 300 011, T1.107, T1.404.

1.1 SONET/SDH Interface

I Termination of a single 155 Mbits/s STS-3/STM-1 or single 51 Mbits/s STS-1/STM-0. I Built-in clock and data recovery circuit at

155 Mbits/s STS-3/STM-1 interface (can be dese-

lected if external clock recovery is provided). I Supports overhead processing for all transport and path overhead bytes. I Optional insertion and extraction of overhead bytes via a serial transport overhead access channel. Con- figurable as dedicated DCC channels. I Software controlled linear 1 + 1 protection via dedi- cated interface to protection card. I Full path termination and SPE extraction/insertion. I SONET/SDH compliant condition and alarm report- ing. I Built-in diagnostic loopback modes. I 8 kHz line frame sync output. * Bellcore is now T elcordia T echnologies. Telcordia Technologies is a trademark of Telcordia Technologies, Inc. † ANSI is a registered trademark of American National Standards Institute, Inc.

1.2 STS/STM Pointer Interpreter

I Interprets STS/AU/TU-3 pointers. I Synchronizes 8 kHz frame and 2 kHz superframe to system/shelf timing reference by setting the transmit STS-3/STM-1 pointers to a fixed value of 522. I Monitors/terminates SPE path overhead.

1.3 Telecom Bus Interface

I Telecom bus interface to mate devices including clock, data[8], parity, SPE-, J0-, J1-, and V1 timing indicator. I Line and path RDI and REI signals passed to mate devices. I Three Super Mapper devices, two configured as mate devices, provide full termination of an STS-3/STM-1. A three-chip solution to terminate 84 DS1s/J1s or 63 E1s.

1.4 VT Termination/Generation (x28/x21)

I Monitors/terminates VT path overhead for 28 VT1.5/TU-11 or 21 VT2/TU-12. I Synchronizes VT/TU SPE to system/shelf timing ref- erence by setting the transmit VT/TU pointers to fixed values for asynchronous mapping or by dynamically changing the transmit VT/TU pointers for byte syn- chronous mapping. I Fixed pointer generation in transmit side for asyn- chronous mapping. I Dynamic pointer generation in transmit side for byte- synchronous mapping.

1.5 Mapping/Multiplexing Modes (x28/x21)

I Maps DS3 clear channel or framed signal into STS-1 or TUG-3. I Maps T1/E1/J1 into VT/TU (including DS1 into TU-12). I Supports asynchronous, byte-synchronous, and bit- synchronous mapping.

2 Agere Systems Inc. TMXF28155 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 May 2001

1 Features (continued)

I Supports UPSR applications via the dedicated ring interface and an external tributary selector. I Supports all valid T1/E1/J1 multiplexing structures into STS-1 and STS-3/STM-1: — STS-3/STS-1/SPE/VTG/VTx — STM-1/AU-3/TUG-2/TU-1x/VC-1x — STM-1/AU-4/TUG-3/TUG-2/TU-1x/VC-1x I Allows grooming of VTs/TUs in granularity of TUG-2s within the STS-3/STM-1 signal. I Supports J2 trace identifier monitoring/insertion. I Configurable VT/TU slot selection for DS1, E1, and J1 insertion and drop. I Automatic receive monitor functions include VT/TU RDI-V , REI-V , BIP-2 errors, AIS- V, LOP- V. I Complies with GR-253-CORE, GR-499, ITU-T G.707, G.704, G.783, T1.105, JT -G707, ETS 300 417-1-1.

1.6 M13 Features

I Configurable multiplexer/demultiplexer for 28 DS1 signals, 21 E1 signals, or 7 DS2 signals to/from a DS3 signal. I Operates in either M23 or C-bit parity mode. I Provisionable time slot selection for DS1, E1, and DS2 insertion or drop. I Full alarm monitoring and generation (LOS, BPV, EXZ, OOF , SEF , AIS, RAI, FEAC, P-bit and C-bit par- ity errors, FEBE). I HDLC transmitter with 128-byte data buffer and HDLC receiver with 128-byte data FIFO for the C-bit parity path maintenance data link. I DS3, DS2, DS1, and E1 loopback and loopback request generation. I Complies with T1.102, T1.107, T1.231, T1.403, T1.404, GR 499, G.747, and G.775.

1.7 DS3/DS2/DS1/E1 Cross Connect

I Highly configurable interconnect for up to 28 DS1 or

21 E1 signals to/from the framer, external pins, M13,

or VT mappers. I Supports up to seven DS2 signals to/from the exter- nal pins or M13. I Sources may be broadcast, looped back, or routed to/from a test-pattern generator or monitor. I Any DS1 or E1 channel may be routed through the jitter attenuator. I DS3 may be configured for the M13 to interconnect with the SPE, or external I/O to interconnect with the M13 or SPE.

1.8 Jitter Attenuation

I PLL-free receive operation using built-in digital jitter attenuator (in VT/VC mode or M13 mode). I Configurable to meet jitter and MTIE requirements.

1.9 PDH Interfaces

I One DS3, 7x DS2. I x28/x21 framed or unframed DS1 or E1 interfaces. I One additional dedicated protection channel for DS2/DS1/E1.

1.10 T1/E1/J1 Framing Features (x28/x21)

I x28/x21 T1/E1/J1 channels. I Line coding: B8ZS, HDB3, ZCS, AMI, and CMI (JJ20-11). I T1 framing modes: ESF , D4, SLC ® -96, T1 DM DDS, and SF (Ft only). I E1 framing: G.704 basic and CRC-4 multiframe con- sistent with G.706. I J1 framing modes: JESF (Japan). I Supports T1 and E1 unframed and transparent trans- mission format. I T1 signaling modes: transparent; register and system access for ESF 2-state, 4-state, and 16-state; D4 2-state, 4-state, and 16-state; SLC -96 2-state, 4-state, and 16-state; J-ESF han- dling groups maintenance and signaling; VT 1.5 SPE 2, 4, 16 state. I E1 signaling modes: transparent; register and system access for entire TS16 multi- frame structure as per ITU G.732. I Signaling debounce and change of state interrupt. I V5.2 Sa7 processing.

3Agere Systems Inc. Preliminary Data Sheet TMXF28155 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 I Alarm reporting and performance monitoring per AT&T, ANSI , ITU-T, and ETSI standards. I Facility data link features: — HDLC or transparent access for either ESF or DDS + FDL frame formats. — Register/stack access for SLC -96 transmit and re- ceive data. — Extended superframe (ESF): automatic transmis- sion of the ESF performance report messages (PRM). Automatic transmission of the ANSI T1.403 ESF performance report messages. Auto- matic detection and transmission of the ANSI T1.403 ESF FDL bit-oriented codes. — Register/stack access for all CEPT Sa-bits trans- mit and receive data. I HDLC features: — HDLC or transparent mode. — Programmable logical channel assignment: any time slot, any bit for ISDN D-channel, also inserts/ extracts C-channels for V5.1, V5.2 interfaces. — 64 logical channels in both transmit and receive di- rection (any framing format). — Maximum channel data rate: 64 kbits/s. — Minimum channel data rate: 4 kbits/s (DS1-FDL or E1 Sa bit). — 128-byte FIFO per channel in both transmit and re- ceive direction. — Tx to Rx loopback supported. I System interfaces: — Concentration highway interface: Single clock and frame sync signals; program mable clock rates at 2.048 MHz, 4.096 MHz, 8.192 MHz, and 16.384 MHz; programmable data rates at 2.048 Mbits/s, 4.096 Mbits/s, and 8.192 Mbits/s; programmable clock edges and bit/byte offsets. — Parallel system bus interface at 19.44 MHz for data and signaling: single clock and frame sync signals. — Time-division multiplex data rate serial interface at 1.544 MHz or 2.048 MHz. Twenty-eight receive data, clock, and frame sync signals. Twenty-eight transmit data signals with a global clock and frame sync. — Network serial multiplexed interface minimal pin count serial interface at 51.84 MHz optimized for data and IMA applications.

1.11 System Test and Maintenance

I A variety of loopback modes implemented on SONET/SDH side as well as on framer level. I Built-in test pattern generator and monitor config- urable for simultaneously testing E1, DS1, DS2, and DS3 (one channel each). Microprocessor Interface I 20-bit address and 16-bit data interface with 16 MHz to 66 MHz read and write access. I Compatible with most industry-standard processors. Chip Testing and Maintenance I IEEE * 1149.1 JTAG boundary scan. Interface to Other Agere ME Devices Seamless interface to the following Agere Systems’ devices: I TADM042G5. * IEEE is a registered trademark of the Institute of Electrical and Electronics Engineers, Inc.

4 Agere Systems Inc. TMXF28155 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 May 2001 Table of Contents By Major Sections Contents Page

2 Preface

6 Agere Systems Inc. TMXF28155 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 May 2001

2 Preface (continued)

The objective of this data sheet is to define the func- tionality of the Super Mapper for hardware and soft- ware developers. The information contained in this data sheet is preliminary, and may change without notice; the reader must therefore ascertain that the latest ver- sion is used when a product is under development. The latest version of this data sheet can be accessed at: http://www.lucent.com/micro/netcom/products/ pdh.html#super_mapper.

2.1 Major Categories

This data sheet is divided into six major categories with sub-sections as follows: I Features I Product Description — Features — Preface — Overview I Interface Specifications — Pin Information — Electrical Characteristics — Timing Characteristics — Ordering Information I Register Descriptions — Microprocessor Interface Registers — TMUX Registers — SPE Mapper Registers — VT/UT Mapper Registers — M13/M23 MUX/deMUX Registers — 28-Channel Framer Registers — Cross Connect (XC) Registers — Digital Jitter Attenuation Registers — Test Pattern Generation/Detection Registers I Functional Descriptions — Microprocessor Interface Description — TMUX Registers Description — SPE Mapper Registers Description — VT/UT Mapper Registers Description — M13/M23 MUX/deMUX Registers Description — 28-Channel Framer Registers Description — Cross Connect (XC) Registers Description — Digital Jitter Attenuation Registers Description — Test Pattern Generation/Detection Registers De- scription I Applications — Application Block Diagrams and Descriptions

2.2 Naming Convention for Registers and

There are many provisioning registers for controlling the Super Mapper. A naming convention for all regis- ters and parameters (bit names) is followed throughout this data sheet. A prefix is attached to the base name of each register or parameter, depending on which functional section the register or parameter is associ- ated with: I SMPR_, for the Microprocessor Interface I TMUX_, for the TMUX I SPE_, for the SPE Mapper I VT_, for the VT/VC Mapper I M13_, for the M13/M23 MUX/deMUX I FRM_, for the 28-Channel Framer I XC_, for the Cross Connect I DJA_, for the Digital Jitter Attenuator I TPG_ and TPM_, for the Test-Pattern Generator/ Detection A suffix is appended to the base name of three com- mon parameters: I _IS, for interrupt signal. I _IM, for interrupt mask. I _SWRS, for software reset.

2.3 Overview

signal directly or to allow for modular growth in terminal or add/drop applications. used for DS3/DS2 applications. Figure 1. Functional Diagram of Super Mapper

3 Pin Information

3 Pin Information (continued)

Figure 2. Pin Diagram of 456-Pin PBGA (Bottom View)

3.2 Pin Assignments

Table 1. Pin Assignments for 456-Pin PBGA by Pin Number Order

Table 1. Pin Assignments for 456-Pin PBGA by Pin Number Order (continued)

Table 2. Pin Assignments for 456-Pin PBGA by Signal Name

Table 2. Pin Assignments for 456-Pin PBGA by Signal Name (continued)

3.3 Pin Descriptions

3.3.1 High-speed I/O Pin Descriptions

optics device. If internal clock recovery is used, the Super Mapper uses THSCP/N as a reference. the high-speed I/O is determined by TMUX_RCV_TX_MODE. Table 3. High-speed I/O Pin Descriptions through a 1 kΩ resistor and the N input pulled low through a 1 kΩ resistor. unit or an higher order (e.g. STS-12) demultiplexing chip. LVDS I Transmit High-speed Clock. Transmit 155.52 MHz or 51.84 MHz clock. may be multiplexed into an STS-12 signal.

3.3.2 Protection Switch I/O Pin Description

Table 4. Protection Switch I/O Pin Description Figure 3. Protection Switch

3.3.3 Telecom Bus (Low-speed I/O) Pin Description

com bus can operate at 19.44 MHz (space for three STS-1 signals) or 6.48 MHz (space for 1 STS-1 signal). ured to operate at 19.44 MHz.

Table 5. Telecom Bus (Low-speed I/O) Pin Description Note: As outputs, these pins have 6 mA drive capability. bytes (1, 2 and 3) are present on RLSDATA(7:0) output bus. Connect to RLSV1 on the slaves.

Table 5. Telecom Bus (Low-speed I/O) Pin Description (continued) output on a master Super Mapper and an input on a slave. Note: As outputs, these pins have 6 mA drive capability. even parity generation or for checking. the STS-1 overhead is present on the TLSDATA(7:0) bus. An output from the master and input on the slaves. synchronous to the receive high-speed input clock (data). Note: As outputs, these pins have 6 mA drive capability. side frame sync input synchronous to a 51.84 MHz input.

3.3.4 TOAC and POAC

head bytes can be identified. port, or through the overhead access channels. TMUX SPE and VT m appers are not used. Table 6. TOAC and POAC clock output for the transport overhead bytes. data output for the transport overhead bytes. clock output for the transport overhead bytes. data input for the transport overhead bytes. clock output for the path overhead bytes. data output for the path overhead bytes.

3.3.5 Miscellaneous Signals

Table 7. Miscellaneous Signals

3.3.6 DS3 Port

will have considerable jitter introduced when the SONET overhead is removed and pointer adjustments are made. clock output for the path overhead bytes. data input for the path overhead bytes. polarity of LOS may be programmed active-high or low. Table 6. TOAC and POAC (continued)

Table 8. DS3 Port the VCXO output is slower than the reference signal. the VCXO output is faster that the reference signal. when the DS3 output port is operating in dual rail-mode. operating in single ended mode. external crystal oscillator, usually associated with a DS3 LIU. left unconnected, or tied to ground. the clock recovery in the external DS3 LIU.

Table 9. DS3 Port, C-Bit, and Datalink Access

3.3.7 M13 Multiplexer/Demultiplexer Receive Section

attenuation and AIS generation processes. Note that these are typically supplied by free-running crystal oscillators. The outputs below provide access to the received C-bits and data link bits extracted from the received DS3 frame. These operate in the same way if the source of the DS3 signal is from an SPE or from the external DS3 port. during the rising edge of TCBCLK that is used to input C2. accepting selected C-bits on input M13_CBDATA. transmit DS3 frame through this input. for accepting path maintenance data link C-bits on input TDLDA TA. transmit DS3 frame through this input. Table 10. M13 Multiplexer/Demultiplexer Receive Section unconnected, or tied to ground, if no E1 options are being used. C-bit parity mode does no require a DS2 reference clock. except during the rising edge of RCD that is used to output C2.

3.3.8 Low-Order Path Overhead Access Channel

the overhead, although that is possible too. Table 11. Low-Order Path Overhead Access Channel Figure 4. DS1/E1 to DXC Block Diagram putting selected C-bits on RCD. for outputting path maintenance data link C-bits on RDLD. AC13 LOPOHCLKIN — I Pull down 6.48 MHz Low Order Path Overhead Clock. AB14 LOPOHVALIDIN — I Pull down Valid LOPOH_DATA. AB15 LOPOHCLKOUT — O 6.48 MHz Low Order Path Overhead Clock. AB18 LOPOHVALIDOUT — O Valid VTMPR_LOPOH_DATA Output. Table 10. M13 Multiplexer/Demultiplexer Receive Section (continued)VT MAPPER VT MAPPER

Table 12. Multifunction System Interface Transmit Path Direction assigned to the M23 multiplexer inputs.

1.544 MHz clock from the TDM system clock (CHI

clock). This applies in PSB and CHI modes. 51.84 Mbits/s serial data input.

LINERXSYNC[28:1] — I Line Receive Synchronous 28:1. Multifunction input. bit wide bus that operates at 19.44 MHz. A13 LINERXSYNC29 — I/O Line Receive Synchronous 29. Multifunction input. when operating in dual-rail mode. Table 12. Multifunction System Interface Transmit Path Direction (continued)

3.3.9 Framer PLL

tem clock may be used as the line clock. Table 13. Framer PLL AD22 VDDD_PLL VDD — Digital VDD for PLL. AE23 VDDS_PLL VDD — Analog VDD for PLL. AF23 VSSA_PLL VSS — Analog VSS for PLL. AD23 VSSS_PLL VSS — Digital VSS for PLL. outputs is generated synchronous to this clock. factory testing as an output. PLL Mode 0. PLL control input 0.

51.84 MHz

26.624 MHz

19.44 MHz

16.348 MHz

8.194 MHz

4.096 MHz

2.048 MHz

Table 14. Microprocessor Interfaces clock must be within the range of 16 MHz— 66 MHz. interface is asynchronous, CPM should be set to 0. should be stable before DS is asserted. ation, or set low for write operation. after data is stable. For read operation, it is similar to AS. that use big-endian byte ordering. is the parity for D[15:8] and CPP[0] is the parity for D[7:0].

Table 15. General Purpose Interface reads. DTA goes high, along with the rising edge of AS. operations. TMS is sampled on the rising edge of TCK. reset for the TAP controller. output is high impedance, except when scanning out test data. Table 14. Microprocessor Interfaces (continued)

3.3.10 Test Pins

left unconnected; each is equipped with a pull-up or pull-down to the inactive (normal operation) state. Table 16. Test Pins Table 17. CDR Power Test Only. Scan enable (active-high). Test Only. Serial scan input for testing (active-high). Test Only. IDD Q input (active-high). with a test clock (active-high). 32 low-speed phases, generated by test logic (active-high). itive pulse > 20ns. Active + pulse. Test Only. Direction of phase changes. Test Only. Enables CDR test mode. Test Only. Enables CDR test mode shift register. AC9 VDDA_CDR — I Analog Power. Isolated analog power supply VDD for CDR. AB12 VSSA_CDR — I Analog Ground. Isolated analog power supply VSS for CDR. Table 18. LVDS Control Pins these two pins as a reference for the LVDS input buffer termination. AC11 REF10 — I Voltage Reference 1. 1.0 V reference voltage input. AD12 REF14 — I Voltage Reference 2. 1.4 V reference voltage input.

common mode rejection of the LVDS input buffers. common mode rejection of the LVDS input buffers. improve the common mode rejection of the LVDS input buffers. Table 18. LVDS Control Pins (continued)

32 Agere Systems Inc. TMXF28155 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 May 2001

3.4 Outline Diagram

3.4.1 456-Pin PBGA Dimensions are in millimeters. 5-6216(F)r.1 SEATING PLANE SOLDER BALL0.60 ± 0.10 0.20 PWB MOLD COMPOUND 35.00 ± 0.20 35.00 ± 0.20 +0.70 –0.0030.00 +0.70 –0.0030.00A1 BALL IDENTIFIER ZONE AF AE AD AC AB AA Y W V U T R G 25 SPACES @ 1.27 = 31.75 P N M L K J H 1 2 3 4 5 6 7 8 9 10 12 14 16 18 22 24 2620 11 13 15 17 21 19 23 25 F E D C B A CENTER ARRAY FOR THERMAL ENHANCEMENT (OPTIONAL)

25 SPACES

@ 1.27 = 31.75 A1 BALL CORNER 0.75 ± 0.15

4 Electrical Characteristics

4 Electrical Characteristics (continued)

4.1 Absolute Maximum Ratings

periods can adversely affect device reliability.

4.2 Handling Precautions

4.3 Operating Conditions

Table 21. Recommended Operating Conditions

• Internal reference voltage is used if SMPR_LVDS_REF_SEL = 1 (Table 70); or else external voltage is used.

Table 19. Absolute Maximum Ratings Table 20. Handling Precaution

4.4 Logic Interface Characteristics

Table 22. Logic Interface Characteristics The input specification for the remaining (nonbalanced) inputs are specified in Figure 5. Figure 5. Single-Ended Input Specification

4.5 LVDS Interface Characteristics

Table 23. LVDS Interface Characteristics

• Buffer will not produce output transition when input is open-circuited.

5 Timing Characteristics

5 Timing Characteristics (continued)

5.1 TMUX Block Timing

For definitions of the signal names, see the pin descriptions section at the beginning of this data sheet. Table 24. High-speed Input Clock Specifications Note: When the true and complement inputs are floating, the input buffer will not oscillate. Figure 6. Generic Clock Timing

The output clock specifications are shown in Table 25, where the symbols match the waveform diagram above. Table 25. Output Clock Specifications

• The specifications for the table are with all loopbacks disabled.

Table 26. Input Timing Specifications Figure 7. Generic Interface Data Timing

Table 27. Output Timing Specifications

• Propagation delay skew, tPLH – tPHL , is ±200 ps.

5.2 DS3 Timing

Table 28. DS3 Input Clock Specifications Table 29. Input Timing Specifications Table 30. Output Timing Specifications

44.736 MHz ±50 ppm —

5.3 M13 Timing

Table 31. M13 Clock Specifications Table 32. Input Timing Specifications Table 33. Output Timing Specifications

5.4 VT Mapper Timing

5.4.1 VT Mapper Lower-Order Path Overhead Interface Timing

Table 34. VT Mapper Receive Path Overhead Detailed Timing Figure 8. VT Mapper Transmit Path Overhead Detailed Timing Figure 9. VT Mapper Receive Path Overhead Detailed Timing

5.5 Concentration Highway (CHI) Timing

Table 35. CHI Transmit Timing Characteristics Figure 10. CHI Transmit I/O Timing

Table 36. CHI Receive Timing Characteristics Figure 11. CHI Receive I/O Timing

5.6 Parallel System Bus Timing

Table 37. PSB Interface Transmit Timing Characteristics

Figure 12. Parallel System Bus Interface Transmit I/O Timing Table 38. PSB Interface Receive Timing Characteristics Figure 13. Parallel System Bus Interface Receive I/O Timing

5.7 NSMI Timing Mode 1 (6 Pin)

Table 39. NSMI (Mode 1) Input Clock Specifications Table 40. Input Timing Specifications Table 41. Output Timing Specifications

5.8 SMI Timing Mode 2 (8 Pin)

Table 42. SMI (Mode 2) Input Clock Specifications

44.736 MHz ±50 ppm

Table 43. Input Timing Specifications Table 44. Output Timing Specifications

5.9 Framer Only Mode Timing

Table 45. Framer Only Mode Clock Specifications

Table 45. Framer Only Mode Clock Specifications (continued) Table 46. Framer Mode Only Input Timing Specifications Table 47. Framer Mode Only Output Timing Specifications

5.10 Framer—LIU Mode Timing

Table 48. Framer—LIU Mode Clock Specifications

Table 49. Framer—LIU Mode Input Timing Specifications Table 50. Framer—LIU Mode Output Timing Specifications

5.11 Microprocessor Interface Timing

5.11.1 Synchronous Mode

VT_RDY bit is set before VT_MAPPER reads/writes can occur. Figure 14. Microprocessor Interface Synchronous Write Cycle (MPMODE (Pin AD17) = 1)

MPCLK 16 MHz minimum to 66 MHz maximum frequency. ADDR [19:0] The address will be available throughout the entire cycle. DATA[15:0] Data will be available during cycle T1. RWN (Input) The read (H) write (L) signal is always high except during a write cycle. CSN (Input) Chip select is an active-low signal. ADSN (Input) Address strobe is active-low. ADSN must be 1 MPCLK clock period wide. Table 51. Microprocessor Interface Synchronous Write Cycle Specifications Figure 15. Microprocessor Interface Synchronous Read Cycle (MPMODE (Pin AD17) = 1)

MPCLK 16 MHz minimum to 66 MHz maximum frequency. DATA [15:0] Read data is stable in Tn –1. RWN (Input) The read (H) write (L) signal is always high during the read cycle. CSN (Input) Chip select is an active-low signal. using the input as feedback to qualify the 3-state term.) DT will become 3-stated when CS is high. Typically DTN is active 4 or 5 MPCLK cycles after ADSN is low. ADSN (Input) Address strobe is active-low. ADSN must be one MPCLK clock period wide. Table 52. Microprocessor Interface Synchronous Read Cycle Specifications

5.12 Asynchronous Mode

Table 54 (see pages 59— 60).

Figure 16. Microprocessor Interface Asynchronous Write Cycle Description (MPMODE (Pin AC18) = 0) able throughout the entire cycle. throughout the entire cycle. RWN (Input) The read (H) write (L) signal is always high except during a write cycle. CSN (Input) Chip select is an active-low signal. DTN (Output) Data transfer acknowledge (active-low). DTN is driven asynchronously based on the arrival of CSN. or DSN is deasserted. DTN will become 3-stated when CSN is high. ADSN (Input) Address strobe is active-low. ADSN must be a minimum of one MPCLK clock period wide. DSN (Input) Data strobe is active-low.

Table 53. Microprocessor Interface Asynchronous Write Cycle Specifications † Falling edges of ADSN and DSN determine falling edge of DTN. ‡ DTN fall is variable, depending on the block selected for access, and may be longer than the typical maximum specified. § Rising edge of ADSN determines rising edge of DTN.

Figure 17. Microprocessor Interface Asynchronous Read Cycle (MPMODE (Pin AC18) = 0) able throughout the entire cycle. the correct timing on the host bus. RWN (Input) The read (H) write (L) signal is always high during a read cycle. CSN (Input) Chip select is an active-low signal. ADSN (Input) Address strobe is active-low. DSN (Input) Data strobe is active-low.

Table 54. Microprocessor Interface Asynchronous Read Cycle Specifications 1 DSN can be asserted up to 20 ns (1 clk at 50 MHz) previous to CSN. 2 ADDR can be asserted up to 60 ns (3 clk at 50 MHz) into cycle from ASDN. 3 DTN fall is variable depending on the block selected for access and may be longer than typical maximum specified. 4 Leading edges of ADSN and DSN determine the falling edge of DTN. 5 Rising edge of ADSN determines the rising edge of DTN. 6 Data toggle 20 ns (1 clk at 50 MHz) previous to CSN.

5.13 General Purpose Interface Timing

Table 55. Input Timing Specifications

Table 56. Output Timing Specifications

• Propagation delay skew, tPLH – tPHL, is ±200 ps.

6 Ordering Information

7 Microprocessor Interface and Global Control and Status Registers

7 Microprocessor Interface and Global Control and Status Registers (continued)

7.1 Super Mapper Global Control and Status Registers

indicate if the register is read only (RO), clear-on-read/clear-on-write (COR/COW), or read/write (R/W). Table 57. SMPR_VCR, Super Mapper Version Control Register (RO) Table 58. SMPR_SYMR[4], Super Mapper Symbol Register4 SMPR (RO) Table 59. SMPR_SYMR[3], Super Mapper Symbol Register3 (RO) Table 60. SMPR_SYMR[2], Super Mapper Symbol Register2 (RO) register will change each time the device is changed. 7:0 SMPR_ID[7:0] SMPR ID Number. 7:0 M Super Mapper Symbol Bit. 7:0 F Super Mapper Symbol Bit. 7:0 8 Super Mapper Symbol Bit.

Table 61. SMPR_SYMR[1], Super Mapper Symbol Register1 (RO) Table 62. SMPR_SYMR[0], Super Mapper Symbol Register0 (RO) Table 63. SMPR_ISR, Super Mapper Interrupt Status Register (RO) 7:0 5 Super Mapper Symbol Bit. 7:0 CR Super Mapper Symbol Bit. which is within the TMUX block. 9S M P R _ P A R I T Y _ I SMicroprocessor Interface Data Bus Parity Error Interrupt. indicating a 1 second event has occurred. has occurred in the test pattern generation block. has occurred in the digital jitter attenuation block. I Power down the framer block in address 0x00012. has occurred in the cross connect block. has occurred in the M13 multiplexer/demultiplexer block. event has occurred in the VT mapper block. event has occurred in the SPE mapper block. event has occurred in the TMUX block.

Table 64. SMPR_IMR, Super Mapper Interrupt Mask Register (RW)

9 SMPR_PARITY_IM Microprocessor Interface Data Bus Parity Error Interrupt

be inhibited from contributing to the interrupt pin INTN. contributing to the interrupt pin INTN.

Table 65. SMPR_GTR, Global Trigger Register (RW) Table 66. SMPR_MSRR, Block Software Reset Register (RW) has to be inserted in the appropriate frame. create a software reset for the test-pattern generation macro. path state machine within the block are also reset. create a software reset for the digital jitter attenuation block. path state machine within the block are also reset. within the block are also reset.

Table 66. SMPR_MSRR, Block Software Reset Register (RW) (continued) state machine within the block are also reset. ware reset and chip-level software reset. within the block are also reset. to 1, it will create a software reset for the SPEMPR block. data path state machine within the block are also reset. state machine within the block are also reset.

Table 67. SMPR_GCR, Global Control Register (RW) 00 = PMRST comes from external pin. 10 = PMRST comes from external pin. 01 = PMRST comes from internal 1 second counter. Note: Please see Ta ble 72 and Table 73.

4 SMPR_P ARITY_EVEN_ODD Even or Odd Parity Indication on the Microproces-

0 = Even parity on microprocessor byte data/parity bus. 1 = Odd parity on microprocessor byte data/parity bus. 0 = Filling the unused overhead bits with 0. 1 = Filling the unused overhead bits with 1. 0 = Filling the fixed stuff bytes with 0. 1 = Filling the fixed stuff bytes with 1. 0 = The delta and event bit is cleared by writing a 1 to it. to all registers in the 28-channel framer block. transmit FDL link register 8 (address 0x8LTD7). cessor read is performed on this delta and event bit.

Table 68. SMPR_TSCR, TMUX, and SPEMPR Control Register (RW) Table 69. SMPR_FCR, Framer Control Register (RW)

3 MPU_RHDZTHD_LB Forces Received High-speed to Transmit High-

speed Data Loopback Prior to the CDR.

2 SMPR_RETIME_CLK_EDGE Retime Clock Edge for the Received High-speed

0 = Clock telecom bus signals out on the falling edge. 1 = Clock telecom bus signals out on the rising edge. is on, or if it is a slave device. 000 = Framer is powered down. No clock required. 010 = Framer receives DS1XCLK (pin AD16) clock input. 011 = Framer receives E1XCLK (pin AC17) clock input.

Table 70. SMPR_CLCR, CDR, and LVDS Control Register (RW) the internal framer PLL is powered on or off. 0 = Internal PLL powered on. 1 = Internal PLL powered off. 0 = External reference voltage is used. 1 = Internal reference voltage is used. 0 = Channel is active, power is on. 1 = Channel is inactive, power to the channel is turned off. the power to the CDR PLL circuit. 0 = PLL is active, power to the PLL is turned on. 1 = PLL is inactive, power to the PLL is turned off. CDR block or from the pins (bypass the CDR). 1 = Use CDR. Receives clock and data through CDR.

Table 71. SMPR_CPCR, Clock and Power Control Register (RW) Table 72. SMPR_PMRCHR, PM Reset Count High Register (RW) 8 SMPR_M13_TCLK M13 MUX/Tx Clock Enable. 0 = M13 MUX/Tx clock is powered down and inactive. 1 = M13 MUX/Tx clock is powered up and active. 7 SMPR_M13_RCLK M13 DeMUX Rx Clock Enable. 0 = M13 deMUX/Rx clock is powered down and inactive. 1 = M13 deMUX/Rx clock is powered up and active. 6 SMPR_DJA_CLK Digital Jitter Attenuation Clock Enable. 0 = DJA DPLL is powered down and inactive. 1 = DJA DPLL is powered up and active. 5 SMPR_VTMPR_TCLK VT Mapper Tx Clock Enable. 0 = VT mapper Tx clock is powered down and inactive. 1 = VT mapper Tx clock is powered up and active. 4 SMPR_VTMPR_RCLK VT Mapper Rx Clock Enable. 0 = VT mapper Rx clock is powered and inactive. 1 = VT mapper Rx clock is powered up and active. 3 SMPR_SPEMPR_TCLK SPE Mapper Tx Clock Enable. 0 = SPE mapper Tx clock is powered down and inactive. 1 = SPE mapper Tx clock is powered up and active. 2 SMPR_SPEMPR_RCLK SPE Mapper Rx Clock Enable. 0 = SPE mapper Rx clock is powered down and inactive. 1 = SPE mapper Rx clock is powered up and active. 1 SMPR_TMUX_TCLK TMUX Tx Clock Enable. 0 = TMUX Tx clock is powered down and inactive. 1 = TMUX Tx clock is powered up and active. 0 SMPR_TMUX_RCLK TMUX Rx Clock Enable. 0 = TMUX Rx clock is powered down and inactive. 1 = TMUX Rx clock is powered up and active. order to reach the desired PMRST rate.

Table 73. SMPR_PMRCLR, PM Reset Count Low Register (RW) Table 74. SMPR_SR, Scratch Register (RW) Table 75. SMPR_TX_LINE_EN1 0x00017 15:0 SMPR_PMRESET_LOW_COUNT[15:0] Performance Monitor Counter Preset. the frequency of the internal PM counter.

7.2 Microprocessor Interface Register Map

Table 76. Microprocessor Interface Register Map

Table 76. Microprocessor Interface Register Map (continued)

8 TMUX Registers

8 TMUX Registers (continued)

8.1 TMUX Register Descriptions

ter indicate if the register is read only (RO), clear-on-read/clear-on-write (COR/COW), or read/write (R/W). Table 77. TMUX_ID_R, TMUX Identification Register (RO) Table 78. TMUX_ONESHOT, TMUX One-Shot Register 0 to 1 (R/W) Table 79. TMUX_RCV_TX_MODE, TMUX Receive/Transmit Mode (R/W) change each time the device is changed. to be forced into the normal state. to be forced into the failed state. degrade algorithm to be forced into the normal state. algorithm to be forced into the degraded state. be forced into the normal state. forced into the failed state. algorithm to be forced into the normal state. algorithm to be forced into the degraded state.

Table 80. TMUX_TX_DLT, Delta/Event (COR/COW) Table 81. TMUX_RPS_DLT, Delta/Event (COR/COW) are TMUX_TLSPARM[3:1] (Table 84). channel. The mask bit is TMUX_TPOAC_PM (Table 84). bit is TMUX_THSILOCM (Table 84). (Table 90). The mask bit is TMUX_RPSLOFM (Table 85). (Table 90). The mask bit is TMUX_RPSOOFM (Ta ble 85). input. The mask bit is TMUX_RPSB2M (Table 85).

Table 82. TMUX_RHS_DLT, Delta/Event (COR/COW) occurring. The mask bit is TMUX_RS1BABM (Table 86). value in the S1 byte. The mask bit is TMUX_RS1MONM.

Table 82. TMUX_RHS_DLT, Delta/Event (COR/COW) (continued) mask bit is TMUX_RF1MONM (Table 86). 5 TMUX_RHSSFD Receive High-speed Signal Fail BER Algorithm Delta. mask bit for this delta bit is TMUX_RHSSFM (Table 86).

4 TMUX_RHSSDD Receive High-speed Signal Degrade BER Algorithm

(Ta ble 91). The mask bit is TMUX_RHSSDM (Table 86). (Ta ble 91) or TMUX_RHSLOSEXTI (Table 91). data input. The mask bit is TMUX_RHSLOSM (Table 86). (Ta ble 91). The mask bit is TMUX_RHSLOFM (Table 86). (Ta ble 91). The mask bit is TMUX_RHSOOFM (Table 86).

Table 83. TMUX_RPOH[1— 3]_DLT, Delta/Event (COR/COW) STS-1 mode. The mask bit is TMUX_RSFB3M1 (Table 87). port 1 information is valid in AU-4 mode and in STS-1 mode. The mask bit is TMUX_RPLMPM1 (Table 87). mask bit is TMUX_RF3MONM1 (Table 87).

Table 83. TMUX_RPOH[1— 3]_DLT, Delta/Event (COR/COW) (continued) mask bit is TMUX_RF2MONM1 (Table 87).

7 TMUX_RRDIPD1 Receive Path RDI (Remote Defect Indication) Monitor

mask bit is TMUX_RRDIPM1 (Table 87). mask bit is TMUX_RC2MONM1 (Table 87). mask bit is TMUX_RNDFM1 (Ta ble 87).

mode. The mask bit is TMUX_RLOPM1 (Ta ble 87). STS-1 mode. The mask bit is TMUX_RSFB3M2 (Table 87). and in STS-1 mode. The mask bit is TMUX_RHSSDB3M2. mode.The mask bit is TMUX_RPLMPM2 (Table 87).

7 TMUX_RRDIPD2 Receive Path RDI (Remote Defect Indication) Monitor Delta. STS-1 mode. The mask bit is TMUX_RTIMPM2 (Table 87). ignored during loss-of-pointer (LOP) condition.

mode. The mask bit is TMUX_RLOPM2 (Ta ble 87). STS-1 mode. The mask bit is TMUX_RSFB3M3 (Table 87). port 1 information is valid in AU-4 mode and in STS-1 mode. The mask bit is TMUX_RPLMPM3 (Table 87).

STS-1 mode. The mask bit is TMUX_RK3MONM3 (Tabl e 8 7). mask bit is TMUX_RF3MONM3 (Table 87). mask bit is TMUX_RF2MONM3 (Table 87).

7 TMUX_RDIPD3 Receive Path RDI (Remote Defect Indication) Monitor

STS-1 mode. The mask bit is TMUX_RTIMPM3 (Table 87).

change in state has taken place. Table 84. TMUX_TX_MSK, Mask Bits for INT Interrupt Signal (R/W) (Mask = 1, No Mask = 0) STS-1 mode. The mask bit is TMUX_RDECM3 (Table 87). STS-1 mode. The mask bit is TMUX_RINCM3 (Ta ble 87). STS-1 mode. The mask bit is TMUX_RPAISM3 (Table 87). mask bit is TMUX_RLOPM3 (Ta ble 87). ber). See Table 80 for description. ity Error Mask. See Table 80 for description. Parity Error Mask. See Table 80 for description.

change in state has taken place. Table 85. TMUX_RPS_MSK, Mask Bits for INT Interrupt Signal (R/W) (Mask = 1, No Mask = 0) change in state has taken place. Table 86. TMUX_RHS_MSK, Mask Bits for INT Interrupt Signal (R/W) (Mask = 1, No Mask = 0) 3 TMUX_RPSILOCM Receive Protection High-speed Loss of Input Clock Mask. See Table 81 for description. 5 TMUX_RHSSFM Receive High-speed Signal Fail BER Algorithm Mask. See Ta ble 82 for description.

4 TMUX_RHSSDM Receive High-speed Signal Degrade BER Algorithm

Mask. See Table 82 for description.

change in state has taken place. Table 87. TMUX_RPOH[1— 3]_MSK, Mask Bits for Interrupt Signal (R/W) (Mask = 1, No Mask = 0) 7 TMUX_RRDIPM1 Receive Path RDI (Remote Defect Indication) Monitor Mask. See Table 83 for description. 7 TMUX_RRDIPM2 Receive Path RDI (Remote Defect Indication) Monitor Mask. See Table 83 for description.

change in state has taken place. Table 87. TMUX_RPOH[1 — 3]_MSK, Mask Bits for Interrupt Signal (R/W) (Mask = 1, No Mask = 0) (continued)

7 TMUX_RRDIPM3 Receive Path RDI (Remote Defect Indication) Monitor

Mask. See Table 83 for description.

change in state has taken place. Table 88. TMUX_APSINT_MSK, Mask Bits for APSINT Interrupt Signal (R/W) (Mask = 1, No Mask = 0) Note: When state bits are set in Table 89, the corresponding function has occurred. Table 89. TMUX_TX_STATE, State Parameters (RO) Note: When state bits are set in Table 90, the corresponding function has occurred. Table 90. TMUX_RPS_STATE, State and Value Parameters (RO)

7 TMUX_RHSSF_APSM Receive High-speed Signal Fail BER Algorithm

APSINT Mask. See Table 82 for description.

6 TMUX_RHSSD_APSM Receive High-speed Signal Degrade BER Algo-

rithm APSINT Mask. See Table 82 for description. 3 TMUX_RHSLOS_APSM Receive High-speed Loss of Signal APSINT Mask. See Table 82 for description. 2 TMUX_RHSLOF_APSM Receive High-speed Loss of Frame APSINT Mask. See Table 82 for description. 1 TMUX_RHSOOF_APSM Receive High-speed Out of Frame APSINT Mask. See Table 82 for description.

0 TMUX_RHSILOC_APSM Receive High-speed Loss of Input Clock APSINT

Mask. See Table 82 for description. 3 TMUX_RPSILOC Receive Protection High-speed Loss of Input Clock State. See Ta ble 81 for description.

Note: When state bits are set in Table 91, the corresponding function has occurred. Table 91. TMUX_RHS_STATE, State and Value Parameters (RO) Note: When state bits are set in Table 92, the corresponding function has occurred. 5 TMUX_RHSSF Receive High-speed Signal Fail BER Algorithm State. See Table 82 for description.

4 TMUX_RHSSD Receive High-speed Signal Degrade BER Algorithm

State. See Table 82 for description. Table 92. TMUX_RPOH[1— 3]_STATE, State and Value Parameters (RO ) 0x40015 15 TMUX_RSFB31 Receive Path Signal Fail BER Algorithm State. See Ta ble 83 for description.

14 TMUX_RSDB31 Receive Path Signal Degrade BER Algorithm

State. See Table 83 for description. 12 TMUX_RPLMP1 Receive Path Payload Label Mismatch State. See Ta ble 83 for description. 5 TMUX_RTIMP1 Receive Path Trace Identifier Mismatch State. See Ta ble 83 for description.

0x40016 15 TMUX_RSFB32 Receive Path Signal Fail BER Algorithm State. See Table 83 for description.

14 TMUX_RSDB32 Receive Path Signal Degrade BER Algorithm

State. See Ta ble 83 for description. 12 TMUX_RPLMP2 Receive Path Payload Label Mismatch State. See Table 83 for description. 5 TMUX_RTIMP2 Receive Path Trace Identifier Mismatch State. See Table 83 for description. 3:2 TMUX_CONCA T_STATE2[1:0] Concatenation Pointer State Machine State. 0x40017 15 TMUX_RSFB33 Receive Path Signal Fail BER Algorithm State. See Table 83 for description.

14 TMUX_RSDB33 Receive Path Signal Degrade BER Algorithm

State. See Ta ble 83 for description. 12 TMUX_RPLMP3 Receive Path Payload Label Mismatch State. See Table 83 for description. 5 TMUX_RTIMP3 Receive Path Trace Identifier Mismatch State. See Table 83 for description. 3:2 TMUX_CONCA T_STATE3[1:0] Concatenation Pointer State Machine State. Table 92. TMUX_RPOH[1— 3]_STATE, State and Value Parameters (RO) (continued)

Table 93. TMUX_RHS_CTL, Receive High-speed Control Parameters (R/W) 3 TMUX_LOSEXT_LEVEL Controls External LOSEXT Polarity. 0 = active-low. 1 = active-high.

1 TMUX_THS2RHSLB Transmit High-speed to Receive High-speed

input; otherwise, the loopback is disabled. otherwise, the signal is not descrambled. Table 94. TMUX_RLS_BITBLK_CTL, Receive Low-speed Control Parameters (R/W) 8:7 TMUX_RCV_SS_EXP[1:0] Expected Receive Pointer Size Bits Value. Expected value of incoming pointer SS bits. or the received pointer value will be invalid. errors (a block equals one frame). errors (a block equals one frame). errors (a block equals one frame). errors (a block equals one frame). errors (a block equals one frame).

Table 95. TMUX_RLS_MODE_CTL, Receive Low-speed Control Parameters (R/W) (pins AC6, AE6, and AD6) (Table 3) outputs. ment or decrement based on majority vote only. 11 TMUX_SDB1B2SEL Receive Signal Degrade Algorithm Input Selection. wise, the B1 error count is used. defined in J1 monitor on page 377. defined in Section 17.5.5 J0 Monitor on page 370. 2 TMUX_RLSPAROEG Receive Low-speed Parity Odd or Even Generation. bit to be even; otherwise, the parity is odd. path RDI; otherwise, a 1-bit value (G1[3]) is monitored.

Table 96. TMUX_RAISINH_CTL, Receive Low-speed Control Parameters (R/W) responding AUTO_AIS output signal. 8 TMUX_RPLMP_AISINH Receive Path Payload Label Mismatch AIS Inhibit. the corresponding AUTO_AIS output signal. outputs as well as the assertion of AUTO_AIS outputs. as well as the assertion of AUTO_AIS outputs. as the assertion of AUTO_AIS outputs.

Table 96. TMUX_RAISINH_CTL, Receive Low-speed Control Parameters (R/W) (continued) Table 97. TMUX_LOSDETCNT, Receive Low-speed Control Parameters (R/W) 2 TMUX_ROOF_AISINH Receive High-speed Out-of-Frame AIS Inhibit. 1 TMUX_RHSLOS_AISINH Receive High-speed Loss-of-Signal AIS Inhibit. all AUTO_AIS output signals. (STS Signal Label Defect Conditions). while a value of 0x798 equals 100 µs.

Table 98. TMUX_CNTD_TOH_[A — B], Continuous N-Times Detect Control Parameters (R/W) value in the incoming STS-3/STM-1 (AU-4) frame. values will be mapped to a value of 0x3. value in the incoming STS-3/STM-1 (AU-4) frame. values will be mapped to a value of 0x3. 11:8 TMUX_CNTDS1FRAME[3:0] Continuous N-Times Detect for S1 Frame Bytes. value in the incoming STS-3/STM-1 (AU-4) frame. values will be mapped to a value of 0x3. 3:0 TMUX_CNTDK2[3:0] Continuous N-Times Detect for K2[2:0] Byte.

Table 99. TMUX_CNTD_POH_[A — B], Continuous N-Times Detect Control Parameters (R/W) be mapped to a value of 0x3. reset whenever the AUTO_AIS signal is asserted.

Table 100. TMUX_C2EXP[1— 2_3], Continuous N-Times Detect Control Parameters (R/W) Table 101. TMUX_RF1MON, Receive Monitor Values (RO) Table 102. TMUX_RAPSMON, Receive Monitor Values (RO) Table 103. TMUX_RS1MON, Receive Monitor Values (RO) contain expected signal label (C2) for port 1. contain expected signal label (C2) for port 3. contain expected signal label (C2) for port 2. matic Protection Switch (APS) Monitor on page 371. Protection Switch (APS) Monitor on page 371.

Table 104. TMUX_RPOHMON[1 — 3][A— D], Receive Monitor Values (RO) C2 Byte Monitor on page 378. Path User Byte F2 Monitor on page 380. User Byte F2 Monitor on page 380. Path User Byte F3 Monitor on page 380. User Byte F3 Monitor on page 380. C2 Byte Monitor on page 378. Path User Byte F2 Monitor on page 380. User Byte F2 Monitor on page 380. Path User Byte F3 Monitor on page 380. User Byte F3 Monitor on page 380. C2 Byte Monitor on page 378. Path User Byte F2 Monitor on page 380. User Byte F2 Monitor on page 380.

Table 104. TMUX_RPOHMON[1 — 3][A— D], Receive Monitor Values (RO) (continued) Table 105. TMUX_TLS_CTL, Transmit Low-speed Control Parameters (R/W) Path User Byte F3 Monitor on page 380. User Byte F3 Monitor on page 380. 6:4 TMUX_TLS_UNEQP[3:1] Transmit Low-speed Unequipped Insert Control. TMUX_TLS_UNEQP1 is used in AU-4 mode. wise, even parity is verified.

Table 106. TMUX_THS_PORT_CTL, Transmit High-speed Port Control Parameters (R/W) Table 107. TMUX_THS_TOH_CTL, Transmit High-speed Control Parameters (R/W) out the THSDP/N (pins AF9, AE9) output.

1 TMUX_RHS2THSLB Receive High-speed to Transmit High-speed Loopback

independent STS-1s (for a 155 MHz signal).

11 TMUX_TPREIRDISEL Transmit MUX Selection Control for Outgoing Path

receive side of the same TMUX.

10 TMUX_TLREIRDISEL Transmit MUX Selection Control for Outgoing Line

receive side of the same TMUX. going pointer value (but not in the concatenation values).

Table 107. TMUX_THS_TOH_CTL, Transmit High-speed Control Parameters (R/W) (continued) STS-3/STM-1 (AU-4) signal; otherwise, line AIS is not sent. on SMPR_OH_DEFLT ( Table 67). logic 0 inserts the default value based on SMPR_OH_D EFLT. allows insertion from the TTOAC channel or a default value. logic 0 inserts the default value based on SMPR_OH_D EFLT. logic 0 inserts the default value based on SMPR_OH_D EFLT.

Table 108. TMUX_THS_POH[1 — 3]_CTL, Transmit High-Speed Control Parameters (R/W)

7 TMUX_TPOHTHRU1 Transmit High-speed Path Overhead Insertion from Low-

speed output signal. Only port 1 control is valid in AU-4 mode. control is valid in AU-4 mode.

Table 108. TMUX_THS_POH[1 — 3]_CTL, Transmit High-Speed Control Parameters (R/W) (continued)

7 TMUX_TPOHTHRU2 Transmit High-speed Path Overhead Insertion from Low-

control is valid in AU-4 mode.

7 TMUX_TPOHTHRU3 Transmit High-speed Path Overhead Insertion from Low-

allows insertion from the TPOAC channel or a default value. Only port 1 control is valid in AU-4 mode.

Table 109. TMUX_TLRDI_CTL, Transmit High-Speed Line RDI Control Parameters (R/W) Table 110. TMUX_TPRDI_CTL, Transmit High-Speed Path RDI Control Parameters (R/W)

6 TMUX_TRHSSD_LRDIINH Transmit Receive High-speed Signal

alarm contributes to the generation of RDI-L.

5 TMUX_TRHSSF_LRDIINH Transmit Receive High-speed Signal Fail

utes to the generation of RDI-L.

4 TMUX_TRLAISMON_LRDIINH Transmit Receive Line AIS Line RDI

3 TMUX_TRHSLOF_LRDIINH Transmit Receive High-speed Loss-of-

Frame Line RDI Inhibit. Same as above.

2 TMUX_TRHSOOF_LRDIINH Transmit Receive High-speed Out-of-

Frame Line RDI Inhibit. Same as above.

1 TMUX_TRHSLOS_LRDIINH Transmit Receive High-speed Loss-of-

Signal Line RDI Inhibit. Same as above.

0 TMUX_TRILOC_LRDIINH Transmit Receive Input Loss-of-Clock

Line RDI Inhibit. Same as above. 4 TMUX_TRUEQ_PRDIINH Transmit Receive Unequipped Path RDI Inhibit. associated alarm contributes to the generation of RDI- P.

3 TMUX_TRPLM_PRDIINH Transmit Receive Payload Label Mismatch Path RDI

ated alarm contributes to the generation of RDI -P. G1[3:1]; otherwise, a one-bit value (G1[3]) is sent.

Table 111. TMUX_TZ0_INS_VAL, Transmit TOH and POH Insert Values (R/W) Table 112. TMUX_TS1_F1_INS_VAL, Transmit TOH and POH Insert Values (R/W) Table 113. TMUX_TAPS_INS_VAL, Transmit TOH and POH Insert Values (R/W) if TMUX_THSZ0INS (Table 107) is asserted. if TMUX_THSZ0INS is asserted. TMUX_THSS1INS ( Table 107) is asserted. TMUX_THSF1INS ( Table 107) is asserted. K2[7:3] bits if TMUX_THSAPSINS (Table 107) is asserted. TMUX_THSK2INS ( Table 107) is asserted. Table 114. TMUX_TPOH[1— 3]_INS_[A— C], Transmit TOH and POH Insert Values (R/W) TMUX_THSC2INS1 ( Table 108) is asserted. TMUX_THSF3INS1 ( Table 108) is asserted. TMUX_THSF2INS1 ( Table 108) is asserted.

TMUX_THSN1INS1 ( Table 108) is asserted. TMUX_THSK3INS1 ( Table 108) is asserted. TMUX_THSN1INS1 ( Table 108) is asserted. TMUX_THSK3INS1 ( Table 108) is asserted. TMUX_THSC2INS1 ( Table 108) is asserted. TMUX_THSF3INS1 ( Table 108) is asserted. TMUX_THSF2INS1 ( Table 108) is asserted. Table 114. TMUX_TPOH[1— 3]_INS_[A— C], Transmit TOH and POH Insert Values (R/W) (continued)

Table 115. TMUX_TBERINS_CTL, Transmit High-Speed Error Insertion Control Parameters (R/W) SMPR_BER_INSRT ( Ta ble 65) input signal. SMPR_BER_INSRT ( Ta ble 65) input signal. port 1 control is valid in AU-4 mode. SMPR_BER_INSRT (Table 65) input signal. SMPR_BER_INSRT (Table 65) input signal. SMPR_BER_INSRT (Table 65) input signal.

Table 116. TMUX_THS_ERR_CTL, Transmit High-Speed Error Insertion Control Parameters (R/W) into the outgoing STS-3/STM-1 (AU-4) frame. mode, only control bit 1 is used. Table 117. TMUX_TOAC_CTL, Receive/Transmit TOAC/POAC Control Parameters (R/W ) receive TOAC channel is in full access mode. receive TOAC channel is in full access mode. otherwise, the parity is odd. 9 TMUX_TTOAC_D412MODE Transmit TOAC DCC4 to DCC12 Only Mode.

0x4004A 8 TMUX_TTOAC_D13MODE Transmit TOAC DCC1 to DCC3 Only Mode. wise, the E1 value depends on SMPR_OH_DEFLT. wise, the E1 value depends on SMPR_OH_DEFLT. Table 117. TMUX_TOAC_CTL, Receive/Transmit TOAC/POAC Control Parameters (R/W) (continued)

Table 118. TMUX_RPOAC_CTL, Receive/Transmit TOAC/POAC Control Parameters (R/W) designates STS-1 #2, 11 designates STS-1 #3. designates STS-1 #2, 11 designates STS-1 #3. TMUX_THSN1INS ( Table 108) control bit is desasserted. TMUX_THSK3INS ( Table 108) control bit is desasserted.

Table 118. TMUX_RPOAC_CTL, Receive/Transmit TOAC/POAC Control Parameters (R/W) (continued) Table 119. TMUX_TFRAMEOFFSET, Transmit High-Speed Offset Control Parameters (R/W) is checked on the transmit TOAC channel. the input frame sync pulse (THSSJ0J1V1I). Table 120. TMUX_SD_CTL[1— 6], B1/B2 Signal Degrade Set/Clear Control Registers (R/W) monitoring block for signal degrade (SD). if a monitoring block is bad.

Table 121. TMUX_SF_CTL[1— 6], B1/B2 Signal Fail Set/Clear Control Registers (R/W) determining if a monitoring block is bad. Table 122. TMUX_B3SD_CTL[1 — 6], B3 Signal Degrade Set/Clear Control Registers (R/W) monitoring block for signal degrade (SD). determining if a monitoring block is bad. Table 120. TMUX_SD_CTL[1— 6], B1/B2 Signal Degrade Set/Clear Control Registers (R/W) (continued)

Table 123. TMUX_B3SF_CTL[1— 6], B3 Signal Fail Set/Clear Control Registers (R/W) Table 124. TMUX_B1ECNT, Receive B1 Error Counts (RO) threshold, then SD is cleared. determining if a monitoring block is bad. determining if a monitoring block is bad. determining if a monitoring block is bad. of B1 errors in the received STS-3/STM-1 (AU-4) frame. SMPR_PMRESET ( Table 65) transitions from a logic 0 to 1. Table 122. TMUX_B3SD_CTL[1 — 6], B3 Signal Degrade Set/Clear Control Registers (R/W) (continued)

Table 125. TMUX_B2ECNT_17_16 and TMUX_B2ECNT_15_0, Receive B2 Error Counts (RO) Table 126. TMUX_B3ECNT[1 — 3], Receive B3 Error Counts (RO) transitions from a logic 0 to 1. SMPR_PMRESET ( Table 65) transitions from a logic 0 to 1. transitions from a logic 0 to 1. transitions from a logic 0 to 1.

Table 127. TMUX_M1ECNT_17_16 and TMUX_M1ECNT _15_0, Receive M1 Error Counts (RO) Table 128. TMUX_G1ECNT[1 — 3], Receive G1 Error Counts (RO) SMPR_PMRESET transitions from a logic 0 to 1. (Tabl e 6 5) transitions from a logic 0 to 1.

Table 129. TMUX_RPTR_INCCNT[1 — 3], Receive Pointer Increment Count (RO) Table 130. TMUX_RPTR_DECCNT[1 — 3], Receive Pointer Decrement Count (RO) Table 131. TMUX_RJ0EXPECTED[1 — 8], Expected J0 Byte Sequence (R/W) Table 132. TMUX_RJ0CAPTURED[1 — 8], Captured J0 Receive Value (RO) Table 133. TMUX_TJ0VALUE[1— 8], J0 Byte Transmit Insert (R/W) transitions from a logic 0 to 1. sequence, depending on the J0 mode. sequence from the J0 byte of the receive input signal. STS-3/STM-1(AU-4) output signal.

Table 134. TMUX_RJ1EXPECTED1_[1 — 32], Expected J1 Byte Value for Port 1 (R/W) Table 135. TMUX_RJ1EXPECTED2_[1 — 32], Expected J1 Byte Value for Port 2 (R/W) Table 136. TMUX_RJ1EXPECTED3_[1 — 32], Expected J1 Byte Value for Port 3 (R/W) Table 137. TMUX_RJ1CAPTURED1_[1 — 32], Captured J1 Value for STS #1 (RO) Table 138. TMUX_RJ1CAPTURED2_[1 — 32], Captured J1 Value for STS #2 (RO) 15:0 TMUX_EXPJ1DMON1[64 — 1][7:0]Expected Receive J1 Value for Port 1. 1, J1 byte of the STS-3/STM-1 (AU-4) input signal. Only port 1 information is valid in AU-4 mode. information is valid in AU-4 mode.

Table 139. TMUX_RJ1CAPTURED3_[1 — 32], Captured J1 Value for STS #3 (RO) Table 140. TMUX_TJ1VALUE_1[1— 32], J1 Byte Transmit Insert for STS #1 (R/W) Table 141. TMUX_TJ1VALUE_2[1— 32], J1 Byte Transmit Insert for STS #2 (R/W) Table 142. TMUX_TJ1VALUE_3[1— 32], J1 Byte Transmit Insert for STS #3 (R/W) byte of the STS-3/STM-1 (AU-4) input signal. Only port 1 information is valid in AU-4 mode. port 1 information is valid in AU-4 mode. J1 byte of the STS-3/STM-1(AU-4) output signal. Only port 1 information is valid in AU-4 mode.

8.2 TMUX Register Map

Table 143. TMUX Register Map Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.

Table 143. TMUX Register Map (continued) Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.

Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.

Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.

Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.

Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.

Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.

Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.

Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.

9 SPE Mapper Registers

Table 158. SPE_SIGDEG_CTL1 — SPE_SIGDEG_CTL6, Si gnal Degrade BER Algorithm Parameters (R/W) .. 146 Table 160. SPE_ERRCNT1 — SPE_ERRCNT6, B3, G1, Bipolar Violation, and Excess

9 SPE Mapper Registers (continued)

9.1 SPE Mapper Register Descriptions

indicate if the register is read only (RO), clear-on-read/clear-on-write (COR/COW), or read/write (R/W). Table 144. SPE_VERSION_R, SPE Version and Identification Register (RO) Table 145. SPE_ONESHOT, One-Shot (R/W) monitor values are in Table 152. each time the device is changed. to be forced into the normal state. be forced into the degraded state. Table 146. SPE_EVENT1— SPE_EVENT3, SPE Deltas/Events (COR/COW) error was detected on the incoming data. error was detected on the incoming POAC.

cations should be ignored during LOP condition. tions should be ignored during LOP condition. when read. The mask bit is SPE_SFB3M. bit clears when read. The mask bit is SPE_SDB3M. 1 SPE_RPLMD Delta Bit for the Payload Label Mismatch Alarm State Bit. Table 146. SPE_EVENT1 — SPE_EVENT3, SPE Deltas/Events (COR/COW) (continued)

Table 147. SPE_MASK1— SPE_MASK3, Mask Bits (R/W) 2 SPE_C2DMONM 1 C2 Data Monitor Mask Bit. Active-high. 1 SPE_F2DMONM 1 F2 Data Monitor Mask Bit. Active-high. 1 SPE_RPLMM Mask Bit for the Payload Label Mismatch Alarm State Bit. 14 SPE_RSY52LOSM Mask Bit for Loss of Sync 52 Signal from Telecom Bus. 13 SPE_RV1LOSM Mask Bit for Loss of V1 Sync Signal from Telecom Bus. 12 SPE_RSPELOSM Mask Bit for Loss of SPE Sync Signal from Telecom Bus.

11 SPE_RJ0J1V1LOSM Mask Bit for Loss of J0J1V1 Sync Signal from Telecom

10 SPE_RDS3LOCM Mask Bit for Loss of DS3 External Clock from External

9 SPE_RC 52LOCM Mask Bit for Loss of 52 MHz Clock from Telecom Bus. 8 SPE_RLSLOCM Mask Bit for Loss of 19 MHz Clock from Telecom Bus. 6 SPE_TSY52LOSM Mask Bit for Loss of Sync 52 Signal from Telecom Bus.

Table 147. SPE_MASK1— SPE_MASK3, Mask Bits (R/W) (continued) Table 148. SPE_STATE1— SPE_STATE2, Receive/Transmit State and Value Parameters (RO) 0x30008 5 SPE_TV1LOSM Mask Bit for Loss of V1 Sync Signal from Telecom Bus.

4 SPE_TSPELOSM Mask Bit for Loss of SPE Sync Signal from Telecom

3 SPE_TJ0J1V1LOSM Mask Bit for Loss of J0J1V1 Sync Signal from Telecom

2 SPE_TDS3LOCM Mask Bit for Loss of DS3 External Clock from External

1 SPE_TC52LOCM Mask Bit for Loss of 52 MHz Clock from Telecom Bus. 0 SPE_TLSLOCM Mask Bit for Loss of 19 MHz Clock from Telecom Bus.

11 SPE_RJ0J1V1LOS State Bit for Loss of J0J1V1 Sync Signal from Telecom

10 SPE_RDS3LOC State Bit for Loss of DS3 External Clock from External

3 SPE_TJ0J1V1LOS State Bit for Loss of J0J1V1 Sync Signal from Telecom

2 SPE_TDS3LOC State Bit for Loss of DS3 External Clock from External

Table 149. SPE_RAOH_CTL1 — SPE_RAOH_CTL3, Receive Control for Alarm and OH Functions (R/W) check for received data; if 1, even parity check. states based on majority rule.

6 SPE_PAIS_AISINH Path AIS State bit Inhibit Signal for Generating Path

AIS. When 1, the inhibit is on.

5 SPE_PAIS_LOPINH Loss of Pointer Inhibit Signal for Generating Path

AIS. When 1, the inhibit is on. 4 SPE_PAIS_SFB3INH Signal Fail Inhibit Signal for Generating Path AIS.

3 SPE_PAIS_SDB3INH Signal Degrade Inhibit Signal for Generating Path

AIS. When 1, the inhibit is on.

2 SPE_PAIS_UNEQINH Path Unequipped Inhibit Signal for Generating Path

AIS. When 1, the inhibit is on.

1 SPE_PAIS_PLMINH Path Label Mismatch Inhibit Signal for Generating

Path AIS. When 1, the inhibit is on.

0 SPE_P AIS_TIMINH Path Trace Indicator Mismatch Inhibit Signal for

Generating Path AIS. When 1, the inhibit is on.

Table 150. SPE_CNTD1— SPE_CNTD2, Cont inuous N-Times Detect Values (R/W)

6 SPE_AIS_LOSSY52INH Loss of Sync 52 State Bit Inhibit Signal for Generat-

ing Path AIS. When 1, the inhibit is on.

5 SPE_AIS_LOSV1INH Loss of V1 Sync Inhibit Signal for Generating Path

AIS. When 1, the inhibit is on.

4 SPE_AIS_LOSSPEINH Loss of SPE Sync Inhibit Signal for Generating Path

AIS. When 1, the inhibit is on.

3 SPE_AIS_LOSJ0J1V1INH Loss of J0J1V1 Sync Inhibit Signal for Generating

Path AIS. When 1, the inhibit is on.

2 SPE_AIS_LOCDS3INH Loss of Ext DS3 Clock Inhibit Signal for Generating

Path AIS. When 1, the inhibit is on.

1 SPE_AIS_LOC52INH Loss of 52 MHz Clock Inhibit Signal for Generating

Path AIS. When 1, the inhibit is on.

0 SPE_AIS_LOCINH Loss of 19 MHz Clock Inhibit Signal for Generating

Path AIS. When 1, the inhibit is on.

Table 151. SPE_ROHC2, Receive Overhead Expected Value for C2 Byte (R/W) Table 152. SPE_RMON1 — SPE_RMON5, R eceive Monitor Values (RO) value to determine payload label mismatch error. Table 153. SPE_MAP_CTL1 — SPE_MAP_CTL3, Tx/Rx Control for Mapping Functions (R/W) selected for transmit data; when 0, STS-3/STM-1. 00 or 01 = DS3 data from M13 block. 10 = DS3 data from loopback (Rx to Tx). 11 = DS3 data from external clear channel. selected; when 0, DS3 input data is selected.

01 = STS-1/TUG-3 data for slot 1 in STS-3/STM-1. 10 = STS-1/TUG-3 data for slot 2 in STS-3/STM-1. 11 = STS-1/TUG-3 data for slot 3 in STS-3/STM-1. selected for receive data. When 0, STS-3/STM-1. of three DS3 output devices. 00 or 01 = DS3 data to M13 block. 10 = DS3 data to loopback (RX to TX). 11 = DS3 data to external clear channel. put; when 0, DS3 data is output. 01 = STS-1/TUG-3 data from slot 1 in STS-3/STM-1. 10 = STS-1/TUG-3 data from slot 2 in STS-3/STM-1. 11 = STS-1/TUG-3 data from slot 3 in STS-3/STM-1.

5 SPE_TDS3CLK_EDGE External DS3 Clock Edge Select for DS3 Input Data

0 = Negative edge is selected. 1 = Positive edge is selected. Table 153. SPE_MAP_CTL1 — SPE_MAP_CTL3, Tx/Rx Control for Mapping Functions (R/W) (continued)

mode, is inverted from its current phase. PLL in DS3 mode, is inverted from its current phase. tion indication instead of negative input pulse. input is bipolar; when 0, the DS3 input is unipolar. put is bipolar; when 0, the DS3 output is unipolar. stream (previously known as the NSMI interface data). (previously known as the NSMI interface data).

Table 154. SPE_TAOH_CTL1 — SPE_TAOH_CTL3, Tx Control for Alarm/OH Functions (R/W) (receive to transmit) lines. depends on SPE_TPOAC_N1 ( Table 154) control bit. SPE_TPOAC_K3 ( Table 154) control bit. depends on SPE_TPOAC_H4 ( Table 154) control bit. depends on SPE_TPOAC_F3 (Table 154) control bit. depends on SPE_TPOAC_F2 (Table 154) control bit. depends on SPE_TPOAC_C2 ( Table 154) control bit. SPE_TPOAC_J1 ( Table 154) control bit. wise, odd parity is checked. frame. When 1, the TPOAC value is inserted in the N1 byte.

Table 154. SPE_TAOH_CTL1 — SPE_TAOH_CTL3, Tx Control for Alarm/OH Functions (R/W) (continued) frame. When 1, the TPOAC value is inserted in the K3 byte. frame. When 1, the TPOAC value is inserted in the H4 byte. frame. When 1, the TPOAC value is inserted in the F3 byte. frame. When 1, the TPOAC value is inserted in the F2 byte. frame. When 1, the TPOAC value is inserted in the C2 byte. frame. When 1, the TPOAC value is inserted in the J1 byte. be inserted into the NPI byte location. be inserted into the NPI byte location. contributes to the generation of RDI-P . utes to the generation of RDI-P . utes to the generation of RDI-P . utes to the generation of RDI-P .

Table 155. SPE_TRDIREI_CTL, Transmit Path RDI and REI Control Register (R/W) Table 156. SPE_TERRINS_CTL, Transmit Error Insertion Control (R/W) Table 157. SPE_TOHINS1— SPE_TOHINS4, Transmit OH Insert Value (R/W) utes to the generation of RDI- P. each time a pulse occurs on the BER_INS line. continuously into the outgoing G1[7:4] bits, until reset to 0.

Table 158. SPE_SIGDEG_CTL1 — SPE_SIGDEG_CTL6, Signal Degrade BER Algorithm Parameters (R/W) Table 159. SPE_SIGFAIL_CTL1— SPE_SIGFAIL_CTL6, Signal Fail BER Algorithm Parameters (R/W)

Table 160. SPE_ERRCNT1 — SPE_ERRCNT6, B3, G1, Bipolar Violation, and Excess Zero Error Count (RO) Table 161. SPE_PTRCNT1 — SPE_PTRCNT3, Receive Pointer Increment and Decrement Count (RO) Table 162. SPE_RJ1MON_R1 — SPE_RJ1MON_R32, Receive J1 Monitor Values (RO) end of a performance monitor interval. end of a performance monitor interval. performance monitor interval. the end of a performance monitor interval. a 64-byte sequence from the J1 byte of each frame.

Table 163. SPE_TJ1DINS_R1— SPE_TJ1DINS_R32, Transmit J1 Insert Values (R/W) Table 164. SPE_RJ1DEXP_R1 — SPE_RJ1DEXP_R32, Receive J1 Expected Values (R/W) Table 165. SPE_SCRATCH_R, Scratch Pad (R/W)

9.2 SPE Mapper Register Map

Note: In T able 166, the reset default of all reserved bits is 0. Shading denotes reserved bits. Table 166. SPE Mapper Register Map

Table 166. SPE Mapper Register Map (continued)

10 VT/TU Mapper Registers

10 VT/TU Mapper Registers (continued)

10.1 VT/TU Mapper Register Descriptions

indicated as either read/write (R/W) or read only (RO), and the value of the bits on reset is given. Table 167. VT_VERSION_R, VT Mapper Ready, Version, and Identification (RO) Table 168. VT_GDELTA, VT Global Deltas (COR/COW) per is ready for microprocessor reads and writes. nal bit error rate detector. H4 loss of multiframe condition.

Table 169. VT_REVENT_DELTA[1 — 28], Receive Event and Delta Per Channel (COR/COW) Table 170. VT_LOPOHFAIL_EVENT, Low-Order Path Overhead Failure Event (COR/COW) that BIP-2 errors have been detected. one indicates an elastic store overflow. cates a change of VTLOPS state. indicates a change of VTPLM state.

Table 171. VT_TEVENT_DELTA[1— 28], Transmit Event and Delta Per Channel (COR/COW) Table 172. VT_GMASK, VT Global Masks (R/W) 1 indicates an elastic store overflow. change of VT_LOFS[1— 28] (Tabl e 1 79) state. of VT_TX_AIS[1— 28] (Table 179) state. VT_SD_D ( Table 168) will not contribute to the interrupt. (Table 168) will not contribute to the interrupt.

Table 173. VT_RMASK[1— 28], Receive Masks Per Channel (R/W) Note: The event and delta bits for these mask bits are in Table 169. will not contribute to the interrupt. will not contribute to the interrupt. not contribute to the interrupt. not contribute to the interrupt. VT_LOPS_D[1 — 28] will not contribute to the interrupt. VT_J2TIM_D[1 — 28] will not contribute to the interrupt. 1, VT_PLM_D[1— 28] will not contribute to the interrupt. VT_UNEQ_D[1 — 28] will not contribute to the interrupt. VT_SIZERR_D[1 — 28] will not contribute to the interrupt. not contribute to the interrupt. will not contribute to the interrupt.

Table 174. VT_LOPOHFAIL_MASK, Low-Order Path Overhead Failure Mask (R/W) Table 175. VT_TMASK[1— 28], Transmit Masks Per Channel (R/W) Table 176. VT_GSTATE, VT Global State (RO) will not contribute to the interrupt. degrade condition on the selected channel.

Table 177. VT_RSTATE[1— 28], Receive State Per Channel (RO) Table 178. VT_RAPSSTATE[1— 28], Receive APS State Per Channel (RO) Table 179. VT_TSTATE[1— 28], Transmit State Per Channel (RO) bits received in the Z7 byte. bits received in the V5 byte. match between the expected trace and the detected trace.

Table 180. VT_GCTL1, VT Global Control Register 1 (R/W) Table 181. VT_GCTL2, VT Global Control Register 2 (R/W) 14:8 VT_RX_GRP_TYPE[6:0] Receive Group Type. VT/TU group type selection. VT2/TU-12 group type. Group 1 is the LSB. 6:0 VT_TX_GRP_TYPE[6:0] Transmit Group Type. VT/TU group type selection. VT2/TU-12 group type. Group 1 is the LSB.

Table 182. VT_GCTL3, VT Global Control Register 3 (R/W) Table 183. VT_GCTL4, VT Global Control Register 4 (R/W) 7:4 VT_LOPS_NTIME[3:0] VT/TU Loss of Phase Sync NTIME Detection Control. 3:0 VT_H4_NTIME[3:0] H4 Multiframe Indication NTIME Detection Control. tion into the VT_H4LOMF (Table 176) state. consistent Z6 bytes required to accept a new value. to transition in and out of J2TIM. preter to go into the VT_LOP[1— 28] (Table 177) state. pointer interpreter to go into the VT_LOP state.

Table 184. VT_GCTL5, VT Global Control Register 5 (R/W) required to accept a new VT_APS[1— 28][3:0] (Table 178).

Table 185. VT_SIGDEG_CTL1, Signal Degrade Control Register 1 (R/W) Table 186. VT_SIGDEG_CTL2, Signal Degrade Control Register 2 (R/W) Table 187. VT_SIGDEG_CTL3, Signal Degrade Control Register 3 (R/W) Table 188. VT_SIGDEG_CTL4, Signal Degrade Control Register 4 (R/W) activated by a 0 to 1 transition. vated by a 0 to 1 transition. which is activated by a 0 to 1 transition. is activated by a 0 to 1 transition. BER monitor. Valid inputs are 00001— 11100.

Table 189. VT_SIGDEG_CTL5, Signal Degrade Control Register 5 (R/W) Table 190. VT_SIGDEG_CTL6, Signal Degrade Control Register 6 (R/W) Table 191. VT_SIGDEG_CTL7, Signal Degrade Control Register 7 (R/W) Table 192. VT_SIGFAIL_CTL1, Signal Fail Control Register 1 (R/W) Table 193. VT_SIGFAIL_CTL2, Signal Fail Control Register 2 (R/W) Table 194. VT_SIGFAIL_CTL3, Signal Fail Control Register 3 (R/W) of bad blocks is below this threshold, then SD is cleared. above this threshold, then SF is set.

Table 195. VT_SIGFAIL_CTL4, Signal Fail Control Register 4 (R/W) Table 196. VT_SIGFAIL_CTL5, Signal Fail Control Register 5 (R/W) Table 197. VT_SIGFAIL_CTL6, Signal Fail Control Register 6 (R/W)

Table 198. VT_TCTL[1— 28], Transmit Control Per Channel (R/W) serial channel or automatic generation. insertion is based on the LOPOH serial channel. transmitted in the specified channel.

Table 199. VT_TTUOH_CTL[1— 28], Transmit TU Overhead Control Per Channel (R/W) Table 200. VT_TAPSRIVAL[1— 28], Transmit APS and Remote Indication Per Channel (R/W) Table 201. VT_TSWOW[1— 28], Transmit Software Overwrite Per Channel (R/W) head Byte Insertion Modes Per Channel on page446. head Byte Insertion Modes Per Channel on page445. Byte Insertion Modes Per Channel on page 445. will be transmitted in bits 1:4 of the Z7/K4 byte. are written into the ERDI-V locations of the Z7 byte. RDI-V location of the V5 byte. RFI-V location of the V5 byte. the overhead bits in asynchronous VT/TU mappings.

Table 202. VT_TSIG_CTL[1— 28], Transmit Signaling Control Per Channel (R/W) Table 203. VT_J2BYTE_INS_R[1— 28][1— 16], J2 Insert Values Per Channel (R/W) cessor interface on the outgoing VT/TU. sions use of the S bits in the outgoing VT/TU. interface on the outgoing VT/TU. Table 204. VT_RCTL[1— 28], Receive Control Per Channel (R/W) frame format is provisioned. ing Behavior per Channel on page 439. ing Behavior per Channel on page 439.

Table 205. VT_RTUOH_CTL[1— 28], Receive TU Overhead Control Per Channel (RO) Table 206. VT_RBIP2_CNT[1— 28], Receive BIP-2 Error Count Per Channel (RO) Table 207. VT_RREIV_CNT[1— 28], Receive REI-V Error Count Per Channel (RO) tor and Termination (J2MON) on page 438. Receive VT/TU Demapping Selection on page 437. 1 transition of SMPR_PMRESET (Table 65). transition of SMPR_PMRESET . Table 204. VT_RCTL[1— 28], Receive Control Per Channel (R/W) (continued)

Table 208. VT_RPTR_CNT[1— 28], Receive Pointer and Count Per Channel (RO) Table 209. VT_J2BYTE_EXP_R[1— 28][1— 16], J2 Expected Values Per Channel (R/W, RO) stored location of the V5 byte within the VT/TU mapping. Table 210. VT_THRES_CTL[1— 28], Transmit Elastic Store Threshold Control (R/W) threshold controlling positive justifications. threshold controlling negative justifications.

10.2 VT/TU Mapper Register Map

Table 211. VT/TU Mapper Register Map Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.

Table 211. VT/TU Mapper Register Map (continued)

Note: Registers from 0x20590 to 0x20969 are reserved and should not be read.

11 M13/M23 MUX/DeMUX Registers

Table 250. M13_DS1_FEAC_LB_DETD_R[1 — 4], DS1 Far-End Alarm and Control Loopback Detect Delta Table 251. M13_DS1_FEAC_LB_DET_R[1 — 4], DS1 Far-End Alarm and Control Loopback Detect

11 M13/M23 MUX/DeMUX Registers (continued)

Table 298. M13_TDL_0DATA_R[0— 63], Tx Data for Path Maintenence Data-Link Buffer 0 Registers Table 299. M13_TDL_1DATA_R[0— 63], Tx Data for Path Maintenence Data-Link Buffer 1 Registers

11.1 M13 Block Register Descriptions

read/write (R/W) or read only (RO), and the value of the bits on reset is given. Table 212. M13_ID_R, M13 Block Identification (RO) Table 213. M13_VERSION_R, M13 Version (RO)

Table 214. M13_DELTA1, Delta (RO)

7 M13_RDL_IDLED This delta bit is set if M13_RDL_IDLE ( Table 224)

to 1 again until another state transition occurs.

6 M13_DS3_LOFD This delta bit is set if M13_DS3_LOF ( Table 224)

to 1 again until another state transition occurs.

5 M13_DS3_OOFD This delta bit is set if M13_DS3_OOF ( Table 224)

to 1 again until another state transition occurs.

4 M13_DS3_C1_DETD This delta bit is set if M13_DS3_C1_DET ( Tabl e 2 24)

1 again until another state transition occurs.

3 M13_DS3_RAI_DETD This delta bit is set if M13_DS3_RAI_DET ( Table 224)

to 1 again until another state transition occurs.

2 M13_DS3_AISPAT_DETD This delta bit is set if M13_DS3_AISP AT_DET

is not set to 1 again until another state transition occurs.

1 M13_DS3_IDLEP AT_DETD This delta bit is set if M13_DS3_IDLEPAT_DET

is not set to 1 again until another state transition occurs.

0 M13_DS3_CBZ_DETD This delta bit is set if M13_DS3_CBZ_DET ( Table 224)

to 1 again until another state transition occurs.

Table 215. M13_DELTA2, Delta (RO) Table 216. M13_DELTA3, Delta (RO)

7 M13_DS1_LB_SD This delta bit summarizes the state of

M13_DS1_LB_DETD[28:1] (Table 237) bits.

6 M13_DS1_AIS_SD This delta bit is set if any M13_DS1_AIS_DETD[2 8:1]

5 M13_DS1_LOC_SD This delta bit is set if any M13_DS 1_LOCD[ 28:1]

4 M13_RDS3_SEFD This delta bit is set if M13_RDS3_SEF ( Table 225)

again until another state transition occurs.

3 M13_RDS3_ALL1_DETD This delta bit is set if M13_RDS3_ALL1_DET (Table 225)

again until another state transition occurs.

2 M13_RDS3_LOSD This delta bit is set if M13_RDS3_LOS ( Table 225)

again until another state transition occurs.

1 M13_TDS3_LOCD This delta bit is set if M13_TDS3_LOC ( Table 225)

again until another state transition occurs.

0 M13_RDS3_LOCD This delta bit is set if M13_RDS 3_LOC (Table 225)

again until another state transition occurs.

7 M13_DS2_RSV_SD This delta bit is high if any M13_DS2_RSV _RCVD[7:1]

6 M13_DS2_LB_SD This delta bit summarizes the state of

5 M13_DS2_RAI_SD This delta bit summarizes the state of

4 M13_DS2_AIS_SD This delta bit summarizes the state of

3 M13_DS2_LOF_SD This delta bit is high if any M13_DS2_LOFD[7:1] (Table 229)

2 M13_DS2_OOF_SD This delta bit is high if any M13_DS2_OOFD[ 7:1]

1 M13_XC_DS2_AIS_SD This delta bit is set if any M13_XC_DS2_AIS_DETD[7:1]

0 M13_XC_DS2_LOC_SD This delta bit is set if any M13_XC_DS2_LOCD[7:1]

Table 217. M13_DELTA4, Delta (RO)

7 M13_TFEAC_DONE This bit is set when the M13 completes transmission of a

is not set to 1 again until the event reoccurs.

6 M13_TDL_DONE This bit is set when the M13 completes transmission of a

again until the event reoccurs.

5 M13_TDL_BUF1_INT This bit is set when the device completes transmission of

4 M13_TDL_BUF0_INT This bit is set when the device completes transmission of

3 M13_RDL_FIFO_AFD This delta bit is set if M13_RDL_FIFO_AF (Table 225)

again until another state transition occurs.

2 M13_RDL_FRM_INT This bit indicates that a new data-link frame closing flag or

is not set to 1 again until the event reoccurs.

1 M13_RFEAC_ALM_INT This bit indicates that a new DS3 FEAC alarm codeword has

(COW), and it is not set to 1 again until the event reoccurs.

0 M13_RFEAC_LB_INT This bit indicates that a new DS3 FEAC loopback codeword

Table 218. M13_DELTA5, Delta (RO) Table 219. M13_MASK1, Mask (R/W)

1 M13_DS2DMX_LOC_SD This delta bit is set if any M13_DS2DMX_LOCD[7:0]

(Table 234) bit register is high.

0 M13_RDL_FIFO_UFD This delta bit is set if bit M13_RDL_FIFO_UF (Tabl e 2 25)

again until another state transition occurs.

7 M13_RDL_IDLEM Setting this mask bit high prevents the delta

output interrupt (INT) to be active.

6 M13_DS3_LOFM Setting this mask bit high prevents the delta

5 M13_DS3_OOFM Setting this mask bit high prevents the delta

4 M13_DS3_C1_DETM Setting this mask bit high prevents the delta

3 M13_DS3_RAI_DETM Setting this mask bit high prevents the delta

block output INT to be active.

2 M13_DS3_AISPAT_DETM Setting this mask bit high prevents the delta

block output INT to be Active.

1 M13_DS3_IDLEPAT_DETM Setting this mask bit high prevents the delta

block output INT to be active.

0 M13_DS3_CBZ_DETM Setting this mask bit high prevents the delta

block output INT to be active.

Table 220. M13_MASK2, Mask (R/W)

7 M13_DS1_LB_SM Setting this mask bit high prevents the summary delta

put interrupt (INT) to be active.

6 M13_DS1_AIS_SM Setting this mask bit high preve nts the summary delta

5 M13_DS1_LOC_SM Setting this mask bit high preve nts the summary delta

4 M13_RDS3_SEFM Setting this mask bit high prevents the delta

3 M13_RDS3_ALL1_DETM Setting this mask bit high prevents the delta

block output INT to be active.

2 M13_RDS3_LOSM Setting this mask bit high preve nts the delta

1 M13_TDS3_LOCM Setting this mask bit high preve nts the delta

0 M13_RDS3_LOCM Setting this mask bit high preve nts the delta

Table 221. M13_MASK3, Mask (R/W)

7 M13_DS2_RSV_SM Setting this mask bit high prevents the summary delta

put interrupt (INT) to be active.

6 M13_DS2_LB_SM Setting this mask bit high prevents the summary delta

5 M13_DS2_RAI_SM Setting this mask bit high prevents the summary delta

4 M13_DS2_AIS_SM Setting this mask bit high prevents the summary delta

3 M13_DS2_LOF_SM Setting this mask bit high prevents the summary delta

1 M13_XC_DS2_AIS_SM Setting this mask bit high prevents the summary delta

0 M13_XC_DS2_LOC_SM Setting this mask bit high prevents the summary delta

Table 222. M13_MASK4, Mask (R/W)

7 M13_TFEAC_DONEM Setting this mask bit high prevents M13_TFEAC_DONE

6 M13_TDL_DONEM Setting this mask bit high prevents M13_TDL_DONE

(Table 217) from causing the block output INT to be active.

5 M13_TDL_BUF1_INTM Setting this mask bit high prevents M13_TDL_BUF1_INT

(Table 217) from causing the block output INT to be active.

4 M13_TDL_BUF0_INTM Setting this mask bit high prevents M13_TDL_BUF0_INT

(Table 217) from causing the block output INT to be active.

3 M13_RDL_FIFO_AFM Setting this mask bit high prevents M13_RDL_FIFO_AFD

(Table 217) from causing the block output INT to be active.

2 M13_RDL_FRM_INTM Setting this mask bit high prevents M13_RDL_FRM_INT

(Table 217) from causing the block output INT to be active.

1 M13_RFEAC_ALM_INTM Setting this mask bit high prevents

0 M13_RFEAC_LB_INTM Setting this mask bit high prevents M13_RFEAC_LB_INT

(Table 217) from causing the block output INT to be active. Table 221. M13_MASK3, Mask (R/W) (continued)

Table 223. M13_MASK5, Mask (R/W)

1 M13_DS2DMX_LOC_SM Setting this mask bit high prevents the summary delta

block output interrupt (INT) to be active.

0 M13_RDL_FIFO_UFM Setting this mask bit high prevents M13_RDL_FIFO _UFD

(Table 218) from causing the block output INT to be active. Table 224. M13_DS3_STATUS1, Status (RO)

7 M13_RDL_IDLE This bit is set if 15 consecutive ones are received on the

6 M13_DS3_LOF This bit is set if M13_DS3_OOF is high continuously for

tinuously low for 28 frame periods. on page 469) This bit is high while out-of-frame.

4 M13_DS3_C1_DET This bit is set if the first C bit of each DS3 frame is received

3 M13_DS3_RAI_DET If both X bits in 2 consecutive frames are received as 0, the

both X bits in 2 consecutive frames are received as 1.

2 M13_DS3_AISPAT_DET The 4704 information bits in each M frame are checked for

1 M13_DS3_IDLEPA T_DET The 4704 information bits in each M frame are checked for

0 M13_DS3_CBZ_DET This bit is set if every C bit in 3 consecutive DS3 frames is

1. It is cleared if the three C bits in a single

Table 225. M13_DS3_STATUS2, Status (RO) Table 226. M13_XC_DS2_LOCD_R, DS2 Loss of Clock Delta (RO) Table 227. M13_XC_DS2_AIS_DETD_R, DS2 Alarm Indication Signal Detection Delta (RO)

5 M13_RDL_FIFO_AF This bit is 1 if the number of unread bytes in the receive

4 M13_RDS3_SEF This bit is 1 if there are three or more F-bit errors in

3 M13_RDS3_ALL1_DET This bit is 1 if the input data is 0 for fewer than 9 out of

2 M13_RDS3_LOS This bit is 1 if there are 175 ±75 contiguous pulse positions

1 M13_TDS3_LOC This bit is 1 if the SMPR_TDS3CLK signal fails to have tran-

transition on SMPR_TDS3CLK resets this bit.

0 M13_RDS3_LOC This bit is 1 if the SMPR_RDS3CLK signal fails to have tran-

transition on SMPR_RDS3CLK resets this bit. (COW), and they are not set to 1 again until the event reoccurs. (Table 239) transitioning either from 0 to 1 or from 1 to 0.

Table 228. M13_DS2_OOFD_R, DS2 Out of Frame Delta (RO) Table 229. M13_DS2_LOFD_R, DS2 Loss of Frame Delta (RO) Table 230. M13_DS2_AIS_DETD_R, DS2 Alarm Indication Signal Detect Delta (RO) Table 231. M13_DS2_RAI_DETD_R, DS2 Remote Alarm Indication Detection Delta (RO) they are not set to 1 again until the event reoccurs.

Table 232. M13_DS2_LB_DETD_R, DS2 Loopback Detect Delta (RO) Table 233. M13_DS2_RSV_RCVD_R, DS2 Receive Reserved Bit Delta (RO) Table 234. M13_DS2DMX_LOCD_R, DS2 DeMUX Loss of Clock Delta (RO) Table 235. M13_DS1_LOCD_R[1 — 4], DS1 Loss of Clock Delta Registers (RO)

1. Delta bits can be programmed to be either clear on

set to 1 again until the event reoccurs.

Table 236. M13_DS1_AIS_DETD_R[1 — 4], DS1 Alarm Indication Signal Delta Registers (RO) Table 237. M13_DS1_LB_DETD_R[1 — 4], DS1 Loopback Detect Delta Registers (RO) Table 238. M13__XC_DS2_LOC_R, DS2 Loss of Clock Status (RO) Table 239. M13_XC_DS2_AIS_DET_R, DS2 Alarm Indication Signal Detect Status (RO) not set to 1 again until the event reoccurs. not set to 1 again until the event reoccurs. clock is detected on the DS2 clock input.

Table 240. M13_DS2_OOF_R, DS2 Out of Frame Status (RO) Table 241. M13_DS2_LOF_R, DS2 Loss of Frame Status (RO) Table 242. M13_DS2_AIS_DET_R, DS2 Alarm Indication Signal Detect Status (RO) Table 243. M13_DS2_RAI_DET_R, DS2 Remote Alarm Indication Detect Status (RO) E1 mode, it is set equal to the RAI bit.

Table 244. M13_DS2_LB_DET_R, DS2 Loopback Detect Status (RO) Table 245. M13_DS2_RSV_RCV_R, DS2 Receive Reserved Bit Delta Status (RO) Table 246. M13_DS2DMX_LOC_R, DS2 DeMUX Loss of Clock Status (RO) Table 247. M13_DS1_LOC_R[1— 4], DS1 Loss of Clock Status Registers (RO) parity mode, M13_DS2_LB_DETy is fixed at 0. clock is detected on the DS2 clock input, XC_DS2DMXCLKy. detected on a low-speed clock input, XC_DS1CLKx.

Table 248. M13_DS1_AIS_DET_R[1— 4], DS1 Alarm Indication Signal Detect Status Registers (RO) Table 249. M13_DS1_LB_DET_R[1 — 4], DS1 Loopback Detect Status Registers (RO) detected on a low-speed data input, XC_DS1DATAx. C bit in received DS2 frames.

Table 251. M13_DS1_FEAC_LB_DET_R[1 — 4], DS1 Far-End Alarm and Control Loopback Detect Status again until another state transition occurs. transitioning either from 0 to 1 or from 1 to 0. vate codeword is received four consecutive times. received four consecutive times.

Table 252. M13_RFEAC_CODE_R, Receive Far-End Alarm and Control Code Status (RO) Table 253. M13_RDL_STATUS, Receive Data-Link Status (RO) Table 254. M13_RDL_DATA_R, Receive Data-Link Data (RO) Table 255. M13_RDL_FRAME_SIZE_R, Receive Data-Link Frame Size (RO) and it is received right to left.

4 M13_RDL_FLAG This bit is high if the closing flag or an abort byte has been

3 M13_RDL_ABORT This bit is high if the frame was ended with an abort byte

2 M13_RDL_NOT_BYTE This bit is set if the number of bits in the frame (after removal

of stuffed zeros) is not a multiple of 8.

1 M13_RDL_OVFL This bit is set if at least 1 byte of the frame was overwritten by

a byte from a succeeding frame before being read.

0 M13_RDL_FCS_ERR This bit is set if the CRC-16 check fails and M13_RDL_FCS =

Table 256. M13_RHDLC_STATUS_R, Receive High-Level Data-Link Control Status (RO) Table 257. M13_DS2_FORCE_OOF_R, DS2 Force Out of Frame (One Shot R/W) Table 258. M13_CONTROL1, Control 1 (One Shot R/W) DS2 framer in M12 demultiplexer Y is forced out of frame.

2 M13_RDL_FRM_CLR If M13_RDL_FRM_CLR is set to 1, the portion of the earli-

est frame still in the receive HDLC FIFO will be deleted. will be discarded without being written into the FIFO.

1 M13_DS3_FORCE_OOF When this bit transitions from 0 to 1, the DS3 framer is

0 M13_BIPOL_ERR A single bipolar violation error is transmitted each time this

bit transitions from 0 to 1. Table 259. M13_CONTROL2, Control 2 (R/W)

7 M13_BPV_IN If this bit is 1, the SMPR_RDS3NEG_BPV input is used as an

6 M13_LOOP_TIME The M23 multiplexer uses the SMPR_TDS3CLK if this bit is 0,

otherwise, the SMPR_RDS3CLK is used.

5 M13_LOOP_T_TO_R Setting this bit to 1 causes the M23 MUX output to be looped

back to the M23 DEMUX input.

4 M13_LOOP_R_TO_T Setting this bit to 1 causes the received DS3 input to be

looped back to the transmit DS3 output.

Table 260. M13_CONTROL3, Control 3 (R/W) Table 261. M13_SP_OFFSET_R, Sync Pulse Offset (R/W) Table 262. M13_SP_D_OFFSET_R, Sync Pulse D Offset (R/W)

2 M13_AUTO_AIS_OOF If this bit is 1, the M13 will automatically insert AIS in all DS2

1 M13_AUTO_FLB If this bit Is 1, the device will automatically loop the received

M13_DS1_FEAC_LB_DETx = 1 ( Table 251).

0 M13_AUTO_LB When M13_AUTO_LB = 1, loopback of DS1 channel x is acti-

vated if M13_DS1_LB_DETx = 1 (Table 249). wise, it is in the C-Bit Parity Mode.

0 M13_BIPOLAR The M13 Performs B3ZS Encoding And Decoding if this

Table 259. M13_CONTROL2, Control 2 (R/W) (continued)

Table 263. M13_M12_MUX_CONTROL1_R[1 — 7], M12 MUX CONTROL 1 Registers [1— 7] (R/W) Table 264. M13_M12_MUX_CONTROL2_R[1 — 7], M12 MUX CONTROL 2 Registers [1— 7] (R/W) Table 265. M13_DS2_RAI_SEND_R, DS2 Remote Alarm Indication Send (R/W) Table 266. M13_DS2_RSV_SEND_R, DS2 Reserve Bit Send (R/W) Multiplexing. The DS1/E1 clocks are inputs to the block. 01 = The M12 MUX operates as an independent multiplexer. The DS1/E1 clocks are inputs to the block. 10 = The M12 MUX operates as an independent multiplexer. The DS1/E1 clocks are outputs from the block.

5 M13_MUXCH2_4_

4 M13_DS1_E1N[1 — 7] If these bits are 1, the M12 multiplexers operate on DS1

inputs; otherwise, they operate on E1 inputs. means that the data is retimed by the falling edge.

Table 267. M13_DS2_MPINV_R, DS2 M Frame Alignment or Parity Error (R/W) Table 268. M13_DS2_FINV_R, DS2 Frame Error (R/W) Table 269. M13_DS2_P_BER_R, Parity Bit Error Rate (R/W) Table 270. M13_DS2M12_EDGE_R, DS2 M12 Edge (R/W) Table 271. M13_DS2_FORCE_AIS_R, DS2 Force Alarm Indication Signal (R/W) Mode are Generated in Error. Signal in the E1 Mode are Generated in Error. (Table 65) are Inverted if these Register Bits are Set to 1. M12 MUXs are Forced to be AIS (All Ones).

Table 272. M13_M12_DEMUX_CONTROL1_R[1 — 7], M12 DeMUX Control 1 Registers [1— 7] (R/W) Table 273. M13_M12_DEMUX_CONTROL2_R[1 — 7], M12 DeMUX Control 2 Registers [1— 7] (R/W) Table 274. M13_M12_DEMUX_CONTROL3, DS2 M12 DeMUX Control 3 (R/W) 10/11 = The M12 deMUX is idle and outputs are held low.

5 M13_DEMUXCH2_

tiplexers are Inverted if these Bits are 1.

4 M13_OUT_

Otherwise, the Data is Retimed By the Falling Edge.

1 M13_DS2_MODE This Bit Controls the DS2 Framing Algorithm In the DS1

in four consecutive M-subframe pairs if M13_DS2_MODE = 1.

0 M13_DS2_FERR_

alignment signal that contains at least 1 bit error.

Table 275. M13_DMDS2_EDGE_R, DS2 Edge for M12 DeMUX (R/W) Table 276. M13_DS3_CONTROL1, DS3 Control 1 (R/W)

7 M13_DS3_FINV For testing purposes, this bit is high to allow the F bit to be

6 M13_DS3_MINV For testing purposes, this bit is high to allow the M bit to

5 M13_DS3_PINV For testing purposes, this bit is high to allow the P Bit to

4 M13_DS3_FORCE_AIS This bit causes the M13 to generate DS3 AIS in place of

the transmit DS3 signal from the M23 multiplexer.

3 M13_DS3_FORCE_IDLE This bit causes the M13 to generate DS3 idle (unless

of the transmit DS3 signal from the M23 multiplexer.

2 M13_TDS3_FORCE_ALL1 This bit causes the M13 to generate unframed all ones

1 M13_M23CLK_MODE If this bit is 1, DS2 clo cks associated with DS2 signals

wise, they are inputs to the block.

Table 277. M13_DS3_CONTROL2, DS3 Control 2 (R/W) Table 278. M13_TFEAC_CONTROL, Tx FEAC Control (R/W)

6 M23_STUFF_MODE A Logic 0 on this Bit Will Cause the M23 Stuffing to be

5 M13_NSMI_MODE A Logic 1 of this Bit will Enable M13 to Receive and Out-

put Ds3 Payload Through a Serial Link.

4 M13_DS3_P_BER The P Bits and, in CBP Mode, the CP Bits in the DS3

1 M13_DS3_RAI_SEND The Transmitted DS3 X Bits are Set to the Inverse of this

Bit During Normal Transmission.

0 M13_FEBE_ERR This Bit is Used to Force Errors in the Transmitted DS3

Transmitted with the FEBE Bits Set to 000. Ones by Setting M13_TFEAC_CTL to 00. value for the alarm or status codeword. M13_TFEAC_DONE ( Table 217) to 1.

Table 279. M13_THDLC_CONTROL1, Tx HDLC Control 1 (R/W) Table 280. M13_THDLC_CONTROL2, Tx HDLC Control 2 (R/W) Table 281. M13_DS2_LB_REQ_R, DS2 Loopback Request (R/W)

5 M13_TDL_BUF1_END If this Bit is 0, all Bytes from HDLC Buffer 1 and at Least

4 M13_TDL_BUF0_END If this Bit is 0, all Bytes from HDLC Buffer 0 and at Least

including the byte set by M13_TDL_BYTE_END[5:0].

3 M13_TDL_ACT If the Data Link is not Used, the User Should set

mitted. Otherwise, this bit should be set to 1.

2 M13_TDL_NTRNL If M13_TDL_NTRNL = 0, the Data Transmitted on the

bit is valid only when M13_TDL_ACT = 1 (Table 279).

1 M13_TDL_NTRNL_ACT Once M13_TDL_NTRNL_ACT is Set to 1, the HDLC

is again set to 1, starting transmission of a new frame.

0 M13_TDL_FCS If M13_TDL_FCS = 1, the HDLC Controller Appends the

Transmitted from the Buffer.

Table 282. M13_SEL_DS2_LB_R, Select DS2 Loopback (R/W) Table 283. M13_RDS2_EDGE_R[1 — 2], Rx DS2 Edge Registers 1— 2 Table 284. M13_DS2_OUT_IDLE_R, DS2 Output Idle (R/W) Table 285. M13_DS2_OUT_AIS_R, DS2 Output Alarm Indication Signal (R/W) Slot y of the Transmitted DS3 Signal. Input DS2 Data. It should normally be set to logic 1 (default). M13_RDS2_EDGE[7:1] = 0 when necessary. Selection Block y is Held Low. the Received DS3 Signal will be Output.

Table 286. M13_TDS2_EDGE_R, Tx DS2 Edge (R/W) Table 287. M13_RDL_CONTROL, RDL Control (R/W) Table 288. M13_PM_CNT_ACT_R, Performance Counter (RO) Table 289. M13_DS3_FERR_CNT_R[1 — 2], DS3 F-Bit Error Registers (RO) 4:3 M13_RDL_FILL[1:0] 00 = sets the receive HDLC FIFO fill level to 16 bytes. 01 = sets the receive HDLC FIFO fill level to 32 bytes. 10 = sets the receive HDLC FIFO fill level to 64 bytes. 11 = sets the receive HDLC FIFO fill level to 96 bytes.

2 M13_RDL_FCS If M13_RDL_FCS = 1, the FCS Bytes will be Checked at

last 2 bytes of the HDLC frame are written into the FIFO. tive M-subframes if M13_DS3_MODE = 1.

0 M13_RDS3_EDGE A logic 1 of this Bit Means that the Received DS3 Data is

logic 0 means the data is retimed by the falling edge.

0 M13_PM_CNT_ACT This Bit Returns a 0 When Read if all Performance

Counter Values are 0; Otherwise, it’s Set to 1. Either a DS3 F Bit, or M Bit.

Table 290. M13_DS3_FEBE_CNT_R[1 — 2], DS3 Far-End Block Error Registers (RO) Table 291. M13_DS3_CPERR_CNT_R[1 — 2], DS3 C-Bit Parity Error Registers (RO) Table 292. M13_DS3_PERR_CNT_R[1 — 2], DS3 P-Bit Error Registers (RO) Parity of the Previous Frame. Table 293. M13_DS2_PERR_CNT[7 — 1]_R[1— 2], P-Bit Error Counter Status Registers (RO)

Table 294. M13_DS2_FERR_CNT[7 — 1]_R, F-Bit Error Counter Status Registers (RO) Table 295. M13_BPV_CNT_R[1— 3], Bipolar Violation Counter Status Registers (RO) DS2 frames with P-bit errors. Table 293. M13_DS2_PERR_CNT[7 — 1]_R[1— 2], P-Bit Error Counter Status Registers (RO) (continued)

Table 296. M13_EXZ_CNT_R[1— 3], Bipolar Violation Counter Status Registers (RO) Table 297. M13_TDL_BUFFER_R, Tx Data-Link Buffer Control (R/W) Table 298. M13_TDL_0DATA_R[0— 63], Tx Data for Path Maintenance Data-Link Buffer 0 Registers Table 299. M13_TDL_1DATA_R[0— 63], Tx Data for Path Maintenance Data-Link Buffer 1 Registers excessive zeros string is detected.

0 M13_TDL_BUFFER If this Bit is 0, Data Written to Registers

Buffer 0. Otherwise, the data is written to buffer 1.

11.2 M13 Register Map

Table 300. Register Address Map Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.

229 Lucent Technologies Inc. Table 300. Register Address Map (continued)

231 Lucent Technologies Inc.

233 Lucent Technologies Inc.

235 Lucent Technologies Inc.

237 Lucent Technologies Inc.

12.1 Framer Global Register Descriptions

Table 301. FRM_SFGR1, Superframer Global Register 1 (R/W) 0x80000 15 FRM_SW_TRN Superframer Configuration Modes. Line Encoder/Decoder Control. I STS-3/STS-1/DS3/DS2 to CHI/parallel system bus/SMI. I STS-3/STS-1/DS3 to line data rate mode. I DS1 to CHI/parallel system bus/SMI channelized. I DS1 to DS2/DS3/STS-1/STS-3.

12 FRM_LOOP_

0 = Superframer is programmed for normal mode.

11 FRM_DS1_

maximum of 28 operational links. ters to select an accurate link count.

10 FRM_PLL_

0 FRM_LG_BUF_

0 = HDLC channel buffers are configured for 128-byte storage. 1 = HDLC channel buffers are combined for 512-byte storage.

Table 302. FRM_SFGR2, Superframer Global Register 2 (R/W) the transmit path system block is powered down. the receive path system block is powered down. 0, the receive path frame formatter block is powered down. 0, the transmit path receive aligner block is powered down.

Table 303. FRM_SFGR3, Superframer Global Register 3 (RO) Table 304. FRM_SFGSR4, Superframer Global Register 4 (R/W)

12.2 Arbiter (Framer) Global Registers

Table 305. FRM_FGR1, Framer Global Register 1 (R/W)

14 FRM_AR_IS A 1 indicates the FRM_AR_IS block has generated an

13 FRM_TP_RDL_IS A 1 indicates the FRM_TP_RDL_IS block has generated

12 FRM_TP_TDL_IS A 1 indicates the FRM_TP_TDL_IS block has generated

11 FRM_RH_IS A 1 indicates the FRM_RH_IS block has generated an

10 FRM_TH_IS A 1 indicates the FRM_TH_IS block has generated an

9 FRM_TS_IS A 1 indicates the FRM_TS_IS block has generated an

8 FRM_RS_IS A 1 indicates the FRM_RS_IS block has generated an

7 FRM_TP_PM_IS A 1 indicates the FRM_TP_PM_IS block has generated

6 FRM_RP_PM_IS A 1 indicates the FRM_RP_PM_IS block has generated

5 FRM_RP_RDL_IS A 1 indicates the FRM_RP_RDL_IS block has generated

4 FRM_RP_TDL_IS A 1 indicates the FRM_RP_TDL_IS block has generated

default is 40 frames (5 ms).

Table 306. FRM_FGR2, Framer Global Register 2 (R/W) Table 307. FRM_FGR3, Framer Global Register 3 (R/W) Table 308. FRM_FGR4, Framer Global Register 4 (COR) 0x80011 15 FRM_TC_EN Terminal Count Enable. 0 = Terminal count disabled use defaults. synchronization status registers, to generate an interrupt.

Table 309. FRM_FGR5, Framer Global Register 5 (COR)

12.3 Performance Monitor Global Registers

Table 310. FRM_PMGR1_B, Performance Monitor Global Register 1_B (R/W)

• P = 0x0 for the receive path, and P = 0x1 for the transmit path.

Table 311. FRM_PMGR1, Performance Monitor Global Register 1 (COR)

• P = 0x0 for the receive path, and P = 0x1 for the transmit path .

be internal to the framer block or external to the framer block. pattern generation/detection are supported.

Table 312. FRM_PMGR2, Performance Monitor Global Register 2 (COR)

• P = 0x0 for the receive path, and P = 0x1 for the transmit path.

Table 313. FRM_PMGR3, Performance Monitor Global Register 3 (R/W)

• P = 0x0 for the receive path, and P = 0x1 for the transmit path.

tains the 16-bit count of test-pattern errors. can be set to meet various standards. bit error to set the FBE status bit, FRM_FBE (Table 386). FBEs; a 1 means count TS24 framing and Fs as FBEs. 6F R M _ C M F R F E N CEPT Multiframe Reframe Enable. 0 = CEPT CRC-4 multiframe reframe disabled. 5 FRM_CRCRFEN CRC Reframe Enable. 0 = CRC errors do not cause a reframe or LOF condition. and LOF condition on excessive CRC errors. 4:3 FRM_CEPTAISM[1:0] CEPT AIS Mode. 10 = Option 2: G.775 section I.2. 11 = Option 3: G.775 section I.2. 1 = Option 1: G.775 section I.2. 0 = Alternating eight ones followed by eight zeros. 0 FRM_RAICLR Clear RAI on Reception of DS1 Idle Signal. 0 = Ignore DS1 idle signal for RAI clearing.

Table 314. FRM_PMGR4, Performance Monitor Global Register 4 (R/W)

• P = 0x0 for the receive path, and P = 0x1 for the transmit path.

Table 315. FRM_PMGR5, Performance Monitor Global Register 5— PMGR5 (R/W)

• P = 0x0 for the receive path, and P = 0x1 for the transmit path.

Table 316. FRM_PMGR6, Performance Monitor Global Register 6 (R/W)

• P = 0x0 for the receive path, and P = 0x1 for the transmit path.

Table 317. FRM_PMGR7, Performance Monitor Global Register 7 (R/W) These bits enable the errored events used to determine errored and severely errored seconds in the DS1 modes.

• P = 0x0 for the receive path, and P = 0x1 for the transmit path .

but less than the severely errored second threshold. which a reframe may be forced.

Table 318. FRM_PMGR8, Performance Monitor Global Register 8 (R/W)

• P = 0x0 for the receive path, and P = 0x1 for the transmit path.

Table 319. FRM_PMGR9, Performance Monitor Global Register 9 (R/W)

• P = 0x0 for the receive path, and P = 0x1 for the transmit path.

Table 320. FRM_PMGR10, Performance Monitor Global Register 10 (R/W) These bits enable the errored events used to determine errored and severely errored seconds in the CEPT modes.

• P = 0x0 for the receive path, and P = 0x1 for the transmit path.

Table 321. FRM_PMGR11, Performance Monitor Global Register 11 (R/W)

• P = 0x0 for the receive path, and P = 0x1 for the transmit path .

which a reframe may be forced. ting the CRE bit status indication.

Table 322. FRM_PMGR12, Performance Monitor Global Register 12 (R/W)

• P = 0x0 for the receive path, and P = 0x1 for the transmit path.

Table 323. FRM_PMGR13, Performance Monitor Global Register 13 (R/W)

• P = 0x0 for the receive path, and P = 0x1 for the transmit path .

12 FRM_CRAI_SA6EQC Send RAI Upon Detection of Sa6 = (0xC) Enable in CEPT

11 FRM_CRAI_SA6EQ8 Send RAI Upon Detection of Sa6 = (0x8) Enable in CEPT

10 FRM_CRAI_CRCTX Send RAI Upon Detection of CRCTX Enable in CEPT

9 FRM_CRAI_LTS0MFA Send RAI Upon Detection of LTS0MFA Enable in CEPT

8 FRM_CRAI_LTS16MFA Send RAI Upon Detection of LTS16MFA Enable in CEPT

7 FRM_CRAI_8MSEX Send RAI Upon Detection of 8 ms Timer Expiration

3 FRM_CFBE_MODE CEPT FBE Mode. 0 = Count only FBEs received in FAS frame.

2 FRM_CEBIT_LTS0MFA Set E Bits Upon Detection of LTS0MFA Enable (CEPT

1 FRM_CEBIT_ESMF Set E Bits Upon Detection of an Errored CEPT_CRC4

0 FRM_CEBIT_CRCTX Set E Bits Upon Detection of CRCTX Enable (CEPT

Table 324. FRM_PMGR14, Performance Monitor Global Register 14 (R/W)

• P = 0x0 for the receive path, and P = 0x1 for the transmit path.

Table 325. FRM_PMGR15, Performance Monitor Global Register 15 (R/W)

• P = 0x0 for the receive path, and P = 0x1 for the transmit path.

Table 326. FRM_PMGR16, Performance Monitor Global Register 16 (R/W)

• P = 0x0 for the receive path, and P = 0x1 for the transmit path .

should be set to 1 before enabling the detection circuitry. check for the selected pattern or its inverse. toring for either framed or unframed test pattern. cate which link to monitor for test patterns. 3:0 FRM_PTRN_SEL[3:0] Receive Pattern Select. 0000 = Pattern detector deactivate. 20 – 1 with zero suppression).

12.4 HDLC Global Configuration and Status Registers

Table 327. FRM_HGR1, Transmit HDLC Global Register 1 (R/W) Table 328. FRM_HGR2, Transmit HDLC Global Register 2 (R/W) Table 329. FRM_HGR3, Transmit HDLC Global Register 3 (R/W) Table 330. FRM_HGR4, Transmit HDLC Global Register 4 (R/W) with the FRM_HTTHRSEL (Table 436) parameter. with the FRM_HTTHRSEL (Table 436) parameter. FRM_HXPIDLE[1:0] (Table 436) parameter.

Table 331. FRM_HGR5, Transmit HDLC Global Register 5 (R/W) Table 332. FRM_HGR6, Transmit HDLC Global Register 6 (R/W) Table 333. FRM_HGR7, Transmit HDLC Global Register 7 (R/W) Table 334. FRM_HGR8, Transmit HDLC Global Register 8 (R/W) Table 335. FRM_HGR9, Transmit HDLC Global Register 9 (R/W) FRM_HXPIDLE[1:0] (Table 435) parameter. FRM_HXPIDLE[1:0] (Table 435) parameter. the FRM_CFLAGS[1:0] (Table 435) parameter. the FRM_CFLAGS[1:0] parameter. the FRM_CFLAGS[1:0] (Table 435) parameter.

Table 336. FRM_HGR10, Transmit HDLC Global Register 10 (R/W) Table 337. FRM_HGR11, Transmit HDLC Global Register 11 (RO ) Table 338. FRM_HGR12, Transmit HDLC Global Register 12 (R/W) Table 339. FRM_HGR13, Transmit HDLC Global Register 13 (R/W) Table 340. FRM_HGR14, Transmit HDLC Global Register 14 (R/W) Table 341. FRM_HGR15, Receive HDLC Global Register 15 (R/W) additional idle flags to be sent between HDLC packets. basis with the FRM_CFLAGS[1:0] parameter. maps channels 15— 0 to bits 15:0. maps channels 31— 16 to bits 15:0. maps channels 47— 32 to bits 15:0. maps channels 63— 48 to bits 15:0. 9:0 FRM_HRTHRSH0[9:0] Indicates the Threshold Levels for the Rx FIFOs. with the FRM_RTHRSEL (Table 442) parameter.

Table 342. FRM_HGR16, Receive HDLC Global Register 16 (R/W) Table 343. FRM_HGR17, Receive HDLC Global Register 17 (R/W) Table 344. FRM_HGR18, Receive HDLC Global Register 18 (R/W) Table 345. FRM_HGR19, Receive HDLC Global Register 19 (R/W) Table 346. FRM_HGR20, Receive HDLC Global Register 20 (R/W) 9:0 FRM_HRTHRSH1[9:0] Indicates the Threshold Levels for the Rx FIFOs. FRM_RTHRSEL ( Table 442) parameter. maps channels 15— 0 to bits 15:0. maps channels 31— 16 to bits 15:0. maps channels 47— 32 to bits 15:0. maps channels 63— 48 to bits 15:0.

12.5 System Interface Global Registers

Table 347. FRM_SYSGR1, System Interface Global Register 1 (R/W) 0x80050 15:12 FRM_SYSMOD[3:0] System Interface Mode Associated Signaling Mode. 0100 = 19.44 Mbits/s PSB (device 0 mode). 0101 = 19.44 Mbits/s PSB (device 1 mode). 0110 = 19.44 Mbits/s PSB (device 2 mode). 11 FRM_ASM System Interface Mode Associated Signaling Mode. 0 = CHI is configured to carry payload data only. is forwarded to the signaling block. 10 FRM_CMS CHI Clock Mode. This bit is only applicable in the CHI mode. Otherwise, it should be set to 0. 0 = CHI clock and CHI data have the same rate. 1 = CHI clock is twice the rate of CHI data. 0 = Enables 32 contiguous time slots.

8 FRM_STUFFL/

on the NSMI. Internally, links are numbered starting at 1. 0 = NSMI link numbering starts at 0. 1 = NSMI link numbering starts at 1.

Table 347. FRM_SYSGR1, System Interface Global Register 1 (R/W) (continued) Table 348. FRM_SYSGR2, System Interface Global Register 2 (R/W) 0x80050 7 FRM_AISLFA System AIS on Loss of Frame Alignment. loss of frame alignment (MFA for DS1, BFA for CEPT) is detected. 6 FRM_AISCRCT System AIS on CEPT Timer Expiration. 5 FRM_DNOTFAS CEPT Dual Not FAS. This bit is applicable in all system modes. receive system interface expects both FAS and NOTFAS time slots. NOTFAS that is repeated twice. 4 FRM_TFSCKE System Interface Transmit Frame Sync Clock Edge Select. 0 = Transmit frame sync is sampled on the falling edge of transmit clock. 1 = Transmit frame sync is sampled on the rising edge of transmit clock.

3 FRM_FSPOL

0 = T ransmit and receive frame sync is active low. 1 = T ransmit and receive frame sync is active-high. 0x80051 15 FRM_HWYENA Transmit System Interface Highway Enable. allows the framer to be fully configured before transmission. 1 = Transmit and receive data is enabled.

14 FRM_RSTDONE

0 = Indicates internal reset is still in process. 1 = Indicates internal reset is complete.

Table 349. FRM_SYSGR3, System Interface Global Register 3 (R/W) Table 350. FRM_SYSGR4, System Interface Global Register 4 (R/W) Table 351. FRM_SYSGR5, System Interface Global Register 5 (R/W) Table 352. FRM_SYSGR6, System Interface Global Register 6 (COR) 1 = Receive CHI time slot is looped back to the system. of the looped back time slot to the line.

14 FRM_STSLLB

CHI Time-Slot Line Loop Back. back time slot to the system. 0 = Odd data parity is transmitted by the system. 1 = Even data parity is transmitted by the system. 0 = Odd signaling parity is transmitted by the system. 1 = Even signaling parity is transmitted by the system.

Table 353. FRM_SYSGR7, System Interface Global Register 7 (COR) Table 354. FRM_SYSGR8, System Interface Global Register 8 (R/W) Table 355. FRM_SYSGR9, System Interface Global Register 9 (R/W) cates a frame sync error was detected in PSB mode. causing an interrupt. A 0 allows the interrupt. 0 = Odd data parity is expected by the receive system. 1 = Even data parity is expected by the receive system. 0 = Odd signaling parity is expected by the receive system. 1 = Even signaling parity is expected by the receive system. 13 FRM_RFSCKE System Interface Receive Frame Sync Clock Edge Select.

Table 356. FRM_SYSGR10 — FRM_SYSGR14, System Interface Global Register 10— 14 (R/W) Table 357. FRM_SYSGR15, System Interface Global Register 15 (COR) Table 358. FRM_SYSGR16, System Interface Global Register 16 (R/W) dition that set it still exists after the read. cates a parity error was detected. status from causing an interrupt. A 0 allows the interrupt.

12.6 Signaling Global Registers

Table 359. FRM_SGR1, Receive Signaling Global Register 1 (R/W) Table 360. FRM_SGR2, Receive Signaling Global Register 2 (R/W) signaling configuration registers. 0 — Reserved. Must write to 0. Receive Signaling Change of State FIFO Depth Threshold.

Table 361. FRM_SGR3, Receive Signaling Global Register 3 (R/W) Table 362. FRM_SGR4, Receive Signaling Global Register 4 (RO) Table 363. FRM_SGR5, Receive Signaling Global Register 5 (RO) Receive Signaling Change of State FIFO Timer Threshold. be generated. The maximum timer setting is 8 s. 01 = The entry being read is the last valid entry. 11 = The entry being read is not the last valid entry. 00 = The entry being read is not valid and should be ignored. the new signaling state received.

Table 364. FRM_SGR6, Receive Signaling Global Register 6 Table 365. FRM_SGR7, Receive Signaling Global Register 7 (R/W)

2 FRM_R_COSDTHI Receive Signaling Change of State FIFO Depth Threshold

Super Mapper global registers.

0 FRM_R_COSOFI Receive Signaling Change of State FIFO Overflow Inter-

cessor interrupt if this bit is set to 1. rupt if this bit is set to 1.

Table 366. FRM_SGR8, Transmit Signaling Global Register 8 (R/W)

12.7 Frame Formatter (Transmit Framer) Global Register

Table 367. FRM_FFGR1, Transmit Framer Global Register 1 (R/W) 1 = Transmit an arbitrary FS when out-of-frame. 11 FRM_PTRN_EN Transmit Pattern. 10 FRM_PTRN_INV Transmit Pattern Normal/Invert Mode. This bit inverts the pattern. 9 FRM_PTRN_FRMT Transmit Pattern Framed/Unframed Mode. 8:4 FRM_PTRN_LNK[4:0] Pattern Generator Link Select. 5-bit link selection to indicate link for pattern insertion. 3:0 FRM_PTRN_SEL[3:0] Transmit Pattern Select. 0000 = Pattern generator deactivated. 20 – 1 with zero suppression).

12.8 Facility Data Link Global Registers

Table 368. FRM_FDLGR1, Receive Facility Data Link Global Register 1 (R/W) Table 369. FRM_FDLGR2, Transmit Facility Data Link Global Register 2 (R/W)

12.9 Super Mapper Framer Per Link Configuration and Status Registers

12.9.1 Signaling Per Link Registers

Table 370. Receive Path Signaling Register Addressing Map

• L and R represent hexidecimal digits used for absolute addressing in Table 372, Table 373, and Ta ble 37 4.

Table 371. Receive Path Signaling Registers Address Indexing Read: for link 1, the hexidecimal digit L is 0x0 and the hexidecimal digit R is 0x2.

Table 372. FRM_RSLR0— FRM_RSLR31, Receive Signaling Link Registers 0— 31 (R/W)

• See Table 371 for values of L and R.

Register includes the following bits: F , G— selects 2, 4, 16 or no state signaling mode; A, B, C, D— signaling data. For DS1 links, address locations 1 through 24 will contain valid data. be accepted and stored in signaling registers.

Table 373. FRM_RSLR32, Receive Signaling Link Register 32 (COR)

• See Table 371 for values of L and R.

alignment for the corresponding group. zeros in the Sp bit position of the corresponding HG. multiframe alignment has been established. Table 374. FRM_RSLR33, Receive Signaling Link Register 33 (R/W) to 0101 for 4-state and 16-state signaling, respectively. in transport mode; otherwise, it should be set to 0. in the system interface block. 0 = Will disable stomping for the corresponding link. 6 — Reserved. Must write to 0. signaling when extracted from the Rx line. link is byte sync mapped and uses the handling group format. the Rx line. A 1 halts the updates.

• See Table 371 for values of L and R.

Table 375. Transmit Path Signaling Register Addressing Map

• L and T represent hexidecimal digits used for absolute addressing in Table 377, Table 378, and Table 379.

Read: for link 1 (pertaining to Table 376), the hexidecimal digit L is 0x0 and the hexidecimal digit T is 0x3 . Table 376. Transmit Path Signaling Registers Address Indexing the F and G values used in handling the ABCD bits. 1 = Implied by the Tx path ASM. configured with an ASM CHI or parallel system bus interface. the source for the ABCD bits. 00 = Signaling programmed by the host. 01 = Signaling extracted from the Rx line. Table 374. FRM_RSLR33, Receive Signaling Link Register 33 (R/W) (continued)

Table 377. FRM_TSLR0— FRM_TSLR31, Transmit Signaling Link Registers 0— 31 (R/W)

• See Table 376 for values of L and T .

Register includes the following bits: F , G— selects 2, 4, 16 or no state signaling mode; A, B, C, D— signaling data. For DS1 links, address locations 1 through 24 will contain valid data. be accepted and stored in signaling registers. For CEPT links, inserted time slot 16 X bits are written to locates 0.

Table 378. FRM_TSLR32, Transmit Signaling Link Register 32 (R/W) *S e e Table 376 for values of L and T . when the receive path has lost TS16 alignment. sponds to the same HG in the Rx path. in each of the Sp bits of the HGs on each link. mode but no signaling data can be inserted. uses the handling group format. either the Rx system or the Rx line. A 1 halts the updates.

Table 378. FRM_TSLR32, Transmit Signaling Link Register 32 (R/W) (continued) *S e e Table 376 for values of L and T. Table 379. FRM_TSLR33, Transmit Signaling Link Register 33 (COR) *S e e Table 376 for values of L and T.

12.10 Performance Monitor Per Link Registers

over or saturate, and may be programmed to clear on read. Registers are only provisionable to clear-on-read (COR). Table 380. Performance Monitor Per Link Register Addressing Map

• L and P represent hexidecimal digits used for absolute addressing in Table 382 through Table 401.

the F and G values used in handling the ABCD bits. 1 = Sourced from the Rx system interface. be the source for the ABCD bits. 00 = Signaling programmed by the host. 01 = Signaling extracted from the Rx line. 10 = Signaling received from the system interface. alignment has been established.

Table 381. Performance Monitor Per Link Register Address Indexing Read: for link 1 on the receive path, the hexidecimal digit L is 0x0 and the hexidecimal digit P is 0x2. Table 382. FRM_PMLR1, Performance Monitor Link Register 1 (R/W) *S e e Table 381 for values of L and P . Table 383. FRM_PMLR2, Performance Monitor Link Register 2 (R/W) *S e e Table 381 for values of L and P . interrupt. A 0 allows an interrupt to be generated. 0 allows an interrupt to be generated.

Table 384. FRM_PMLR3, Performance Monitor Link Register 3 (R/W) *S e e Table 381 for values of L and P . rupt. A 0 allows an interrupt to be generated. Table 385. FRM_PMLR4, Performance Monitor Link Register 4 (COR) page 488 lists the loss of frame criteria for the framing bit. tion 4.3.2). The CRC error count is provisionable.

*S e e Table 381 for values of L and P . been lost when multiframe alignment is lost. with 0.15 s of all ones modified by the AIS-CI signature pattern. right-to-left at 386-bit intervals). It takes 4 ms to detect AIS-CI. Table 385. FRM_PMLR4, Performance Monitor Link Register 4 (COR) (continued)

*S e e Table 381 for values of L and P .

*S e e Table 381 for values of L and P . not detected during the read. 2.1.5.) This is the y-bit input from the signaling block.

*S e e Table 381 for values of L and P . on the TDM bus from the mapper. DDS: Bit 6 of time slot 24 is a 0 for 12 frames. Monitor Global Register 3 (R/W) on page 248. time. RAI is inactive when bit 3 is set to a 0. Monitor Link Register 13 (COR) on page 286.

• See Table 381 for values of L and P.

that either the 100 ms or the 400 ms interworking timer expired. one good multiframe bit is seen. CEPT with CRC-4 only. In all other modes, this bit is a 0. page 249 and CEPT links in Tabl e 3 19.

*S e e Table 381 for values of L and P . page 249 and CEPT links in Table 319 on page250. BES is not valid in any CEPT mode. Table 317. FRM_PMGR7, Performance Monitor Global Register 7 (R/W) on page 249 and for CEPT links in Section T able 320.

Table 386. FRM_PMLR5, Performance Monitor Link Register 5 (COR) *S e e Table 381 for values of L and P . and CEPT CRC-4 (G.704 section A.3) modes. second interval containing ≥991 E bit = 0 events in each second. 7F R M _ L T F A Loss of Transmit Frame Alignment. DS1: Always 0.

Table 386. FRM_PMLR5, Performance Monitor Link Register 5 (COR) (continued) *S e e Table 381 for values of L and P . dual-rail mode of operation. 10th occurrence of the BOM message.

Table 387. FRM_PMLR6, Performance Monitor Link Register 6 (COR) *S e e Table 381 for values of L and P . Table 388. FRM_PMLR7, Performance Monitor Link Register 7 (COR) *S e e Table 381 for values of L and P . tern is no longer being detected. could also be set by FF_PLB (manual PLB indication) input. when it is read if the pattern is no longer being detected. tern is no longer being detected. tern is no longer being detected.

Table 389. FRM_PMLR8, Performance Monitor Link Register 8 (COR) *S e e Table 381 for values of L and P . Table 390. FRM_PMLR9, Performance Monitor Link Register 9 (COR) *S e e Table 381 for values of L and P . Table 391. FRM_PMLR10, Performance Monitor Link Register 10 (COR) *S e e Table 381 for values of L and P . Table 392. FRM_PMLR11, Performance Monitor Link Register 11 (COR) *S e e Table 381 for values of L and P . Table 393. FRM_PMLR12, Performance Monitor Link Register 12 (COR) *S e e Table 381 for values of L and P . 0x8LP87 15:0 FRM_FBEC[15:0] Frame Bit Error Counter. loss of CRC multiframe alignment. counted during loss of CEPT CRC-4 multiframe alignment. ment. This detection is not qualified by Sa5 = 1. not counted during loss of CRC-4 multiframe alignment. This detection is not qualified by Sa5 = 1.

decoded from the A, Sa5, and Sa6 bits. The Sa6 code words are synchronized to the CRC-4 multiframe. Table 394. FRM_PMLR13, Performance Monitor Link Register 13 (COR) *S e e Table 381 for values of L and P .

13 FRM_FE_OP Defect FCET in the ET or FCDLd in the Digital Link Between V3

and V3 or Defect FCDLu Between the V3 and V3. AIS.

12 FRM_FE_N Reception of AIS at V3 Reference Point of LT and FC4 Simulta-

11 FRM_FE_M Reception of AIS at V3 Reference Point of LT (Reaction to FCDL

digital section and the exchange termination (ET) as defined in ETS 300 233 section 9.3 and Tables 3 and 4 . Table 395. FRM_PMLR14, Performance Monitor Link Register 14 (COR) *S e e Table 381 for values of L and P . Table 396. FRM_PMLR15, Performance Monitor Link Register 15 (COR) *S e e Table 381 for values of L and P . Table 397. FRM_PMLR16, Performance Monitor Link Register 16 (COR) *S e e Table 381 for values of L and P . Table 398. FRM_PMLR17, Performance Monitor Link Register 17 (COR) *S e e Table 381 for values of L and P . Table 399. FRM_PMLR18, Performance Monitor Link Register 18 (COR) *S e e Table 381 for values of L and P . 16-bit count of bursty errored seconds. 16-bit count of severely errored seconds.

Table 400. FRM_PMLR19, Performance Monitor Link Register 19 (COR) This register applies to the receive path only. *S e e Table 381 for values of L and P . Table 401. FRM_PMLR20, Performance Monitor Link Register 20 (COR) *S e e Table 381 for values of L and P .

12.11 Receive Facility Data Link Configuration and Status Registers

Table 402. Receive Facility Data Link Register Addressing Map

• L and R represent hexidecimal digits used for absolute addressing in Table 404 through Table 408.

ment is lost or handling groups are disabled.

00 L N K 4 L N K 3 L N K 2 L N K 1 L N K 0 R X P = 0 1100 R D L 3 R D L 2 R D L 1 R D L 0

Table 403. Receive Path Facility Data Link Registers Address Indexing Read: for link 1, the hexidecimal digit L is 0x0 and the hexidecimal digit R is 0x2. Table 404. FRM_RFDLLR1 — FRM_RFDLLR5, Receive FDL Link Registers 1— 5 (RO) *S e e Table 403 for values of L and R. Table 405. FRM_RFDLLR6, Receive FDL Link Register 6 (R/W) *S e e Table 403 for values of L and R. Table 406. FRM_RFDLLR7, Receive FDL Link Register 7 (RO) *S e e Table 403 for values of L and R. alignment can be established. before continuing to read the stack.

Table 407. FRM_RFDLLR8, Receive FDL Link Register 8 (COR) *S e e Table 403 for values of L and R. Table 408. FRM_RFDLLR9, Receive FDL Link Register 9 (R/W) *S e e Table 403 for values of L and R.

12.12 Transmit Facility Data Link Configuration and Status Registers

Table 409. Transmit Facility Data Link Register Addressing Map

• L and R represent hexidecimal digits used for absolute addressing in Ta bl e 4 11 through Table 415.

Table 410. Transmit Path Facility Data Link Registers Address Indexing Read: for link 1, the hexidecimal digit L is 0x0 and the hexidecimal digit T is 0x3. Table 411. FRM_TFDLLR1— FRM_TFDLR5, Transmit FDL Link Registers 1— 5 (COR) *S e e Table 410 for values of L and T . been filled with data following the format of the associated link.

00 L N K 4 L N K 3 L N K 2 L N K 1 L N K 0 T X P = 1 1101 T D L 3 T D L 2 T D L 1 T D L 0

Table 412. FRM_TFDLLR6, Transmit FDL Link Register 6 (R/W) *S e e Table 410 for values of L and T. Table 413. FRM_TFDLLR7, Transmit FDL Link Register 7 (R/W) *S e e Table 410 for values of L and T . block. 0 indicates that Sa8 is sourced from the framer Sa stack. block. 0 indicates that Sa7 is sourced from the framer Sa stack. block. 0 indicates that Sa6 is sourced from the framer Sa stack. block. 0 indicates that Sa5 is sourced from the framer Sa stack. block. 0 indicates that Sa4 is sourced from the framer Sa stack. inserted whenever the TDM data is requested. most bit being transmitted first.

Table 414. FRM_TFDLLR8, Transmit FDL Link Register 8 (RO/COW) *S e e Table 410 for values of L and T. Table 415. FRM_TFDLLR9, Transmit FDL Link Register 9 (R/W) *S e e Table 410 for values of L and T.

12.13 System Interface, Arbiter, and Frame Formatter Mapping

Table 416. System Interface, Arbiter, and Frame Formatter Link Register Addressing Map

• L and P represent hexidecimal digits used for absolute addressing in Ta bl e 41 9 through Ta bl e 42 5.

Table 417. System Interface, Arbiter, and Frame Formatter Link Register Address Indexing Read: for link 1 on the receive path, the hexidecimal digit L is 0x0 and the hexidecimal digit P is 0x2.

12.14 System Interface Per Link Registers

Table 418. FRM_SYSLR1, System Interface Link Register 1 (R/W) *S e e Table 417 for values of L and P . added to the offsets. CHI CMS mode only.

Table 419. FRM_SYSLR2, System Interface Link Register 2 (R/W) This register applies to the receive path only, inserted in the transmit system interface on demand. *S e e Table 417 for values of L and P . *S e e Table 417 for values of L and P . 0x8LPE1 15 FRM_CEPTMAIS Transmit CEPT TS16 AIS. 1 = Time slot 16 is forced to all ones. 14 FRM_CEPTAAIS Transmit CEPT TS16 AIS on Loss of MFA. 13 FRM_MANAIS Transmit System AIS. 1 = Transmit system AIS to the system. 12 FRM_CEPTSTMP Transmit System CEPT TS16 Stomp. changed to 1111 toward the transmit system interface. Table 420. FRM_SYSLR3— FRM_SYSLR6, System Interface Link Registers 3— 6 (R/W)

12.15 Arbiter Framer Per Link Registers

Table 421. FRM_ARLR1, Arbiter Link Register 1 (R/W) *S e e Table 417 for values of L and P . 0x8LPF0 15 FRM_LNK_ENA Link Enable. 14 FRM_LNK_TRANSP Transparent Mode Selection. 13 FRM_LNK_REST ARTN Restart Link. 1 = Normal operational mode for the link. 12 FRM_LNK_REFRAME Force Reframe. 0 = Normal operational mode for the link. 1 = Link is forced to reframe. 9 FRM_ICKEDGE Input Clock Edge Selection. 0 = Sample data on rising edge of input clock. 1 = Sample data on falling edge of input clock.

Table 422. FRM_ARLR2, Arbiter Link Register 2 (R/W) *S e e Table 417 for values of L and P . 0x8LPF1 15 FRM_ESF_CRC_EN CRC Framing Enable. 0 = ESF CRC framing disabled. 0 = Multiframe reframe disabled. errors will cause a search for a new multiframe alignment. 14 FRM_FAST Fast Frame Mode. 0 = Disable quick frame recovery. D4 and J-D4: 36 fewer frame bits are checked. 0 = Disable quick frame recovery. conditions results in a new search in frame (n + 2).

Table 422. FRM_ARLR2, Arbiter Link Register 2 (R/W) (continued) *S e e Table 417 for values of L and P . 0x8LPF1 13:12 FRM_OPT[1:0] Frame Options. Verify NOTFAS frame (n + 1). Verify second FAS in frame (n + 2). Verify second NOTFAS frame (n + 3). 11 FRM_FBE_MODE DDS FBE Mode. FBE for the time slot 24 frame alignment signal. 1 = Only 1 FBE is detected in a frame in DDS mode.

*S e e Table 417 for values of L and P . 0x8LPF1 10:8 FRM_LF_CRT[2:0] Loss of Frame Criteria. 000 = 2 errored framing bits out of 4 FT and FS bits. 001 = 2 errored framing bits out of 5 FT and FS bits. 010 = 2 errored framing bits out of 6 FT and FS bits. 100 = 2 errored framing bits out of 4 FT bits only. 101 = 2 errored framing bits out of 5 FT bits only. 110 = 2 errored framing bits out of 6 FT bits only. 000 = 3 consecutive errored FAS patterns. tive errored NOTFAS bits (bit 2). x10 = 3 consecutive errored frames (FAS and NOTFAS). forced to 1 when out of frame. 5:4 FRM_RAIL3_DEC[1:0] Third Rail Option. 00 = Third input signal to the frame aligner is ignored. passed through the frame aligner).

*S e e Table 417 for values of L and P . Table 423. FRM_ARLR3, Arbiter Link Register 3 (R/W) This register applies to the transmit path only. *S e e Table 417 for values of L and P . 0x8LPF1 3:0 FRM_MODE[3:0] Framing Mode. 0010 = CEPT with CRC-4 and 100 ms timer. 0100 = CEPT with CRC-4 and 400 ms timer. 1101 = J-D4 (SF with Japanese Y ellow Alarm). Framer Transmit Path Clock Source Enable. (Table 301) bit controls clock source. FRM_TP_CK_SRC and FRM_TP_DD_SRC.

14 FRM_TP_CK_

13 FRM_TP_DD_

Transmit Path Default Data Source. synchronization signal in the transmit framer formatter.

12.16 Frame Formatter Per Link Registers

Table 424. FRM_FFLR1, Frame Formatter Link Register 1 (R/W) *S e e Table 417 for values of L and P . 11 FRM_ESFRAMD ESF Remote Alarm Indicator Mode. 0 = Data link remote alarm sequence is 1111 1111 0000 0000. 1 = Data link remote alarm is all ones. 10:8 FRM_ZCSMD[2:0] Zero Code Suppression Modes. 001 = Set bit 6 (numbered 0— 7) of all time slots. 011 = Set bit 6 of all 0-byte time slots. 101 = Set bit 6 of all voice time slots. 111 = Set bit 6 of all 0-byte voice time slots. 6 FRM_OCKEDGE Output Clock Edge Selection. 0 = Data clocked out on rising clock edge. 1 = Data clocked out on falling clock edge. 3 FRM_AUTOPLB Automatic Payload Loopback (ESF Framing Only). 0 = Ignore received payload loopback requests. 2 FRM_AUTOLLB Automatic Line Loopback (SF and ESF Framing Only). 0 = Ignore received line loopback requests. 1 FRM_AUTOEBIT Automatic E-Bit Insertion (CEPT Framing Only). 0 = Ignore E-bit insertion requests from PM. 1 = Automatically insert E bits when indicated by PM. 0 FRM_AUTORAI Automatic RAI Insertion. 0 = Ignore RAI insertion requests from PM. 1 = Automatically insert RAI when indicated by PM.

Table 425. FRM_FFLR2, Frame Formatter Link Register 2 (R/W) *S e e Table 417 for values of L and P . 0x8LPF5 15:14 FRM_TXLBMD[1:0] Transmit Loopback Modes. 9 FRM_TXLLBOFF Transmit D4 SF Line Loopback Off Code. 0 = Do not transmit the D4 SF line loopback off code. 8F R M _ T X L L B O NTransmit D4 SF Line Loopback On Code. 0 = Do not transmit the D4 SF line loopback on code. 1 = On demand idle ID on (send idle ID). 1 = On demand AUXP on (send AUXP). 3 FRM_TXRAICI Transmit RAI-CI (ESF modes only). 1 = On demand RAI-CI on (send RAI-CI). 1 = On demand RAI on (send RAI). 1 FRM_TXAISCI Transmit AIS-CI (ESF modes only). 1 = On demand AIS-CI on (send AIS-CI). 1 = On demand AIS on (send AIS).

12.17 Line Decoder/Encoder Per Link Registers

Table 426. Line Decoder Per LInk Register Addressing Map

• L and R represent hexadecimal digits used for absolute addressing in Ta bl e 411 through Table 415.

Table 427. Line Decoder Per Link Registers Address Indexing Read: for link 1, the hexadecimal digit L is 0x0 and the hexadecimal digit T is 0x3. Table 428. Line Encoder Per Link Register Addressing Map

• L and R represent hexadecimal digits used for absolute addressing in Table 404 through Table 408.

Table 429. Line Encoder Per Link Registers Address Indexing Read: for link 1, the hexadecimal digit L is 0x0 and the hexidecimal digit R is 0x2.

00 L N K 4 L N K 3 L N K 2 L N K 1 L N K 0 T X P = 1 1111 1 1 0 0

00 L N K 4 L N K 3 L N K 2 L N K 1 L N K 0 R X P = 0 1111 1 1 0 0

12.18 Line Encoder/Decoder Per Link Registers

Table 430. FRM_LDLR1, Line Decoder Link Register 1 (R/W) *S e e Table 427 for values of L and T. Table 431. FRM_LDLR2, Line Encoder Link Register 2 (R/W) *S e e Table 429 for values of L and R. 5 FRM_EXCZERO Line Format Violation Option. 1 = Excessive zeros are included in bipolar violations. 4 FRM_RLCLK_EDGE Receive Line Clock Edge Select. itive edge of the receive line interface clock (RLCLK). ative edge of the receive line interface clock (RLCLK0). 2:0 FRM_LD_MODE[2:0] Line Decoder Mode. 000 = Single rail (CMI use single rail). 4 FRM_TLCLK_EDGE Transmit Line Clock Edge Select. edge of the transmit line interface clock (TL_CLK). edge of the transmit line interface clock (TL_CLK). 2:0 FRM_LE_MODE[2:0] Line Encoder Mode. 000 = Single rail (CMI use single rail).

12.19 HDLC Per Channel Configuration and Status Registers

Table 432. HDLC Per Channel Register Addressing Map

• H and P represent hexidecimal digits used for absolute addressing in Ta ble 43 3 through Ta ble 44 6.

Table 433. FRM_HCR1, Transmit HDLC Channel Register 1 (R/W) *S e e Table 432 for mapping of H and P. Table 434. FRM_HCR2, Transmit HDLC Channel Register 2 (R/W) *S e e Table 432 for mapping of H and P .

01 HDLC Channels 1 — 64 (000000— 111111) RXP= 0/

000 Per Channel Register

12:8 FRM_TTIMESLOT[4:0] Transmit HDLC Time-Slot. 7:0 FRM_TBIT_IM[7:0] Transmit HDLC Bit Assignment. assigned to this channel (1 = bit assigned). bered frames assigned to this channel. 10 = Data to odd frames selected (FT, NOTFAS, ESF-DL). 11 = Data to all (even and odd) frames selected. 4:0 FRM_TLINK[4:0] Transmit HDLC Link Select.

*S e e Table 432 for mapping of H and P . Table 435. FRM_HCR3, Transmit HDLC Channel Register 3 (R/W ) and clears the FIFO for the channel. value as currently programmed has no effect. onds of PRM information are valid. before enabling the Tx channel for loopback. selects FRM_HTTHRSH1 (Table 328)). FCS will not be inserted at the end of the packet.

Table 435. FRM_HCR3, Transmit HDLC Channel Register 3 (R/W) (continued) *S e e Table 432 for mapping of H and P. Table 436. FRM_HCR4, Transmit HDLC Channel Register 4 (RO) *S e e Table 432 for mapping of H and P. Table 437. FRM_HCR5, Transmit HDLC Channel Register 5 (R/W) *S e e Table 432 for mapping of H and P . with flags (01111110). A 1 means fill with idle (11111111). patterns to be sent when the Tx FIFO is empty.

Table 438. FRM_HCR6, Transmit HDLC Channel Register 6 (WO) *S e e Table 432 for mapping of H and P. Table 439. FRM_HCR7, Transmit HDLC Channel Register 7 (RO ) *S e e Table 432 for mapping of H and P. Table 440. FRM_HCR8, Receive HDLC Channel Register 8 (R/W) *S e e Table 432 for mapping of H and P. Table 441. FRM_HCR9, Receive HDLC Channel Register 9 (R/W) *S e e Table 432 for mapping of H and P . 00 = Add DATA to the Tx FIFO (non-EOP). FIFO for the specific channel. binary) the time slot number assigned to this channel. 01 = Data from even frames selected (Fs, FAS). 11 = Data from all (even and odd) frames selected. the link number assigned to this channel.

Table 442. FRM_HCR10, Receive HDLC Channel Register 10 (R/W) *S e e Table 432 for mapping of H and P. Table 443. FRM_HCR11, Receive HDLC Channel Register 11 (RO) *S e e Table 432 for mapping of H and P . selects FRM_HRTHRSH1[9:0] (Table 342)). FRM_MATCH[7:0] code is found.

Table 444. FRM_HCR12, Receive HDLC Channel Register 12 (R/W) *S e e Table 432 for mapping of H and P . channel’s idle detection interrupt. channel’s FIFO overflow interrupt. channel’s exceeded FIFO threshold interrupt.

Table 445. FRM_HCR13, Receive HDLC Channel Register 13 (RO) *S e e Table 432 for mapping of H and P. Table 446. FRM_HGR14, Receive HDLC Channel Register 14 (COR) *S e e Table 432 for mapping of H and P . empty and no information was available. FRM_HR_DATA[7:0] is status information. received was a complete byte. These bits should be ignored if EOP is 0.

Table 447. Framer Register Map Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.

0 FRM_AR_IS FRM_TP_

Table 447. Framer Register Map (continued)

13 Cross Connect (XC) Registers

13 Cross Connect (XC) Registers (continued)

13.1 Cross Connect Register Descriptions

Table 448. XC_ID_R, XC Global Register 1 (RO) Table 449. XC_CHI_MODE1_R, XC System Interface Global Register 1 (R/W) Table 450. XC_CHI_MODE2_R, XC System Interface Global Register 2 (R/W) 10:8 XC_VERSION[2:0] Version. These bits identify the version number of the XC. 2 — Reserved. Must write to 0. output transmit system data. Otherwise, set to 0. interface is in PSB mode; otherwise, 0 in CHI mode. put 4i – 1 is used as T1/E1 line output.

Table 452. XC_FRP_SRC[1— 14], XC1 Framer Receive Path Data Source Configuration (R/W) Table 453. XC_M13_SRC[1— 14], XC1 M13 Data Source Configuration (R/W)

000 TPG (Test-Pattern Generator)/Special 100 VTMPR (VT Mapper)

001 PIN (External I/O) 101 DJA (Jitter Attenuator)

010 FRM TP (Superframer) 110 FRM RP (Framer Line Interface)

011 M13 (M13 MUX) 111 FRM TS (Framer System Interface)

Table 451. XC_PIND_SRC[1— 15], XC1 External I/O TXDATA and TXCLK Source Configuration (R/W) Note: External I/O has 29 channels. Source Identifier for Framer Receive Path Connection. RP_RCLK, RP_RFS, RP_AIS, and RP_RAI (even channels). Source Identifier for Framer Receive Path Connection. RP_RCLK, RP_RFS, RP_AIS, and RP_RAI (odd channels). inputs if operating in LOW_CLOCK_OUT mode. inputs if operating in LOW_CLOCK_OUT mode.

Table 454. XC_VT_SRC[1— 14], XC1 VT Mapper Source Configuration (R/W) Table 455. XC_DJA_SRC[1— 14], XC1 Digital Jitter Attenuator Source Configuration (R/W) Table 456. XC_FTP_SRC[1— 14], XC1 Framer Transmit Path Data Source Configuration (R/W) Table 457. XC_FRS_SRC[1— 14], XC1 Framer Receive System Interface Source Configuration (R/W) DS1/E1 data, clock, sync, and RAI inputs (even channels). DS1/E1 data, clock, sync, and RAI inputs (odd channels). Source Identifier for Framer Transmit Path Connection. Framer transmit path DS1/E1 input signals (even channels). Source Identifier for Framer Transmit Path Connection. Framer transmit path DS1/E1 input signals (odd channels).

Table 458. XC_TPM_SRC[1— 4], XC1 Test-Pattern Monitor Source Configuration (R/W) Table 459. XC2_M12_SRC[1— 7], XC2 M12 DS2 Clock and Data Source Configuration (R/W) Table 460. XC2_M23_SRC[1— 7], XC2 M23 DS2 Data Source Configuration (R/W) identifier for TPM DS1 idle channel inputs. identifier for TPM E1 test channel inputs.

00 TPG (DS2 Test-Pattern Generator)

01 M13:M12 MUX

10 M13:M23 DeMUX

11 External I/O

multiplexers. Refer to M12 MUX section for more details. plexers. Refer to M12 deMUX section for more details.

Table 461. XC2_TPM_SRC, XC2 Test-Pattern Monitor Source Configuration (R/W) Table 462. XC_MISC, XC Global Register 2 (R/W) Table 463. XC3_TPM_SRC, XC3 Test-Pattern Monitor Source Configuration (R/W) mal DS2 clock and data input mode. the normal DS1 clock and data input mode. channel output and 0 to disable. channel output and 0 to disable. SPEMPR (logic 0) receive POAC channel. SPEMPR (logic 0) transmit POAC channel. 7 — Reserved. Must write to 0. 00 = TPM receives DS3 from external pins. 10 = TPM receives DS3 from SPE. 4:0 — Reserved. Must write to 0.

Table 464. XC3_MDS3_SRC, XC3 DS3 Source Configuration (R/W) Table 465. XC_PINS_SRC[1— 15], XC1 External I/O TXSYNC Source Configuration (R/W) Table 466. XC_ALCO_SRC[1 — 15], XC1 External I/O RXCLK Clock Out Source Configuration (R/W) tivity at DS3 level among external I/O, M13, and SPE. 00 = M13 inputs/outputs DS3 through external pins. 01 = M13 and SPE pass data to each other. is used as a monitor for the transmit DS3. is used as a monitor for the receive DS3. ensure the system data output properly. Note: External I/O has 29 channels. Note: External I/O has 29 channels.

13.2 Cross Connect Register Map

Table 467. Register Address Map Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.

0 XC_SYNC_

Table 467. Register Address Map (continued)

14 Digital Jitter Attenuation Controller Registers

Table 469. DJA_EVENT1— DJA_EVENT2, Loss of Clock and Overflow/Underflow Delta Table 471. DJA_STATE1— DJA_STATE2, Loss of Clock and VT Pointer Adjustment Indicators

14 Digital Jitter Attenuation Controller Registers (continued)

14.1 Digital Jitter Attenuation Controller Register Descriptions

indicate if the register is read only (RO), clear-on-read/clear-on-write (COR/COW), or read/write (R/W). Table 468. DJA_VERSION, DJA Version and Identification (RO) Table 470. DJA_MASK1— DJA_MASK2, Loss of Clock and Overflow/Underflow Masks (R/W) will change each time the device is changed.

14 DJA_DS1_MSK PIN_DS1XCLK Loss of Clock Indication

13 DJA_G_E1_MSK G_PIN_E1XCLK Loss of Clock Indication

Table 472. DJA_E1GAINH— DJA_E1GAINL, E1 Accumulator Gain Threshold (R/W) Table 473. DJA_DS1GAINH— DJA_DS1GAINL, DS1 Accumulator Gain Threshold (R/W) Table 474. DJA_E1SCALE, E1 Scale Factor (R/W) Table 475. DJA_DS1SCALE, DS1 Scale Factor (R/W) ment rates for E1 signals (see Table 622).

Table 476. DJA_E1PTRH— DJA_E1PTRL, E1 First-Order Loop Counter (R/W) Table 477. DJA_DS1PTRH — DJA_DS1PTRL, DS1 First-Order Loop Counter (R/W) Table 478. DJA_DS1SELH— DJA_DS1SELL, DS1 E1 Mode Select (R/W) Table 479. DJA_CLK_CTL1— DJA_CLK_CTL4, Reference Clock Rate and Edge Transitions (R/W)

16 X (01) the line rate or exactly the line rate

DS1/E1 data transitions (1 = rising edge). DS1/E1 data is retimed (1 = rising edge).

14.2 Digital Jitter Attenuation Controller Register Map

The register bank architecture of the microprocessor interface is shown in Table 76 on page73. Table 480. DJA Register Map Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.

15 Test-Pattern Generation/Detection Registers

15 Test-Pattern Generation/Detection Registers (continued)

15.1 Test-Pattern Generation/Detection Register Descriptions

register bits are indicated as either read/write (R/W) or read only (RO), and the value of the bits on reset is given. Table 481. TPG_ID, Status Register (RO) Table 482. TPG_ISRC_OOFD, Delta Register (RO) Table 483. TPG_ISRC_OOSD, Delta Register (RO)

2 TPM_OOF2D This bit is set when the TPM monitor E1 test signal out-of-frame

detector changes state (transitions).

0 TPM_OOF0D This bit is set when the TPM monitor DS1 test signal out-of-frame

detector changes state (transitions).

5 TPM_OOS5D This bit is set when the TPM monitor DS3 test signal out-of-sync

detector changes state (transitions).

4 TPM_OOS4D This bit is set when the TPM monitor DS3 test signal out-of-sync

detector changes state (transitions).

2 TPM_OOS2D This bit is set when the TPM monitor E1 test signal out-of-sync

detector changes state (transitions).

0 TPM_OOS0D This bit is set when the TPM monitor DS1 test signal out-of-sync

detector changes state (transitions).

Table 484. TPG_ISRC_BERE, Event Register (RO) Table 485. TPG_ISRC_FERE, Event Register (RO) Table 486. TPG_ISRC_BPVE, Event Register (RO)

5 TPM_BERE5 This bit is set when the TPM monitor determines that the incom-

ing DS3 test signal has a single bit error.

4 TPM_BERE4 This bit is set when the TPM monitor determines that the incom-

ing DS2 test signal has a single bit error.

2 TPM_BERE2 This bit is set when the TPM monitor determines that the incom-

ing E1 test signal has a single bit error.

0 TPM_BERE0 This bit is set when the TPM monitor determines that the incom-

ing DS1 test signal has a single bit error.

2 TPM_FERE2 This bit is set when the TPM monitor determines that the incom-

ing E1 test signal has a framing error.

0 TPM_FERE0 This bit is set when the TPM monitor determines that the incom-

ing DS1 test signal has a framing error.

2 TPM_BPVE2 This bit is set w hen the TPM monitor determines that the incom-

ing E1 test signal has a bipolar violation error.

0 TPM_BPVE0 This bit is set w hen the TPM monitor determines that the incom-

ing DS1 test signal has a bipolar violation error.

Table 487. TPG_ISRC_AISD, Delta Register (RO) Table 488. TPG_ISRC_CRCE, Event Register (RO) Table 489. TPG_IMSK_OOFD, Register (R/W) Table 490. TPG_IMSK_OOSD, Register (R/W)

5 TPM_AIS5D This bit is set when the TPM monitors DS3 test signal AIS detec-

tor changes state (transitions).

4 TPM_AIS4D This bit is set when the TPM monitors DS2 test signal AIS detec-

tor changes state (transitions).

2 TPM_AIS2D This bit is set when the TPM monitors E1 test signal AIS detector

changes state (transitions).

0 TPM_AIS0D This bit is set when the TPM monitors DS1 test signal AIS detec-

tor changes state (transitions).

2 TPM_OOF2DM This mask bit is set to suppress an interrupt when the TPM moni-

tor E1 test signal out-of-frame indicator changes.

0 TPM_OOF0DM This mask bit is set to suppress an interrupt when the TPM moni-

tor DS1 test signal out-of-frame indicator changes.

5 TPM_OOS5DM This mask bit is set to suppress an interrupt when the TPM moni-

tor DS3 test signal out-of-sync indicator changes.

4 TPM_OOS4DM This mask bit is set to suppress an interrupt when the TPM moni-

tor DS2 test signal out-of-sync indicator changes.

2 TPM_OOS2DM This mask bit is set to suppress an interrupt when the TPM moni-

tor E1 test signal out-of-sync indicator changes.

0 TPM_OOS0DM This mask bit is set to suppress an interrupt when the TPM moni-

tor DS1 test signal out-of-sync indicator changes.

Table 491. TPG_IMSK_BERE, Register (R/W) Table 492. TPG_IMSK_FERE, Register (R/W) Table 493. TPG_IMSK_BPV, Register (R/W)

5 TPM_BERE5M This mask bit is set to suppress an interrupt when the TPM moni-

tor determines that the incoming DS3 test signal has a bit error.

4 TPM_BERE4M This mask bit is set to suppress an interrupt when the TPM moni-

tor determines that the incoming DS2 test signal has a bit error.

2 TPM_BERE2M This mask bit is set to suppress an interrupt when the TPM moni-

tor determines that the incoming E1 test signal has a bit error.

0 TPM_BERE0M This mask bit is set to suppress an interrupt when the TPM moni-

tor determines that the incoming DS1 test signal has a bit error.

2 TPM_FERE2M This mask bit is set to suppress an interrupt when the TPM moni-

tor determines that the E1 test signal has a framing error.

0 TPM_FERE0M This mask bit is set to suppress an interrupt when the TPM moni-

tor determines that the DS1 test signal has a framing error.

2 TPM_BPV2M This mask bit is set to suppress an interrupt when the TPM moni-

tor determines that the E1 test signal has a bipolar violation error.

0 TPM_BPV0M This mask bit is set to suppress an interrupt when the TPM moni-

Table 494. TPG_IMSK_AISD, Register (R/W) Table 495. TPG_IMSK_CRCE, Register (R/W) Table 496. TPG_VAL_OOF, Register (RO)

5 TPM_AIS5DM This mask bit is set to suppress an interrupt when the TPM moni-

tor DS3 test signal AIS indicator changes.

4 TPM_AIS4DM This mask bit is set to suppress an interrupt when the TPM moni-

tor DS2 test signal AIS indicator changes.

2 TPM_AIS2DM This mask bit is set to suppress an interrupt when the TPM moni-

tor E1 test signal AIS indicator changes.

0 TPM_AIS0DM This mask bit is set to suppress an interrupt when the TPM moni-

tor DS1 test signal AIS indicator changes.

2 TPM_CRCE2M This mask bit is set to suppress an interrupt when the TPM moni-

tor detects an E1 test signal CRC-4 error.

0 TPM_CRCE0M This mask bit is set to suppress an interrupt when the TPM moni-

tor detects a DS1 test signal CRC-6 error.

2 TPM_OOF2 This status bit is set whenever the TPM E1 test monitor has

encountered an out-of-frame condition.

0 TPM_OOF0 This status bit is set whenever the TPM DS1 test monitor has

encountered an out-of-frame condition.

Table 497. TPG_VAL_OOS, Register (RO) Table 498. TPG_VAL_AIS, Register (RO) Table 499. TPG_VAL_FER, Register (RO)

5 TPM_OOS5 This status bit is set whenever the TPM DS3 test monitor has

encountered an out-of-sync condition.

4 TPM_OOS4 This status bit is set whenever the TPM DS2 test monitor has

encountered an out-of-sync condition.

2 TPM_OOS2 This status bit is set whenever the TPM E1 test monitor has

encountered an out-of-sync condition.

0 TPM_OOS0 This status bit is set whenever the TPM DS1 test monitor has

encountered an out-of-sync condition.

5 TPM_AIS5 This status bit is set whenever the TPM DS3 test monitor has

encountered an AIS condition.

4 TPM_AIS4 This status bit is set whenever the TPM DS2 test monitor has

encountered an AIS condition.

2 TPM_AIS2 This status bit is set whenever the TPM E1 test monitor has

encountered an AIS condition.

0 TPM_AIS0 This status bit is set whenever the TPM DS1 test monitor has

encountered an AIS condition.

2 TPM_FER2 This status bit is set whenever the TPM E1 test monitor has

encountered an FER condition.

0 TPM_FER0 This status bit is set whenever the TPM DS1 test monitor has

encountered an FER condition.

Table 500. TPG_VAL_CRCE, Register (RO) Table 501. TPG_BER_INSRT, Register (R/W) Table 502. TPG_FER_INSRT, Register (R/W) Table 503. TPG_CRCE_INSRT, Register (R/W)

2 TPG_CRCEINS2 This bit is set when the user desires to inject a single CRC error

into the E1 test signal (via 0 to 1 transition).

0 TPG_CRCEINS0 This bit is set when the user desires to inject a single CRC error

into the DS1 test signal (Via 0 to 1 transition).

5 TPG_BERINS5 This bit is set when the user desires to inject a single bit error into

SMPR_GTR, Global Trigger Register (RW) on pag e66).

4 TPG_BERINS4 This bit is set when the user desires to inject a single bit error into

the DS2 test signal via SMPR_BER_INSRT.

2 TPG_BERINS2 This bit is set when the user desires to inject a single bit error into

the E1 test signal via SMPR_BER_INSRT.

0 TPG_BERINS0 This bit is set when the user desires to inject a single bit error into

the DS1 test signal via SMPR_BER_INSRT.

2 TPG_FERINS2 This bit injects a single framing error into the E1 test signal (via 0

0 TPG_FERINS0 This bit injects a single framing error into the DS1 test signal (via

into the E1 test signal (via 0 to 1 transition). CRC-6 error Into the DS1 test signal (via 0 to 1 transition).

Table 504. TPG_ESFDL_TX, Register (R/W) Table 505. TPG_E1SA_TX12, Register (R/W) Table 506. TPG_E1SA_TX34, Register (R/W)

Table 507. TPG_CONFIG0, Register (R/W)

10 TPM_EDGE0 This bit, if set, selects the rising edge of XC_TCLK[0] for use as

the retiming clock edge; or else selects falling edge.

9 TPG_EDGE0 This bit, if set, selects the rising edge of TPG_CLK[0] for use as

the transmit clock edge; or else selects falling edge. Don ’t Use Line Coding/decoding when 00. Use HDB3 coding/decoding when 01. Use B8ZS coding/decoding when 10. Use AMI coding/decoding when 11. This code is common to the generator and monitor sides.

4 TPG_FINV0 If this bit is set, the frame bit in the 12th frame of each superframe

is inverted in the DS1 test pattern.

3 TPG_FRAME0 This bit is set to select a framed DS1 test pattern in the genera-

Transmitted by the TPG on the DS1 Test Output.

Table 508. TPG_CONFIG2, Register (R/W)

11 TPG_TPINV2 This Bit, if Set, Inverts the Transmitted Data for E1 Test Sig-

10 TPM_EDGE2 This Bit, if Set, Selects the Rising Edge of XC_TCLK[2] for

This bit is common to the generator and monitor sides. Don ’t uSe Line Coding/decoding when 00. Use HDB3 coding/decoding when 01. Use B8ZS coding/decoding when 10. Use AMI coding/decoding when 11. This code is common to the generator and monitor sides. 0011011) is Transmitted with the Last Bit Inverted (0011010).

Table 509. TPG_CONFIG4, Register (R/W)

12 TPM_TPINV4 This Bit, if Set, Inverts the Received Data for DS2 Test Sig-

11 TPG_TPINV4 This Bit, if Set, Inverts the Transmitted Data for DS2 Test Sig-

10 TPM_EDGE4 This Bit, if Set, Selects the Rising Edge of XC_TCLK[4] for

Transmitted by the TPG on the DS2 Output (TPG_DATA[4]).

Table 510. TPG_CONFIG5, Register (R/W) Table 511. TPG_USER, Register (R/W) Table 512. TPM_USER, Register (R/W) Table 513. TPG_BERCNT0, Register (RO)

12 TPM_TPINV5 This Bit, if Set, Inverts the Received Data for DS3 Test Sig-

11 TPG_TPINV5 This Bit, if Set, Inverts the Transmitted Data for DS3 Test Sig-

10 TPM_EDGE5 This Bit, if Set, Selects the Rising Edge of XC_TCLK[5] for

Transmitted by the TPG on the DS3 Output (TPG_DATA[5]). tern Bit Errors as Detected by the TPM.

Table 514. TPG_BERCNT2, Register (RO) Table 515. TPG_BERCNT4, Register (RO) Table 516. TPG_BERCNT5, Register (RO) Table 517. TPM_ESFDL_RX, Register (RO) Table 518. TPM_E1SA_RX12, Register (RO) Table 519. TPM_E1SA_RX34, Register tern Bit Errors as Detected by the TPM. tern Bit Errors as Detected by the TPM. tern Bit Errors as Detected by the TPM.

15.2 Test-Pattern Generation/Detection Register Map

Table 520. Test-Pattern Generation/Detection Register Map Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.

Table 520. Test-Pattern Generation/Detection Register Map (continued)

16 Microprocessor Interface Functional Description

355Agere Systems Inc. Preliminary Data Sheet TMXF28155 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

16 Microprocessor Interface Functional Description (continued)

16.1 Introduction

The Super Mapper microprocessor interface consists of a 20-bit address and a 16-bit data bus. In addition, this block contains global control and status registers. These registers include the summary of interrupt status of major functional blocks and the control to enable them or power them down.

16.2 Features

I 20-bit address/16-bit data bus microprocessor interface. I Synchronous (16 MHz to 66 MHz)/asynchronous microprocessor interface modes. I Microprocessor data bus parity monitoring. I Summary of interrupts from major functional blocks/maskable. I Separate device interrupt outputs for automatic protection switch and the Super Mapper global interrupt. I Global configuration of network performance monitoring counters operation. I Global software resets. I Global enabling and powering down of major functional blocks. I Miscellaneous global configuration and control.

16.3 Microprocessor Interface

This device is equipped with a generic 20-bit address/16-bit data microprocessor interface that allows operation with most commercially available microprocessors. Device input pin MPMODE (pin AD17) is used to configure this interface into one of two possible modes (synchronous or asynchronous). In synchronous mode (MPMODE = 1), the microprocessor interface can operate at speeds from 16 MHz up to 66 MHz. In asynchronous mode (MPMODE = 0), a 16 MHz to 66 MHz clock is required on the MPCLK (pin AE17) pin for proper operation. Two parity detectors are provided for the microprocessor data bus, one for the higher-order byte and one for the lower-order byte. The parity sense is programmed as even or odd with register bit SMP R_PARITY_EVEN_ODD (Table 67 on page68). The composite status of both parity detectors is indicated in register bit SMPR_ PARITY_IS (Table 63 on page64). The interrupt from this status indicator may be masked with register bit SMPR _PARITY_IM (Table 64 on page65). A bad parity event does not inhibit a data transfer. The microprocessor interface is fully functional without parity supplied by the host processor. The interrupt status from each of the major blocks, the automatic protection switch, and the microprocessor data bus parity are summarized in Table 63 on page 64. Each interrupt is maskable with the complementary bit set in the interrupt mask register, see Table 64 on page65.

16.4 MPU Block Diagram

Figure 18. Microprocessor Interface

16.5 Super Mapper Register Address Mapping

ble, device pins ADDR[19:16], and allocated a 16-bit address range, pins ADDR[15:0], as defined in Table 521. Table 521. Super Mapper Register Address Mapping

16.6 Performance Monitoring (PM) Counters Operation

anew. The count holding register holds the data that microprocessor actually reads.

Figure 19. PM Reset Counter SMPR_PMMODE[1:0] = 00, 10: PM counter control is sourced from external pin PMRST. no effect. The device pin, PMRST, is enabled as an output. Figure 20. PM Reset Signal Generation

358 Agere Systems Inc. TMXF28155 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 May 2001

16.7 Super Mapper Global Interrupt Status and Control

The Super Mapper provides two hardware interrupt output pins: one global (INTN pin AB24) and one for the SONET automatic protection switching (APS_INTN pin AC25). Both interrupt pins are active-low and are open- drain outputs to allow a wired OR with complementary devices. Interrupt status for major functional blocks are summarized in Table 63 and maskable in Ta ble 64.

16.8 Global Control

Several registers in this block provide global control of Super Mapper features. The register descriptions are self- explanatory, but some highlights are listed as follows: I Global enabling and powering down of major functional blocks is shown in Table 71 SMPR_CPCR, Clock and Power Control Register (RW) on page 71. I Software resets for major functional blocks are shown in Table 66 SMPR_MSRR, Block Software Reset Register (RW) on page66. I Global reset of the Super Mapper is controlled with SMPR_SWRS, bit 8 in Table 65 SMPR_GTR, Global Trigger Register (RW) on page 66.

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 359Agere Systems Inc.

17 TMUX Functional Description

17 TMUX Functional Description (continued)

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 361Agere Systems Inc.

17.1 TMUX Introduction

The TMUX multiplexer block implements SDH/SONET -compliant, byte-interleave multiplexing/demultiplexing, over- head insertion and termination, multiplex section protection (MSP) 1 + 1 switch capability, and serializer/deserial- izer for 155.52 Mbits/s and 51.84 Mbits/s traffic. As shown in Figure 23 on page 365, the TMUX provides three modes of operation: STS-3 mode, STM-1 mode, and STS-1 mode. In STS-3 mode, the TMUX implements the functions necessary to multiplex and demultiplex up to three STS-1 signals to/from a SONET STS-3 signal. In STM-1 (VC-4) mode, the TMUX provides the functionality to multiplex and demultiplex up to three TUG-3 signals to/from an STM-1(VC-4) signal. The device can also build/ extract up to three AU-3 signals to/from an STM-1(VC-3) stream. In STS-1 mode, the TMUX implements the func- tions necessary to interface a single STS-1 to/from an external serial link. On the high-speed side or line side, the block can be configured for either a 155.52 Mbits/s (STS-3/STM-1) or 51.84 Mbits/s (STS-1) serial data interface. On the low-speed side or tributary side, the TMUX provides a byte-wide bus that can communicate with up to three STS-1/TUG-3/AU-3 devices at a 19.44 MHz rate. If single STS-1 mode is employed, the bus rate will be 6.48 MHz. The TMUX therefore provides complete multiplexing/demultiplexing to/from an STS-3/STM-1 signal for up to 84 DS1, 84 JT1, or 63 E1 signals. In STS-1 mode, the TMUX provides multiplexing/demultiplexing for up to 28 DS1, 28 JT1, or 21 E1 streams. In STS-3/STM-1 mode, the TMUX from only one device is required. The TMUX in other connected devices may be powered down to reduce consumed power. This architecture allows flexible and modular growth in equipment capacity for both 51.84 Mbits/s and 155.52 Mbits/s links.

17.2 TMUX Features

I Multiplexes three STS-1 signals into a SONET STS-3 signal. I Multiplexes three VC-3 signals into an SDH STM-1 (AU-4) signal via a TUG-3 construction. I Multiplexes three VC-3 signals into an SDH STM-1 (AU-3) signal. I Demultiplexes three STS-1 signals from a SONET STS-3 signal. I Demultiplexes three VC-3 signals from an SDH STM-1 (AU-4) signal via a TUG-3 deconstruction. I Demultiplexes three VC-3 signals from an SDH STM-1 (AU-3) signal. I Provides STS-1-only mode for receive and transmit directions. I Provides complete functionality for SDH MSP 1 + 1 protection switching. I Detects STS-3/STM-1 loss-of-signal (LOS) conditions. I Detects STS-3/STM-1 out-of-frame and loss-of-frame (OOF/LOF) conditions. I Provides an 8-bit parallel bus interface that can accommodate up to three STS-1/AU-3s. I Provides STS-3/STM-1/STS-1 selectable scrambler/descrambler functions and B1/B2/B3 generation/detection. I Provides STS-3/STM-1/STS-1 pointer interpretation. Detects AIS-P and L OP.

17.3 TMUX Receive Path Overview

the telecom bus drop interface which drops traffic from up to three STS-1/TUG-3 paths on the TMUX receive path.

17.3.1 Receive Line Framer and Transport Overhead Termination

reported, and, if not masked, cause an interrupt. The B1 and B2 byte parity check supports bit and block modes. reached, or in a rollover mode. These counters should be optimally read (and cleared) at least once per second. ured to provide an interrupt to the control system, or the device can be operated in a polled mode.

17.3.2 Receive Transport Overhead Monitor and RTOAC Drop

576 kbits/s data stream onto the RTOAC drop channel. Figure 21. TMUX RTOAC Timing Diagram

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 363Agere Systems Inc.

17.3.3 Receive MSP 1 + 1 Payload Switch

Output from both receive framer blocks provides the input to the MSP 1 + 1 payload switch.This portion of the TMUX implements a payload 1 + 1 protection switch. In the receive direction, this occurs prior to pointer interpreta- tion. If the protection switch is activated, then the data is selected from the receive protection interface rather than from the high-speed input path. Only the selected input traffic is provided downstream to the pointer interpreter. The interface consists of a 155.52 MHz or 51.84 MHz clock, data, and sync pulse.

17.3.4 Receive Pointer Interpreter

The pointer interpreter is implemented via a state machine which implements the pointer interpretation algorithm described in ETS 300 417-1-1: January 1996 -Annex B. The pointer interpreter evaluates the current pointer state for the normal state, path AIS state, or LOP conditions, as well as pointer increments and decrements. The current pointer state and any changes in pointer condition are reported to the control system. The number of consecutive frames for invalid pointer and invalid concatenation indication is fixed at nine.

17.3.5 Receive High-Order Path Overhead Termination and RPOAC Drop

Path overhead (POH) termination is performed in the receive path on either all three STS-1s or on the VC-4 POH only. The receive POH circuitry includes: J1 byte monitoring, B3 byte BIP-8 checking, C2 byte signal label monitor- ing, REI-P and RDI-P detection, H4 byte multiframe monitoring; F2, F3, and K3 byte APS monitoring, N1 byte tan- dem connection monitoring (TCM), signal degrade BER and signal fail BER detection; receive path overhead access channel (RPOAC) drop, and AIS-P/HO-AIS insertion and automatic AIS generation (with individual inhibit). The J1 monitor provides five modes of operation for a programmable length (1 byte to 64 bytes) of the trace identi- fier. These five modes are comprised of: cyclic checking against the last received sequence, compare against a programmed sequence, SONET framing mode, SDH framing mode, and consecutive consistent occurrences of a new pattern. B3 is monitored either in bit or block mode. Provisionable N-times detection counters are implemented for the C2, F2, F3, N1, and K3 bytes. The K3 APS byte and N1 TCM byte can be monitored as an entire 8-bit word or two 4-bit nibbles. The receive RPOAC provides access to all the path overhead bytes. Even or odd parity is calculated over all bytes. The RPOAC has a data rate of 9 bytes per 8 kHz frame and consists of clock, data, and an 8 kHz sync pulse.

17.3.6 Receive Byte Interleave Demultiplexer

The byte interleave demultiplexer accepts serial traffic and demultiplexes that information into one (STS-1 mode) or three (STS-3/STM-1 mode) traffic streams for input via the telecom bus to the VT/VC mapper. The demultiplexer takes the bytes in the order they are presented and places that traffic onto the telecom bus.

17.3.7 Receive Telecom Bus

The TMUX can communicate with up to three SPE mappers via the telecom bus interface. In typical applications, since one SPE mapper is included in the Super Mapper device, two external SPE mappers reside on the telecom bus. The bus operates at 19.44 MHz for STS-3/STM-1 modes and at 6.48 MHz for STS-1 mode. In the receive direction, the Super Mapper outputs one parallel clock at 19.44 MHz, three sync signals (SPE, J0J1V1, and V1), an 8-bit data bus, and an odd/even parity bit. The data bus carries either three STS-1/TUG-3 signals, each in their own time slot, or it carries one STS-1 signal. A 51.84 MHz low-speed clock and sync signal is also output from this cir- cuit.

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 May 2001 364 Agere Systems Inc.

17.4 TMUX Transmit Path Overview

The TMUX transmit path is depicted in the top half of Figure 24 on page366. The transmit path of the TMUX imple- ments the inverse function to the receive path. Transmit input traffic at the telecom bus interface from up to three STS-1/TUG-3 paths is managed via the transmit path bus control circuitry. Transmit traffic, alarms, or unequipped indication information is inserted as needed depending on the status and provisioning of the device. The 3:1 multi- plexer provides byte interleave multiplexing of the incoming traffic and insertion of the path overhead bytes. A serial path provides input for the transmit protection traffic and the framer and serial-to-parallel converter formats this traf- fic for input to the transmit MSP 1 + 1 payload switch. The selected output from the transmit MSP 1 + 1 switch is input to the transport overhead insert block and the parallel to serial converter sends a serial stream to the device output. The TMUX transmit path provides path overhead byte insertion and transport overhead byte insertion via the respective POAC insert and TOAC insert interfaces. Local clock and frame generation control circuitry is implemented in the TMUX for controlling the STS-1, STS-3, and STM-1 termination and generation functions. Internal loopbacks in the TMUX provide near-end line loopback and far-end line loopback capability.

17.4.1 Transmit Telecom Bus

The transmit side of Super Mapper drives a clock and three sync signals (SPE, J0J1V1, and V1) onto the telecom bus. These signals control when the internal SPE m apper or one of the mate devices talks on the data bus. Because it is on the receive side, the transmit telecom bus operates at 19.44 MHz for STS-3/STM-1 modes and at 6.48 MHz for STS-1 mode. The TMUX communicates with up to three VT/VC mappers, via an 8-bit data word and an odd/even parity bit from the telecom bus. The data consists of the STS-1/TUG-3 from up to three mappers; each in its own time slot, or it carries one single STS-1 signal. A 51.84 MHz low-speed clock and sync are also output. Transmit High-Order Path Overhead Generation and TPOAC Insert. In the transmit direction, J1 path trace byte insertion, B3 byte calculation and insertion, C2 signal label byte insertion, REI-P and RDI-P insertion; F2 byte insertion, H4 multiframe byte insertion, F3 path user byte insertion, K3 byte insertion, N1 byte insertion, and AIS-P insertion via POAC or software control is supported. The transmit TPOAC allows insertion of all overhead bytes other than the B3 byte, which is automatically calculated. Even or odd parity is checked over all bytes. Bytes which are not enabled for insertion are set to an all-ones or all-zeros stuff value. Transport path overhead bytes are added to the payload stream during multiplexing in the byte interleave multiplexer. Transmit Byte Interleave Multiplexer. In STS-3/STM-1 mode, the transmit byte interleave multiplexer block multi- plexes up to three STS-1/TUG3 signals to form a SONET/SDH STS-3/STM-1 structured signal. The STS-3/STM-1 multiplexer function processes the input bytes in the order in which they are presented on the transmit telecom bus and multiplexes these bytes into a single high-speed stream. Grooming of the VTs/VCs is performed in the SPE mapper of each of the three devices. High-order path overhead bytes are interleaved with the data traffic during the byte interleave multiplexing. Transmit Payload Framer and MSP 1 + 1 Payload Switch. In the transmit direction, the MSP 1 + 1 switch func- tion incorporates dual MSP 1 + 1 payload switch structures. In operation, the traffic from the transmit byte inter- leave multiplexer are presented to both MSP 1 + 1 payload switches. The output of the signal from the 3:1 multiplex is broadcast to both switch paths, and the output of the receive payload framers is also input respectively to one of the two switch paths. For normal operation, one of the two outputs from the two MSP 1 + 1 blocks is selected. The path from the receive framer to the MSP switch structures provides a means to perform far-end loopback. Transmit Transport Overhead Generation and TTOAC Insert. The transmit transport overhead generator per- forms TTOAC byte insertion, sync status byte (S1) insertion, M0/M1— REI-L insertion, K1 and K2 byte insertion, AIS-L insertion, B2 byte calculation and insertion, F1 byte insertion, B1 byte generation and error insertion, scram- bling, J0 byte insertion control, and A2 byte error insertion. All insert control functions that are inhibited will insert optionally either an all-zeros or an all-ones word.

mode, the TTOAC channel will comprise a serial 192 kbits/s or a 576 kbits/s data stream. The insertion (overwrite by TOAC) of programmed S1, F1, J0, Z0-2, and Z0-3 bytes can be enabled via registers. the receive side. B1 and B2 BIP-8 values are calculated and inserted. Both values can be optionally inverted. Figure 22. TMUX TTOAC and RTOAC Timing Diagram Figure 23. High-Level TMUX Interconnect

Figure 24. Detailed Block Diagram of the TMUX

telecom bus in a parallel format. The TOH receive side functional blocks are shown in Figure 25. Figure 25. Receive Direction Functional Block Diagram

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 May 2001 368 Agere Systems Inc.

17.5 Receive Direction (Receive Path from Sonet Global/SDH)

All functions supported by the TMUX in the receive direction are summarized here: I Input clock monitoring and loss-of-signal monitoring I High-speed loopback I Frame alignment I Receive side frame sync output I B1 BIP-8 check I J0 monitor I Descrambler I F1 monitor I B2 BIP-8 check I APS (automatic protection switch) monitor I K2 monitor, AIS-L and RDI-L detect I M1 REI-L detect I Sync status monitor I Receive transport overhead access channel (RTOAC) I MSP 1 + 1 payload switch I Pointer interpreter I J1 monitor I B3 BIP-8 check I Signal label C2 byte monitor I RDI-P detect I REI-P detect I Path user byte F2 monitor I H4 multiframe indicator I Path user byte F3 monitor I K3 byte monitor I N1 tandem connection byte monitor I Signal degrade BER algorithm I Signal fail BER algorithm I Path overhead access channel (POAC) drop I AIS-P insertion and AUTO_AISO[1— 3] generation I Receive side telecom bus interface

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 369Agere Systems Inc.

17.5.1 Input Clock and Loss-of-Signal Monitoring

The TMUX detects and reports the loss of the 155 MHz input clock for STS-3 mode and the loss of the

51.84 MHz clock for STS-1 mode with register bits TMUX_RHSILOC— state (Table 91, starting on page92),

TMUX_RHSILOCD — delta state (Table 91, starting on page 92), TMUX_RHSILOCM — interrupt mask (Table 91, starting on page 92). LOC is determined by a stuck high or stuck low for a time greater than 10 µs and uses the microprocessor clock as its reference. The TMUX will detect and report a loss-of-signal condition with register bits TMUX_RHSLOS— state (Table 91 on page 92), TMUX_RHSLOSD — delta state (Table 91, starting on pag e92), TMUX_RHSLOSM — interrupt mask (Table 86 on page88), by monitoring the external input signal pin, LOSEXT (pin AE5), or detecting a continuous all-zeros/ones pattern for 51.44 ns to 105 µs in 51.44 ns steps before data is descrambled. The detection time is determined by the value programmed in register bits, TMUX_LOSDETCNT[ 10:0] (Table 97 on pag e97). The LOS state will clear after reception of two consecutive receive frames with the correct framing pattern spaced 125 µs apart without an incoming LOS all-zeros/ones pattern. This recovery applies to both internal and external LOS fail- ure causes.

17.5.2 High-Speed Loopback Select Logic

The device can be configured to loopback the transmit STS-3/STM-1 (AU-4) TMUX_THS2RHSLB = 1 (Table 93 on page 94) or accept the local STS-3/STM-1 (AU-4) signal TMUX_THS2RHSLB = 0.

17.5.3 Frame Alignment— STS-3/STM-1 (AU-4) Framing or STS-1 Framing

The device will frame on the incoming signal. The state of the framer, out of frame (OOF) (register bit TMUX_RHSOOF , see Table 91 on page92) as well as any changes to this state (register bits TMUX_RHSOOFD— delta state, see Table 91, starting on pag e92 and TMUX_RHSOOFM — interrupt mask; see Table 86 on page88) will be reported. The 32-bit (A1-2, A1-3, A2-1, and A2-2) framing pattern will be used in the frame detection for the STS-3/STM-1 case and a 16-bit pattern will be used for the STS-1 case. The device will be considered out of frame until two successive framing patterns separated in time by 125 µs occur without framing byte errors. The device will be considered in frame until five successive frames, separated in time by 125 µs, occur with errored framing patterns. If the framer transitions to the out of frame state, the framer will remain synchronized to the last known frame boundary or the latest detected unerrored framing pattern. A loss of frame (LOF) (register bit TMUX_RHSLOF; see Table 91 on page 92) state bit as well as any changes to this state (register bits TMUX_RHSLOFD— delta state, see Table 91, starting on page92, TMUX_RHSLOFM — interrupt mask; see Table 86 on page88) will be reported. These state and mask and delta bits are the same for both types of input data, STS-3/STM-1 or STS-1. The device will be considered in the LOF state when an OOF condition persists for 24 consecutive frames (3 ms). The device will transition out of the LOF state after receiving 24 consecutive frames with the correct framing pat- terns spaced 125 µs apart and the OOF condition is clear.

17.5.4 B1 BIP-8 Check

A BIP-8 even parity will be computed over all the incoming bits of the STS-3/STM-1 frame (STS-1 frame in STS-1 mode), which are scrambled (except for the bits in the A1, A2, and J0/Z0 bytes) and compared to the B1 byte received in the next frame. The total number of B1 BIP-8 bit errors (raw count), or block errors (as determined by register bit TMUX_BITBLKB1; see Table 95 on page 95), are counted. Upon the assertion of the performance monitor control signal as configured in the microprocessor interface block, the raw count will be reset to zero and the value trans- ferred to a 16-bit counter for B1 error counts B1ECNT[15:0] (Table 124 on pag e118).

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 May 2001 370 Agere Systems Inc. In case of overflow, depending on the value programmed in the microprocessor interface register bit SMPR_SAT_ROLLOVER ( Table 67 SMPR_GCR, Global Control Register (RW) on page 68), the B1 error counter will either roll over or saturate at the maximum value until cleared.

17.5.5 J0 Monitor

J0 (section trace overhead) monitoring is done via register bits TMUX_J0MONMODE[2:0] (Table 95 on pag e95). This J0 monitoring has six different monitoring modes, as follows: I TMUX_J0MONMODE[2:0] = 000: the TMUX latches the value of the J0 byte every frame for a total of 16 bytes into registers TMUX_J0DMON[16— 1][7:0]; see Table 132 on page121. The TMUX compares the incoming J0 byte with the next expected value (the expected value is obtained by cycling through the previously stored 16 received bytes in round-robin fashion) and, if different, setting the section trace identifier mismatch state register bit, TMUX_RTIMS, see Table 91 on page92. Any change to TMUX_RTIMS will be reported via delta and interrupt register bits TMUX_RTIMSD; see Table 82, starting on pag e79 and TMUX_RTIMSM; see Table 86 on page88. I TMUX_J0MONMODE[2:0] = 001: this is the SONET framing mode. The hardware looks for a 0x0A character to indicate that the next byte is the first byte of the path trace message. The J0 byte message is continuously writ- ten into TMUX_J0DMON[1— 16][7:0] registers with the first byte residing at the first address. If any received byte does not match the previously received byte for its location, then the state register bit, TMUX_RTIMS, is set. Any change to RTIMS will be reported via delta and interrupt mask register bits TMUX_RTIMSD and TMUX_RTIMSM. I TMUX_J0MONMODE[2:0] = 010: this is the SDH framing mode. The hardware looks for the byte with the most significant bit (MSB) set to one, which indicates that the next byte is the second byte of the message. The rest of operation is the same as in SONET framing mode. I TMUX_J0MONMODE[2:0] = 011: a new J0 byte (TMUX_J0DMON[1][7:0]) will be detected after the number of consecutive consistent occurrences of a new pattern in the J0 overhead byte as determined by the values in reg- isters TMUX_CNTDJ0[3:0]; see Table 98 on page98. Any changes to this byte are reported via delta and inter- rupt mask registers TMUX_RTIMSD and TMUX_RTIMSM. The TMUX_RTIMSD delta bit in this mode indicates a change in state for the TMUX_J0DMON[1][7:0] byte and the state register bit, TMUX_RTIMS, is not used. I TMUX_J0MONMODE[2:0] = 100: the user will program the 16 expected values of J0 in the SONET frame into registers TMUX_EXPJ0DMON[1 — 16][7:0]; see Table 131 on page 121. The first expected byte, the byte follow- ing the 0x0A character, is written into the first location TMUX_J0DMO N[1][7:0]. The TMUX compares the incom- ing J0 sequence with the stored expected value and sets the state register bit, TMUX_RTIMS (Table 91 on page 92), if they are different. Any change to TMUX_RTIMS is reported via register bits TMUX_RTIMSD (delta state) and TMUX_RTIMSM (interrupt mask). I TMUX_J0MONMODE[1:0] = 101: the user will program the 16 expected values of J0 in the SDH frame in regis- ters TMUX_EXPJ0DMON[1 — 16][7:0]. The first byte of the message has the MSB set to 1. The TMUX compares the incoming J0 sequence with the stored expected value, setting the state register bit, TMUX_RTIMS, if they are different. Any change to TMUX_RTIMS will be reported via register bits TMUX_RTIMSD (delta state) and TMUX_RTIMSM (interrupt mask). I TMUX_J0MONMODE[1:0] = 110 and 111 are currently undefined.

17.5.6 Descrambler

A frame synchronous descrambler of length 127 and generating polynomial x 7 + x6 + 1 will descramble the entire STS-3/STM-1 (or STS-1) signal except for the first row of overhead. The scrambler will be set to 1111111 on the first byte following the last section overhead byte in the first row (i.e., after byte J0 for STS-1). The descrambler operates in a byte-wide mode. The frame descrambler can be enabled or disabled using register bit TMUX_RHSDSCR (Table 93 on page94).

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 371Agere Systems Inc.

17.5.7 F1 Monitor

The TMUX monitors the fault location byte TMUX_RF1MON0[7:0] (Table 101 on page 100). A new fault location state will be detected after the number of consecutive consistent occurrences of a new pattern in the F1 overhead byte as determined by the value programmed in TMUX_CNTDF1[3:0] (Table 98 on pag e98). The TMUX maintains a history of the previous, valid F1 byte in TMUX_RF1MON1[7:0] (Table 101 on pag e100), and any changes will be reported via TMUX_RF1MOND (delta state) (Table 82, starting on pag e79) and TMUX_RF1MONM — (interrupt mask) (Table 86 on page88). This continuous N-times detection counter will be reset to 0 upon the transition of the framer into the out of frame state.

17.5.8 B2 BIP-8 Check

A B2 BIP-8 even parity is computed over all the incoming bits (except for the nine section overhead bytes) of the STS-1 frame after descrambling, and compared to the B2 byte received in the next frame. The total number of B2 BIP-8 bit errors (raw count), or block errors (as determined by TMUX_BITBLKB2; Table 94 on page 94), is counted. Upon the assertion of the performance monitor control signal as configured in the microprocessor interface, the raw count will be reset to zero and the value transferred to an 18-bit holding register for B2 error counts (TMUX_B2ECNT[17:0]; see Table 125 on page119). In case of overflow, depending on the value programmed in the microprocessor interface register bit SMPR_SA T_ROLLOVER (Table 67 on pag e68), the B2 error counter will either roll over or saturate at the maximum value until cleared.

17.5.9 Automatic Protection Switch (APS) Monitor

The TMUX monitors the receive APS value (the K1 byte, and the five most significant bits of the K2 byte) and stores this value in TMUX_RAPSMON[12:0] (Table 102 on page100). This register is updated after the reception of a programmed number of identical consecutive frames as determined by the value in TMUX_CNTDK1K 2[3:0] (Table 98 on page98). Whenever the contents of TMUX_RAPSMON[12:0] changes, a delta bit, TMUX_RAPSMOND will be set (Table 82, starting on page 79) and the interrupt can be masked using TMUX_RAPSMONM ( Table 86 on pag e88). This indication also contributes to a separate device interrupt indica- tion specifically intended for automatic protection switching. The TMUX monitors this same 13-bit APS value (K1[7:0], K2[7:3]) in the receive direction and reports when the APS value is inconsistent, using TMUX_RAPSBABE— Receive APS Babble Event (Table 82 on pag e79) and TMUX_RAPSBABM — Receive APS Babble Mask (Table 86 on page 88). Inconsistent APS bytes are defined as the number of successive frames of ASP data where no frames satisfy the criteria for updating the TMUX_RAPSMON register (Table 102 on page100). The number of inconsistent frames allowed before reporting is programmed in TMUX_CNTDK1K2FRAME[3:0] (default = 12, see Table 98 on page98). This continuous N- times detection counter will be reset to 0 upon the transition of the framer into the out-of-frame state or upon the detection of a B1 error.

17.5.10 K2 Monitor, AIS-L and RDI-L Detect

The three least significant bits of K2 are independently monitored and the current value is stored in TMUX_K2MON[2:0] ( Table 102 on page100). The register will be updated after the programmed number of con- secutive identical K2[2:0] bits. This number is programmed by the value in TMUX_CNTDK2[3:0] (Table 98 on page 98). Whenever the contents of TMUX_K2MON[2:0] changes, a delta bit, TMUX_RK2MOND will be set (Table 82, starting on page79), and the interrupt can be masked using TMUX_RK2MONM (Table 86 on pag e88). The TMUX monitors for line AIS (AIS-L/MS-AIS) in the K2[2:0] bits (K2[2:0] = 111). When line AIS is detected, TMUX_RLAISMON ( Table 91 on page92) will be set to 1 after a number of consecutive occurrences of line AIS as determined by the value programmed in TMUX_CNTDK2[3:0]. Once set, AIS-L will be cleared after a number of consecutive frames of no line AIS as determined by this same value in TMUX_CNTDK2[3:0].

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 May 2001 372 Agere Systems Inc. Any change to TMUX_RLAISMON will be reported in TMUX_RLAISMOND (Table 82, starting on page 79) and the interrupt can be masked using TMUX_RLAISMONM (Table 86 on page 88). The TMUX monitors for a remote defect indication (RDI-L/MS-RDI) condition in the K2[2:0] bits (K2[2:0] = 110) .A line RDI condition will be detected and TMUX_RLRDIMON (Table 91 on page92) will be set to 1 after a number of consecutive occurrences of RDI as determined by the value in TMUX_CNTDK2[3:0]. Once set, RDI-L will be cleared after a number of consecutive frames of no RDI as determined by this same value programmed in TMUX_CNTDK2[3:0]. Any change to TMUX_RLRDIMON, will be reported in TMUX_RLRDIMOND (Table 82, start- ing on page79) and the interrupt can be masked using TMUX_RLRDIMONM ( Table 86 on page 88). This continu- ous N-times detection counter will be reset to 0 upon the transition of the framer into the out-of-frame state.

17.5.11 M1 REI-L Detect

One byte (M1) is allocated for use as a line remote error indication function (REI-L). For STS-3/STM-1 signals, all eight bits of the M1 byte are allocated for REI-L information. The REI-L value reflects the error count detected by the line terminating equipment (LTE) (using the line BIP-8 code) back to its peer LTE. For STS-3/STM-1 signals, the value of the error count can be up to 24. A value of 25 and above will be interpreted as no errors. If TMUX_R_M1_BIT7 ( Table 96 on pag e96) is 1, then the most significant bit of the byte is ignored. The TMUX allows access to the accumulated M1-REI errored bit count from the M1 byte via TMUX_M1ECNT[17:0] (Table 126 on page 119). The counter will count in bit or block mode, depend ing upon the value of TMUX_BITBLKM1 ( Table 94 on page94). At the selected performance monitor (PM) interval, the value of the inter- nal running raw counter is placed into a holding register, TMUX_M1ECNT[17:0], and then cleared. Depending on the value of SMPR_SAT_ROLLOVER (Table 67 on pag e68) in the microprocessor interface, the internal counter will either roll over or saturate at its maximum value until cleared.

17.5.12 Sync Status Monitor

The S1 byte is allocated for synchronization status. S1 bits [7:4] are used to convey a 4-bit code of which only six patterns are defined with the remaining codes reserved for quality levels defined by individual administrations. The S1 byte can be monitored in two modes: (1) as an entire 8-bit word or (2) as one 4-bit nibble (bits [7:4]), as pro- grammed by TMUX_S1MODE4 ( Table 95 on page 95). I TMUX_S1MODE4 = 0 the associated state, delta, and mask registers are TMUX_RS1MON[7:0] (Table 103 on page 100), TMUX_RS1MOND ( Table 82, starting on page79), and TMUX_RS1MONM ( Table 86 on page 88), respectively. I TMUX_S1MODE4 = 1 the associated state, delta, and mask registers are TMUX_RS1MON[7:4], TMUX_RS1MOND, and TMUX_RS1MONM. A new value will be detected after a programmed number of consecutive occurrences of a consistent new value in the incoming S1 byte as determine by the value in TMUX_CNTDS1[3:0] (Table 98 on page98). A maskable event, TMUX_RS1BABE ( Table 82, starting on page79), is set if a programmed number of consecutive frames pass with- out a validated message occurring as determined by the value in TMUX_CNTDS1FRAME[3:0] (Table 98). In 8-bit mode, the entire value is monitored for an inconsistent value, while in 4-bit mode, only the most significant nibble is monitored for an inconsistent value. This continuous N-times detection counter will be reset to 0 upon the transition of the framer into the out-of-frame state.

17.5.13 Receive Transport Overhead Access Channel (RTOAC)

A transport overhead access channel (TOAC) is provided on-chip to drop the transport overhead (TOH) portion of the incoming SDH or SONET frame. The TOAC channel supports three modes of operation based on the configu- ration of TMUX_RTOAC_D13MODE and TMUX_RTOAC_D412MODE ( Table 117 on page113).

the values of TMUX_RTOAC_D13MODE and TMUX_RTOAC_D412MODE. See Table 522 below. the values of TMUX_RTOAC_D13MODE and TMUX_RTOAC_D412MODE. See Table 522 below. (the eighty-first byte for all TOH modes), the sync signal is driven high. order: DCC1, DCC2, and DCC3. The data signal is partitioned into frames of 3 bytes with a repetition rate of 8 kHz. Receive TOAC DCC4 — DCC12 Mode. In this mode, DCC bytes 4 — 12 are transmitted serially on the data output. frames of 9 bytes. The frame repetition rate is 8 kHz. frame repetition rate is 8 kHz. Each byte consists of 8 bits that are transmitted/received most significant bit first. remaining 7 bits of this byte are not specified. dard, but are available on the receive TOAC data signal. Table 522. Receive TOAC Modes Table 523. Transport Overhead Byte Access— Receive Direction

going frame by programming TMUX_RTOAC_OEPINS (Table 117 on pag e113).

17.5.14 MSP 1 + 1 Payload Switch

normal (working) path device pins, RHSDP/N (pins AF7/AE7) and RHSCP/N (pins AC7/AD8).

17.5.15 Pointer Interpreter

INC, DEC, and NDF states into the LOP state have been added. Figure 26. Pointer Interpretation State Diagram

8 INVALID POINTERS

3 NEW POINTERS

8 NDF ENABLE

3 ANY 3 ANY

3 ANY POINTERS

8 INVALID

8 INVALID POINTERS*

3 AIS INDICATIONS

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 375Agere Systems Inc. I The pointer interpreter transitions into the LOP state based on the following conditions: — Continuous NDF. If NDF (1001, 0001, 1101, 1011, and 1000) is received in 8, 9, or 10 consecutive frames, as determined by the value in TMUX_CTDLOPCNT[1:0] (Table 98 on page98), then LOP will be declared. — Invalid pointer values. If 8, 9, or 10 consecutive frames (determined by TMUX_CTDLOPCNT[1:0]) are received with a pointer that is not a normal value, NDF, AIS, increment, or decrement, then LOP will be declared. I The pointer interpreter will transition out of the LOP state based on the following conditions: — Following three consecutive frames with all ones in the H1 and H2 bytes, the pointer interpreter will transition from the LOP state into the AIS state. — Following three new consecutive, consistent, and valid pointers, the pointer interpreter will transition from the LOP state into the NORM state. — The pointer interpreter will not transition from the LOP state into the NDF state. I The pointer interpreter will transition into the AIS state based on the following conditions: — Following three consecutive frames with all ones in the H1 and H2 bytes, AIS will be declared. I The pointer interpreter will transition out of the AIS state based on the following conditions: — Following three new consecutive, consistent, and valid pointers, the pointer interpreter will transition from the AIS state into the NORM state. — Following eight consecutive invalid pointers, the pointer interpreter will transition from the AIS state into the LOP state. — If NDF is enabled on the incoming H1 and H2 bytes, the pointer interpreter will transition from the AIS state into the NDF state. I The pointer interpreter will transition into the NDF state based on the following condition: — If NDF is enabled on the incoming H1 and H2 bytes, the pointer interpreter will transition from the NORM, NDF , AIS, INC, and DEC states into the NDF state. I The pointer interpreter will transition out of the NDF state based on the following conditions: — Continuous NDF. If NDF (1001, 0001, 1101, 1011, and 1000) is received for eight consecutive frames, the pointer interpreter will transition from the NDF state into the LOP state. — Following any three consecutive, consistent, and valid pointers, the pointer interpreter will transition from the NDF state into the NORM state. — Following three consecutive frames with all ones in the H1 and H2 bytes, the pointer interpreter will transition from the NDF state into the AIS state. — Following three new, consecutive, consistent, and valid pointers, the pointer interpreter will transition from the NDF state into the NORM state. — Following eight consecutive invalid pointers, the pointer interpreter will transition from the NDF state into the LOP state. I The pointer interpreter will transition into the NORM state based on the following conditions: — Following three new consecutive, consistent, and valid pointers, the pointer interpreter will transition into the NORM state. — Following any three consecutive, consistent, and valid pointers, the pointer interpreter will transition into the NORM state, i.e., transitioning from the INC, DEC, and NDF states.

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 May 2001 376 Agere Systems Inc. I The pointer interpreter will transition out of the NORM state based on the following conditions: — Following eight consecutive invalid pointers, the pointer interpreter will transition from the NORM state into the LOP state. — If NDF is enabled on the incoming H1 and H2 bytes, the pointer interpreter will transition from the NORM state into the NDF state. — Following three consecutive frames with all ones in the H1 and H2 bytes, the pointer interpreter will transition from the NORM state into the AIS state. — When operating in the 8 of 10 mode, controlled by TMUX_8ORMAJORITY = 1 (Table 95 on page95), if 8 of the 10 I and D bits are correct for a pointer decrement on the incoming H1 and H2 bytes, the pointer inter- preter will transition from the NORM state into the DEC state. Otherwise, if 3 of the 5 I bits and 3 of the 5 D bits are correct for a pointer decrement on the incoming H1 and H2 bytes, the pointer interpreter will transition from the NORM state into the DEC state. — When operating in the 8 of 10 mode (TMUX_8ORMAJORITY = 1), if 8 of the 10 I and D bits are correct for a pointer increment on the incoming H1 and H2 bytes, the pointer interpreter will transition from the NORM state into the INC state. Otherwise, if 3 of the 5 I bits and 3 of the 5 D bits are correct for a pointer increment on the incoming H1 and H2 bytes, the pointer interpreter will transition from the NORM state into the INC state.The pointer interpreter will transition into the INC state based on the following conditions: — When operating in the 8 of 10 mode (TMUX_8ORMAJORITY = 1), if 8 of the 10 I and D bits are correct for a pointer increment on the incoming H1 and H2 bytes, the pointer interpreter will transition into the INC state. Otherwise, if 3 of the 5 I bits and 3 of the 5 D bits are correct for a pointer increment on the incoming H1 and H2 bytes, the pointer interpreter will transition into the INC state. I The pointer interpreter will transition out of the INC state based on the following conditions: — If NDF is enabled on the incoming H1 and H2 bytes, the pointer interpreter will transition from the INC state into the NDF state. — Following three consecutive frames with all ones in the H1 and H2 bytes, the pointer interpreter will transition from the INC state into the AIS state. — Following three new consecutive, consistent, and valid pointers, the pointer interpreter will transition from the INC state into the NORM state. — Following any three consecutive, consistent, and valid pointers, the pointer interpreter will transition from the INC state into the NORM state. — Following eight consecutive invalid pointers, the pointer interpreter will transition from the INC state into the LOP state. I The pointer interpreter will transition into the DEC state based on the following conditions: — When operating in the 8 of 10 mode (TMUX_8ORMAJORITY = 1), if 8 of the 10 I and D bits are correct for a pointer decrement on the incoming H1 and H2 bytes, the pointer interpreter will transition into the DEC state. Otherwise, if 3 of the 5 I bits and 3 of the 5 D bits are correct for a pointer decrement on the incoming H1 and H2 bytes, the pointer interpreter will transition into the DEC state. I The pointer interpreter will transition out of the DEC state based on the following conditions: — If NDF is enabled on the incoming H1 and H2 bytes, the pointer interpreter will transition from the DEC state into the NDF state. — Following three consecutive frames with all ones in the H1 and H2 bytes, the pointer interpreter will transition from the DEC state into the AIS state. — Following three new consecutive, consistent, and valid pointers, the pointer interpreter will transition from the DEC state into the NORM state. — Following any three consecutive, consistent, and valid pointers, the pointer interpreter will transition from the DEC state into the NORM state. — Following eight consecutive invalid pointers, the pointer interpreter will transition from the DEC state into the LOP state.

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 377Agere Systems Inc. I Pointer increments and decrements will be counted and presented to the microprocessor as follows: — Pointer increments and decrements will be monitored and counted internally. — The internal and latched counts will be forced to clear (0x00) if TMUX_RLOP[3— 1] = 1 (Table 92 on page 92) or TMUX_RP AIS[3— 1] = 1 (Table 92), where [3— 1] designates the tributary number. — Upon the configured performance monitoring interval, raw counts are transferred to holding registers for pointer increments (TMUX_RPTR_INC[1— 3][10:0] (Table 129 on page121)) and decrements TMUX_RPTR_DEC[1 — 3][10:0] (Table 130), allowing access by the microprocessor. The raw counters will reset (to 0x00). — Depending on the value of SMPR_SAT_ROLLOVER (Table 67 on page68) in the microprocessor interface block, the internal running counts saturate at their maximum value or rollover. — However, increment and decrement event indications should be ignored during LOP station. I The current pointer state is read from TMUX_RLOP[3— 1] and TMUX_RPAIS[3— 1]. Any changes in pointer con- dition are read from the delta state bits TMUX_RLOPD[3— 1] and TMUX_RPAISD[3— 1] (Tabl e 8 3). The associ- ated interrupt mask bits are TMUX_RLOPM[3— 1] (Table 87 on page89) and TMUX_RP AISM[3— 1] (Table 87). When the device is receiving a concatenated signal (STM-1(AU-3)), the receive concatenation mode register bit, TMUX_RCONCATMODE ( Table 95 on page 95), must be set for the concatenation state machines (register bits TMUX_CONCAT_STA TE[3 — 2][1:0] (Table 92 on page92)) on ports 2 and 3 to contribute to pointer evaluation. This state machine implements the pointer interpretation algorithm described in ETS 300 417-1-1: January 1996 - Annex B.

17.5.16 Path Monitoring Functions

The following sections describe the path monitoring functions. For STM-1 signals, the values corresponding to STS-1 #1 are the relevant signals. For STS-3 input data, there are three versions of each path monitor, one corre- sponding to each STS-1. The mode bits are applied to the monitors of all three STS-1s. J1 Monitor. J1 (path trace) monitoring has six different monitoring modes controlled by TMUX_J1MONMODE[2:0] (Table 95 on page95). The J1 monitoring mode for all three STS-1s within an STS-3 signal is the same. I TMUX_J1MONMODE[2:0] = 000: The TMUX latches the value of the J1 byte every frame for a total of 64 bytes in TMUX_J1DMON[1 — 3][1— 64][7:0] (Table 137 on page122, Table 138, and Table 139). The TMUX compares the incoming J1 byte with the next expected value (the expected value is obtained by cycling through the previ- ous stored 64 received bytes in round-robin fashion) and setting the path trace identifier state register bit(s), TMUX_RTIMP[1 — 3] (Table 92 on page92), if different. Any change to the path trace identifier is reported in TMUX_RTIMPD[1 — 3] (Table 83), with interrupt mask bits, TMUX_RTIMPM[1— 3] (Table 87 on page89). I TMUX_J1MONMODE[2:0] = 001: This is the SONET framing mode. The hardware looks for the 0x0A character to indicate that the next byte is the first byte of the path trace message. The J1 byte message is continuously written into registers, TMUX_J1DMON[1— 3][1— 64][7:0], with the first byte residing at the first address. If any received byte does not match the previously received byte for its location, then the state bit(s), TMUX_RTIMP[1 — 3], is set. Any change to the path trace identifier is reported in TMUX_RTIMPD[1— 3], with interrupt masks bits, TMUX_RTIMPM[1— 3]. I TMUX_J1MONMODE[2:0] = 010: This is the SDH framing mode. The hardware looks for the byte with the MSB set to one, which indicates that the next byte is the second byte of the message. The rest of operation is the same as in SONET framing mode, except that there are 16 bytes instead of 64. I TMUX_J1MONMODE[2:0] = 011: A new J1 byte (TMUX_J1DMON[1][7:0]) will be detected after a number of consecutive consistent occurrences of a new pattern (determined by the value in TMUX_CNTDJ1[3:0] (Tabl e 9 9 on pag e99)) in the J1 overhead byte. Any changes to this byte must be reported in TMUX_RTIMPD[1— 3], with the interrupt mask bits, TMUX_RTIMPM[1— 3]. The delta bit(s) in this mode indicate a change in state for the TMUX_J1DMON[1][7:0] byte, and the state bits, TMUX_RTIMP[1— 3], are not used.

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 May 2001 378 Agere Systems Inc. I TMUX_J1MONMODE[1:0] = 100: The user will program the 64 expected values of J1 in TMUX_EXPJ1DMON[1 — 3][1— 64][7:0] (Table 134 on page122, Table 135, and Table 136), in SONET framing mode, where the first expected byte, the byte following the 0x0A character, is written into the first location of TMUX_EXPJ1DMON[1][7:0]. The TMUX will compare the incoming J1 sequence with the stored expected value, setting the path trace identifier state bit(s), TMUX_RTIMP[1— 3] if they are different. Any change to the path trace identifier is reported in TMUX_RTIMPD[1— 3], with interrupt mask bits, TMUX_RTIMPM[1— 3]. I TMUX_J1MONMODE[1:0] = 101: The user will program the 16 expected values of J1 in EXPJ1DMON[1 — 16][7:0] in SDH framing mode, where the first byte of the message has the MSB set to 1. The TMUX compares the incoming J1 sequence with the stored expected value, setting the state register bit(s), TMUX_RTIMP[1 — 3], if they are different. Any change to path trace identifier is reported in register bits, TMUX_RTIMPD[1 — 3], with interrupt mask bits, TMUX_RTIMPM[1— 3]. I TMUX_J1MONMODE[1:0] = 110 and 111 are currently undefined. B3 BIP-8 Check. A B3 BIP-8 even parity is computed over all the incoming synchronous payload envelope bits of the STS-3/STM-1/STS-1 signal after descrambling, and compared to the B3 byte received in the next frame. The total number of B3 BIP-8 bit errors (raw count), or block errors (as determined by TMUX_BITBLKB3 (Table 95 on page 95), is counted. Upon the configured performance monitor (PM) interval, the value of the internal running counter is placed into holding registers TMUX_B3ECNT[1 — 3][15:0] (Table 126 on page119) and then cleared. Depending on the value of SMPR_SAT_ROLLOVER (Table 67 on pa ge68) in the microprocessor interface block, the internal counter will either roll over or stay at its maximum value until cleared. Signal Label C2 Byte Monitor. The C2 byte per STS-1/STM-1 is stored in TMUX_C2MON[1— 3][7:0] (Table 104 on page101). Each register will be updated after a number, determined by the value in TMUX_CNTDC2[3:0] (Table 99 on pag e99), of consecutive frames of identical C2 bytes for a given STS-1/STM-1, i.e., the 8-bit pattern must be identical for a programmed number frames prior to updating the C2 register. Any change to C2 byte moni- tor is reported via the corresponding delta and mask register bits, TMUX_RC2MOND[1— 3] (Tabl e 8 3) and TMUX_RC2MONM[1 — 3] (Table 87 on pag e89). In addition, there are programmable expected value(s) for the C2 bytes of each STS-1/STM-1 in TMUX_C2EXP[1 — 3][7:0] (Table 100 on page100). If the current value of a C2 byte in TMUX_C2MON[1— 3][7:0] does not equal the expected C2 value in TMUX_C2EXP[1— 3][7:0]), then a payload label mismatch defect may be declared for that STS-1/STM-1 in TMUX_RPLMP[1— 3] (Table 92 on page92). Also, if the current value of a C2 byte is all 0s, then the corresponding unequipped defect is declared in TMUX_RUNEQP[1— 3] (Ta ble 92). Note: The payload label mismatch and unequipped defects are mutually exclusive and unequipped takes priority. The following table describes the conditions for generating payload label mismatch (TMUX_RPLMP[1— 3]) and unequipped defects (TMUX_RUNEQP).

Table 524. STS Signal Label Defect Conditions TMUX_REPRDI_MODE = 1, then the 3-bit enhanced path RDI code is supported. will be reported in TMUX_RRDIPD[1— 3] with interrupt mask bits,TMUX_RRDIPM[1— 3] (Table 87 on page89). REI-P Detection. Bits [7:4] of the G1 byte are allocated for use as a path remote error indication function (REI-P). detected by the PTE (using the path BIP-8 code B3) back to its peer PTE as shown in Table 525.

Table 525. STS-1 P-REI Interpretation counter(s) will count in bit or block mode, depending on the value of TMUX_BITBLKG1 (Table 95 on page95). either roll over or stay at its maximum value until cleared. uous N-times detection counter(s) will be reset to 0 upon the transition of the framer into the out of frame state. SPEs, this byte is used as a multiframe indicator. put pin (pin number W4) on the telecom bus during that frame. Note: The three H4 bytes of an STS-3 signal can occur at any time with respect to one another within a frame. tern must be identical for the programmed number of frames prior to updating the F3 register.

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 381Agere Systems Inc. Any change to F3 byte monitor registers is reported in TMUX_RF3MOND[1— 3] (Table 83), with interrupt mask bits, TMUX_RF3MONM[1 — 3] (Table 87 on page89). The TMUX also maintains a history of the previous valid F3 byte in TMUX_F3MON1[1— 3][7:0] (Table 104 on page 101). The continuous N-times detection counter(s) will be reset to 0 upon the transition of the framer into the out of frame state. K3 Byte Monitor. The TMUX monitors the K3 byte for each STS-1/STM-1. The K3 byte(s) are stored in TMUX_K3MON[1 — 3][7:0] (Table 104). Each register will be updated after a number determined by the value in TMUX_CNTDK3[3:0] (Table 99 on page99) of consecutive frames of identical K3[7:0] for that particular STS-1/STM-1. That is, the 8-bit pattern must be identical for a number of frames prior to updating the K3 register. Any change to K3 monitor registers is reported in TMUX_RK3MOND[1— 3] (Ta ble 83), with interrupt mask bits, TMUX_RK3MONM[1 — 3] (Table 87 on page89). The continuous N-times detection counter(s) will be reset to 0 upon the transition of the framer into the out of frame state. N1 Byte Monitor. The TMUX monitors the N1 byte for each STS-1/STM-1. The N1 byte(s) are stored in TMUX_N1MON[1 — 3][7:0] (Table 104 on page101). Each register will be updated after a number determined by the value in TMUX_CNTDN1[3:0] (Table 99 on page 99) of consecutive frames of identical N1[7:0] for that particu- lar STS-1/STM-1. That is, the 8-bit pattern must be identical for a number of frames prior to updating the N1 regis- ter. Any change to N1 monitor registers will be reported in TMUX_RN1MOND[1— 3] (Ta ble 83), with interrupt mask bits, TMUX_RN1MONM[1 — 3] (T able 87 on page89). The continuous N-times detection counter(s) will be reset to 0 upon the transition of the framer into the out of frame state. Signal Degrade BER Algorithm. A signal degrade state in register bit TMUX_RHSSD (Table 91 on page 92) and change of state indication is reported in register bit, TMUX_RHSSDD (Table 82, starting on page79), with the interrupt mask bit, TMUX_RHSSDM (Table 87 on page 89). This bit error rate algorithm can operate on either B1 or B2 errors, determined by the value of TMUX_SDB1B2SEL (Table 95 on page95). Each B3 monitor has an inde- pendent signal degrade function as well in TMUX_RSDB3[1— 3] (Table 92 on page92). Declaring the signal degrade state requires the definition of two measurement windows, a monitoring block consist- ing of a number of frames in TMUX_SDNSSET[18:0] (Table 120 on page116) and a measurement interval consist- ing of a number of monitoring blocks in TMUX_SDBSET[11:0] (Tabl e 1 20). A block is determined bad when the number of bit errors equals or exceeds a threshold set in TMUX_SDLSET[3:0] (Table 120). Signal degrade is declared when a number of bad monitoring blocks equals or exceeds the threshold in TMUX_SDMSET [7:0] (Table 526) for the measurement interval. Clearing the signal degrade state requires the definition of two measurement windows, a monitoring block consist- ing of a number of frames in TMUX_SDNSCLEAR[18:0] (Table 120) and a measurement interval consisting of a number of monitoring blocks in TMUX_SDBCLEAR[11:0] (Table 120). A block is determined good when the num- ber of bit errors is less than a threshold set in TMUX_SDLCLEAR[3:0] (Table 120). Signal degrade is cleared when a number of good monitoring blocks equals or exceeds the threshold in TMUX_SDMCLEAR[7:0] (Table 120) for the measurement interval. The set parameters are used when the signal degrade state is clear, and the clear parameters are used when the signal degrade state is declared. The signal degrade state may be forced to the declared state with TMUX_SDSET (Table 78 on page 77) and forced to the cleared state with TMUX_SDCLEAR (Table 78). One shot signal must be provided to force the BER algo- rithm into the failed state or normal state, respectively. The algorithm described above can detect bit error rates from 1 x 10 –3 to 1 x 10–9.

Table 526. Signal Degrade (SD) Parameters TMUX_SDLCLEAR[3:0] parameters. algorithm as well with the failure indicated in TMUX_RSFB3[1— 3] (Table 92 on pag e92). (Table 121) for the measurement interval. ber of bit errors is less than a threshold set in TMUX_SFLCLEAR[3:0] (Table 121). TMUX_SDNSSET[18:0] ( Table 120) Signal Degrade Ns Set. Number of frames in a monitoring block for SD. threshold, then SD is cleared. into the failed state (active 0 to 1). into the normal state (active 0 to 1). erwise, B2 errors are used to calculate the error rate. TMUX_RHSSD ( Table 91) Signal Degrade BER Algorithm State Bit. TMUX_RHSSDD ( Table 82) Signal Degrade BER Algorithm Delta Bit. TMUX_RHSSDM ( Tabl e 8 6) Signal Degrade BER Algorithm Mask Bit.

TMUX_SFMCLEAR[7:0] ( Table 121) for the measurement interval. the failed state or normal state, respectively. The above algorithm can detect bit error rates from 1 x 10–3 to 1 x 10–9. Table 527. Signal Fail Parameters TMUX_SFLCLEAR[3:0] parameters. TMUX_SFNSSET[18:0] ( Table 121) Signal Fail Ns Set. Number of frames in a monitoring block for SF . TMUX_SFBSET[15:0] (Table 121) Signal Fail B Set. Number of monitoring blocks. Signal Fail Ns Clear. Number of frames in a monitoring block for SF . TMUX_SFBCLEAR[15:0] ( Table 121) Signal Fail B Clear. Number of monitoring blocks. a logic 1, causes the signal fail bit error rate algorithm to use B2 errors. failed state (active 0 to 1). the normal state. (active 0 to 1). TMUX_RHSSF ( Table 91) Signal Fail BER Algorithm State Bit. TMUX_RHSSFD ( Table 82) Signal Fail BER Algorithm Delta Bit. TMUX_RHSSFM ( Table 86) Signal Fail BER Algorithm Mask Bit.

that the RPOAC channel is not driven by the TMUX. I A 576 kHz inverted clock signal sourced by the TMUX (RPOACCLK, pin AE3). I A 576 kbits/s data signal sourced by the TMUX (RPOACDATA, pin AD4). odd/even parity bit over the 72 bits of the previous frame. The remaining 7 bits of this byte are not specified. Bytes shown in Table 529 summarize the access capabilities of the receive POAC. Table 529. Path Overhead Byte Access with TMUX_RPOAC_OEPINS ( Table 118 on page115). STS-1, also informs the other blocks within the Super Mapper to insert AIS downstream due to detected failures. LOS, LOF , OOF , LOP-P , SF (B1, B2, or B3), SD (B1, B2, or B3), payload label mismatch, or payload unequipped. each STS-1 signal has a corresponding AUTO_AISO signal. Table 528. Signal Fail or Signal Degrade Recommended Programming Values

binations of signal status states register bits and inhibit state register bits that form the criteria. STS-1 basis, while sending path AIS occurs on the complete STS-3/STM-1 signal (or STS-1 for STS-1 only mode). at 6.48 MHz instead of 19.44 MHz. Figure 27. Receive Low-Speed Bus Interface Signals for STS-3/STM-1 Signals

3 BYTES 3 BYTES 3 BYTES 3 BYTES 3 BYTES

17.6 Transmit Direction (Transmit Path to SONET/SDH Line)

17.6.1 Transmit Side Telecom Bus Interface

The parallel clock operates at 19.44 MHz for STS-3/STM-1 modes and at 6.48 MHz for STS-1 mode. Figure 28. Transmit Low-Speed Bus Interface Signals for STS-3/STM-1 Signals

17.6.2 Transmit Path and Transport Overhead Insertion Diagram

SPE to generate a complete SONET/SDH frame.

Figure 29. Transmit Direction POH and TOH Insertion Diagram

sor register bit, SMPR_OH_DEFLT (Table 67 on pag e68).

17.6.3 POAC Insert

on page115) designate which STS-1s POH is inserted from the transmit POAC channel. I A 576 kHz inverted clock signal sourced by the TMUX (TPOACCLK, pin AE4). I A 576 kbits/s serial data signal received by the TMUX in the transmit direction (TPOACDA TA, pin AD5). An 8 kHz synchronization signal (TPOACSYNC, pin AC5), sourced by the TMUX. The sync signal is normally low. H4 transmit path overhead bytes are not provisionable via the POAC channel. Table 530. Path Overhead Byte Access— Transmit Direction

and is configured with TMUX_TPOAC_OEPMON ( Table 117 on page113). Table 531. TPOAC Control Bits

17.6.4 AIS Path Generation

(section and line overhead).

17.6.5 J1 Insert Control

the default value is inserted when TMUX_TPOAC_J1 is logic 0.

17.6.6 B3 BIP-8 Calculation and Insert

current frame, also before scrambling. is asserted, the corresponding B3 byte is inverted each time the SMPR_BER_INSRT bit is asserted.

17.6.7 C2 Signal Label Byte Insert

bit value. If SMPR_OH_DEFLT = 0, then all 0s are inserted. If SMPR_OH_DEFLT = 1, then all ones are inserted.

17.6.8 Path RDI (RDI-P) Insert

mode, the relevant defects are AIS- P, LOP- P, PLM- P, and UNEQ- P. last for at least 20 frames before clearing, even if the original failure cause has cleared in less than 20 frames. Table 532 describes the encoding of the path RDI defects. Table 532. RDI-P Defects for Enhanced RDI-P Mode the protection board rather than from the receive side of the same TMUX.

17.6.9 REI-P: G1(7:4) Insert

detected in error by the BIP-8 (B3) detector on the received signal. STS-1(s) each time the microprocessor interface block SMPR_BER_INSRT (Table 65 on page66) bit is asserted. the protection board rather than from the receive side of the same TMUX. 0 0 0 No defects (nonenhanced RDI-P mode). 0 0 1 No defects (enhanced RDI-P mode). 0 1 0 LCD-P , PLM-P (LCD-P not supported in Super Mapper). 0 1 1 No defects (nonenhanced RDI-P mode). 1 0 0 AIS-P , LOP-P (nonenhanced RDI-P mode). 1 0 1 AIS-P , LOP-P (enhanced RDI-P mode). 1 1 0 TIM-P , UNEQ-P (enhanced RDI-P mode). 1 1 1 AIS-P , LOP-P (nonenhanced RDI-P mode).

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 391Agere Systems Inc.

17.6.10 F2 Byte Insert

When TMUX_THSF2INS = 1 (Table 108 on page 105), the value in TMUX_TF2INS[1— 3][7:0] (Table 114 on page 110) is inserted into the outgoing signal. Otherwise, the associated POAC value is inserted when TMUX_TPOAC_F2 = 1 ( Table 118 on page115). If both TMUX_THSF2INS and TMUX_TPOAC_F2 = 0, then the value inserted depends on the value of microprocessor interface block SMPR_OH_DEFLT (Table 67 on pag e68) bit. If SMPR_OH_DEFLT = 0, then all 0s are inserted. If SMPR_OH_DEFLT = 1, then all ones are inserted.

17.6.11 H4 Insert Control

A 4-byte sequence (0, 1, 2, and 3) will be inserted into the outgoing H4 bytes. Note that the assertion of pin TLSV1 (pin AB3) occurs after the J1 byte(s) during the frame where the H4 count equals one.

17.6.12 F3 Byte Insert

When TMUX_THSF3INS = 1 (Table 108), the value in TMUX_TF3INS[1— 3][7:0] (Table 114 on page110) is inserted into the outgoing signal. Otherwise, the associated POAC value is inserted when TMUX_TPOAC_F3 = 1 (Table 118 on page 115). If both TMUX_THSF3INS and TMUX_TPOAC_F3 = 0, then the value inserted depends on the value of microprocessor interface block SMPR_OH_DEFLT (Table 67 on page68) bit. If SMPR_OH_DEFLT = 0, then all 0s are inserted. If SMPR_OH_D EFLT = 1, then all ones are inserted.

17.6.13 K3 Byte Insert

When TMUX_THSK3INS = 1 ( Table 108 on page105), the value in TMUX_TK3INS[1— 3][7:0] (Tabl e 1 14) is inserted into the outgoing signal. Otherwise, the associated POAC value is inserted when TMUX_TPOAC_K3 = 1 (Table 118 on page 115). If both TMUX_THSK3INS and TMUX_TPOAC_K3 = 0, then the value inserted depends on the value of microprocessor interface block SMPR_OH_DEFLT (Table 67) bit. If SMPR_OH_DEFLT = 0, then all 0s are inserted. If SMPR_OH_DEFLT = 1, then all ones are inserted.

17.6.14 N1 Byte Insert

When TMUX_THSN1INS = 1 ( Table 108 on page 105), the value in TMUX_TN1INS[1— 3][7:0] (Table 114 on page 110) is inserted into the outgoing signal. Otherwise, the associated POAC value is inserted when TMUX_TPOAC_N1 = 1 ( Table 118). If both TMUX_THSN1INS and TMUX_TPOAC_N1 = 0, then the value inserted depends on the value of microprocessor interface block SMPR_OH_DEFLT (Table 67 on page68) bit. If SMPR_OH_DEFLT = 0, then all 0s are inserted. If SMPR_OH_D EFLT = 1, then all ones are inserted.

17.6.15 MSP 1 + 1 Payload Switch

For the working transmit high-speed data output (THSDP/N, pins AF9/AE9), it is possible to select the normal transmit path low-speed data by setting TMUX_TPSMUXSEL2 = 0 (Table 106 on page 103) or the receive-side protection input data by setting TMUX_TPSMUXSEL2 = 1. Note that if the receive-side protection input is selected, then the local clock and frame sync are generated based on the receive-side protection inputs as well. To create the transmit high-speed protection outputs (TPSD155P/N and TPSC155P/N; pins AF13/AE13 and AC12/AD13), it is possible to select the normal transmit path low-speed input data with TMUX_TPSMUXSEL3 = 0 (Table 106 on page 103) or the receive-side working inputs with TMUX_TPSMUXSEL3 = 1. Note: Clocks and timing signals are selected by TMUX_TPSMUXSEL3 as well as the parallel data.

17.6.16 Transmit Transport Overhead Access Channel (TTOAC)

The TMUX provides a transmit transport overhead access channel (TTOAC) to provision the TOH portion of the outgoing frame. The TTOAC channel supports three modes of operation based on values in TMUX_TTOAC_D13MODE and TMUX_TTOAC_D412MODE ( Table 117 on page113).

TMUX_TTOAC_D13MODE and TMUX_TTOAC_D412MODE. See Table 533 below. Table 533. Transmit TOAC Modes DCC2, and DCC3. The data signal is partitioned into frames of 3 bytes. The frame repetition rate is 8 kHz. 9 bytes. The frame repetition rate is 8 kHz. the previous frame. The remaining 7 bits of this byte are not specified. ues of these bytes in the outgoing transmit frame are not related to the values on the TTOAC channel. Table 534. Transmit Transport Overhead Byte Full Access Mode

Table 535 summarizes the insertion options for the specified overhead bytes for TOAC in full TOH access mode. Table 535. TTOAC Control Bits in Full Access Mode maskable with TMUX_TTOAC_PM (Table 84 on page87).

17.6.17 Sync Status Byte (S1) Insert

17.6.18 REI-L: M1 Insert

detected in error by the line BIP-8 (B2) detector on the received signal. The TMUX provides a protection switch MUX for REI-L insertion, controlled by TMUX_TLREIRDISEL (Table 107). rather than from the receive side of the same TMUX.

17.6.19 APS Value and K2 Insert Control Parameters

depending on the value of microprocessor interface block SMPR_OH_DEFLT (Table 67) bit.

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 May 2001 394 Agere Systems Inc. An APS babbling test is controlled with TMUX_TAPSBABINS ( Table 116 on page113). Setting TMUX_T APSBABINS = 1 forces the K1[7:0], K2[7:3) to an inconsistent state; no three consecutive values are con- tinuously the same. When the transmit K2 software insert bit TMUX_THSK2INS = 1 (Table 107 on page103), data from bits TMUX_TK2INS[2:0] (Table 113 on page110) is written into the K2[2:0] output bits. When TMUX_THSK2INS = 0, hardware insertion of RDI-L is enabled.

17.6.20 Criteria for Insert Line RDI

Hardware insertion of line RDI is generated using the following equation. Each defect contribution to line RDI can be individually inhibited. (TMUX_RILOC AND TMUX_TRILOC_LRDIINH ) OR (TMUX_RHSLOS AND TMUX_TRLOS_LRDIINH ) OR (TMUX_RHSLOF AND TMUX_TRLOF_LRDIINH ) OR (TMUX_RHSOOF AND TMUX_TROOF_LRDIINH ) OR (TMUX_RLAISMON AND TMUX_TRLAISMON_LRDIINH ) OR (TMUX_RHSSF AND TMUX_TRSF_LRDIINH) OR (TMUX_RHSSD AND TMUX_TRSD_LRDIINH ) When a failure condition exists that will cause RDI-L to be generated, the generation of RDI-L must last for at least 20 frames before clearing, even if the original failure cause has cleared in less than 20 frames. The TMUX provides a protection switch MUX for RDI-L insertion. The MUX is controlled by TMUX_TLREIRDISEL (Table 107). If TMUX_TLREIRDISEL = 1, then the RDI-L value for insertion is taken from the value on the protec- tion board rather than from the receive side of the same TMUX.

17.6.21 Line AIS Generation

Line AIS is specified as all ones in the entire STS/STM signal before scrambling, excluding the section overhead. Line AIS can be generated by setting TMUX_THSLAISINS = 1 (Table 107).

17.6.22 B2 BIP-8 Calculation and Insert

The B2 byte is allocated for a line overhead error monitoring function. This function will be a bit interleaved parity-8 code (BIP-8) using even parity. The BIP-8 is computed before scrambling, over all the bits of the previous STS-1 frame (except for the 9 bytes of section overhead) and is placed in byte B2 of the current frame also before scram- bling. A bit error rate can be inserted on any B2 byte. When bit(s) TMUX_THSB2ERRINS[1— 3] (Table 115 on page112) is (are) asserted, the corresponding B2 byte is inverted each time the microprocessor interface block SMPR_BER_INSRT ( Table 65 on page66) bit is asserted.

17.6.23 F1 Byte Insert

When TMUX_THSF1INS = 1 ( Table 107 on page 103), the value in TMUX_TF1INS[7:0] (Table 112 on page 110) is inserted into the F1 byte of the outgoing signal. Otherwise, the associated TOAC value is inserted when TMUX_TTOAC_F1 = 1 ( Table 117 on page113). If both TMUX_THSF1INS and TMUX_TTOAC_F1 = 0, then the value inserted depends on the value of microprocessor interface block SMPR_OH_DEFLT (Table 67 on page 68) bit. If SMPR_OH_DEFLT = 0, then all 0s are inserted. If SMPR_OH_DEFLT = 1, then all ones are inserted.

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 395Agere Systems Inc.

17.6.24 B1 Generate and Error Insert

The section bit interleaved parity code (BIP-8) byte (even parity) is used to check for transmission errors over a section. Its value is calculated over all bits in the previous frame after scrambling and placed in the B1 byte of time slot 1 before scrambling. A bit error rate can be inserted on the B1 byte. When TMUX_THSB1ERRINS = 1 (Table 115 on page 112), the B1 byte is inverted each time the microprocessor interface block SMPR_BER_INSRT (Table 65 on page66) bit is asserted.

17.6.25 Scrambler

The outgoing frame will be scrambled with the frame synchronous scrambler of length 127 and generating polyno- mial x 7 + x6 + 1. The entire STS/STM signal will be scrambled except for the first row of overhead. The scrambler will be set to 1111111 on the first byte following the last overhead byte in the first row. For test purposes, the scrambler will be disabled when TMUX_THSSCR = 0 (Table 106 on page 103).

17.6.26 J0 Insert Control

A 16-byte sequence stored in TMUX_TJ0DINS[1— 16][7:0] (Table 133 on page121) will be inserted into the outgo- ing J0 byte if TMUX_THSJ0INS = 1 (Table 107 on pag e103). If TMUX_THSJ0INS = 0, then the value inserted depends on the value of microprocessor interface block SMPR_OH_DEFLT (Ta ble 67) bit. If SMPR_OH_DEFLT = 0, then all 0s are inserted. If SMPR_OH_DEFLT = 1, then all ones are inserted.

17.6.27 Z0-2, Z0-3 Insert Control

The 2 bytes, Z0-2 and Z0-3, that follow J0 are not scrambled. If TMUX_THSZ0INS = 1 (Table 107), then the values stored in TMUX_TZ02INS[7:0] (Table 111 on pag e110) and TMUX_TZ03INS[7:0] (Tabl e 1 11) will be inserted. If TMUX_THSZ0INS = 0, then the value inserted depends on the value of microprocessor interface block SMPR_OH_DEFLT bit. If SMPR_OH_DEFLT = 0, then all zeros are inserted. If SMPR_OH_DEFLT = 1, then all ones are inserted.

17.6.28 A2 Error Insert

The TMUX allows, under software control, from 1 to 32 continuous frames to have an inverted A2-1 (0x28 to 0xD7) pattern in the outgoing frame. The value in TMUX_TA2ERRINS[4:0] (Table 106) specifies the number of frames to insert errors into while assertion of microprocessor interface block, SMPR_BER_INSRT bit, starts the error inser- tion process.

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 May 2001 396 Agere Systems Inc.

18 SPE Mapper Functional Description

18.6 DS3 to AU-3/STS-1 SPE Mapping (Used in

18 SPE Mapper Functional Description (continued)

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 May 2001 398 Agere Systems Inc.

18.1 Introduction

This section describes the functions of the SPE mapper block. The SPE mapper is highly configurable; it can operate in two different modes, as an AU-3/STS-1 mapper or as a TUG-3 mapper. In both modes, it can map/demap data from/to either the VT mapper block, the M13 MUX/deMUX block, the DS3 clear channel, or the DS3 loopback channel. The SPE mapper supports numerous automatic monitoring functions. It can provide interrupts to the control sys- tem, or it can be operated in a polled mode. Additionally, this block has a built-in auxiliary channel known as the path overhead access channel (POAC). This channel is mainly used for path overhead insertion and drop functions.

18.2 Features

I The SPE mapper accepts/delivers TUG-2 data from/to the VT mapper. The TUG-2 data is mapped/demapped either to/from an AU-3/STS-1 signal for the North American digital systems or to/from a TUG-3 signal for the European digital systems. I Flexibility down to TUG-2 level is provided for choosing which TUG-2s (between 1 and 7) are mapped into which TUG-3s (between 1 and 3) for generating STM-1 signals. Similarly, any TUG-2s (up to 7) may be dropped/termi- nated from the 21 TUG-2s of an STM-1 signal. I The SPE mapper accepts/delivers DS3 data from/to the M13 MUX/deMUX. The DS3 data is mapped/demapped either to/from an AU-3/STS-1 signal for the North American digital systems or to/from a TUG-3 signal for the European digital systems. I The SPE mapper accepts/delivers a clear DS3 signal at 44.736 Mbits/s rate. The clear DS3 signal is mapped/ demapped essentially the same way as M13 signal described above. I The SPE mapper has a DS3 loopback circuit placed for the functions of demapping and remapping a DS3 signal. It is particularly useful in cases where a DS3 signal mapped as an AU-3/STS-1 signal is needed to be remapped as a TUG-3 signal or vice versa. I The SPE mapper supports a path overhead access channel more commonly known as the POAC channel. Seven path overhead bytes namely J1, C2, F2, H4, F3, K3, and N1 may be inserted/dropped through this chan- nel. This channel works as the master which means that this channel provides a clock in both transmit and receive directions and POH data may be inserted by the user on the transmit side or dropped by the block in the receive side. I Path overhead byte B3 (BIP error) generation/detection and programmable BIP-2 bit error rate insertion. I Programmable clear on read/clear on write registers. I Signal fail and signal degrade indicators available to report bit error rates above a certain programmable thresh- old. I Capable of detecting/inserting alarm indication signals (AIS), remote defect indication signals (RDI) and remote error indication signals (REI). I Numerous monitoring functions provided on all the TUG-3 path overhead bytes. I Supports unidirectional path switch ring (UPSR) applications. I N1 tandem connection support is provided.

18.3 SPE Mapper Functional Block Diagrams

Figure 30. SPE Mapper Block with Connections to External Pins and Other Blocks in the Devic e

Figure 31. Basic Functional Flow of the SPE Mapper Transmit Section

51.84 MHz CLOCK FROM TMUX

51.84 MHz CLOCK, CONTROL FROM TMUX

Figure 32. Basic Functional Flow of the SPE Mapper Receive Section

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 May 2001 402 Agere Systems Inc. The SPE mapper basically interfaces to three other blocks within the Super Mapper device: I The VT mapper. I The M13 MUX/deMUX. I The TMUX. The interface between the SPE m apper and the VT mapper consists of clock, parallel data, sync, and control type interfaces and is completely internal to the Super Mapper device. The interface between the SPE mapper and the M13 MUX/deMUX consists of a serial clock, serial data, and clock enable type interface and is also completely internal to the Super Mapper device. The interface between the SPE m apper and the TMUX consists of the telecom bus and every signal that flows between these two blocks is also brought in/out through external device pins connected to the telecom bus. As outlined in the features, the SPE mapper can map/demap seven TUG-2 or a DS3 to/from AU3/STS-1 or TUG-3. Each TUG-2 assembled/disassembled by the VT mapper consist of three TU-12 (E1) or four TU-11 (DS1) virtual tributaries. The following is a brief description of the supported standards based mappings. For greater details, please refer to the appropriate standard.

18.4 TUG-2 to AU-3/STS-1 SPE Mapping (Used in North American Systems)

A TUG-2 payload capacity, which is 9 rows by 12 columns or 108 bytes, may contain four TU-11s or three TU-12s byte interleavingly multiplexed. The 27-byte capacity of a TU-11 is equivalent to three-column capacity in an STS-1 frame of 125 µs. Four TU-11s are byte interleavingly multiplexed into a TUG-2 payload capacity which has a capacity of 12 columns. Seven TUG-2s can then be byte interleavingly multiplexed into the payload capacity of a VC-3. The VC-3 has a structure of 9 rows by 85 columns: one column is VC-3 path overhead and the other 84 columns are seven TUG-2s evenly distributed within the payload. Two columns of fixed stuffing are then added to the payload to build the complete STS-1 SPE frame of 9 rows by 87 columns. The 36-byte capacity of a TU-12 is equivalent to four-column capacity in an STS-1 frame of 125 µs. Three TU-12s are byte interleavingly multiplexed into a TUG-2 payload capacity which has a capacity of 12 columns. Seven TUG-2s can then be byte interleavingly multiplexed into the payload capacity of a VC-3. The VC-3 has a structure of 9 rows by 85 columns: one column is VC-3 path overhead and the other 84 columns are seven TUG-2s evenly distributed within the payload. Two columns of fixed stuffing are then added to the payload to build the complete STS-1 SPE frame of nine rows by 87 columns.

18.5 TUG-2 to TUG-3 Mapping (Used in ITU/ETSI Standard Based Systems)

A TUG-2 payload capacity, which is nine rows by 12 columns or 108 bytes, may contain four TU-11s or three TU-12s byte interleavingly multiplexed. The 27-byte capacity of a TU-11 is equivalent to three-column capacity in an STM-1 frame of 125 µs. Four TU-11s are byte interleavingly multiplexed into a TUG-2 payload capacity which has a capacity of 12 columns. Seven TUG-2s can then be byte interleavingly multiplexed into the payload capacity of a TUG-3. The TUG-3 has a struc- ture of nine rows by 86 columns: one column of NPI (null pointer indication) plus fixed stuffing bytes, one column of fixed stuffing and the other 84 columns are seven TUG-2s evenly distributed within the TUG-3 payload. The 36-byte capacity of a TU-12 is equivalent to four-column capacity in an STM-1 frame of 125 µs. Three TU-12s are byte interleaving multiplexed into a TUG-2 payload capacity which has a capacity of 12 columns. Seven TUG-2s can then be byte interleavingly multiplexed into the payload capacity of a TUG-3.

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 403Agere Systems Inc. The TUG-3 has a structure of 9 rows by 86 columns: one column of null pointer indication (NPI) plus fixed stuffing bytes, one column of fixed stuffing, and the other 84 columns are seven TUG-2s evenly distributed within the TUG-3 payload.

18.6 DS3 to AU-3/STS-1 SPE Mapping (Used in Telcordia/ANSI Standards Based Systems)

DS3 is an asynchronous signal with a rate of 44.736 Mbits/s. This payload with other information bits (total 3.648 Mbits/s) is used to form the container C-3 (48.384 Mbits/s) which occupies 84 columns of an STS-1 frame. One column of path overhead bytes is added to the C-3 container to make a VC-3. Finally, two columns of fixed stuffing (column numbers 30 and 59) are added to VC-3 to form an STS-1 SPE (87 columns). Stuffing (S bits) is used to rate adapt the DS3 payload to the SPE. Nine stuffing S bits are included in the C-3 con- tainer. When no stuffing is used, the STS-1 SPE can accommodate a rate of 44.712 Mbits/s. When all nine stuffing S bits are used, the STS-1 SPE can accommodate 44.784 Mbits/s. Since the DS3 coming from the M13 has a nominal rate of 44.736 Mbits/s, stuffing is used for every third row of an STS-1 frame; or in other words, three S bits per 125 µs are used for stuffing to achieve the DS3 rate.

18.7 DS3 to TUG-3 Mapping (Used in ITU/ETSI Standard Based Systems)

DS3 is an asynchronous signal with a rate of 44.736 Mbits/s. This payload with other information bits (total 3.648 Mbits/s) is used to form the container C-3 (48.384 Mbits/s) which occupies 84 columns of an STM-1 frame. One column of path overhead bytes are added to the C-3 container to make a VC-3 (85 columns). Now a TUG-3 signal consists of 86 columns by 9 rows, therefore 3 bytes of TU-3 pointer (H1, H2, and H3 bytes) are placed on rows 1 through 3 of the newly added column and fixed stuffing bits are placed on the remaining rows. Thus, a TUG-3 frame of 9 rows by 86 columns is formed. Three TUG-3s are byte interleavingly multiplexed by the TMUX to form an STM-1 signal. Stuffing (S bits) is used to rate adapt the DS3 payload to the TUG-3. Nine stuffing Sbits are included in the C-3 container. When no stuffing is used, the TUG-3 payload can accommodate a rate of 44.712 Mbits/s. When all nine stuffing S bits are used, the TUG-3 payload can accommodate 44.784 Mbits/s. Since the DS3 coming from the M13 has a nominal rate of 44.736 Mbits/s, stuffing is used for every third row of a TUG-3 frame; or in other words, three S bits per 125 µs are used for stuffing to achieve the DS3 rate.

18.8 SPE Mapper Basic Configuration

SPE mapper configuration programming is provided through registers SPE_MAP_CTL1 — SPE_MAP_CTL3 (Table 153 on page 140). When mapping to a STS-3/STM-1 rate, the SPE mapper requires configuration to select one of the three time slots on the telecom bus that interfaces the TMUX. The register bits for selection are SPE_TSTS3TMSLOT[1:0] and SPE_RSTS3TMSLOT[1:0] ( Table 153). Selection of AU-3/STS-1 or TUG-3 mapping is provided through bits SPE_T_AU3_TUG3 and SPE_R_AU3_TUG3 (Table 153). TUG-2 (virtual tributary) or DS3 data is selected with bits, SPE_T_AU3_TUG3 and SPE_R_AU3_TUG3.

18.9 DS3 Configuration

The SPE mapper is configured to select the source and destination of the DS3 signals. The configuration is deter- mined with register bits, SPE_TDS3SRCTYP[1:0] and SPE_RDS3OUTTYP[1:0] (Table 153). DS3 source/destina- tion may be selected as loopback, external device pins, or M13.

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 May 2001 404 Agere Systems Inc.

18.9.1 DS3 M13

The SPE mapper is configured to/from the M13 MUX/deMUX as the source/destination of data by setting bits, SPE_TDS3SRCTYP[1:0] = SPE_RDS3OUTTYP[1:0] = 00 or 01.

18.9.2 DS3 Loopback Channel

The DS3 loopback circuit is placed in the SPE mapper to allow demapping and remapping of a DS3 signal. When SPE_TDS3SRCTYP[1:0] = SPE_RDS3OUTTYP[1:0] = 10, the SPE mapper extracts the asynchronous DS3 data and clock from the received payload. The recovered DS3 is looped back to the transmit path and either mapped as AU-3/STS-1 SPE signal for the North American digital systems or mapped as TUG-3 for the European digital systems. It is particularly useful in cases where a DS3 signal mapped as an AU-3/STS-1 signal is needed to be remapped as a TUG-3 signal or vice versa.

18.9.3 DS3 Clear Channel from External Pins

The SPE mapper is configured for a DS3 signal at 44.736 MHz rate from external device pins by setting SPE_TDS3SRCTYP[1:0] = SPE_RDS3OUTTYP[1:0] = 11. The DS3 data can either be unipolar or bipolar. Unipolar data and clock is selected (device pins DS3POSDATAIN, DS3DATAINCLK, DS3POSDATAOUT, and DS3DA TAOUTCLK (pins M22, J22, R22, and N22, respectively)) when bits SPE_TDS3_BIPOLAR and SPE_RDS3_BIPOLAR = 0 ( Table 153). Bipolar data and clock is selected (device pins DS3POSDATAIN, DS3NEGDATAIN, DS3DATAINCLK, DS3POSDATAOUT, DS3NEGDATAOUT, and DS3DATAOUTCLK (pins M22, K22, J22, R22, P22, and N22, respectively)) when bits SPE_TDS3_BIPOLAR and SPE_RDS3_BIPOLAR = 1. When bipolar data is selected for the transmit path (SPE_TDS3_BIPOLAR = 1), the data received from the external pins is expected to be B3ZS encoded. A B3ZS decoder is used to recover the DS3 data prior to being mapped into a container. The B3ZS decoder also checks for bipolar coding violations. The SPE m apper contains a counter that increments on each occurrence of a received bipolar coding violation (BPV). It also monitors the occurrence of excessive zeros (EXZ), which is defined as any zero string length equal to or greater than three. These are part of the performance monitoring counters that can be sampled and simultaneously reset. Their last sampled values are available through SPE_BIPOL_CNT[23:0] and SPE_EXZ_CNT[23:0] (Table 160). When bipolar data is selected for the receive path (SPE_RDS3_BIPOLAR = 1), the data out from the external pins will be B3ZS encoded. A single bipolar violation may be inserted in the data when SPE_BIPOL_ERR is asserted (Table 145). The clock edge for sampling the transmit path data (device pin DS3DATAINCLK (pin J22)) is selected with SPE_TDS3CLK_EDGE ( Table 153).

18.10 Phase Detector for External DS3 PLL

The receive section of the SPE mapper has a phase detector circuit built inside the device. This phase detector cir- cuit generates the necessary up and down signals (device pins PHASEDETUP and PHASEDETDOWN (pins V22 and U22, respectively)) for an external phase-lock loop (PLL) circuit to generate a smooth DS3 clock at 44.736 MHz rate. The logic sense of the phase detector up and down outputs may be inverted with bits SPE_PHDETUP_INV (Table 153) and SPE_PHDETDN_INV, respectively.

18.11 Serial STS-1 SPE Channel (NSMI)

map/demap the network serial multiplexed interface (NSMI) interface data. through bits SPE_R_NSMI_BIT[2:0] (Table 153) and SPE_R_NSMI_COL[6:0] (Table 153). through bits, SPE_T_NSMI_BIT[2:0] and SPE_T_NSMI_COL[6:0] (Table 153). The STS-1 SPE data is then mapped as AU-3 signal for the North American digital systems. Figure 33. STS-1 NSMI Receive Operation

Figure 34. STS-1 NSMI Transmit Operation

18.12 TMUX Interface to the SPE Mapper

three TUG-3 signals, receiving through the telecom bus, to form one STS-3 or STM-1 signal, respectively. mapper, and the information is also passed along to the VT mapper for synchronizing the V1 counters. MUX/deMUX because of its serial mode of working. telecom bus at the time period when the clock is low.

18.13 PATH Termination Block

Figure 35. Receive Direction Path Termination Block

18.13.1 Pointer Interpretation Block

The TUG-3 pointer interpreter logic block performs all necessary functions to support TU-3 pointer interpretation. The SPE mapper includes event or change of state indicators for pointer interpreter states except the NORM state. and SPE_RLOPM (all in Table 147 on page136).

INC, DEC, and NDF states into the LOP state have been added. Figure 36. Pointer Interpretation State Diagram decrement, then LOP-TU3 is declared. the LOP-TU3 state into the AIS-TU3 state. LOP-TU3 state into the NORM state. — The pointer interpreter will not transition from the LOP-TU3 state into the NDF state. — Following three consecutive frames with all ones in the H1 and H2 bytes AIS-TU3 is declared. SPE_CNTDLOPCNT[1:0]) the pointer interpreter transitions from the AIS-TU3 state into the LOP-TU3 state.

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 409Agere Systems Inc. I The pointer interpreter transitions into the NDF state based on the following conditions: — If NDF is enabled on the incoming H1 and H2 bytes, the pointer interpreter transitions from the NORM, NDF, AIS, INC, and DEC states into the NDF state. I The pointer interpreter transitions out of the NDF state based on the following conditions: — Continuous NDF. If NDF (1001, 0001, 1101, 1011, 1000) is received for the number of consecutive frames (determined by the value programmed in SPE_CNTDLOPCNT[1:0] (Table 149)), the pointer interpreter tran- sitions from the NDF state into the LOP-TU3 state. — Following any three consecutive, consistent, and valid pointers, the pointer interpreter transitions from the NDF state into the NORM state. — Following three consecutive frames with all ones in the H1 and H2 bytes, the pointer interpreter transitions from the NDF state into the AIS-TU3 state. — Following three new, consecutive, consistent, and valid pointers, the pointer interpreter transitions from the NDF state into the NORM state. — Following the number of consecutive invalid pointers (determined by the value programmed in SPE_CNTDLOPCNT[1:0]), the pointer interpreter transitions from the NDF state into the LOP-TU3 state. I The pointer interpreter transitions into the NORM state based on the following conditions: — Following three new consecutive, consistent, and valid pointers, the pointer interpreter transitions into the NORM state. — Following any three consecutive, consistent, and valid pointers, the pointer interpreter transitions into the NORM state. i.e., transitioning from the INC, DEC, and NDF states. I The pointer interpreter transitions out of the NORM state based on the following conditions: — Following the number of consecutive invalid pointers (determined by the value programmed in SPE_CNTDLOPCNT[1:0]), the pointer interpreter transitions from the NORM state into the LOP-TU3 state. — If NDF is enabled on the incoming H1 and H2 bytes, the pointer interpreter transitions from the NORM state into the NDF state. — Following three consecutive frames with all ones in the H1 and H2 bytes, the pointer interpreter transitions from the NORM state into the AIS-TU3 state. — When operating in the 8 of 10 mode (SPE_8ORMAJORITY = 1 (Table 149)), if 8 of the 10 I and D bits are correct for a pointer decrement on the incoming H1 and H2 bytes the pointer interpreter transitions from the NORM state into the DEC state. Otherwise, if 3 of the 5 I bits and 3 of the 5 D bits are correct for a pointer decrement on the incoming H1 and H2 bytes, the pointer interpreter transitions from the NORM state into the DEC state. — When operating in the 8 of 10 mode (SPE_8ORMAJORITY = 1), if 8 of the 10 I and D bits are correct for a pointer increment on the incoming H1 and H2 bytes, the pointer interpreter transitions from the NORM state into the INC state. Otherwise, if 3 of the 5 I bits and 3 of the 5 D bits are correct for a pointer increment on the incoming H1 and H2 bytes, the pointer interpreter transitions from the NORM state into the INC state. I The pointer interpreter transitions into the INC state based on the following conditions: — When operating in the 8 of 10 mode (SPE_8ORMAJORITY = 1), if 8 of the 10 I and D bits are correct for a pointer increment on the incoming H1 and H2 bytes the pointer interpreter transitions into the INC state. Oth- erwise, if 3 of the 5 I bits and 3 of the 5 D bits are correct for a pointer increment on the incoming H1 and H2 bytes, the pointer interpreter transitions into the INC state. I The pointer interpreter transitions out of the INC state based on the following conditions: — If NDF is enabled on the incoming H1 and H2 bytes, the pointer interpreter transitions from the INC state into the NDF state. — Following three consecutive frames with all ones in the H1 and H2 bytes, the pointer interpreter transitions from the INC state into the AIS-TU3 state. — Following three new consecutive, consistent, and valid pointers, the pointer interpreter transitions from the INC state into the NORM state. — Following any three consecutive, consistent, and valid pointers, the pointer interpreter transitions from the INC state into the NORM state. — Following the number of consecutive invalid pointers (determined by the value programmed in SPE_CNTDLOPCNT[1:0] ( Table 149)), the pointer interpreter transitions from the INC state into the LOP-TU3 state.

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 May 2001 410 Agere Systems Inc. I The pointer interpreter transitions into the DEC state based on the following conditions: — When operating in the 8 of 10 mode (SPE_8ORMAJORITY = 1 (Table 149)), if 8 of the 10 I and D bits are correct for a pointer decrement on the incoming H1 and H2 bytes, the pointer interpreter transitions into the DEC state. Otherwise, if 3 of the 5 I bits and 3 of the 5 D bits are correct for a pointer decrement on the incoming H1 and H2 bytes the pointer interpreter transitions into the DEC state. I The pointer interpreter transitions out of the DEC state based on the following conditions: — If NDF is enabled on the incoming H1 and H2 bytes, the pointer interpreter transitions from the DEC state into the NDF state. — Following three consecutive frames with all ones in the H1 and H2 bytes, the pointer interpreter transitions from the DEC state into the AIS-TU3 state. — Following three new consecutive, consistent, and valid pointers, the pointer interpreter transitions from the DEC state into the NORM state. — Following any three consecutive, consistent, and valid pointers, the pointer interpreter transitions from the DEC state into the NORM state. — Following the number of consecutive invalid pointers (determined by the value programmed in SPE_CNTDLOPCNT[1:0]), the pointer interpreter transitions from the DEC state into the LOP-TU3 state. I Pointer increments and decrements will be counted and presented to the microprocessor as follows: — Pointer increments and decrements will be monitored and counted internally. — The internal and latched counts will be forced to 0x00 if device pin AUTO_AIS (AC6, AE6, and AD6) = 1 (from TMUX), bit SPE_RLOP = 1 (Table 148), or bit SPE_RAIS = 1 (Table 148). — Latched counts, SPE_RPTR_INC[10:0] (Table 161) and SPE_RPTR_DEC[10:0] (Table 161), will be updated coincident with the end of a performance monitor interval. — The internal counters will reset to 0x00 coincident with the end of a performance monitor interval. — If SMPR_SAT_ROLLOVER = 1 (Table 67), the internal running counts will hold at their maximum value. Oth- erwise, the counts will roll over. — However, increment and decrement event indications should be ignored during LOP state. I LOP-TU3 (TU-3 path LOP) and AIS-TU3 (TU-3 path AIS) will be detected and reported to the microprocessor. Both the LOP-TU3 and AIS-TU3 conditions will contribute to the AUTO AIS control signal from the SPE mapper to the VT mapper. Any change in state of SPE_RLOP (Table 148) or SPE_RAIS (Table 148) will be reported to the microprocessor via SPE_RLOPD (Table 146) and SPE_RAISD ( Table 146). Unless the appropriate mask bit is set (SPE_RLOPM/SPE_RAISM (Table 147)), SPE_RLOPD = 1 or SPE_RAISD = 1 will generate an interrupt. I The current TU-3 pointer value is stored in SPE_STORED_PTR[9:0] (Table 161).

18.14 SPE Mapper Receive Direction Requirements

All monitoring functions supported by the SPE mapper in the receive direction are summarized here: I Loss of CLOCK and loss of sync monitors I J1 monitor I B3 BIP-8 check I C2 signal label monitor I F2 monitor I F3 monitor I N1 monitor I K3 monitor I AIS-P and RDI-P detect I REI-P detect I Signal degrade BER algorithm I Signal fail BER algorithm I Path overhead access channel (POAC) drop I Insertion of AIS-P

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 411Agere Systems Inc. Whenever the continuous N-times detect signals are defined, they require not only that the monitored signal be consistent for N consecutive frames, but also that the frame bytes be error free for all N frames before the status can be updated. If there are any errors in the framing pattern, then the consecutive N-times detection counters must be reset to 0. N can range from 1 to 15. Programming a CNTD block with any value less than 1 will set the CNTD to 1 time detect.

18.14.1 Loss of Clock and Loss of Sync Monitors

The SPE mapper detects and reports loss of the input clocks state for RLSCLK (pin V4) (19 MHz clock) in bit SPE_RLSLOC ( Table 148 on page 137), RLSC52 (pin AC2) (52 MHz clock) in bit SPE_RC52LOC (Table 148), and DS3DATAINCLK (pin J22) (DS3 external clock) in bit SPE_RDS3LOC (Tabl e 1 48), as determined by stuck high or stuck low for time T. The detection time T will be greater than 10 µs but less than 125 µs. The function uses the microprocessor clock as its reference. The device will report changes in the states using bits, SPE_RLSLOCD (Table 146 on page 134), SPE_RC52LOCD (Table 146), and SPE_RDS3LOCD (Table 146); interrupt mask bits SPE_RLSLOCM ( Table 147), SPE_RC52LOCM ( Table 147), and SPE_RDS3LOCM ( Table 147 on page136), respectively. The SPE mapper will detect loss-of-sync conditions for the telecom bus sync signals. The states are reported in the bits, SPE_RSY52LOS (Table 148), SPE_RJ0J1V1LOS (Table 148), SPE_RSPELOS (Table 148), and SPE_RV1LOS ( Table 148). The device will report changes in the states in bits SPE_RSY52LOSD ( Tabl e 1 46), SPE_RJ0J1V1LOSD ( Table 146), SPE_RSPELOSD ( Table 146), SPE_RV1LOSD (Table 146); interrupt mask bits SPE_RSY52LOSM ( Table 147), SPE_RJ0J1V1LOSM (Table 147), SPE_RSPELOSM ( Table 147), and SPE_RV1LOSM ( Table 147), respectively.

18.14.2 J1 Monitor

J1 (path trace) monitoring has six different monitoring modes controlled by bits SPE_J1MONMODE[ 2:0] (Table 149): I SPE_J1MONMODE[2:0] = 000: the SPE mapper will latch the value of the J1 byte every frame for a total 64 bytes in SPE_RJ1DMON[1— 64][7:0] (Table 162). The SPE mapper compares the incoming J1 byte with the next expected value (the expected value is obtained by cycling through the previous stored 64 received bytes in round-robin fashion) and setting the path trace identifier state bit, SPE_RTIM (Table 148), if different. Any change in state is reported in bit, SPE_RTIMD (Table 146), using interrupt mask bit SPE_RTIMM (Tabl e 1 47). CRC is not checked by the hardware. I SPE_J1MONMODE[2:0] = 001: this is the SONET framing mode. The hardware looks for 0x0D and then the 0x0DA characters to indicate that the next byte is the first byte of the path trace message. The J1 byte message is continuously written into SPE_RJ1DMON[1— 64][7:0] with the first byte residing at the first address. If any received byte does not match the previously received byte for its location, then the state bit SPE_RTIM is set. Any change in state is reported in bit SPE_RTIMD, using interrupt mask bit SPE_RTIMM. I SPE_J1MONMODE[2:0] = 010: this is the SDH framing mode. The hardware looks for the byte with the most sig- nificant bit (MSB) set to one, which indicates that the next byte is the second byte of the message. The rest of operation is the same as in SONET framing mode. I SPE_J1MONMODE[2:0] = 011: a new J1 byte (SPE_RJ1DMON[1][7:0]) will be detected after a number of con- secutive consistent occurrences (SPE_CNTDJ1[3:0] (Table 150)) of a new pattern in the J1 overhead byte. Any changes to this byte is reported in bit SPE_RTIMD, using interrupt mask bit SPE_RTIMM. The delta bit in this mode indicates a change in state for the J1 byte, and the bit SPE_RTIM is not used. I SPE_J1MONMODE[2:0] = 100: the user will program the 64 expected values of J1 in registers, SPE_RJ1DEXP[1 — 64][7:0] (Table 164), in SONET framing mode, where the first expected byte, the byte follow- ing the 0x0A character, is written into the first register location, SPE_RJ1DEXP[1][7:0]. The SPE mapper com- pares the incoming J1 sequence with the stored expected value, setting the SPE_RTIM state bit if they are different. Any changes in the state is reported in bit SPE_RTIMD, using interrupt mask bit SPE_RTIMM.

SPE_RJ1DEXP[1 — 16][7:0] in SDH framing mode, where the first byte of the message has the MSB set to 1. I SPE_J1MONMODE[1:0] = 110 and 111 are currently undefined. SPE m apper to the VT mapper). I Unless mask bit SPE_RTIMM is set, bit SPE_RTIMD can generate an interrupt. Table 536. J1 Monitor

18.14.3 B3 BIP-8 Check

18.14.4 Signal Label C2 Byte Monitor

Table 537. STS Signal Label Defect Conditions SPE_J1MONMODE[2:0] ( Table 149) J1 Monitoring Type. SPE_RJ1DEXP[1 — 64][7:0] (Tabl e 1 64) J1 Expected Data Storage (64/1 Byte). SPE_RJ1DMON[1 — 64][7:0] (Table 162) J1 Received Data Storage (64/1 Byte). SPE_CNTDJ1[3:0] (Tabl e 1 50) Continuous Times Detect Value. SPE_RTIM (Table 148) J1 Mismatch State Bit. SPE_RTIMD ( Table 146) J1 Mismatch Delta Bit, Active-High. SPE_RTIMM ( Table 147) J1 Mismatch Mask Bit, Active-High.

to updating SPE_C2DMON[7:0]. (Table 146 on page 134) is set and bit SPE_C2DMONM ( Table 147 on page136) is the interrupt mask bit. (Table 146) with an interrupt mask SPE_RUNEQM (Table 147). Table 538. C2MON Processing

18.14.5 Path User Byte F2 Monitor

number of frames equal to the value of SPE_CNTDF2[3:0] prior to updating SPE_F2DMON0[7:0]. (Table 146) is set. The interrupt mask is SPE_F2DMONM (Table 147). The SPE mapper maintains a history of the previous valid F2 byte in SPE_F2DMON1[7:0] (Table 152). SPE_C2DMON[7:0] ( Table 152) C2 Current Data Monitor. SPE_C2DEXP[7:0] (Table 151) Expected Value of C2 Byte. SPE_CNTDC2[3:0] (Tabl e 1 50) Continuous Times Detect Count Value for C2. SPE_C2DMOND ( Table 146) C2 Data Monitor Event Bit. SPE_C2DMONM ( Table 147) C2 Data Monitor Mask Bit. SPE_RPLM ( Table 148) Payload Label Mismatch State. SPE_RPLMD ( Table 146) Payload Label Mismatch Delta Bit. SPE_RPLMM ( Table 147) Payload Label Mismatch Mask Bit. SPE_RUNEQ ( Table 148) Unequipped Path State. SPE_RUNEQD ( Table 146) Unequipped Path Delta Bit. SPE_RUNEQD ( Table 147) Unequipped Path Mask Bit.

Table 539. F2 Monitor

18.14.6 Path User Byte F3 Monitor

be identical for a number of frames, determined by SPE_CNTDF3[ 3:0], prior to updating SPE_F3DMON0[7:0]. (Table 146) is set. The interrupt mask is in register bit SPE_F3DMONM (Table 147). The SPE mapper maintains a history of the previous valid F3 byte in SPE_F3DMON1[7:0] (Table 152). Table 540. F3 Monitor

18.14.7 N1 Monitor

bits SPE_CNTDN1[3:0] prior to updating the N1 register. Table 541. N1 Monitor SPE_F2DMON0[7:0] (Table 152) Fault Location Current Consistent Value. SPE_F2DMON1[7:0] (Table 152) Fault Location Previous Consistent Value. SPE_CNTDF2[3:0] (Table 150) Continuous N-Times Detect (3— 15). SPE_F2DMOND ( Tabl e 1 46) F2 Data Monitor Delta Bit. SPE_F2DMONM ( Table 147) F2 Data Monitor Mask Bit. SPE_F3DMON0[7:0] (Table 152) User Channel Current Consistent Value. SPE_F3DMON1[7:0] (Table 152) User Channel Previous Consistent Value. SPE_CNTDF3[3:0] (Table 150) Continuous N-Times Detect (3— 15). SPE_F3DMOND ( Table 146) F3 Data Monitor Delta Bit. SPE_F3DMONM ( Table 147) F3 Data Monitor Mask Bit. SPE_N1DMON[7:0] (Table 152) Fault Location Current Consistent Value. SPE_CNTDN1[3:0] (Table 150) Continuous N-Times Detect (3— 15). SPE_N1DMOND ( Table 146) N1 Data Monitor Delta Bit. SPE_N1DMONM ( Tabl e 1 47) N1 Data Monitor Mask Bit.

18.14.8 K3 Byte Monitor

mined by the value of SPE_CNTDK3[3:0] prior to updating the K3 register. SPE_K3DMONM ( Table 147 on page 136). Table 542. K3 Monitor

18.14.9 AIS-P and RDI-P Detect

using SPE_RAISM (Table 147 on page136). the G1 byte (G1[3:1]) are reserved for the RDI-P signal. condition in the G1[3:1] bits and stores the current value in bits SPE_PRDIDMON[2:0] (Table 152 on page140). frames, determined by the value of SPE_CNTDPRDI[3:0] prior to updating SPE_PRDIDMON[2:0]. is set. The interrupt generated by SPE_PRDIDMOND can be masked off by SPE_PRDIDMONM ( Table 147). Table 543. AIS-P and RDI-P Detect SPE_K3DMON[7:0] (Table 152) Fault Location Current Consistent Value. SPE_CNTDK3[3:0] (Table 150) Continuous N-Times Detect (3— 15). SPE_K3DMOND ( Table 146) K3 Data Monitor Delta Bit. SPE_K3DMONM ( Tabl e 1 47) K3 Data Monitor Mask Bit. SPE_CNTDPRDI[3:0] (Table 150) Continuous Times Detect Count Value for G1[3:1] Bits (3— 15). SPE_PRDIDMOND ( Table 146) Path RDI Delta Bit. SPE_PRDIDMONM ( Table 147) Path RDI Mask Bit.

18.14.10 REI-P Detect

Bits 7 through 4 of the G1 byte are allocated for use as a path remote error indication function (REI-P). by the PTE (using the path BIP-8 code B3) back to its peer PTE as follows. Table 544. STS-1 P-REI Interpretation

18.14.11 Signal Degrade BER Algorithm

algorithm operates on B3 errors. (Table 158)), for the measurement interval. signal degrade state is declared. rithm into the failed state or normal state, respectively.

Table 545. Signal Degrade Parameters

18.14.12 Signal Fail BER Algorithm

(Table 146) with the interrupt mask bit SPE_SFB3M (Table 147). This bit error rate algorithm operates on B3 errors. monitoring blocks equals or exceeds the threshold, M (SPE_SFMCLEA R[7:0] (v)), for the measurement interval. to the cleared state with bit SPE_SFCLEAR (Table 145). SPE_SDNSSET[18:0] (Table 158) Signal Degrade Ns Set. Number of frames in a monitoring block for SD. SPE_SDNSCLEAR[18:0] ( Table 158) Signal Degrade Ns Clear. Number of frames in a monitoring block for SD. threshold, then SD is cleared. the failed state (active 0 to 1). into the normal state (active 0 to 1). SPE_SDB3 ( Table 148) Signal Degrade BER Algorithm State Bit. SPE_SDB3D ( Table 146) Signal Degrade BER Algorithm Delta Bit. SPE_SDB3M ( Tabl e 1 47) Signal Degrade BER Algorithm Mask Bit.

Table 546. Signal Fail Parameters

18.14.13 POAC Drop

The SPE mapper accommodates one path overhead access channel (POAC output channel). I A 576 kHz inverted clock signal sourced by the TMUX (RPOACCLK, pin AE3). I A 576 kbits/s data signal sourced by the TMUX (RPOACDATA, pin AD4). an odd/even parity bit over the 72 bits of the previous frame. The remaining 7 bits of this byte are not specified. Bytes shown in Table 547 summarize the access capabilities of the receive POAC. SPE_SFNSSET[18:0] (Table 159) Signal Fail Ns Set. Number of frames in a monitoring block for SF. SPE_SFBSET[15:0] (Table 159) Signal Fail B Set. Number of monitoring blocks. SPE_SFNSCLEAR[18:0] ( Tabl e 1 59) Signal Fail Ns Clear. Number of frames in a monitoring block for SF. SPE_SFBCLEAR[15:0] (Tabl e 1 59) Signal Fail B Clear. Number of monitoring blocks. failed state (active 0 to 1). the normal state (active 0 to 1). SPE_SFB3 ( Table 148) Signal Fail BER Algorithm State Bit. SPE_SFB3D ( Table 146) Signal Fail BER Algorithm Delta Bit. SPE_SFB3M ( Table 147) Signal Fail BER Algorithm Mask Bit.

Table 547. Path Overhead Byte Access selected with register bit, SPE_RPOAC_OEPINS (Table 149 on page138).

18.14.14 Insertion of AIS-P

pointer state (SPE_RLOP (Table 148)) and the appropriate inhibit signals are inactive. I AIS is requested by signals from the TMUX interface. I AIS is forced by setting bit SPE _PAISINS (Table 149). I Any one of the loss-of-clock or loss-of-sync bits are active and their corresponding inhibit bits are inactive. inhibit signals are inactive. The SPE mapper starts/stops generating AIS-P within 125 µs of the detection/absence of a failure condition. AIS-P consists of writing all ones into the H1, H2, and H3 bytes and into the entire payload.

18.15 Transmit Direction (to SONET/SDH Line)

value of microprocessor register bit SMPR_OH_DEFLT (Table 67).

18.15.1 PATH Insertion Block

error bytes and the rest of the path overhead bytes to form a TUG-3 frame. Figure 37. Transmit Direction Path Insertion Block

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 421Agere Systems Inc.

18.15.2 Loss of Clock and Loss of Sync Detectors

The SPE mapper detects and reports the loss of the input clocks for the transmit telecom bus clock, device pin TLSCLK (AA2), in bit SPE_TLSLOC (Table 148 on page137); the 51.84 MHz transmit low-speed clock, device pin TLSC52 (AC3), in bit SPE_TC52LOC (Table 148), and the external DS3 clock, device pin DS3DATAINCLK (J22), in bit SPE_TDS3LOC (Table 148). Loss of clock is determined by stuck high or stuck low for time T. The detection time T will be greater than 10 µs but less than 125 µs. The function uses the microprocessor clock as its reference. The device will report a change in the loss of clock state for the monitored clocks using bits SPE_TLSLOCD (Table 146 on page 134), SPE_TC52LOCD (Table 146), and SPE_TDS3LOCD (Table 146), respectively. The microprocessor interrupt may be masked using bits SPE_TLSLOCM (Table 147 on pag e136), SPE_TC52LOCM (Table 147), and SPE_TDS3LOCM (Table 147), respectively. The SPE mapper detects loss-of-sync conditions for the telecom bus sync signals, device pins TLSSYNC52 (AD2), TLSJ0J1V1 (AB4), TLSSPE (AB2), and TLSV1 (AB3). The loss of sync states are reported in bits SPE_TSY52LOS ( Table 148), SPE_TJ0J1V1LOS (Table 148), SPE_TSPELOS (Table 148), and SPE_TV1LOS (Table 148), respectively. The device will report a change in the loss of sync state for the monitored sync signals in bits SPE_TSY52LOSD (Table 146), SPE_TJ0J1V1LOSD (Table 146), SPE_TSPELOSD (Table 146), and SPE_TV1LOSD ( Table 146), respectively. The microprocessor interrupt may be masked using bits SPE_TSY52LOSM ( Table 147), SPE_TJ0J1V1LOSM (Table 147), SPE_TSPELOSM ( Table 147), and SPE_TV1LOSM ( Table 147), respectively.

18.15.3 J1 Byte Insert

A 64-byte sequence stored in SPE_TJ1DINS[1— 64][7:0] (Table 163 on page 148) will be inserted into the outgoing J1 byte when bit SPE_TJ1INS = 1 (Table 154 on page143); otherwise, the associated POAC value is inserted when bit SPE_TPOAC_J1 = 1 (Tabl e 1 54) or the default value, determined by the value of microprocessor bit SMPR_OH_DEFLT ( Table 67 on pag e68), is inserted when SPE_TPOAC_J1 = 0. The CRC for the J1 trace has to be programmed into the J1 bytes by the user.

18.15.4 B3 BIP-8 Calculation and Insert

The B3 bytes are allocated for path overhead error monitoring function. This function is a bit interleaved parity 8 code (BIP-8) using even parity. The BIP-8 is computed before scrambling over all bits of the previous AU-3/TUG-3 frame, and is placed in byte B3 of the current frame also before scrambling. When enabled with control bit, SPE_TB3ERRINS ( Table 156), a single B3 byte can be inverted each time bit SPE_BERR_INS (Table 156) is asserted.

18.15.5 C2 Signal Label Byte Insert

When bit SPE_TC2INS = 1 (Table 154), the value in SPE_TC2DINS[7:0] (Table 157) is inserted into the outgoing C2 byte; otherwise, insert the associated POAC value when SPE_TPOAC_C2 = 1 (Table 154) or insert the default value determined by the microprocessor bit SMPR_OH_DEFLT when bit SPE_TPOAC_C2 = 0.

18.15.6 REI-P G1(7:4) Insert

Four bits of the G1 byte G1(7:4) are allocated for use as a path remote error indication (REI). For AU-3/TUG-3 sig- nals, these bits convey the count (in the range of 0 to 8) of interleaved bit blocks that have been detected in error by the BIP-8 (B3) detector on the received signal. This function can be inhibited with bit SPE_TREIP_INH (Table 155) and the value in SPE_TG1DINS[7:4] (Table 157) is inserted in G1(7:4) bits. A continuous error in the G1 byte can be transmitted using control bit SPE_TREIERRINS ( Table 156). A value of 0x03 will be inserted when SPE_TREIERRINS = 1, subject to SPE_BERR_INS and SMPR_BER_INSRT being enabled.

18.15.7 Path RDI (RDI-P) Insert

LOP-P . For enhanced RDI-P mode, the relevant defects are AIS-P , LOP-P , TIM-P , PLM-P , and UNEQ-P , and TIM-P. last for at least 20 frames before clearing, even if the original failure cause has cleared in less than 20 frames. The following table describes the encoding of the path-RDI defects. Table 548. RDI-P Defects for Enhanced RDI-P Mode

18.15.8 F2 Byte Insert

default value determined by the microprocessor bit SMPR_OH_DEFLT (Table 67) when SPE_TPOAC_F2 = 0.

18.15.9 H4 Insert Control

determined by the microprocessor bit SMPR_OH_DEFLT when SPE_TPOAC_H4 = 0.

18.15.10 F3 Byte Insert

default value determined by the microprocessor bit SMPR_OH_DEFLT (Table 67) when SPE_TPOAC_F3 = 0.

18.15.11 K3 Insert Control Parameters

default value determined by the microprocessor bit SMPR_OH_DEFLT when SPE_TPOAC_K3 = 0.

18.15.12 N1 Insert Control Parameters

default value determined by the microprocessor bit SMPR_OH_DEFLT when SPE_TPOAC_N1 = 0.

18.16 POAC Insert

I A 576 kHz inverted clock signal sourced by the SPE m apper (TPOACCLK, pin AE4). I A 576 kbits/s data signal received by the SPE m apper in the transmit direction (TPOACDATA, pin AD5). the access capabilities of the transmit POAC channel. Table 549. Path Overhead Byte Access— Transmit Direction SPE_TPOAC_PE ( Table 146). The interrupt can be masked with bit SPE_TPOAC_PM (Table 147 on page136). inserted on the corresponding POAC value.

Table 550. TPOAC Control Bits

18.17 AIS Path Generation

SPE_TAISPINS = 1 (Table 154 on page143).

19 VT/TU Mapper Functional Description

19 VT/TU Mapper Functional Description (continued)

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 427Agere Systems Inc.

19.1 VT/TU Mapper Introduction

This section describes the requirements of the SONET/SDH virtual tributary payload mapping block. This block supports the following mappings: I 28 asynchronous, byte synchronous, or bit synchronous DS1 signals into seven virtual tributary groups (VTGs). I 28 asynchronous, byte synchronous, or bit synchronous DS1 signals into seven tributary unit groups (TUG-2s). I 28 asynchronous, byte synchronous, or bit synchronous J1 signals into seven virtual tributary groups (VTGs). I 28 asynchronous, byte synchronous, or bit synchronous J1 signals into seven tributary unit groups (TUG-2s). I 21 asynchronous, byte synchronous, or bit synchronous E1 signals into seven tributary unit groups (TUG-2s). I Any valid DS1/E1 combination resulting in mixed VTGs and TUG-2s. Additionally, this block has two auxiliary channels: one for DS1/E1 signaling insertion and drop, and another for low-order path overhead (LOPOH) insertion and drop. Control inputs and outputs for each internal block are speci- fied, along with appropriate control register bit definitions.

19.2 VT/TU Mapper Features

I Maps T1/E1/J1 into VT/TU structures: — T1 into VT1.5/TU-11/TU-12. — J1 into VT1.5/TU-11/TU-12. — E1 into VT2/TU-12. I Supports asynchronous, byte synchronous, and bit synchronous mappings. I Supports automatic generation or microprocessor overwrite of one bit RDI and one bit RFI. I Supports automatic generation or microprocessor overwrite of enhanced RDI. I Supports ADM applications via tributary loopback and tributary pointer processing. I Supports unidirectional path switch ring (UPSR) applications via low-order path overhead access channel. I Supports five J2 trace identifier modes. I Programmable BIP-2 error insertion. I Monitors BIP-2 bit error rate. I Programmable clear-on-read/clear-on-write registers. I Supports automatic AIS generation for downstream devices. I VC-BIP-2, VC-REI one second error counters. I Programmable saturation or rollover of internal counters.

19.3 VT/TU Mapper Functional Block Diagram

Figure 38. VT Mapper Interface Diagram

Figure 39. VT Mapper Functional Block Diagram

19.4 VT/TU Mappings

Table 551. VT2/TU-12 Payload Mapping Table 552. VT1.5/TU-11 Payload Mapping

19.5 VT/TU Locations

Table 553. VT2/TU-12 Locations provisioned to map any external E1 to any VT2. † See VT2/TU-12 Payload Mapping on page 430. Table 554. VT1.5/TU-11 Locations provisioned to map any external DS1 to any VT1.5. † See VT1.5/TU-11 Payload Mapping on page 430.

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 May 2001 432 Agere Systems Inc.

19.6 VT/TU Mapper Receive Path Description

This section describes all necessary functions of the receive logic (see Figure 39, right to left): I Virtual tributary demultiplexor (VTDEMUX) I Virtual tributary pointer interpreter (VTPI) I Virtual tributary terminator (VTTERM) I Output selector (OUTSEL) I J2 16-byte sequence monitor (J2MON) I Receive VT/TU signaling (RX_VTSIG) I Receive low-order path overhead (RX_LOPOH)

19.7 VT Demultiplexer (VTDEMUX)

The VTDEMUX logic block (in Figure 39 on page429) will perform all necessary functions to decode which virtual tributary (VT) is active on the data bus. This block monitors the H4 byte and frames on the H4 multiframe indication. In frame (VT_H4LOMF = 0 (Table 176)) will be declared following two consecutive, nonerrored multiframe indications. A multiframe indication consists of four consecutive frames containing a (00, 01, 10, 11) pattern in the two LSBs of the H4 byte. Once framed, H4 loss of multiframe (VT_H4LOMF = 1) will be declared following the number of consecutive mismatches in the H4 multiframe indication programmed into bits VT_H4_NTIME[3:0] (Table 182). Loss of H4 multiframe align- ment will generate AIS downstream. A change in H4 multiframe alignment is indicated by bit VT_H4LOMF_D (Table 168) and will generate an interrupt unless the mask is set (VT_H4LOMF_M = 1 (Tabl e 1 80)). Bits VT_RX_GRP_TYPE[6:0] (Table 180) are programmed to determine whether the incoming tributary is a VT1.5/TU-11 or a VT2/TU-12. See Table 551 through Table 554 on page 430 through page 431 for VT/TU mapping formats.

19.8 VT Pointer Interpreter (VTPI)

The VTPI logic block (in Figure 39 on page429) will perform all necessary functions to support VT/TU pointer inter- pretation. The following features are implemented: The pointer interpreter consists of the following states: I Loss of pointer (LOP-V) I VT -AIS (AIS-V) (all ones in V1 and V2) I NDF enabled (NDF) (1001, 0001, 1101, 1011, 1000) I Normal (NORM) (disabled NDF, normal pointer) I Increment (INC) (inverted I bits) I Decrement (DEC) (inverted D bits)

INC, DEC, and NDF states into the LOP state have been added. Figure 40. Pointer Interpretation State Diagram frames programmed in bits VT_NDF_NTIME[3:0] (Table 183), then LOP-V will be declared. or decrement, then LOP-V will be declared. The SS bits contribute to an invalid pointer indication. sition from the LOP-V state into the AIS-V state. LOP-V state into the NORM state. — The pointer interpreter does not transition from the LOP-V state into the NDF state. — Following three consecutive superframes with all ones in the V1 and V2 bytes AIS-V will be declared. AIS-V state into the NORM state. terpreter will transition from the AIS-V state into the LOP-V state.

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 May 2001 434 Agere Systems Inc. I The pointer interpreter will transition into the NDF state based on the following conditions: — If NDF is enabled on the incoming V1 and V2 bytes, the pointer interpreter will transition from the NORM, NDF, AIS, INC, and DEC states into the NDF state. I The pointer interpreter will transition out of the NDF state based on the following conditions: — Continuous NDF. If NDF (1001, 0001, 1101, 1011, 1000) is received for the number of consecutive super- frames programmed in bits VT_NDF_NTIME[3:0] (Table 183), the pointer interpreter will transition from the NDF state into the LOP-V state. — Following any three consecutive, consistent, and valid pointers, the pointer interpreter will transition from the NDF state into the NORM state. — Following three consecutive superframes with all ones in the V1 and V2 bytes, the pointer interpreter will tran- sition from the NDF state into the AIS-V state. — Following three new consecutive, consistent, and valid pointers, the pointer interpreter will transition from the NDF state into the NORM state. — Following the number of consecutive invalid pointers programmed in bits VT_INV_NTIME[3:0] (Table 183), the pointer interpreter will transition from the NDF state into the LOP-V state. I The pointer interpreter will transition into the NORM state based on the following conditions: — Following three new consecutive, consistent, and valid pointers, the pointer interpreter will transition into the NORM state. — Following any three consecutive, consistent, and valid pointers, the pointer interpreter will transition into the NORM state. i.e., transitioning from the INC, DEC, and NDF states. I The pointer interpreter will transition out of the NORM state based on the following conditions: — Following the number of consecutive invalid pointers programmed in bits VT_INV_NTIME[3:0], the pointer in- terpreter will transition from the NORM state into the LOP-V state. — If NDF is enabled on the incoming V1 and V2 bytes, the pointer interpreter will transition from the NORM state into the NDF state. — Following three consecutive superframes with all ones in the V1 and V2 bytes, the pointer interpreter will tran- sition from the NORM state into the AIS-V state. — When operating in the 8 of 10 mode (VT_8ORMAJORITY = 1 (Table 181)), if 8 of the 10 I and D bits are correct for a pointer decrement on the incoming V1 and V2 bytes, the pointer interpreter will transition from the NORM state into the DEC state. Otherwise, if 3 of the 5 I bits and 3 of the 5 D bits are correct for a pointer decrement on the incoming V1 and V2 bytes, the pointer interpreter will transition from the NORM state into the DEC state. — When operating in the 8 of 10 mode (VT_8ORMAJORITY = 1), if 8 of the 10 I and D bits are correct for a pointer increment on the incoming V1 and V2 bytes, the pointer interpreter will transition from the NORM state into the INC state. Otherwise, if 3 of the 5 I bits and 3 of the 5 D bits are correct for a pointer increment on the incoming V1 and V2 bytes, the pointer interpreter will transition from the NORM state into the INC state. I The pointer interpreter will transition into the INC state based on the following conditions: — When operating in the 8 of 10 mode (VT_8ORMAJORITY = 1), if 8 of the 10 I and D bits are correct for a pointer increment on the incoming V1 and V2 bytes, the pointer interpreter will transition into the INC state. Otherwise, if 3 of the 5 I bits and 3 of the 5 D bits are correct for a pointer increment on the incoming V1 and V2 bytes, the pointer interpreter will transition into the INC state. I The pointer interpreter will transition out of the INC state based on the following conditions: — If NDF is enabled on the incoming V1 and V2 bytes, the pointer interpreter will transition from the INC state into the NDF state. — Following three consecutive superframes with all ones in the V1 and V2 bytes, the pointer interpreter will tran- sition from the INC state into the AIS-V state. — Following three new consecutive, consistent, and valid pointers, the pointer interpreter will transition from the INC state into the NORM state. — Following any three consecutive, consistent, and valid pointers, the pointer interpreter will transition from the INC state into the NORM state. — Following the number of consecutive invalid pointers programmed in bits VT_INV_NTIME[3:0], the pointer in- terpreter will transition from the INC state into the LOP-V state.

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 435Agere Systems Inc. I The pointer interpreter will transition into the DEC state based on the following conditions: — When operating in the 8 of 10 mode (VT_8ORMAJORITY = 1 (Table 181)), if 8 of the 10 I and D bits are correct for a pointer decrement on the incoming V1 and V2 bytes, the pointer interpreter will transition into the DEC state. Otherwise, if 3 of the 5 I bits and 3 of the 5 D bits are correct for a pointer decrement on the incoming V1 and V2 bytes, the pointer interpreter will transition into the DEC state. I The pointer interpreter will transition out of the DEC state based on the following conditions: — If NDF is enabled on the incoming V1 and V2 bytes, the pointer interpreter will transition from the DEC state into the NDF state. — Following three consecutive superframes with all ones in the V1 and V2 bytes, the pointer interpreter will tran- sition from the DEC state into the AIS-V state. — Following three new consecutive, consistent, and valid pointers, the pointer interpreter will transition from the DEC state into the NORM state. — Following any three consecutive, consistent, and valid pointers, the pointer interpreter will transition from the DEC state into the NORM state. — Following the number of consecutive invalid pointers programmed in bits VT_INV_NTIME[3:0] (Table 183), the pointer interpreter will transition from the DEC state into the LOP-V state. Pointer increments and decrements are monitored and counted internally. The performance monitoring reset signal transfers the count to the holding registers for pointer increment (VT_PTR_INC[1— 28][3:0] (Table 208)), and pointer decrement (VT_PTR_DEC[1— 28][3:0] (Table 208)) for microprocessor read and resets the running count registers to 0. When SMPR_SAT_ROLLOVER = 1 (Tabl e 6 7), the internal running counts will hold at their maxi- mum value. Otherwise, the counts will roll over. The running count and holding register counts will be forced to 0, if the SPE mapper is requesting AUTO AIS or VT_LOP[1— 28] = 1 (loss of pointer) (Table 177) or VT_AIS[1— 28] = 1 (VT AIS) (Table 177) (or VT_H4LOMF = 1 (loss of H4 multiframe alignment) (Table 176)). LOP-V (VT_LOP) and AIS-V (VT_AIS) will be detected and reported to the microprocessor. Both the LOP-V and AIS-V conditions will contribute to the VT/TU mapper automatic AIS generation that is driven over a 28-bit internal output bus to the cross connect (XC). Any change in state of VT_LOP or VT_AIS will be reported to the micropro- cessor via VT_LOP_D[1— 28] and VT_AIS_D[1— 28] (Table 169). Unless the appropriate mask bit is set (VT_LOP_M[1 — 28] or VT_AIS_M[1— 28]) (Tabl e 1 73), VT_LOP_D[1— 28] = 1 or VT_AIS_D[1— 28] = 1 will gener- ate an interrupt. A check for VT/TU size mismatches is performed by comparing the expected VT/TU size bits (VT1.5 = 11, VT2 = 10) with the actual received SS bits in the V1 byte. After three consecutive mismatches, size errors will be reported with bit VT_SIZERR[1— 28] (Table 177). Any change in state of VT_SIZERR[1— 28] will be reported with bit VT_SIZERR_D[1— 28] (Table 169). Unless the VT_SIZERR_M[1— 28] (Table 173) mask bit is set, VT_SIZERR_D[1 — 28] = 1 will generate an interrupt. The accepted pointer is stored and accessible by the microprocessor. This block supports tributary loopback.

19.9 VT Termination (VTTERM)

The VTTERM logic block (in Figure 39) will perform all necessary functions to support complete VT/TU termination. The following features are implemented.

19.9.1 V5 Termination

The V5 byte is checked for BIP-2 errors. If BIP-2 errors are detected, REI-V is transmitted in the V5 byte of the cor- responding transmit VT, if enabled by bit VT_REI_EN[1— 28] = 1 (Table 198). BIP-2 errors and reception of REI-V in the V5 byte is counted on a per-superframe basis. BIP-2 errors can counted on either a bit or block basis selected by bit, VT_BIT_BLOCK_CNT (1 = bit, 0 = block) (Table 181).

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 May 2001 436 Agere Systems Inc. BIP-2 errors and REI-V reception are monitored and counted internally. The performance monitoring reset signal transfers the count to the holding registers for BIP-2 error count (VT_BIP2ERR_CNT[1 — 28][11:0]; Table 206), and REI-V count (VT_REI_CNT[1— 28][10:0] (Table 207)) for microprocessor read, and resets the running count regis- ters to 0. When SMPR_SAT_ROLLOVER = 1 (Table 67), the internal running counts will hold at their maximum value. Otherwise, the counts will roll over. The running count and holding register counts will be forced to 0, if the SPE mapper is requesting AUTO AIS, VT_LOP[1— 28] = 1 (loss of pointer), VT_AIS[1— 28] = 1 (VT AIS) (Table 177) or VT_H4LOMF = 1 (loss of H4 multiframe alignment) (Table 176). The V5 byte will be checked for received RFI-V via VT_RFI[1— 28] bits (Table 177). New values will be latched into the register after the number of consecutive values programmed in bits VT_RDI_NTIME[3:0] (Table 184) have been received. A VT_RFI[1— 28] change of state is reported by bit VT_RFI_D[1— 28] (Table 169). When operating in the DS1 byte synchronous mode, RFI-V = 1 will force DS1 RAI downstream to the framer. Unless the VT_RFI_M mask bit (Table 173) is set, VT_RFI_D[1— 28] = 1 will generate and cause an interrupt. When operating in normal RDI-V mode (VT_RX_ERDI_EN[1— 28] = 1 (Table 204, starting on page168)), the V5 byte will be checked for received RDI-V and reported via VT_RDI[1— 28] bits (Table 177). New values will be latched to this register after VT_RDI_NTIME[3:0] consecutive values have been received. A VT_RDI[1— 28] change of state is reported via VT_RDI_D[1— 28] (Table 169). Unless the VT_RDI_M[1— 28] (Table 173) mask bit is set, VT_RDI_D[1— 28] = 1 will generate and cause an interrupt. When operating in enhanced RDI-V mode (VT_RX_ERDI_EN[1 — 28] = 0 (Table 204, starting on page168)), the V5 byte will be checked for received RDI-V and reported via VT_RDI[1— 28] bit (Table 177). New values will be latched to this register after VT_ERDI_NTIME[3:0] (Table 184) consecutive ERDI-V values (V5 bit 8 and Z7 bits 5— 7) have been received. A VT_ERDI[1— 28][2:0] change of state is reported via VT_ERDI_D[1— 28] (Tabl e 1 69). Unless the VT_ERDI_M[1— 28] mask bit (Table 173) is set, VT_ERDI_D[1— 28] = 1 will generate and cause an interrupt. The V5 byte VT/TU signal label will be monitored and reported to the microprocessor using bits VT_LAB[1 — 28][2:0] (Tabl e 1 77). New values will be latched to the microprocessor after the number of consecutive values programmed in bits VT_LAB_NTIME[3:0] (Table 184) have been received. An all zeros signal label will set bit VT_UNEQ[1— 28] (Tabl e 1 77). Any change in state of VT_UNEQ[1— 28] will be reported to the microprocessor via bit VT_UNEQ_D[1— 28] (Table 169). Unless the VT_UNEQ_M[1— 28] (Table 173) mask bit is set, VT_UNEQ_D[1 — 28] = 1 will generate an interrupt. VT_UNEQ[1— 28] will contribute to automatic AIS generation. The latched signal label will be compared to the expected signal label. If the expected signal label is 001 or if VT_UNEQ[1 — 28] is detected, the detection of PLM-V is disabled. Otherwise, any mismatch is reported to the microprocessor via bit VT_PLM[1— 28] (Table 177). Any change in state of VT_PLM[1— 28] will be reported to the microprocessor via bit VT_PLM_D[1— 28] (Table 169). Unless the VT_PLM_M[1— 28] mask bit is set (Table 173), VT_PLM_D[1 — 28] = 1 will generate an interrupt.

19.9.2 Z6/N2 Termination

For SONET applications, the Z6 byte is monitored and presented to the microprocessor using bits VT_Z6_BYTE[1 — 28][7:0] (Table 205) for growth and monitoring purposes only. The Z6 byte is updated to when three consecutive consistent bytes are received. N2 is defined for tandem connection applications per ETS 300 417-1-1 and ITU-T G.707/G.783. Low-order tandem connection is not supported.

19.9.3 Z7/K4 Termination

This termination will support enhanced RDI when bit VT_RX_ERDI_EN[1 — 28] = 1(Table 204, starting on page 168). The Z7/K4[3:1] byte will be monitored and reported to the microprocessor with bits VT_ERDI[1— 28][2:0] (Table 177). New values will be latched to the microprocessor after the number of consecu- tive values programmed in register bits VT_ERDI_NTIME[3:0] (Table 184) have been received. A change of state is reported using bit VT_ERDI_D[1— 28] (Tabl e 1 69). Unless the VT_ERDI_M[1— 28] (Table 173) mask bit is set, VT_ERDI_D[1 — 28] = 1 will generate an interrupt.

The Z7/K4[7:4] byte will be monitored and reported to the microprocessor via bits VT_APS[1— 28][3:0] (Table 178).

19.9.4 Payload Termination

Bellcore GR-253 and ANSI T1.105. SDH TU11s and TU12s per ITU-T G.707 and ETS 300 417-4-1. Table 555. Receive VT/TU Demapping Selection VT_RX_ESOVFL_D[1 — 28] = 1 will generate an interrupt. ping a byte synchronous payload.

19.10 Output Signal Selection (OUTSEL)

DS1/E1 signals with the appropriate AIS clock, data, and frame synchronization.

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 May 2001 438 Agere Systems Inc. VT/TU mapper automatic AIS, which is driven over a 28-bit internal output bus to the cross connect (XC), is gener- ated according to the following equation: SPEMPR_AUTO_AIS or VT_LOP[1 — 28] or VT_AIS[1— 28] or (VT_H4LOMF and (VT_LOMF_AIS_INH or (VT_UNEQ[1 — 28] and (VT_UNEQ_AIS_INH or (VT_PLM[1— 28] and (VT_PLM_AIS_INH or (VT_J2TIM[1— 28] and (VT_J2TIM_AIS_INH)) or (VT_LOPS[1 — 28] and VT_LOPS_AIS_INH)) The output of the VT/TU mapper receive path will be as shown in Figure 43 on page451 and Figure 44 on page 452.

19.11 J2 Byte Monitor and Termination (J2MON)

The J2MON logic block (in Figure 39 on page429) will perform all necessary functions to monitor the incoming J2 trace identifier. The following features are implemented: I J2 monitoring will support five different monitoring modes defined by VT_J2MON_MODE[1— 28][2:0] Table 204 on pag e168: — VT_J2MON_MODE[1 — 28][2:0] = 000: this mode captures an incoming 16-byte sequence and stores it in VT_J2BYTE_DET[1 — 28][1— 16][7:0] (Table 209). TIM-V is disabled for this mode. — VT_J2MON_MODE[1 — 28][2:0] = 001: this mode captures an incoming 16-byte sequence with SDH framing and stores it in VT_J2BYTE_DET[1— 28][1— 16][7:0]. TIM-V is disabled for this mode. — VT_J2MON_MODE[1 — 28][2:0] = 010: this mode captures a constant 1-byte sequence and stores it in VT_J2BYTE_DET[1 — 28][1][7:0]. TIM-V is disabled for this mode. — VT_J2MON_MODE[1 — 28][2:0] = 011: this mode monitors a 16-byte sequence with SDH framing and com- pares it to a programmable expected value. The expected value is programmed by the user using register bits VT_J2BYTE_EXP[1 — 28][1— 16][7:0] (Table 209). The hardware frames by looking for the byte with the MSB set to one, which indicates that the next byte is the second byte of the message. CRC is verified based on the value programmed in VT_J2BYTE_EXP[1— 28][1— 16][7:0]. TIM-V is enabled for this mode. — VT_J2MON_MODE[1 — 28][2:0] = 100: this mode monitors a constant 1-byte sequence and compares it to an programmable expected value. The expected value is programmed by the user using register bits VT_J2BYTE_EXP[1 — 28][1][7:0]. TIM-V is enabled for this mode. I Trace identifier mismatch (TIM-V) will be detected following the number of consecutively errored sequences (1-byte or 16-byte sequences) programmed in bits, VT_ J2_NTIME[3:0] (Table 183), and reported to the micro- processor via bit VT_J2TIM[1— 28] (Table 177). If TIM-V is detected, the J2 byte monitor will transition into the capture mode and start searching for two consecutive consistent 1-byte or 16-byte sequences. Once two con- secutive consistent sequences are detected, the J2 byte monitor will transition into the monitor mode and start searching for the number of consecutive mismatches programmed in register bits VT_ J2_NTIME[3:0], on a per 1-byte or 16-byte sequence basis. Once the hardware finds synchronization (VT_ J2TIM[1— 28] = 0), the new sequence is latched into VT_ J2BYTE_DET[1 — 28][1— 16][7:0] (Table 209). The synchronization algorithm used will not allow single bit errors to pass through to VT_ J2BYTE_DET[1 — 28][1— 16][7:0].

I Any change in state of VT_ J2TIM[1— 28][1— 16][7:0] will be reported in bit VT_ J2TIM_D[1— 28] (Table 169). Unless the VT_ J2TIM_M[1— 28] (Table 173) mask bit is set, VT_ J2TIM_D[1— 28] = 1 will generate an interrupt.

19.12 Receive Signaling (RX_VTSIG)

I The signaling is sent to the appropriate framer link selected by bits VT_RXSIG_CH_SEL[1— 28][4:0] (Table 204). (Table 169) will be forced to 0. VT_LOPS[1 — 28] state will be detected and reported to the microprocessor with bit VT_LOPS_D[1— 28]. I Unless VT_LOPS_M[1 — 28] (Table 173) mask bit is set, VT_LOPS_D[1— 28] will generate an interrupt. I See Table 556 below for signaling behavior based on the receive status and control. Table 556. Rx Signaling Behavior per Channel or ESF framing pattern based on a random starting position. Robbed-bit signaling will not be accessible under such a condition. † When operating in the ESF mode, the Ft bits will be overwritten with the ESF frame and the C and M bits passed transparently. 0 0 X X Pass F-bit transparently. 0 1 0* X Overwrite outgoing F bit with ESF pattern. 0 1 1 X Overwrite outgoing F bit with SF pattern. † 0 Overwrite outgoing F bit with ESF pattern. 1 1 1 0 Overwrite outgoing F bit with SF pattern. 1 X X 1 Transmit DS1 AIS downstream.

19.13 Receive Lower-Order Path Overhead (RX_LOPOH)

ted as a burst of 224 bits on the rising edge of the SPE mapper Rx clock. Note: The number of valid bits transmitted is dependent upon the VT/TU group types. i.e., full VT2 equals 168 bits. data type 001. Data type headers will be defined as shown in Table 557 below. All data types must be transmitted within 500 µs. Table 557. Data Type Header Definitions

• All overhead bytes will be transmitted from MSB to LSB.

which they are received within a VT, starting with the MSB of the nibble following the J2 byte. Figure 45 on pag e452, contains the RX_LOPOH block serial channel format and timing.

19.14 VT/TU Mapper Transmit Path Requirements

This section describes all necessary functions of the transmit logic (see Figure 39 on page429, left to right). 0 0 1 TMUX and SPE m apper RDI/REI. 0 1 0 V5 byte, 28/21 bytes starting with VT 1*. 0 1 1 J2 byte, 28/21 bytes starting with VT 1. 1 0 0 Z6/N2 byte, 28/21 bytes starting with VT 1. 1 0 1 Z7/K4 byte, 28/21 bytes starting with VT 1. 110 O bits, 28/21 bytes starting with VT 1†. 1 1 1 Reserved. Data will be ignored.

19.14.1 Input Selector (INSEL)

DS1/E1 CLOCK is used to retime the signal; otherwise, the falling edge is used. VT_TX_LOC_D = 1 will generate an interrupt. I If LOC is detected (VT_TX_LOC[1— 28] = 1), DS1/E1 AIS will be inserted in the appropriate transmit path VT. DS1/E1 AIS consists of a valid VT/TU pointer, valid VT/TU overhead, and an all ones payload. VT_LOFS_D[1 — 28] = 1 will generate an interrupt. writing an all ones pattern into the entire VT, including V1~4. (Table 179). Any change in state of VT_TX_AIS[1— 28] is reported in bit VT_TX_AIS_D[1— 28] (Tabl e 1 71). periods and cleared when each of two consecutive 512-bit periods contain more than two zeros. Transmit mapping modes are shown in Table 558 below. Table 558. Transmit VT/TU Mapping Selection per Channel, VT_TX_MAPTYPE[1— 28][3:0] 0 0 0 0 Asynchronous VT1.5/TU-11 (DS1 input). 0 0 0 1 Asynchronous VT2/TU-12 (E1 input). 0 0 1 0 Byte synchronous VT1.5/TU-11 (DS1 input). 0 0 1 1 Byte synchronous VT2/TU-12 (E1 input). 0 1 0 0 Bit synchronous VT1.5/TU-11 (DS1 input). 0 1 0 1 Bit synchronous VT2/TU-12 (E1 input). 0110— 0111 Undefined, generates VT1.5/TU-11 UNEQ-V . 1 0 0 0 Asynchronous VT2/TU-12 (DS1 input). 1 0 0 1 Byte synchronous VT2/TU-12 (DS1 input). 1 0 1 0 Bit synchronous VT2/TU-12 (DS1 input). 1011— 1111 Undefined, generates VT2/TU-12 UNEQ-V.

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 May 2001 442 Agere Systems Inc.

19.14.2 Transmit Elastic Store (TES)

The TES logic block (in Figure 39 on pag e429) will perform all functions necessary to synchronize the incoming DS1/E1 or VT1.5/VT2 signals to the local STS-1/STS-3 clock. I This logic block will support the following modes of operation: — Asynchronous, bit synchronous, and byte synchronous mapping from DS1/E1 input. — Asynchronous, bit synchronous, and byte synchronous mapping from loopback VT1.5/VT2 input. The TES logic block has programmable stuffing thresholds. The value programmed in the VT_HIGH_THRES[6:0] (Table 210) controls positive justification. The value programmed in the VT_LOW_THRES[6:0] (Table 210) controls negative justification. The recommended values for nontributary loopback (VT_LB_SEL[1— 28] = 0 (Table 198)) are VT_HIGH_THRES[6:0] = 0x28 and VT_LOW_THRES [6:0] = 0x27. Otherwise (VT_LB_S EL[1— 28] = 1), the rec- ommended values are VT_HIGH_THRES[6:0] = 0x05 and VT_LOW_THRES[6:0] = 0x04. The TES logic block monitors for elastic store overflow conditions and reports with bit VT_TX_ESOVFL_E[1— 28] (Table 171). Unless the VT_TX_ESOVFL_M[1— 28] (Table 175) mask bit is set, VT_TX_ESOVFL_E[1— 28] = 1 will generate and interrupt.

19.14.3 Virtual Tributary Generator (VTGEN)

The VTGEN logic block (in Figure 39 on page429) performs all functions necessary to map all possible DS1/E1 inputs to the appropriate VT/TU structure. This includes VT/TU pointer generation, positive/negative stuffing, VT/TU overhead generation/insertion and DS1/E1 data insertion. The following features will be implemented: I This logic block will support the following modes of operation: — Asynchronous — Byte synchronous — Bit synchronous

19.14.4 Pointer Generation

I The pointer generator will support the following features when operating in asynchronous or bit synchronous mode: — If transmit AIS-V is not requested, the following requirements apply: 1. A fixed pointer value of decimal 78 is generated for VT1.5/TU-11 mappings. 2. A fixed pointer value of decimal 105 is generated for VT2/TU-12 mappings. 3. The VT size field will be set to binary 11 for VT1.5/TU-11 mappings. 4. The VT size field will be set to binary 10 for VT2/TU-12 mappings. 5. The new data flag (NDF) set to binary 0110 for VT1.5/VT2 mappings. 6. V3 and V4 is set to the selected overhead default (SMPR_OH_DEFLT ( Table 67) in the microprocessor inter- face block) for all mappings: — If transmit AIS-V is requested, V1~V4 will be forced to 0xFF. — Bit stuffing, using the C and S bits, will be performed based on the fullness of the elastic store. I The pointer generation will support the following features when operating in byte synchronous mode: — If transmit AIS-V is not requested, the following requirements apply: 1. The pointer value is generated based on the location of the incoming frame sync for VT1.5/VT2 mappings. 2. The VT size field is set to 11 for VT1.5/TU-11 mappings. 3. The VT size field is set to 10 for VT2/TU-12 mappings. 4. The new data flag (NDF) is set to 0110 for normal VT1.5/VT2 mappings. If a NDF is requested, the NDF will be set to 1001 (binary).

1. If an increment is requested, the pointer bytes, V1 and V2, are programmed with the I-bits inverted. The

instead of the increment indication.

1. If a decrement is requested, the pointer bytes, V1 and V2, will be programmed with the D bits inverted. The

of the decrement indication.

1. The V4 byte will be programmed to the selected overhead default (microprocessor bit SMPR_OH_DEFLT) for

— If transmit AIS-V is requested, V1~V4 will be forced to 0xFF. accessible in the asynchronous and bit synchronous modes. V5 Overhead Byte Format/Generation. The V5 overhead byte will be mapped as defined in Table 559. Table 559. V5 Overhead Byte Format ated and inserted while all other bits are programmed from the received LOPOH serial access channel storage. VT_TX_MAPTYPE[1 — 28][3:0] (Table 198) and automatically inserted. including V1~4, with all ones. Signal Label Definition on page445. poses. See Table 560 below for error insertion modes. Table 560. BIP-2 Error Insertion Modes 00 No BIP-2 errors inserted. 01 Insert continuous BIP-2 errors.

10 Insert BIP-2 errors based on microprocessor register bit

SMPR_BER_INSRT ( Ta ble 65). 11 No BIP-2 errors inserted.

when enabled by bit, VT_REI_EN = 1. Otherwise, the REI-V bit is set to 0. channel storage. Otherwise, RFI-V is automatically generated and inserted as defined in Table 561 on page 444. When operating in byte synchronous mode, RFI-V is also based on the incoming DS1 RAI from the framer. age. Otherwise, RDI-V is automatically generated and inserted as defined in Table 561 below. and 7 of the Z7 byte are programed with the value of bits VT_ERDI_INS[1— 28][2:0] (Table 200), respectively. automatically generated and inserted as defined in Tabl e 5 61 below. Table 561. RDI-V , RFI-V, and REI-V Automatic Generation 1 AIS-V , LOP-V , UNEQ-V , PLM-V or automatic AIS detected from SPEMPR. 1 AIS-V , LOP-V , UNEQ-V , or TIM-V . 0 0 1 0 PLM-V (VT payload mismatch). 1 1 1 0 UNEQUIP-V or TIM-V .

values supported are defined in Table 562. J2 Overhead Byte Insertion. Three modes of programming the J2 byte as defined in Table 563 will be supported. Table 563. J2 Overhead Byte Insertion Modes Per Channel Z6/N2 Overhead Byte Insertion. The modes of programming the Z6/N2 byte, defined in Table 564 are supported. Table 564. Z6/N2 Overhead Byte Insertion Modes Per Channel Table 562. VT Signal Label Definition 00 Default based on SMPR_OH_D EFLT (Tabl e 6 7). 01 Microprocessor insert (VT_J2BYTE_INS[1 — 28][1— 16][7:0] (Table 203)). 10 LOPOH serial access channel insert. 11 Default based on SMPR_OH_DEFLT. 00 Default based on SMPR_OH_DEFLT. 01 Insert from bits VT_Z 6BYTE_INS[1 — 28][7:0] (Table 201). 10 LOPOH serial access channel insert.

by register bits VT_Z7_INS[1— 28][1:0] (Table 199) as defined in Table 565. Table 565. Z7/K4 Overhead Byte Insertion Modes Per Channel defined in Table 566 will be supported. Table 566. O-Bit Insertion Modes Per Channel C1, C2 = stuff indication bits. 00 Default based on microproces sor bits SMPR_OH_DEFLT (Ta ble 67).

01 Insert from bits VT_APS_INS[1 — 28][3:0] (Table 200) and

10 LOPOH serial access channel insert. 11 Default based on microproces sor bits SMPR_OH_DEFLT. 00 Default based on microproces sor bits SMPR_OH_DEFLT. 01 Insert from bits VT_OBIT_INS[1 — 28][7:0] (Table 201). 10 LOPOH serial access channel insert. 11 Default based on microproces sor bits SMPR_OH_DEFLT.

Table 567. Asynchronous VT1.5 SMPR_FXD_STFF_DEFLT ( Ta bl e 67). Table 568. Bit Synchronous SMPR_FXD_STFF_DEFLT ( Ta bl e 67). Table 569. Byte Synchronous SMPR_FXD_STFF_DEFLT ( Ta ble 67).

Table 570. Asynchronous VT2 SMPR_FXD_STFF_DEFLT ( Ta bl e 67). Table 571. Bit Synchronous VT2 SMPR_FXD_STFF_DEFLT ( Ta bl e 67). Table 572. Byte Synchronous SMPR_FXD_STFF_DEFLT ( Ta ble 67).

Table 573. VC-11 to TU-12 Conversion *R — value based on SMPR_FXD_STFF_DEFLT (Table 67).

19.14.5 VT Multiplexer (VTMUX)

data onto the outgoing mapper transmit path data bus. See Table 551 through Table 554 on page 430 through page 431 for VT/TU mapping formats.

19.14.6 Transmit Signaling (TX_VTSIG)

phase and data from the framer and insert it into the outgoing VT/TU. Note: This block is only enabled when operating in the byte synchronous mode. routing information programmed within the cross connect (XC) block. (Table 202)), they will be set to SMPR_FXD_STFF_DEFLT (Table 67) in the microprocessor interface block. gramming signaling inserting. Table 574. Framing Byte Generation Per Channel *X — value based on SMPR_OH_DEFLT (Table 67), R— value based on SMPR_FXD_STFF_DEFLT (Table 67).

19.14.7 Transmit Lower Path Overhead (TX_LOPOH)

counter reaches its maximum count, for the active data type, and LOPOHVALIDIN does not transition to 0.

(Table 174) is set, VT_LOPOH_FAIL_E = 1 will generate an interrupt. Figure 46 on pag e453 contains the TX_LOPOH block serial channel format and timing.

19.15 VT Mapper System Interface Timing

19.15.1 VT Mapper DS1/E1 Receive Interface (to System Interface)

(VTMPR_RDAT A) and is one cycle in width. Figure 41. DS1 Mode Gapped Clocking Scheme Figure 42. E1 Mode Gapped Clocking Scheme (VTMPR_RFSYNC) is coincident with the DS1 frame-bit position and with the MSB of E1 time slot 0. Note: The VT mapper 8 kHz frame sync is only transmitted for byte synchronous mappings.

• Maximum gap between rising clock edges = 1848 ns.

Figure 43. DS1 Interface

• Maximum gap between rising clock edges = 1386 ns.

Figure 44. E1 Interface

19.15.2 VT Mapper DS1/E1 Transmit Interface (from System Interface)

edge when VT_TX_CLKEDGE[1 — 28] = 0. See VT Mapper Timing on page 45 for VT mapper interface and clock timing numbers.

19.16 VT Mapper Lower-Order Path Overhead Interface Timing

19.16.1 VT Mapper Receive Path Overhead Interface Description

Figure 45 contains the VT mapper receive path overhead serial channel format and timing. Figure 45. VT Mapper Receive Path Overhead Serial Access Channel

frame. REI and RDI values will be latched during the A1 time of the of the received SONET frame. Definitions on pag e440, for automatic generation requirements. 171 bits (VT2 mode) on the rising edge of the clock, LOPOHCLKOUT, which is driven out on external pin AB15. the rising edged of the clock, LOPOHCLKOUT. I The LOPOHVAL IDOUT signal (driving external output pin AB18) is set to 1 when valid data is being transmitted. I All data types must be transmitted within 500 µs.

19.16.2 VT Mapper Transmit Path Overhead Interface Description

Figure 46 contains the VT mapper transmit path overhead serial channel format and timing. Figure 46. VT Mapper Transmit Path Overhead Serial Access Channel

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 May 2001 454 Agere Systems Inc. The VT mapper transmit path overhead will perform all necessary functions for the low-order path overhead as well as the REI and RDI values from the internal SPE mapper and TMUX blocks. The following are supported: I The interface clocks all incoming signals on the falling edge of external input LOPOHCLKIN (pin AC13). I The first 3 bits received, following a rising edge of external input pin LOPOHVALIDIN (AB14), will define the data type on the incoming stream. Data types are defined in Table 557, Data Type Header Definitions on page 440. I The source of the external input LOPOHD ATAIN (AC14), LOPOHVALIDIN, and LOPOHCLKIN signals is required to hold the LOPOHVALIDIN at 0 for a minimum of eight LOPOHCLKIN cycles. The VT mapper will monitor the incoming LOPOHVALIDIN and detect failure conditions. A failure exists if there are less than eight LOPOHCLKIN cycles between a falling edge of LOPOHVALIDIN and the next rising edge, or if the LOPOH bit count (LOPOH BITCNT) reaches its maximum count for the active data type and LOPOHVALIDIN does not transition to 0. I LOPOH failure is reported in bit VT_LOPOH_FAIL_E (Table 170). If a failure exists (VT_LOPOH_FAIL_E = 1), the incoming data will be ignored and unless the mask bit, VT_LOPOH_FAIL_M (Table 174), is set, the LOPOH failure will generate an interrupt. I The VT mapper logic block will latch new REI and RDI values for the TMUX and SPE mapper during the A1 time of the SONET/SDH frame. The timing figures in this section are functional timing diagrams. See VT Mapper Timing on page 45 for VT mapper interface and clock timing numbers.

20 M13/M23 MUX/DeMUX Block Functional Description

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 May 2001 456 Agere Systems Inc.

20 M13/M23 MUX/DeMUX Block Functional Description (continued)

20.1 M13 Introduction

The M13 block is a highly configurable multiplexer/demultiplexer. It can operate as an M13 in either the C-bit parity or M23 mode, a mixed M13/M23, or an M23. In the C-bit parity mode, the M13 provides a far-end alarm and control (FEAC) code generator and receiver, an HDLC transmitter and receiver, and automatic far-end block error (FEBE) generation and detection. Each internal M12 MUX/deMUX and the M23 MUX/deMUX may be configured to operate as independent MUX/ deMUX. The M13 supports numerous automatic monitoring functions. It can provide an interrupt to the control system, or it can be operated in a polled mode.

20.2 Features

I Configurable multiplexer/demultiplexer for up to 28 DS1 signals, 21 E1 signals, or 7 DS2 signals to/from a DS3 signal. I M23 or C-bit parity mode operation. I Seven configurable independent M12 multiplexer/demultiplexers for up to 28 DS1 signals or 21 E1 signals to/from 7 DS2 signals. I Provisionable time slot selection for DS1, E1, and DS2 insertion or drop. I DS3 multiplexer capable of generating alarm indication signal (AIS), remote alarm indicator (RAI), idle, far-end alarm and control (FEAC), and far-end block error (FEBE) signals. I Automatic DS3 receive monitor that detects loss of signal (LOS), bipolar violation (BPV), excessive zeros (EXZ), out of frame (OOF), severely errored frame (SEF), AIS, RAI, FEAC codes, P-bit parity errors, C-bit parity errors, and FEBE indications. I HDLC transmitter with 128-byte data buffer and HDLC receiver with 128-byte data FIFO for the C-bit parity path maintenance data link. I DS3, DS2, DS1, and E1 loopback and loopback request generation.

20.2.1 M13 Applications

I M13 and M23 multiplexers. I M13 multiplexers supporting G.747 format. I Independent M12 multiplexers. I Digital access cross connects (DACS). I DS1/E1/DS2 broadcast.

20.3 Block Diagrams

The following diagram illustrates the high-level interface between M13 block and other functional blocks. Figure 47. M13 Block Diagram

Figure 48. M12 Functional Block Diagram

Figure 49. M23 Functional Block Diagram

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 May 2001 460 Agere Systems Inc.

20.4 M13 Functional Description

In the descriptions below, some of the register bits exist for each of the DS1, E1, or DS2 signals. The names of these register bits have a lower case x or a y suffix to show that there are actually 28 or 7 of them, respectively.

20.5 M13 Multiplexing Path

There are seven M12 multiplexers and one M23 multiplexer on the transmit side of this M13 block and all of them can operate independently. Twenty-eight DS1 inputs in groups of four, or twenty-one E1 input signals in groups of three can feed into individual M12 MUXs, while the M23 MUX can take DS2 signals from outputs of M12 MUXs, or direct DS2 inputs, or loopback deMUXed DS2s.

20.5.1 M12 Multiplexers

M12 multiplexers have four operation modes provisionable through M13_M12_MODEy[1:0] (Table 263): I M13_M12_MODEy[1:0] = 00: the M12 operates as the first stage of M13 multiplexing. It takes 4 DS1s (M13_DS1_E1Ny = 1(Table 263)) or 3 E1s (M13_DS1_E1Ny = 0) and MUXes into a DS2 signal which will be fed into the M23 MUX. In this mode, the DS1/E1 clocks are independent inputs to the block. There should be no valid DS2 input (XC_DS2M23DATAy). This is the default mode. I M13_M12_MODEy[1:0] = 01: the M12 operates as an independent multiplexer. It takes 4 DS1s (M13_DS1_E1Ny = 1) or 3 E1s (M13_DS1_E1Ny = 0) and MUXes into a DS2 signal which will be sent directly to the DS2 output (M13_DS2M12DATAy) of the block and not be passed to M23 MUX input. In this mode, the DS1/E1 clocks are independent inputs to the block and a DS2 input clock (XC_DS2M12CLKy) is required. I M13_M12_MODEy[1:0] = 10: the M12 operates as an independent multiplexer. It takes 4 DS1s (register bit M13_DS1_E1Ny = 1) or 3 E1s (register bit M13_DS1_E1Ny = 0) and MUXes into a DS2 signal which will be sent directly to the DS2 output (M13_DS2M12DATAy) of the block and not be passed to M23 MUX input. In this mode, the associated DS1/E1 clocks are outputs from the block and derived from the DS2 input clock (XC_DS2M12CLKy). I M13_M12_MODEy[1:0] = 11: the M12 is idle. The output from this M12 multiplexer will be held low.

20.5.2 DS1/E1 Interface

The incoming DS1/E1 clock signals (XC_DS1CLK[28— 1]) are first checked for activity or loss of clock (LOC). This is reported to the microprocessor via bits M13_DS1_LOC[28:1] (Table 247). Once LOC is detected, AIS will be inserted into the associated DS1/E1 channel using the clock from external pins, DS1XCLK /E1XCLK (AD16/AC17) (Table 3). The incoming DS1/E1 data signals are retimed immediately by the associated clocks. The edge of the clocks that is used to retime the data is user provisionable to either the rising edge (M13_RDS1_EDGEx = 1 (Tabl e 2 64)) or fall- ing edge (M13_RDS1_EDGEx = 0). After being retimed, the incoming data stream is checked for AIS. When the input is DS1, the M13 will declare AIS if the input data is logic 0 for fewer than 9 out of 8192 clock periods (T1.231). When the input is E1, AIS is declared if there are less than 3 zeros in each of two consecutive 512-bit periods and cleared when each of two consecutive 512-bit periods contains more than 2 zeros (G.775). If AIS is detected on any of the DS1/E1 inputs (XC_DS1DATA[28 — 1]), the associated M13_DS1_AIS_DET[28:1] (Table 248) bit is set.

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 461Agere Systems Inc.

20.5.3 Loopback Select

DS1/E1 loopback selectors allow DS1 or E1 received within the DS2 or DS3 inputs from the deMUX path to be looped back. This loopback can be performed automatically if M13_AUTO_FLB (Table 259) or M13_AUTO_LB (Table 259) bits are set. Regardless of the state of M13_AUTO_FLB and M13_AUTO_LB, the user can force a DS1 or E1 loopback by setting M13_SEL_DS1_LBx (Table 264) to 1. When M13_AUTO_LB = 1, loopback of channel x is activated if M13_DS1_LB_DETx = 1 (Table 249) (see Section 20.11.4 M12 Demultiplexers on page 472). In the C-bit parity mode, automatic loopback can also be activated as a result of receiving a loopback request through the far-end alarm and control (FEAC) channel. Such a request is indicated by status bit M13_DS1_FEAC_LB_DETx (Table 251) (see Section 20.7.6 FEAC on page 465). If status bit M13_DS1_FEAC_LB_DETx = 1 and M13_AUTO_FLB = 1, loopback of channel x is activated.

20.5.4 DS1/E1 FIFOs

When M13_M12_MODEy[1] = 0 (Tabl e 2 63), the 4 selected DS1 or 3 selected E1 signals for each M12 MUX are fed into single bit 16-word-deep FIFOs that are used to synchronize the selected signals to the DS2 frame genera- tion clock. The DS2/DS3 transmit clock (XC_DS2M12CLKy) is used to derive the clock source for DS2 frame gen- eration blocks. In the C-bit parity mode, all DS2 stuff opportunities are used, which produces a nominal 6.306 MHz DS2 clock. In the M23 mode, the DS2 stuffing ratio is fixed such that the DS2 clock is nominally 6.312 MHz. The fill level of each FIFO determines the need for bit stuffing its DS1/E1 input. This block allows the M13 to accept DS1/E1 signals with nominal frequency offsets of ±130 ppm and up to 5 unit intervals peak jitter. When operating in M13_M12_MODEy[1:0] = 10 mode, the FIFOs are not used.

20.6 DS2 Frame Generation

Each M12 MUX generates a DS2 frame either from 4 DS1 signals multiplexed as specified in T1.107 and GR-499- CORE when M13_DS1_E1Ny = 1 ( Table 263), or from 3 E1 signals multiplexed using the format specified in ITU-T recommendation G.747 when M13_DS1_E1Ny = 0. When M13_M12_MODEy[1:0] = 01/10 (Table 263), each M12 MUX is operating independently. In this case, the output DS2 signals are retimed by the associated clocks. The edge of the clocks that is used to retime the data is user provisionable to either the rising edge (M13_DS2M 12_EDGEy (Table 275) = 1) or falling edge (M13_DS2M12_EDGEy = 0). The AIS signal can be inserted into any DS2 output by setting M13_DS2_FORCE_AISy ( Table 271) to 1.

20.6.1 DS1 Mode

In the DS1 mode, the 4 signals interleaved to generate the y th DS2 signal are the outputs from DS1/E1 loopback selectors 4y – 3, 4y – 2, 4y – 1, and 4y. Bits multiplexed into the second and fourth channels (from selectors 4y – 2 and 4y) are inverted before being interleaved (T1.107) when bit M13_MUXCH2_4_INVy = 1 (Table 263). Loopback requests for a DS1 channel are indicated by inverting the third C bit for that channel (T1.107). This is done when bit M13_DS1_LB_REQx is set to 1 (Table 263). The 4 M13_DS1_LB_REQx bits that affect the yth DS2 are 4y – 3, 4y – 2, 4y – 1, and 4y. The X bit is set to the inverse of the remote alarm indication (RAI) bit (T1.107) M13_DS2_RAI_SENDy (Table 265). For testing purposes, the M frame alignment signal (normally 011) is generated with the last bit inverted (010) if M13_DS2_MPINVy is set (Table 267), and the M-subframe alignment signal (01) is generated as (00) if M13_DS2_FINVy is set (Table 268).

20.6.2 E1 Mode

M13_DS1_LB_REQx bits that affect the yth DS2 are 4y – 3, 4y – 2, and 4y – 1. M13_DS2_RSV_SENDy register bits, (Tabl e 2 66) respectively (G.747). last bit inverted (111010001) if M13_DS2_FINVy is set, and the parity bit is inverted if M13_DS2_MPINVy is set. Figure 50. DS3 NSMI Transmit Operation Figure 51. DS3 NSMI Receive Operation

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 463Agere Systems Inc.

20.7 M23 Multiplexer

The M23 multiplexer generates a transmit DS3 frame and fills the information bits in the frame with data either from the 7 DS2 select blocks when M13_NSMI_MODE = 0 (Table 277) or from the serial payload input XC_NSMI_DATA (when M13_NSMI_MODE = 1). It generates the frame using either the SMPR_TDS3CLK or the SMPR_RDS3CLK input clocks. In the receive loop timing mode (M13_LOOP_TIME = 1 (Table 259)), the received clock, SMPR_RDS3CLK, is selected. Otherwise, SMPR_TDS3CLK is used for DS3 frame generation. SMPR_TDS3CLK is monitored for loss of clock, which is reported through bit M13_TDS3_LOC (Table 225). The serial data interface, when enabled (M13_NSMI_MODE = 1), generates a clock M13_NSMI_CLK and an enable M13_NSMI_EN for accepting DS3 payload data XC_NSMI_DA TA. A sync pulse, in reference to and ahead of the first M bit within a DS3 frame, is also generated. The offset from the sync pulse to the first M bit is program- mable through bits M13_NSMI_SP_OFFSET[7:0] (Table 261). The M23 MUX can be provisioned to operate in either the M23 mode (M13_M23_CBP = 1 (Table 260)) or the C-bit parity mode (M13_M23_CBP = 0). An unframed all ones data stream is generated if M13_TDS3_FORCE_ALL1 is set to 1 (Table 276).

20.7.1 DS2 Interface

The clocks associated with input DS2 signals can be either inputs to the M23 MUX (M13_M23CLK_MODE = 0 (Table 276)) or outputs from the M23 MUX (M13_M23CLK_MODE = 1).The incoming DS2 clock signals are checked for activity or loss of clock (LOC). This is reported to the microprocessor via bits M13_XC_DS2_LOC[ 7:1] (Table 238). In case LOC is detected, AIS will be inserted into the associated DS2 channel using DS2AISCLK (pin E10). The incoming DS2 data signals (XC_DS2M23DATA[7 — 1]) are retimed immediately by the associated clocks. The edge of the clocks that is used to retime the data is user provisionable to either the rising edge (M13_RDS2_EDGEy = 1 ( Table 283)) or falling edge (M13_RDS2_EDGEy = 0). After being retimed, the incoming data stream is checked for AIS. The M13 w ill declare AIS if the input data is 0 for fewer than 5 clock cycles in each of two consecutive 840 clock periods. The AIS is not cleared until there are more than 4 zeros in each of two consecutive 840-bit periods (G.775). If AIS is detected on any of DS2 inputs, the asso- ciated M13_XC_DS2_AIS_DET[7:1] bit is set (Table 239).

20.7.2 DS2 Select Logic

The selection of DS2 signal source for each DS2 time slot is controlled by M13_AUTO_LB (Table 259), M13_DS2_LB_DETy ( Table 244), M13_SEL_DS2_LBy (Table 282), and M13_M12_MODEy (Table 263) bits. When M13_AUTO_LB = 1 and M13_DS2_LB_DETy = 1, the DS2 signal from time slot y in the received DS3 signal is looped back into time slot y of the transmitted DS3 signal (see C-Bit Processing on page 470). The user can also force a loopback by setting M13_SEL_DS2_LBy to 1. DS2 loopback should not be done in the C-bit parity mode. If a loopback is not active, the DS2 signal selector is controlled by bits M13_M12_MODEy[1:0]. If register bits M13_M12_MODEy[1:0] = 00, the output of M12 multiplexer y is chosen for the y th DS2 time slot in the transmitted DS3 signal; otherwise, the input DS2 signal XC_DS2M23DATAy is selected for the yth DS2 time slot in the transmit- ted DS3 signal.

20.7.3 Overhead Bit Generation (GR-499)

For testing purposes the F bits, M bits, and P bits can be generated with errors. The frame alignment signal (F-bit pattern that is normally 1001) is generated with the last bit inverted (1000) if M13_DS3_FINV (Tabl e 2 76) is set. The multiframe alignment signal (M-bit pattern that is normally 010) is generated as (011) if M13_DS3_MINV (Table 276) is set.

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 May 2001 464 Agere Systems Inc. The parity bits (P bits) are generated as odd rather than the normal even parity if M13_DS3_PINV (Table 276) is set. Both P bits within the first DS3 frame after a 0 to 1 transition of SMPR_BER_INSRT (Ta ble 65) are also inverted if M13_DS3_P_BERy (Table 277) is set to 1. The X bits are set to the inverse of the remote alarm indication (RAI) bit (GR-499) M13_DS3_RAI_SEND (Table 277). C-bit transmission is a function of whether the M13 MUX/deMUX is in the M23 mode or the C-bit parity mode.

20.7.4 M23 Mode

Please refer to M13_M23_CBP = 1 in Table 260. The information bits in the DS3 frame are drawn from the 7 DS2 select blocks. If M13_M23CLK_MODE = 0 (Table 276) and a select block is in the loopback or direct DS2 input state, the selected DS2 must be synchronized to the DS3 frame generation clock. To do this, the M13 contains 7 DS2 FIFOs each with a depth of 8. The fill level of each FIFO determines the need for bit stuffing its DS2 input. When M13_M23CLK_MODE = 0 and DS2 select blocks are not in the loopback or direct DS2 input state, the selected DS2s are generated using the DS3 frame generation clock. In this case, a fixed stuffing ratio is used for the DS2s in order to produce a nominal 6.312 MHz DS2 clock rate. When M13_M23CLK_MODE = 1, the FIFOs are not used and DS2 stuff request inputs (XC_DS2STFREQ[7— 1]) will determine when stuff bits are needed. The three C bits in each M-subframe of the DS3 frame are stuff indication bits. If the stuff opportunity bit in an M subframe is filled by a DS2 bit, the first and second C bits in that M-subframe are transmitted as zeros. If the stuff opportunity bit in an M-subframe is filled with a stuff bit, the first and second C bits in that M-subframe are transmit- ted as ones. The third C bit in each M-subframe is normally transmitted with the same value as the first and second C bits. How- ever, if M13_DS2_LB_REQy = 1 (Table 281), the third C bit is transmitted as the inverse of the first two C bits (which indicates a loopback request for DS2 channel y).

20.7.5 C-Bit Parity Mode

Please refer to M13_M23_CBP = 0 in Table 260. The M23 MUX can operate in the C-bit parity mode under the fol- lowing two circumstances: I When M13_M23CLK_MODE = 0 and 28 DS1 or 21 E1 signals are being MUXed into the DS3. I When M13_M23CLK_MODE = 1 and 7 DS2 signals are being MUXed into the DS3. In the C-bit parity mode, every DS2 stuffing opportunity is filled with a stuff bit. Because stuffing is not used for syn- chronization, the selected DS2s cannot come directly from the M13 inputs, and the selected DS2s cannot be looped back from the M23 demultiplexer. The 21 C bits in each DS3 frame are not required as stuffing indicators. Their use is described in Table 575 on page 465.

Table 575. C-Bit Parity Description and Transmit Value

20.7.6 FEAC

FEAC code words are defined in T1.107 and GR-499-CORE. mit continuous ones by setting M13_TFEAC_CTL[1:0] to 00 (Table 278). be a 1 or a 0. The code words are transmitted right to left one bit each DS3 frame for 16 consecutive frames. where x5x4x3x2x1x0 is the appropriate value for the alarm or status code word. the activate or deactivate commands. 0x5x4x3x2x1x0 0 11111111. After transmitting this 40 octet sequence, it will set M13_TFEAC_DONE to 1. C1 C-Bit Parity Identification 1. C2 Network Requirements Bit If M13_CBIT2_ACT = 0 ( Table 277), the C2 bit is set to 1. C3 Far-End Alarm and Control (FEAC) See FEAC below. C7 — C9 CP Bits (path DS3 parity) Set to the same value as the P bits. C10 — C12 Far-End Block Error (FEBE) Bits See Section 20.7.7 FEBE on page 466.

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 May 2001 466 Agere Systems Inc.

20.7.7 FEBE

C bits 10, 11, and 12 provide a far-end block error (FEBE) indication. Each frame of the received DS3 signal is checked for errors in the F-bit or M-bit framing sequences and for errors in the CP-bit path parity. If no errors are found, the FEBE bits are set to 111 in the next transmitted DS3 frame. If one or more errors are detected, the FEBE bits are transmitted as 000. The user can force the transmission of FEBE error indications by setting M13_FEBE_ERR to 1 (Table 277). This causes all DS3 frames to be transmitted with the FEBE bits set to 000, regardless of whether or not errors were detected in the received DS3 signal.

20.7.8 Terminal-to-Terminal Path Maintenance Data Link

C bits 13, 14, and 15 can be used as a 28.2 kbit/s data link. If the data link is not used, the user should set M13_TDL_ACT to 0 (Table 279), which causes all ones to be transmitted. When M13_TDL_ACT = 1 and M13_TDL_NTRNL = 0 ( Table 279), the data transmitted on this link comes directly from the M13 input pin, pin TDLDATA (E8). Otherwise (M13_TDL_ACT = 1 and M13_TDL_NTRNL = 1), the data link is controlled by the inter- nal HDLC transmitter. HDLC Transmitter. The internal HDLC transmitter circuitry is composed of two 64-byte data buffers (registers M13_TDL_0DATA_R[0 — 63] (Table 298) and M13_TDL_1DA TA_R[0— 63] (Table 299)), a CRC-16 frame check sequence (FCS) generator, and control circuits. The HDLC transmitter continually outputs flag bytes (01111110) with MSB first until the user sets M13_TDL_NTRNL_ACT to 1 (Table 279). Following the completion of the next flag byte, the HDLC transmitter begins transmitting the first byte of the first data buffer (register M13_TDL_0DATA_R[0]), which should be filled by the user with the first byte of the address field. (For LAPD mes- sages, this byte contains the service access point identifier, the command/response bit, and a zero extended address bit.) Bytes from the data buffer are transmitted least significant bit (LSB) first (GR-499). The HDLC controller inserts a 0 after any sequence of five consecutive ones in the data buffer to prevent the occurrence of a flag pattern prior to the closing flag. Buffer Usage. The number of bytes transmitted from the data buffers before completing the frame is controlled as follows. M13_TDL_BUF0_END (Table 279) and M13_TDL_BUF1_END ( Table 279) are two bits which indicate whether or not the final buffer byte to be transmitted is currently in buffer 0 or buffer 1. While bytes from buffer 0 are being transmitted, the HDLC controller checks the value of M13_TDL_BUF0_END bit. If it is 0, all bytes from buffer 0 and at least one byte from buffer 1 are transmitted. If it is 1, bytes from buffer 0 are transmitted sequentially up to and including byte K, where M13_TDL_BYTE_END[5:0] = K (Table 280). Similarly, the number of bytes transmitted from buffer 1 is controlled by the value of M13_TDL_BUF1_END and M13_TDL_BYTE_END[5:0] bits. Bytes are transmitted alternately from buffer 0 and buffer 1 until bit M13_TDL_BUF[0, 1]_END = 1 for the active transmission buffer and the value of bits M13_TDL_BYTE_END[5:0] is equal to the byte number being transmitted. When the HDLC controller completes transmission of register M13_TDL_0DATA_ R[63] (the last byte of buffer 0), the interrupt bit M13_TDL_BUF0_INT is set to 1 (Table 217). Similarly, the interrupt bit M13_TDL_BUF1_INT (Table 217) is set after the last byte of buffer 1 is transmitted. These bits indicate that the corresponding buffer has been emptied and is available for refilling. The user may abort the transmission of an HDLC frame by clearing M13_TDL_NTRNL_ACT to 0 prior to complet- ing transmission of the last byte from the data buffers. If so, the HDLC controller will stop transmission from the buffers and send an abort byte (01111111) transmitted MSB first. The abort byte will then be followed by flag bytes until M13_TDL_NTRNL_ACT is again set to 1, starting transmission of a new frame.

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 467Agere Systems Inc. FCS Generation. Once the last buffer byte is transmitted, the HDLC controller either transmits a closing flag byte (when M13_TDL_FCS = 0 (Table 279)), or it first appends the 2-byte ITU-T FCS with the necessary zero stuffing before sending the closing flag (when M13_TDL_FCS = 1). In either case, the HDLC controller sets M13_TDL_DONE ( Table 217) to 1 after the transmission of the frame is complete. For testing purposes, the user can send corrupted FCS bytes by clearing M13_TDL_FCS to 0 and filling the last 2 bytes in the buffer with an incor- rect CRC value. LAPD Example. T1.107 defines three standard LAPD messages that may be transmitted on the path maintenance data link. After the opening flag, each of these messages contains 79 bytes of address, control, and information. These are followed by the 2-byte FCS and the closing flag. To transmit one of these messages using the internal HDLC transmitter, the microprocessor should first set M13_TDL_ACT ( Table 279) to 1, M13_TDL_NTRNL (Table 279) to 1, and M13_TDL_NTRNL_ACT (Table 279) to 0. This causes the continuous generation of flag bytes. The microprocessor may then fill buffer 0 with the first 64 bytes of the message and fill bytes 0 through 14 of buffer 1 with the last 15 bytes prior to the FCS of the message. By setting M13_TDL_BUF0_END (Table 279) to 0, M13_TDL_BUF1_END ( Table 279) to 1, and M13_TDL_BYTE_END[5:0] (Table 280) to 001110, the microproces- sor can indicate that 79 buffer bytes are to be transmitted. The microprocessor can then set M13_TDL_FCS to 1 and M13_TDL_NTRNL_ACT to 1. This will cause the inter- nal HDLC transmitter to send the 79 buffer bytes, append the FCS and closing flag, set M13_TDL_DONE to 1, and resume continuous flag transmission. If the same LAPD message is to be transmitted later without first having transmitted a different message, the micro- processor only needs to toggle M13_TDL_NTRNL_ACT to 0 and back to 1, as the values of the other control parameters and the buffer bytes are not modified by the internal HDLC transmitter.

20.8 AIS/Idle Insertion

The AIS/idle insertion block can be provisioned to operate in the normal mode (M13_DS3_FORCE_AIS = 0 (Table 276) and M13_DS3_FORCE_IDLE = 0 (Table 276)), generate DS3 AIS (M13_DS3_FORCE_AIS = 1) or generate DS3 idle (M13_DS3_FORCE_AIS = 0 and M13_DS3_FORCE_IDLE = 1). In the normal mode, data from the M23 multiplexer is passed unchanged to the B3ZS encoder block. During AIS insertion (M13_DS3_FORCE_AIS = 1), the generated DS3 frame is altered by overwriting the informa- tion bits with an alternating 1010 . . . pattern, starting with a 1 after each overhead bit. In addition, the X bits are overwritten with ones, and the C bits are overwritten with all zeros (T1.107 and T1.404). During idle signal generation (M13_DS3_FORCE_AIS = 0 and M13_DS3_FORCE_IDLE = 1), the information bits the M23 mode (M13_M23_CBP = 1 (Table 260)), the C bits are overwritten with all zeros. In the C-bit parity mode, the C bits are passed unchanged (T1.107 and T1.404).

20.9 B3ZS Encoder (GR-499)

The transmit DS3 device output can either be in the form of unipolar data (M13_DS3POS _DATA when M13_BIPOLAR = 0 (Tabl e 2 60)) or positive data, and negative data (M13_DS3POS_DATA, and M13_DS3NEG when M13_BIPOLAR = 1). If M13_BIPOLAR = 1, the DS3 data is B3ZS encoded with M13_DS3POS_DATA = 1 indicating a positive pulse and M13_DS3NEG = 1 indicating a negative pulse. The B3ZS encoder block accepts data output from the M23 multiplexer and when M13_BIPOLAR = 1, performs coding as follows: for each input data bit that is a 1, the encoder outputs a 1 (or pulse) on either its positive or neg- ative output. The positive or negative output is chosen such that the resulting pulse is opposite in polarity to the last nonzero output.

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 May 2001 468 Agere Systems Inc. For each input data bit that is a 0, the encoder outputs zeros on both its positive and negative outputs, unless doing so would cause three consecutive output periods of positive and negative zeros. In the latter case, the three con- secutive input zeros are output as either [00V] or [B0V], where B is a pulse on either the positive or negative output that is opposite in polarity to the last non-zero output, and V is a pulse that is the same polarity as the last nonzero output. The choice of [00V] or [B0V] is made so that the polarity of consecutive V-pulses alternates (which is equiv- alent to forcing the number of B-pulses between successive V-pulses to be odd). When M13_BIPOLAR = 1, the user can force errors in the bipolar coding by setting M13_BIPOL_ERR (Table 258) to 1. When this is done, the M13 transmits the next 1 as a bipolar violation.

20.10 DS3 R-to-T Loopback

The received DS3 signal can be looped directly back to the transmit DS3 output. If either M13_LOOP_R_TO_T = 1 (Table 260), or both M13_AUTO_FLB = 1 (Table 259) and M13_DS3_FLB_DET = 1 (Table 251) (see Section 20.7.6 FEAC on page 465), the loopback is activated. (During loopback, the SMPR_RDS3POS_D ATA and SMPR_RDS3NEG_BPV input signals are looped to the M13_DS3POS_DATA and M13_DS3NEG outputs, respec- tively.)

20.10.1 DS3 Transmit Path Interface

When cross connected to the DS3 device pins, the DS3 data out DS3POSDATAOUT (pin R22) and DS3NEGDATAOUT (pin P22) is clocked out on the falling edge of DS3DATAOUTCLK (pin N22). If the M13 DS3 interface is optioned for loop timing (M13_LOOP_TIME = 1), the DS3 data is clocked out on the ris- ing edge of DS3DATAINCLK (pin J22).

20.11 M13/M23 Demultiplexer

20.11.1 DS3 LOC and LOS

SMPR_RDS3CLK is monitored for loss of clock, which is reported through bit M13_RDS3_LOC (Table 225). The user can configure which edge of SMPR_RDS3CLK retimes the data (M13_RDS3_EDGE = 1 ( Table 287) selects the rising edge; M13_RDS3_EDGE = 0 selects the falling edge). The receive DS3 signal is also checked for loss of signal (LOS), which is reported through bit M13_RDS3_LOS (Table 225). An LOS defect, according to T1.231, is the occurrence of 175 ±75 contiguous pulse positions with no pulses of either positive or negative polarity at the DS3 input. An LOS defect is terminated upon detecting an aver- age pulse density of at least 33% over a period of 175 ±75 contiguous pulse positions starting with the receipt of a pulse. An LOS defect will not be terminated if, at the end of the pulse-position interval, any subintervals of 100 pulse positions containing no pulses of either polarity were observed (T1.231). B3ZS Decoder. The receive DS3 device input can either be in the form of unipolar clock and data (SMPR_RDS3CLK and SMPR_RDS3POS_DATA when M13_BIPOLAR = 0 ( Table 260 on pag e216)) or unipolar clock, positive data, and negative data (SMPR_RDS3CLK, SMPR_RDS3POS_DA TA, and SMPR_RDS3NEG_BPV when M13_BIPOLAR = 1 and M13_BPV_IN = 0 (Table 259)) or unipolar clock, data, and bipolar violation indication (external input) (SMPR_RDS3CLK, SMPR_RDS3POS_DATA, and SMPR_RDS3NEG_BPV when M13_BIPOLAR = 0 and M13_BPV_IN = 1). When M 13_BIPOLAR = 0, the received DS3 data and clock are passed directly to the M23 demultiplexer. When M13_BIPOLAR = 0 and M13_BPV_IN = 1, the received DS3 data and clock are passed to the M23 demultiplexer while the bipolar violation indication is forwarded to the internal BPV counter for performance monitoring (B3ZS decoder is not used). When M13_BIPOLAR = 1 and M13_BPV_IN = 0, the received SMPR_RDS3POS_DATA and SMPR_RDS3NEG_BPV data inputs are first B3ZS decoded.

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 469Agere Systems Inc. The B3ZS decoder block performs decoding as follows. For each clock period that both SMPR_RDS3POS_DA TA and SMPR_RDS3NEG_BPV are 0 (no pulse), the decoder outputs a 0. For each clock period that either SMPR_RDS3POS_DATA or SMPR_RDS3NEG_BPV is 1 (pulse), the decoder determines whether or not the pulse is part of a zero substitution (ZS) sequence. A ZS sequence is [00V] or [B0V], where B is a pulse on either the pos- itive or negative input that is opposite in polarity to the last nonzero input, and V is a pulse that is the same polarity as the last nonzero input. If the received pulse is not part of a ZS sequence, the decoder outputs a 1. Otherwise, the decoder outputs three consecutive zeros in place of the received ZS sequence. The B3ZS decoder also checks for bipolar coding violations. Bipolar coding violations are defined as received V-pulses that are not opposite in polarity to the last V-pulse or are not immediately preceded by a 0, or received zeros that are immediately preceded by two other zeros. The M13 contains a counter that increments on each occurrence of a received bipolar coding violation (BPV). It also monitors the occurrence of excessive zeros (EXZ), which is defined as any zero string length equal to or greater than 3 (T1.231). These are part of the performance monitoring counters that can be sampled and simulta- neously reset (see DS3 Performance Monitors on page 472). Their last sampled values are available in registers M13_BPV_CNT_R[1 — 3] (Table 295) and M13_EXZ_CNT_R[1 — 3] (Table 296).

20.11.2 DS3 T-to-R Loopback

The M13 can be configured to loopback the internal transmit DS3 from the output of the M23 MUX (M13_LOOP_T_TO_R = 1 ( Table 259)) or accept the received DS3 signal after B3ZS decoding (M13_LOOP_T_TO_R = 0) and send it into the M23 deMUX block.

20.11.3 M23 Demultiplexer

The M23 demultiplexer will take the received DS3 signal and either deMUX it into 7 DS2 data streams or strip off the overhead bits and send payload out through the NSMI serial interface when M13_NSMI_MODE ( Table 277) = The serial data interface, when enabled (M13_NSMI_MODE = 1), generates a clock M13_DNSMI_CLK and an enable M13_DNSMI_EN for outputting DS3 payload data M13_DNSMI_DATA. A sync pulse M13_DNSMI_SYNC, in reference to and ahead of the first M bit within a DS3 frame, is also generated. The offset from the sync pulse to the first M bit is programmable through bits M13_D_SP_OFFSET[7:0] (Table 262). In the case of the received DS3 signal being deMUXed into 7 DS2s, those DS2s can be sent out of the device, or looped back to the transmit side, or passed to M12 demultiplexers for further breakdown into DS1s/E1s. DS3 Framer. After being B3ZS decoded, the incoming DS3 data stream is checked for the presence of unframed all ones. If the input data is 0 for fewer than 9 out of 8192 clock periods, bit M13_RDS3_ALL1_DET (Table 225) will be set. The M23 demultiplexer determines if the input signal contains valid DS3 framing. This is done in two stages by first finding a bit position that matches the frame alignment pattern (F bits), and then locating the multiframe alignment signal (M bits). After a matching F-bit sequence is found, in-frame is declared (M13_DS3_OOF = 0 (Table 224)) when correct M bits are received for three consecutive M frames (T1.231). The maximum average reframe time is 0.5 ms in the presence of a bit error rate of 10 –3. Once the deMUX is in-frame, the received frame bits are monitored for out-of-frame. Out-of-frame is declared (M13_DS3_OOF = 1) when too many errors are received in either the F bits (three errors in 16 bits when M13_DS3_MODE = 0 ( Table 287), or at least 1 F-bit error in each of four consecutive M-subframes when M13_DS3_MODE = 1) or the M bits (at least 1 error in each of three consecutive M frames) (T1.231). For testing purposes, the user may also force the framer out-of-frame by setting M13_DS3_FORCE_OOF (Tabl e 2 58) to 1.

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 May 2001 470 Agere Systems Inc. The traditional algorithm for declaring out-of-frame (three errors in 16 F bits) results in false out-of-frame approxi- mately every 30 seconds when the received bit error rate is 10–3. By waiting for four consecutive M-subframes with F bit errors before declaring out-of-frame (M13_DS3_MODE = 1), the M13 normally stays in frame for over an hour when the bit error rate is 10–3. The M13_DS3_LOF ( Table 224) bit is set if bit M13_DS3_OOF is high continuously for 28 frame periods (approxi- mately 3 ms). Once set, M13_DS3_LOF is not cleared until M13_DS3_OOF is continuously low for 28 frame peri- ods. The user can provision the M13 to automatically output AIS if either bit M13_DS3_OOF = 1 (by setting M13_AUTO_AIS_OOF ( Table 259) to 1), or M13_DS3_LOF = 1 (by setting M13_AUTO_AIS_LOF to 1). The received DS3 frames are also checked for severely errored frames (SEF). An SEF defect is the occurrence of three or more F-bit errors in 16 consecutive F bits and is reported through bit M13_RDS3_SEF (Table 225). An SEF defect is terminated when the signal is in-frame and there are less than three F-bit errors in 16 consecutive F bits. AIS, Idle, and RAI Detection. Each M frame, the 4704 information bits are checked for the presence of the AIS (1010) or idle (1100) pattern. In order to detect these patterns in the presence of a high error rate, AIS (M13_DS3_AISPAT_DET = 1 (Table 224)) or idle (M13_DS3_IDLEPAT_DET = 1 (Tabl e 2 24)) pattern detection is declared if fewer than five pattern errors are received in each of two consecutive frames. Once AIS or idle is declared, these bits are not cleared until at least 16 pattern errors are received in each of 2 consecutive frames (T1.231). In addition to the fixed information bit patterns, AIS and idle signals are transmitted with all C bits set to 0 and both X bits set to 1. These conditions are monitored by the M13 and reported in bits M13_DS3_CBZ_DET ( Table 224) and M13_DS3_RAI_DET ( Table 224). If every C bit in three consecutive DS3 frames is 0, the M13 sets M13_DS3_CBZ_DET to 1. If the three C bits in a single M-subframe are all 1, M13_DS3_CBZ_DET is cleared. If both X bits in two consecutive frames are received as 0, the device sets M13_DS3_RAI_DET to 1. Once M13_DS3_RAI_DET is set, it is not cleared until both X bits in two consecutive frames are received as 1. The user may wish to declare AIS or idle based on a combination of some or all of the following bits: M13_DS3_CBZ_DET, M13_DS3_RAI_DET, and M13_DS3_AISPA T_DET or M13_DS3_IDLEPAT_DET. C-Bit Processing. The M13 can be provisioned to operate in either the M23 mode (M13_M23_CBP = 1 (Table 260)) or the C-bit parity mode (M13_M23_CBP = 0). In the M23 mode, the C bits in each M-subframe are interpreted as stuff indicator bits, and they are checked for loopback requests. If the third C bit differs from the first and second C bits in the y th M-subframe for 5 successive DS3 frames, M13_DS2_LB_DETy (Table 244) is set to 1. The M13_DS2_LB_DETy bit is cleared when the third C bit does not differ from the first two C bits in subframe y for five successive DS3 frames. The first C bit of each frame, C1, provides C-bit parity identification. If for eight consecutive frames it is received as a 1, the M13 sets M13_DS3_C1_DET (Table 224) to 1. Once M13_DS3_C1_DET bit is set, three consecutive frames with C1 = 0 must be received before it is cleared. The RCBDATA (pin E15) output provides access to the received C2, C4, C5, C6, and C16 through C21 C bits. The received data link bits, C13 through C15, are output as a serial stream on RDLDATA pin (H22). FEAC. In the C-bit parity mode, the third C bit of each DS3 frame, C3, is monitored for FEAC signals. Active FEAC signals consist of repeating 16-bit code words of the form 0 x5x4x3x2x1x0 0 11111111, where xi can be a 1 or a 0, and the bits are received right-to-left. The same code word must be received four consecutive times before it is accepted. When a code word is accepted, the action taken by the M13 depends on the value of x5x4x3x2x1x0, which may be an alarm indication, a loopback activation, or a loopback deactivation.

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 471Agere Systems Inc. The values of M13_DS1_FEAC_LB_DETx and M13_DS3_FLB_DET bits are not changed if an activate or deacti- vate control signal is accepted, but the next code word to be accepted is not a channel indication control signal (010011, 011011, or 100001 through 111100). Alarm, Status, or Unassigned Signals. If a FEAC signal is accepted that is not a loopback activate (000111), deactivate (011100), or channel indication (010011, 011011, or 100001 through 111100) signal, the M13 will set bits M13_RFEAC_CODE[5:0] = x5x4x3x2x1x0 and M13_RFEAC_ALM_INT (Table 217) to 1. Control Signals. EAC control signals are defined for activating or deactivating a loopback. If a loopback activate (000111), deactivate (011100), or channel indication (010011, 011011, or 100001 through 111100) is accepted, the M13 will set bits M13_RFEAC_CODE[5:0] (Table 252) = x5x4x3x2x1x0 and M13_RFEAC_LB_INT (Table 217) to 1. If a loopback activate (000111), followed by the all-DS1 channels indication (010011) is accepted, the device sets all M13_DS1_FEAC_LB_DETx (Table 251) bits. All M13_DS1_FEAC_LB_DETx bits are cleared if a loopback deactivate (011100), followed by the all-DS1 channels indication, is accepted. If a loopback activate (000111), followed by the DS3 indication (011011) is accepted, the device sets the M13_DS3_FLB_DET ( Table 251) bit. The M13_DS3_FLB_DET bit is cleared if a loopback deactivate (011100), fol- lowed by the DS3 indication, is accepted. Similarly, if the M13 accepts an activate or deactivate control signal followed by a DS1 channel indication (100001 through 111100), it sets or clears the M13_DS1_FEAC_LB_DETx bit, where x is equal to the binary value of x5x4x3x2x1x0. Terminal-to-Terminal Path Maintenance Data Link. C bits 13, 14, and 15 can be used as a 28.2 kbit/s data link. These bits are available directly at device output pin RDLDATA (H22). The M13 also contains an internal HDLC receiver for processing the received data link bits. HDLC Receiver. The internal HDLC receiver circuitry is composed of a 128-byte FIFO, a CRC-16 frame check sequence (FCS) error detector, and control circuits. The HDLC receiver searches for flag bytes (01111110) and processes the bits received between flag bytes as fol- lows. The receiver removes zeros that immediately follow any sequence of five consecutive ones. Sequences of 8 bits after zero destuffing are grouped into bytes and written into the FIFO. As bytes are received, the CRC-16 value, based on the ITU-T polynomial, is calculated. When the closing flag is received, the receiver checks that the received FCS in the final 2 bytes matches the calculated CRC-16. If M13_RDL_FCS = 1 (Table 287) and the FCS does not match, M13_RDL_FCS_ERR (Table 253) is set. If M13_RDL_FCS = 0, M13_RDL_FCS_ERR is held reset at 0. M13_RDL_FCS bit also determines whether or not the final 2 bytes of the frame are written into the FIFO. They are written into the FIFO only when M13_RDL_FCS = 0. The receiver allows frames to be sent back-to-back with the closing flag of one frame shared as the opening flag of the next frame. If fewer than three complete destuffed bytes are received between flag bytes, the receiver ignores the data and writes nothing into the FIFO. FIFO Usage. The FIFO is large enough to hold one full and two partial standard DS3 LAPD frames of 79 bytes. In case shorter frames are being transmitted, the M13 can keep track of up to four frames in the FIFO that have not been read. The receive data-link frame interrupt bit, M13_RDL_FRM_INT (Table 217), is set when a frame closing flag or an abort byte is received. The M13_RDL_FIFO_UF (Table 225) bit is set if the buffer underflows, and the M13_RDL_FIFO_AF ( Table 225) bit is set if the buffer reaches a provisionable fill level. The fill level can be set to 16 bytes (M13_RDL_FILL[1:0] = 00 (Table 287)), 32 bytes (M13_RDL_FILL[1:0] = 01), 64 bytes (M13_RDL_FILL[1:0] = 10), or 96 bytes (M13_RDL_FILL[1:0] = 11). The user may read bytes from the FIFO through register M13_RDL_DATA_R (Tabl e 2 54). The portion of the earli- est frame still in the FIFO can be deleted by setting M13_RDL_FRM_CLR ( Tabl e 2 58) to 1. (This is normally done to purge a corrupted or aborted frame.) The user must reset M13_RDL_FRM_CLR be fore another frame can be deleted. If M13_RDL_FRM_CLR is set before the closing flag of the frame currently being read from the FIFO has been received, all subsequent bytes of the frame will be discarded without being written into the FIFO.

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 May 2001 472 Agere Systems Inc. Frame Status and Error Reporting. The M13 provides information on the earliest frame still in the FIFO through status register M13_RHDLC_STATUS_R (Tabl e 2 56). The status register has 1 bit to indicate whether or not the closing flag (or an abort byte) for the current frame has been received, 1 bit to indicate if the current frame is corrupted, 5 bits to indicate the size of the current frame mod- ulo-32, and 1 bit to indicate whether or not there are less than 32 bytes of the earliest frame left in the FIFO. There are four ways in which the M13 can identify that the current frame has been corrupted. The frame may have been aborted (M13_RDL_ABORT = 1 (Table 253)), it may have failed the CRC check (M13_RDL_FCS_ERR = 1 ( Table 253)), the number of bits between opening and closing flags may not have been a multiple of 8 (M13_RDL_NOT_BYTE = 1 (Table 253)), or it may have been overwritten before being read from the FIFO (M13_RDL_OVFL = 1 (Table 253)). Also, there is a separate bit M13_RDL_FLAG (Table 253) to indicate whether or not the closing flag (or an abort byte) for the current frame has been received. The size of the current frame modulo-128 (including FCS bytes only if M13_RDL_FCS = 0 (Table 287)) is indicated by register M13_RDL_FRAME_SIZE_R (Table 255). DS3 Performance Monitors. For performance monitoring purposes, there are a number of error counters in the M13. All of these internal counters are comprised of a running error counter and a hold register that presents stable results to the microprocessor. The counts in all of the running counters are latched to the hold registers and the running counters cleared with the configured internal performance monitor reset signal. The latched results are then held to be read by the microprocessor. All of the internal counters have the ability to store more than the maximum possible count in a one second interval for a bit error rate of 10 –3. As long as the per- formance monitor reset occurs at least once every second, no counts will be lost. In case this doesn’t happen, all of the running counters will either hold their maximum value or roll over to zero, depending on the control signal input SMPR_SAT_ROLLOVER ( Table 67). Within the M23 demultiplexer, there are four performance monitoring counters. M13_DS3_FERR_CNT[11:0] (Table 289) increments each time an error is detected in either an F bit or M bit, and M13_DS3_PERR_CNT[13:0] (Table 292) increments if at least one of the P bits disagrees with the parity of the previous frame. In the C-bit parity mode only, M13_DS3_CPERR_CNT[13:0] (Table 291) counts frames with at least two of the three C-bit parity bits indicating an error, and M13_DS3_FEBE_CNT[ 13:0] (Table 290) accumulates FEBE error indications (1 error indi- cation for each DS3 frame with at least one FEBE bit equal to zero).

20.11.4 M12 Demultiplexers

Each M12 demultiplexer outputs either 4 DS1 signals from the DS2 frame as specified in GR-499-CORE (when M13_DS1_E1Ny = 1 (Table 263)), or three E1 signals from the DS2 format specified in ITU-T Recommendation G.747 (when M13_DS1_E1Ny = 0). In the DS1 mode, the demultiplexed second and fourth channels are inverted before being sent to the output selectors when M13_DEMUXCH2_4_INVy = 1 (Table 272). Each M12 DeMUX can be programmed independently to receive DS2 signal either from M23 deMUX (when M13_M12DMX_MODEy[1:0] = 00 ( Table 272)) or direct DS2 input XC_DS2DMXDA TAy (when M13_M12DMX_MODEy[1:0] = 01). In the latter case, an input DS2 clock XC_DS2DMXCLKy is also required. When M13_M12DMX_MODEy[1:0] = 10/11, the M12 demultiplexer is idle and the outputs are held low. The DS2 signal is monitored for AIS, which is declared (M13_DS2_AIS_DE Ty = 1 (Table 242)) if the demultiplexer input is 0 for fewer than five clock cycles in each of two consecutive 840 clock periods, and cleared if there are more than 4 zeros in each of two consecutive 840-bit periods (G.775).

20.11.5 DS1 Mode

Framer. The M12 demultiplexers determine if the input signal contains valid DS2 framing. This is done in two stages by first finding a bit position that matches the M-subframe alignment pattern (F bits), and then locating the M frame alignment signal (M bits). After a matching F-bit sequence is found, in-frame is declared (M13_DS2_OOFy = 0 (Table 240)) when correct M bits are received for three consecutive M frames. The maximum average reframe time is 2.5 ms in the presence of a bit error rate of 10 –3.

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 473Agere Systems Inc. Once the deMUX is in-frame, the received frame bits are monitored for out-of-frame. Out-of-frame is declared (M13_DS2_OOFy = 1) if too many errors are received in either the F bits (two errors in 4 bits when M13_DS2_MODE = 0 ( Table 274), or at least one F-bit error in four consecutive M-subframe pairs when M13_DS2_MODE = 1) or the M-bits (at least one error in three consecutive M frames). For testing purposes, the user may also force the framer out-of-frame by setting M13_DS2_FORCE_OOFy (Table 257) to 1. The traditional algorithm for declaring out-of-frame (two errors in 4 F bits) results in false out-of-frame approxi- mately every 5 seconds when the bit error rate is 10 –3. By waiting for four consecutive errored M-subframe pairs (containing 4-F bits) before declaring out-of-frame (M13_DS2_MODE = 1), the M13 normally stays in frame for over 4four days when the bit error rate is 10 –3. Overhead Processing. The C bits for each DS1 channel are checked for loopback requests. If the third C bit dif- fers from the first and second C bits in the zth M-subframe for five successive DS2 frames, M13_DS1_LB_DETx (Table 249) is set to 1, where x = (4y – 4 + z). M13_DS1_LB_DETx is cleared when the third C bit does not differ from the first two C bits in the zth M-subframe for five successive DS2 frames. If the X bit in four consecutive frames is received as 0, the M13 sets M13_DS2_RAI_DETy (Table 243) to 1. Once M13_DS2_RAI_DETy is set, it is not cleared until the X bit is received as 1 in four consecutive frames.

20.11.6 E1 Mode

Framer. The M12 demultiplexers determine if the input signal contains a valid frame format as specified in ITU-T recommendation G.747. Frame alignment is declared (M13_DS2_OOFy = 0 (Table 240)) when a correct frame alignment signal is received for three consecutive frames. The maximum average reframe time is 0.5 ms in the presence of a bit error rate of 10 –3. Out-of-frame is declared (M13_DS2_OOFy = 1) if the frame alignment signal contains at least 1-bit error for four consecutive frames. For testing purposes, the user may also force the framer out-of-frame by setting M13_DS2_FORCE_OOFy (Table 257) to 1. Overhead Processing. The C bits for each E1 channel are checked for loopback requests. If the third Cz bit differs from the first and second Cz bits for five successive frames, M13_DS1_LB_DETx (Table 249) is set to 1, where x = (4y – 4 + z). M13_DS1_LB_DETx is cleared when the third Cz bit does not differ from the first two Cz bits for five successive frames. If the RAI bit in four consecutive frames is received as 1, the M13 sets M13_DS2_RAI_DETy to 1 (Table 243). Once M13_DS2_RAI_DETy is set, it is not cleared until the RAI bit is received as 0 in four consecutive frames. The received reserved bit is reported through the M13_DS2_RSV_RCVy (Tabl e 2 45), which is updated only when a new value is received in four consecutive frames. Loss of Frame and Automatic AIS Insertion. The M13_DS2_LOFy ( Table 241) bit is set when M13_DS2_OOFy is high continuously for 28 DS3 frame periods (approximately 3 ms). Once set, M13_DS2_LOFy is not cleared until M13_DS2_OOFy is continuously low for 28 DS3 frame periods. The user can provision the M13 to automatically output AIS if either bit M13_DS2_OOFy = 1 (by setting M13_AUTO_AIS_OOF to 1), or M13_DS2_LOFy = 1 (by setting M13_AUTO_AIS_LOF to 1). DS2 Performance Monitors. Within each M12 demultiplexer, there are two performance monitoring counters. These counters are cleared and read as described above (see DS3 Performance Monitors on page 472). Registers M13_DS2_FERR_CNT[7 — 1]_R (Table 294) count errors in the frame alignment signal. In the DS1 mode, M13_DS2_FERR_CNTy ( Table 294) increments each time an error is detected in either an F bit or M bit. In the E1 mode, this counter increments either for each frame alignment signal bit error (when M13_DS2_FERR_MODE = 0 ( Table 274)), or once for each frame alignment signal that contains at least one bit error (when M13_DS2_FERR_MODE = 1). In the E1 mode only, registers M13_DS2_PERR_CNT[7— 1]_R[1— 2] (Table 293) count errors in P bits.

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 May 2001 474 Agere Systems Inc.

20.11.7 Output Select Logic

DS2 Output Selection. The M23 demultiplexer outputs are fed into seven DS2 output selection logic blocks. This allows the M13 to output the demultiplexed DS2 signals or insert AIS. Each selector is identified by a number y that ranges from one to seven and corresponds directly to M13 outputs M13_DS2DATA[7 — 1]. The outgoing DS2 signals are retimed by an associated clock, M13_DS2CLK[7— 1]. The edge of the clocks that is used to retime the data is provisionable to either the rising edge (M13_TDS2_EDGE = 1 (Table 294)) or falling edge (M13_TDS2_EDGE = 0). The output from each selection block is controlled by the values of bits M13_DS2_OUT_IDLEy ( Table 284) and M13_DS2_OUT_AISy ( Tabl e 2 85). I Output is held low when M13_DS2_OUT_IDLEy = 1; otherwise, the deMUXed DS2 signal is output when M13_DS2_OUT_AISy = 0 and DS2 AIS is output when M13_DS2_OUT_AISy = 1. The all ones DS2 AIS signal is also output under all failure conditions at DS3 level which require automatic AIS insertion at DS2 level. DS1/E1 Output Selection. The M12 demultiplexer outputs are fed into 28 DS1/E1 output selection logic blocks. This allows the M13 to output the demultiplexed DS1/E1 (M13_DS1_OUT_AISx = 0 (Table 273)), or insert AIS (M13_DS1_OUT_AISx = 1). The all ones AIS signal is also output under all failure conditions at DS3 or DS2 level which require automatic AIS insertion at DS1/E1 level. Each selector is identified by a number x that ranges from 1 to 28 and corresponds directly to a block output M13_DS1DATA[28 — 1]. The outgoing DS1 and/or E1 signals are retimed by an associated clock, M13_DS1CLK[28 — 1]. The edge of the clock that is used to retime the data is provisionable to either the rising edge (M13_TDS1_EDGEx = 1 (Table 272)) or falling edge (M13_TDS1_EDGEx = 0). Each output selector number, x can be expressed as either 4y – 3, 4y – 2, 4y – 1, or 4y, where y ranges from 1 to 7. For a given y, the 4 selectors in the group output DS1 signals when M 13_OUT_TYPEy = 1 (Table 272), or E1 signals when M13_OUT_TYPEy = 0. In either of these modes, the four selectors in the group are controlled by the 2-bit values OUTSELx, where x = 4y – 3, 4y – 2, 4y – 1, and 4y. When M13_OUT_TYPEy = 0, the output of selector 4y is held low.

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 475Agere Systems Inc. 21 28-Channel Framer Block Functional Description Table of Contents Contents Page

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 May 2001 476 Agere Systems Inc. 21 28-Channel Framer Block Functional Description (continued) Table of Contents (continued) Contents Page 21.22.9 21.22.14

into two basic modes: DS0/E0 switching mode and DS1/E1 transport/monitoring mode.

21.1.1 DS0/E0 Switching Applications

transmits or receives framed (channelized) or unframed (unchannelized) DS0/E0 time slots. block. The data consists of data, clock, and frame sync. to the facility data link in the transmit line path. Figure 52. Switching Application of the Super Mapper

Figure 53. Super Mapper Switching Configuration

21.2 Transport Applications

mance monitoring on the data and in ESF mode transmit PRMs back to its line interface. Figure 55. Transport Application of the Super Mapper

Figure 56. Super Mapper Transport Configuration

Figure 57. Super Mapper Transport (with Intrusive Performance Monitoring) Mode (The Optional Byte-

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 485Agere Systems Inc. 21 28-Channel Framer Block Functional Description (continued)

21.3 Framer-to-Line Interface Unit Physical Interface

The framer-LIU interface of the Super Mapper framer consists of 28 groups of six connections. The internal DS1 cross connect must be configured to connect the framer-LIU interface through the multifunction system interface to external T1/E1 line interface devices. The six connections for each framer are TND, TPD, and TLCK driven from the transmit framer (receive path) and RPD, RND, and RCLK (transmit path) sourced from the external line interface device. The connections can optionally be from/to the protected switch. See Table 3 on page 15 for the external pin names that correspond to the desired six connections. The line interface may operate in single-rail or dual-rail mode. The default mode of the line encoder is single-rail (FRM_LD_MODE[2:0] = 000 (Table 430), FRM_LE_MODE[2:0] = 000 (Table 431)). In this mode, the input signals are passed transparently through the line encoder. In single rail mode, the link’s framer internal bipolar line encoder/decoder is disabled and monitoring of received line format violation is accomplished with the use of the RND input. When RND = 1 on the rising edge of RLCK, the line format violation FRM_BPV[15:0] (Table 388) counter increments by one. The link’s transmit framer transmits data via the TPD output pin while TND is forced to a 0 state. In dual rail mode, the internal line encoder/decoder and monitoring are enabled. The line code may be selected by provisioning FRM_LD_MODE[2:0] and FRM_LE_MODE[2:0]: 1. Alternate Mark Inversion (AMI). 2. High-Density Bipolar of Order 3— G.703, A.1 (HDB3). 3. Binary 8 Zero Code Suppression— G.703, A.2 (B8ZS). Line format violations due to excessive zeros will be optionally monitored as follows: 1. B8ZS— 8 consecutive zeros cause a violation. 2. HDB3— 4 consecutive zeros cause a violation.

21.3.1 Line Interface References/Standards

1. ITU-T Recommendation G.703, Physical/Electrical Characteristics of Hierarchical Digital Interfaces;1991. 2. ANSI T1.403-1995, Network-to-Customer Installation - DS1 Metallic Interface; March 21, 1995.

21.3.2 Frame Formats

The 28 superframers support the following frame formats: 1. DS1 superframe D4. 2. DS1 superframe J-D4 with Japanese remote alarm. 3. DS1 superframe DDS. 4. DS1 superframe SLC -96. 5. DS1 extended superframe (ESF). 6. Japanese extended superframe J-ESF (J1 standard with different CRC-6 algorithm). 7. Nonalign DS1 (transparent 193 bits). 8. CEPT basic frame {ITU G.706}. 9. CEPT CRC-4 multiframe with 100 ms timer {ITU G.706}. 10. CEPT CRC-4 multiframe with 400 ms timer (automatic CRC-4/nonCRC-4 equipment interworking) {ITU G.706 Annex B}. 11. Nonalign E1 (transparent 256 bits). 12. 2.048 coded mark inversion (CMI) coded interface (TTC Standards JJ-20.11). 13. 6.312 Mbits/s interface (ITU G.704/NTT J2).

21.3.3 Transmit Framer Functions

1. Transmits alarm indication signal (AIS) to the line automatically and on demand.
2. Transmits AIS-CI to the line automatically and on demand.
3. Transmits remote alarm indication (RAI) to the line automatically and on demand. Conditions for transmitting

equals 8, and received Sa6 equals C.

1. Transmits RAI-CI to the line automatically and on demand.
2. Transmits auxiliary test pattern (AUXP) to the line automatically and on demand.
3. Transmits CEPT E bits based received CRC-4 errors.
4. Support the CEPT double not-FAS system mode.
5. Transmits a PRBS test pattern to the line on demand.
6. In transport mode, when not in frame alignment, to optionally send AIS or transparently pass data.

21.3.4 Framing References/Standards

1. ITU-T Recommendation G.703, Physical/Electrical Characteristics of Hierarchical Digital Interfaces; 1991.
2. ITU-T Recommendation G.704, Synchronous Frame Structures used at 1554, 6312, 2048, 8488 and

44736 kbits/s Hierarchical Levels; July 1995.

1. ITU-T Recommendation G.706, Frame Alignment and Cyclic Redundancy Check (CRC) Procedures Relating to

Basic Frame Structures defined in Recommendation G.704; 1991.

1. TTC Standard JT-G704, Synchronous Frame Structures used at 1554, 6312, 2048, 8488 and 44736 kbits/s Hier-

21.4 DS1 Transparent Framing Format

The transmit framer can be programmed to transparently transmit 193 bits of CHI system data to the line. Frame integrity is maintained in both the transmit and receive framer sections. Figure 58. DS1 Transparent Frame Structure

32 TIME-SLOT CHI FRAMETIME-SLOT 2 TIME-SLOT 3 TIME-SLOT 31 TIME-SLOT 32

0000000 F B I T

insert the 193rd bit of the receive line data into bit 8 of time slot 1 of the transmit system data. Bit 8 of time slot 1 of the receive system interface is inserted as the 193rd data bit into the transmit line data. (Table 422) to 1000 (nonalign 193rd bit). remaining bits in time slot 1 are set to 0. Bit 8 of time slot 1 of the receive system interface is inserted in the transmit line framing bit position. priate framing mode with FRM_MODE[3:0] (Table 422). transmit framer must be programmed to transparent framing mode 1 . time slot of the transmit line interface. Frame integrity is maintained in both the transmit and receive framer sections. Figure 59. CEPT Transparent Frame Structure payload is transmitted unmodified to the CHI. (Table 422) to 0000 (non-align 256th bit). of receive line data is performed and data is transmitted to the CHI as programmed. priate framing mode with FRM_MODE[3:0] (Table 422).

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 May 2001 488 Agere Systems Inc. 21 28-Channel Framer Block Functional Description (continued)

21.6 Receive Framer Nonalignment Mode (DS1/E1)

In the non-align framing modes the receive frame aligner does not frame to the receive line data. Other than bipolar violations, AIS, and AUXP monitoring, there is no processing of the receive line data. The entire receive line frame is given unmodified to the system interface.

21.6.1 Loss of Frame Alignment Criteria

There are two criteria for declaring loss of frame: frame bit errors and CRC errors. Frame Bit Errors. 1. T1: two frame bit errors out of 4 frame bits (F T and FS bits checked). 2. T1: two frame bit errors out of 5 frame bits (FT and FS bits checked). 3. T1: two frame bit errors out of 6 frame bits (FT and FS bits checked). 4. T1: three frame bit errors out of 12 frame bits— DDS only (FT, FS, and time slot 24 F bits). 5. T1: two frame bit errors out of 4 frame bits (only FT bits checked). 6. T1: two frame bit errors out of 5 frame bits (only FT bits checked). 7. T1: two frame bit errors out of 6 frame bits (only FT bits checked). 8. T1: four frame bit errors out of 12 frame bits— DDS only (FT, FS and time slot 24 FAS pattern). 9. E1: three consecutive incorrect frame alignment signals. 10. E1: three consecutive incorrect frame alignment signals or three consecutive incorrect non-FAS frames as indi- cated by bit 2 in time slot 0 in frames not containing the frame alignment signal. 11. E1: 3 consecutive incorrect FAS or non-FAS frames. 12. 2.048 Mbits/s CMI: 2 consecutive missing code rule violations (CRVs). CRC Errors. The use of CRC errors to declare loss of frame is optional. CRC errors are monitored in the performance monitor block. In DS1 mode, ESF , and J-ESF formats only, N or more CRC-6 errors in a 1 second interval results in loss of frame alignment. N is provisionable. N defaults to 320 in DS1 mode. In CEPT mode N, or more, CRC-4 errors in a 1 second interval results in loss of frame alignment. N is provision- able. N defaults to 915 in CEPT modes.

21.7 Frame Alignment Criteria

Table 576 describes the frame alignment criteria for the formats supported by the superframer. Table 576. Frame Alignment Criteria

21.8 Receive and Transmit Signaling Processor

21.8.1 Signaling Introduction and Feature Description

received. Only the FT framing bits are checked (36 bits checked). received (72 bits checked in D4, 66 bits checked in J-D4). received (42 bits checked: FT, FS, and time slot 24).

1. All the while the FT frame position must remain error free.

CEPT Basic Frame Uses the strategy outlined in G.706 paragraph 4.1.2. CEPT CRC-4 400 ms Timer Uses the strategy outlined in G.706 paragraph 4.1.2 and ANNEX B.

2.048 Mbits/s CMI Coded

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 May 2001 490 Agere Systems Inc. 21 28-Channel Framer Block Functional Description (continued) The following system bus modes are supported (no special provisioning is needed for the signaling processor to distinguish between these system bus modes): I Parallel system bus I CHI bus in ASM mode The VT mapper interface in the signaling processor supports VT1.5, VT 2 byte sync mapping, as well as VC-11 byte sync mapping using handling groups. The host can read the signaling data extracted from the line, system, or VT mapper interface at any time. The transmit signaling processor can be configured so that the host provides the signaling data to be forwarded to the line, system, or VT mapper interface. Other signaling features include: I Debounce on all signaling data extracted from the line interface or the VT mapper interface. I Host interrupt upon change of signaling state in the receive path. I Signaling extraction inhibit based on frame alignment and framing bit errors. I Stomping of DS1 robbed-bit signaling positions. I Support of zero-code suppression on the line interface in the transmit path. I Superframe signaling integrity. No signaling data transmitted will be a mix of old and new due to a mid super- frame update of signaling information.

21.8.2 Signaling References/Standards

I ITU Rec. G.704 10/98 CEPT Multiframe Signaling Structure I ITU Rec. G.775 10/98 CEPT TS16 AIS Detection, Remote Alarm Detection I ITU Rec. G.732 1998 CEPT Time-Slot 16 mfa, Time-Slot 16 rfa I ITU Rec. O.162 10/92 CEPT Time-Slot 16 rfa Detection I T1.403 1995 Robbed-Bit Signaling I TTC JJ-20.11 CMI Coded Interface I ANSI T1.105 SONET Payload Mapping I Telcordia GF-253-CORE SONET Transport Systems I ITU Rec G.707 10/98 Network Node Interface for SDH I TTC JT G.704 Japanese Synchronous Frame Structures

21.9 Receive Signaling Per-Link Feature Provisioning

The receive signaling processor requires the provisioning of four items for each link in order to enable signaling extraction and delivery: 1. Signaling state mode source (host or Rx CHI interface). 2. Signaling state mode (2-, 4-, and 16-state mode or no-signaling). 3. Signaling source (receive line, VT mapper, or host interface). 4. Signaling destination (transmit system or transmit line interface).

21.9.1 Signaling State Mode Source Selection

links. The default state mode selected is 16-state signaling.

21.9.2 Signaling State Mode Selection

nition for each of those 32 registers is shown below. Table 577. Receive Signaling Link Registers 0— 31 Bit Description The signaling state mode definitions are shown in the table below. Table 578. Receive Signaling Link Registers 0— 31 G-Bit and F-Bit Description ing state mode for CMI type links must be set to 11. detect a toggle code. In this case, signaling will be collected over two superframes and stored as a 4-bit code. face before the first valid signaling code has been extracted from the receive line or VT mapper interface. mode selection. Any combination is acceptable.

21.9.3 Signaling Source Selection

page 268 for each of the links. nel signaling from CEPT links, and time slot 0 signaling from CMI links compliant with the following standards.

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 May 2001 492 Agere Systems Inc. 21 28-Channel Framer Block Functional Description (continued) I ITU Rec G.704 10/98 CEPT multiframe signaling structure I T1.403 1995 robbed-bit signaling I TTC JJ-20.11 CMI coded interface If the VT mapper is transporting byte sync mapped DS1 links into SONET frames, then the signaling source should be set to VT mapper interface. In that case, the receive signaling processor will start collecting valid signaling codes from the VT mapper and store them into the D, C, B, and A locations of FRM_RSLR0— FRM_RSLR31, Receive Signaling Link Registers 0— 31 (R/W), Table 372 on page 268 for each of the links. If the VT mapper is the source of signaling, data will be extracted based on the standards listed below. I ANSI T1.105SONET payload mapping I Bellcore GF-253-CORE SONET transport systems I ITU Rec G.707 10/98 network node interface for SDH If the VT mapper is transporting byte sync mapped CEPT links into SONET frames, then the signaling source should be set to the receive line interface. In that case, the receive signaling processor will extract the entire time slot 16 multiframe and store that information into FRM_RSLR0— FRM_RSLR31, receive signaling link registers 0— 31 (R/W) for each of the links. If the signaling source is set to be the host, the host may write to FRM_RSLR0— FRM_RSLR31, receive signaling link registers 0— 31 (R/W) and those values will be forwarded to the selected destination. The host mode can also be used to manually freeze signaling. When the source is switched from receive line to host, for example, the exist- ing signaling codes will be held until modified by the host or until the signaling source is switched back to the receive line interface. If the host mode is used to manually freeze signaling, then the signaling debounce feature must be enabled. To enable signaling debounce set FRM_R_SIGDEB in Table 374, FRM_RSLR33, Receive Sig- naling Link Register 33 (R/W) on page 269, bits 5 to 1. Each of the links is completely independent from one another with respect to the signaling source selection. Any combination of receive line, VT mapper, and host is acceptable.

21.9.4 Signaling Destination Selection

There are three destinations for the signaling extracted from the receive line or VT mapper interface: 1. Transmit system interface. 2. Transmit line interface. 3. FRM_RSLR0 — FRM_RSLR31, receive signaling link registers 0— 31 (R/W), Table 372 on page268. The signaling extracted from the receive line or VT mapper interface will automatically be delivered to the transmit system interface when the framer section of the Super Mapper is programmed for switch mode. This is done by set- ting FRM_SW_TRN in FRM_SFGR1, Superframer Global Register 1 (R/W), Table 301 on pag e243, bits 15 to 1. The system interface will need to be configured for ASM mode in order for the signaling to be transmitted on the PSB or CHI buses. ASM mode is controlled by FRM_SYSGR1, System Interface Global Register 1 (R/W), Table 347 on page257 bit 11. The signaling extracted from the VT mapper interface can be inserted into the transmit line interface when the framer section of the Super Mapper is programmed for transport mode. This is done by setting FRM_SW_TRN in FRM_SFGR1, Superframer Global Register 1 (R/W), Table 301 on page243, bits 15 to 0, and by setting FRM_R_SIGI in Table 374, FRM_RSLR33, Receive Signaling Link Register 33 (R/W) on page 269, bit 8 to 1. The signaling will be inserted based on the programming of state modes of each time slot. The receive signaling processor cannot provide data to the transmit system and the transmit line interface on differ- ent links simultaneously. Signaling extracted from the VT mapper or receive line interface will always be available in FRM_RSLR0— FRM_RSLR31, Receive Signaling Link Registers 0— 31 (R/W), Table 372 on page268 for each link. The host can read these registers regardless of whether or not the signaling is forwarded to the transmit system or transmit line interface. Receive Signaling Link Registers 0— 31 DS1/CEPT/CMI Data, Table 577 on page 491 shows the position of the data in those 32 registers for each of the receive line formats.

Table 579. Receive Signaling Link Registers 0— 31 DS1/CEPT/CMI Data Table 372 on page 268 also depends on the signaling state mode selected for each time slot as shown inTable 580.

1 GF0 DCBA (Channel 1) 000 DCBA (Channel 1) 110 DCBA (Channel 1)

2 GF0 DCBA (Channel 2) 000 DCBA (Channel 2) 110 DCBA (Channel 2)

3 GF0 DCBA (Channel 3) 000 DCBA (Channel 3) 110 DCBA (Channel 3)

4 GF0 DCBA (Channel 4) 000 DCBA (Channel 4) 110 DCBA (Channel 4)

5 GF0 DCBA (Channel 5) 000 DCBA (Channel 5) 110 DCBA (Channel 5)

6 GF0 DCBA (Channel 6) 000 DCBA (Channel 6) 110 DCBA (Channel 6)

7 GF0 DCBA (Channel 7) 000 DCBA (Channel 7) 110 DCBA (Channel 7)

8 GF0 DCBA (Channel 8) 000 DCBA (Channel 8) 110 DCBA (Channel 8)

9 GF0 DCBA (Channel 9) 000 DCBA (Channel 9) 110 DCBA (Channel 9)

10 GF0 DCBA (Channel 10) 000 DCBA (Channel 10) 110 DCBA (Channel 10)

11 GF0 DCBA (Channel 11) 000 DCBA (Channel 11) 110 DCBA (Channel 11)

12 GF0 DCBA (Channel 12) 000 DCBA (Channel 12) 110 DCBA (Channel 12)

13 GF0 DCBA (Channel 13) 000 DCBA (Channel 13) 110 DCBA (Channel 13)

14 GF0 DCBA (Channel 14) 000 DCBA (Channel 14) 110 DCBA (Channel 14)

15 GF0 DCBA (Channel 15) 000 DCBA (Channel 15) 110 DCBA (Channel 15)

16 GF0 DCBA (Channel 16) ——

17 GF0 DCBA (Channel 17) 000 DCBA (Channel 17) 110 DCBA (Channel 17)

18 GF0 DCBA (Channel 18) 000 DCBA (Channel 18) 110 DCBA (Channel 18)

19 GF0 DCBA (Channel 19) 000 DCBA (Channel 19) 110 DCBA (Channel 19)

20 GF0 DCBA (Channel 20) 000 DCBA (Channel 20) 110 DCBA (Channel 20)

21 GF0 DCBA (Channel 21) 000 DCBA (Channel 21) 110 DCBA (Channel 21)

22 GF0 DCBA (Channel 22) 000 DCBA (Channel 22) 110 DCBA (Channel 22)

23 GF0 DCBA (Channel 23) 000 DCBA (Channel 23) 110 DCBA (Channel 23)

24 GF0 DCBA (Channel 24) 000 DCBA (Channel 24) 110 DCBA (Channel 24)

Table 580. Receive Signaling Link Registers 0— 31 Expected Data If the state mode is 4 state or 2 state, then the unused bits will be set to 0.

21.10 Optional Receive Signaling Features Provisioned for Each Link

21.10.1 Support of DS1 Robbed-Bit Stomping

21.10.2 Support of CEPT Time Slot 16 Stomping

configured to transmit AIS on the system bus in time slot 16 when the signaling block loses time slot 16 alignment.

21.10.3 Support of Signaling Debounce

in FRM_RSLR33, Receive Signaling Link Register 33 (R/W), Table 374 on page269, bit 5.

21.10.4 Support of Japanese Handling Groups

1. This mode forces the signaling data for the channels contained in each handling group to 1 if HG alignment has

2, 6, 10, 14, 18, and 22 forwarded to the system would be forced to 1.

21.11 Receive Signaling Global Feature Provisioning

I Link count (number of active receive links).

21.11.1 Link Count Selection

FRM_FGR2, framer global register 2 (R/W), Table 306 on page246, bits [7:0].

21.12 Other Receive Signaling Global Features

21.12.1 Support of Automatic Signaling Freeze on Framing Bit Errors

feature is enabled in FRM_RSLR33, Receive Signaling Link Register 33 (R/W), Table 374 on pag e269, bit 5.

21.12.2 Support of Change of Signaling State FIFO

The FIFO is located at signaling receive global register 3. The word read by the host has the following format. Table 581. Signaling Receive Global Register 3, Bit Definition that the FIFO is empty. The signaling code presented will reflect the associated GF value programmed by the host. and C bits will be set to 0. The A and B bit will identify the valid signaling code. This feature can be used in combination with any other feature (i.e., debounce). processed and the signaling interrupt timer has expired, then the host will be interrupted. 0, which results in the host being interrupted whenever an entry is made into the FIFO. however, subsequent entries will be stored normally. The host can poll the change of state FIFO without the use of interrupts.

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 May 2001 496 Agere Systems Inc. 21 28-Channel Framer Block Functional Description (continued)

21.13 Receive Signaling Interrupts

There are three interrupts which are maintained in the receive signaling processor, which are located in FRM_SGR7, receive signaling global register 7 (R/W), Table 365 on page264. The three interrupts reflect the sta- tus of the change of signaling state FIFO. These interrupt bits can be reset based on a clear-on-read protocol, which is provisioned in the Super Mapper global registers. I Threshold overflow interrupt. This bit is set to 1 when the programmed threshold for the FIFO capacity has been exceeded. I Interrupt timer interrupt. This bit is set to 1 when the programmed interrupt timer has expired and there are valid entries in the FIFO to be processed. I FIFO overflow interrupt. This bit is set to 1 when the FIFO overflows. There are mask bits associated with each of the three interrupt status bits which are located in FRM_SGR7, receive signaling global register 7 (R/W).

21.13.1 Maintenance of the Change of Signaling State FIFO Status Bits

There is one bit which reflects the status of the change of signaling state FIFO. The location of this status bit is in FRM_SGR5, receive signaling global register 5 (RO), Table 363 on page263. I FIFO depth threshold overflow status. This bit is set to 1 when the programmed threshold for the FIFO capacity has been exceeded.

21.13.2 Maintenance of Handling Group Related Status Bits

There are three bits which reflect the status of the handling groups extracted from the VT mapper interface. There are four handling groups on each link therefore there will be three copies of the following bits for each link. The location of these status bits are in FRM_RSLR33, Receive Signaling Link Register 33 (R/W), Table 374 on page 269. I Loss of HG alignment. Alignment uses the 0101010 . . . framing pattern and follows the alignment algorithm shown in Figure 60 on page497. I AIS detection within each handling group (AIS detection 48 consecutive ones, AIS loss any two zeros). I RDI detection within each handling group (RDI detection is the presence of three consecutive zeros in the Sp bit position).

Figure 60. HG Alignment Algorithm

21.14 Transmit Signaling Per-Link Feature Provisioning

21.14.1 Signaling State Mode Source Selection

ming the state mode. If so, the host will have to program the state mode for all of the time slots on each link.

each of the time slots on each link.

21.14.2 Signaling State Mode Selection

isters is illustrated below. Table 582. Transmit Signaling Link Registers 0— 31 Bit Description The signaling state mode definitions are illustrated in the table below. Table 583. Transmit Signaling Link Registers 0— 31 G-Bit and F-Bit Description ing state mode for CMI type links must be set to 11. to detect a toggle code. In this case, signaling will be collected over two superframes and stored as a 4-bit code. before the first valid signaling code has been extracted from the receive line or receive system interface. mode selection. Any combination is acceptable.

21.14.3 Signaling Source Selection

There are three sources for signaling in the transmit path. of signaling data in those registers for the different types of links.

10 No signaling

Table 584. Transmit Signaling Link Registers 0— 31 DS1/CEPT/CMI Data correct time slot 16 multiframe alignment pattern is to be transmitted. The reset value of all TSLR locations is 0. source back to the receive system interface. If the source of signaling is the host, only the relevant bits need be written in each transmit signaling link register. for each time slot as shown in Table 585.

16 GF0 DCBA (Channel 16) 000 0000 —

Table 585. Transmit Signaling Link Registers 0— 31 Expected Data T_SIGDEB in the transmit signaling link register, bit 5 to 1. registers 0— 31 for each of the links. channel signaling from CEPT links, and time slot 0 signaling from CMI links compliant with the following standards. signaling source is set to the receive system interface. different links simultaneousl y.

21.14.4 Signaling Destination Selection

There are two destinations for transmit path signaling.

1. The transmit signaling processor will automatically detect the format of each link and insert the signaling accord-

signaling link registers 0— 31.

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 501Agere Systems Inc. 21 28-Channel Framer Block Functional Description (continued) The signaling will be byte sync mapped based on the standards listed below. I ANSI T1.105 SONET Payload Mapping I Telcordia GF-253-CORE SONET Transport Systems I ITU Rec G.707 10/98 Network Node Interface for SDH

21.15 Optional Transmit Signaling Features Provisioned for Each Link

21.15.1 Support of Automatic Maintenance of the Time-Slot 16 Remote Frame Alarm

For CEPT links, the time slot 16 remote frame alarm (Y bit) can be automatically maintained in the transmit path by setting FRM_T_ATS16RFA in FRM_TSLR32, Transmit Signaling Link Register 32 (R/W), Table 378 on pag e272, bit 14, to 1. In that case, the Y bit transmitted will reflect the TS16 multiframe alignment status in the receive path. Bit 1 in the transmit signaling link register 0 will be ignored. If the receive path time slot 16 alignment for a particular link is lost, then the corresponding Y bit in the transmit path will be set to 1.

21.15.2 Support of DS1 Robbed-Bit Stomping

The DS1 robbed-bit positions of voice time slots will be set to 0 in the payload when FRM_T_TXSTOMP in FRM_TSLR32, Transmit Signaling Link Register 32 (R/W), bit 7 is set to 1. This feature is a programmable option required for byte sync mapping.

21.15.3 Support of CEPT Time-Slot 16 Stomping

Stomping of time slot 16 for CEPT links can by accomplished by setting the source of signaling to be the host and then programming the transmit signaling link registers 0— 31 to all ones.

21.15.4 Support of Signaling Debounce

If programmed to do so, the signaling extracted from the receive line interface will be debounced. This implies that a valid signaling code would have to be detected twice before it is updated in the transmit signaling link registers 0— 31. This feature is enabled by setting FRM_T_SIGDEB in FRM_TSLR32, Transmit Signaling Link Register 32 (R/W), bit 5 to a 1.

21.15.5 Support of Japanese Handling Groups

If the signaling is transported by the VT mapper within four handling groups compliant to the Japanese standard, TTC JT G.704, then FRM_T_HGEN in FRM_TSLR32, Transmit Signaling Link Register 32 (R/W), bit 4, must be set to 1. The signaling state mode will be assumed to be 2-state signaling, and the value programed into the GF bits of the transmit signaling link registers 0— 31 will be ignored. By default, the transmit signaling processor will drive the Sp bit of each handling group on each link to 1.This bit can be manually forced to 0 for all the handling groups within a link by setting FRM_T_MSP in FRM_TSLR32, Transmit Signaling Link Register 32 (R/W), bit 11, to 1. The Sp bit can be automatically maintained by setting FRM_T_ASPLB in FRM_TSLR32, Transmit Signaling Link Register 32 (R/W), bit 12, to 1. In that case, the Sp bits in the transmit path will reflect the corresponding handling group alignment in the receive path. For example, if HG2 on link 3 is the only HG out of alignment on that link, then the Sp bit transmitted to the VT mapper for HG2 will be set to 0. The Sp bit for HG 1, 3, and 4 will be set to 1.

21.15.6 Support of Zero-Code Suppression

If the frame formatter is configured to perform zero-code suppression, then FRM_T_ZCSM in FRM_TSLR32, T ransmit Signaling Link Register 32 (R/W), bit 10, must be set to 1. Zero-code suppression in the frame formatter is enabled by programming FRM_ZCSMD[2:0] in FRM_FFLR1, Frame Formatter Link Register 1 (R/W), Table 424 on page 300, bits [10:8].

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 May 2001 502 Agere Systems Inc. 21 28-Channel Framer Block Functional Description (continued)

21.16 Transmit Signaling Global Feature Provisioning

The transmit signaling processor requires the provisioning of one global item in order to enable signaling extraction and delivery. I Link Count (number of active transmit links).

21.16.1 Link-Count Selection

The link count is specified by programming FRM_T_LINKCNT[4:0] in FRM_SGR8, transmit signaling global regis- ter 8 (R/W), Table 366 on page265, bits [14:10]. The reset value is 28, which is appropriate for a 28 link DS1 appli- cation. A value of 21 is appropriate for a 21 link CEPT application. If the application mixes DS1 and CEPT links or the TDM clock supplied to the framer is less than 51.84 MHz, this value should match the terminal count (FRM_TC[7:0]) set in FRM_FGR2, framer global register 2 (R/W), Table 306 on page246, bits [7:0].

21.17 Other Transmit Signaling Global Features

21.17.1 Support of Automatic Signaling Freeze on Framing Bit Errors

This feature is valid when extracting signaling from the receive line interface (transport mode). By default, signaling extraction from a particular receive line will halt when the appropriate alignment has been lost. In order to guaran- tee that signaling freeze takes place as soon as possible, FRM_T_AFZFBE in FRM_SGR8, Transmit Signaling Global Register 8 (R/W), bit 1, must be set to 1. When enabled, FRM_T_AFZFBE halts signaling extraction for 32 frames upon detection of a frame bit error. When FRM_T_AFZFBE is enabled, the transmit signaling debounce feature must also be enabled. The FRM_T_SIGDEB feature is enabled in FRM_TSLR32, Transmit Signaling Link Register 32 (R/W), bit 5.

21.17.2 Support of Byte Sync SONET Mapping

A provisionable feature related to SONET byte sync mapping requires that those time slots which are configured for no-signaling should have a signaling value of 0 transported by the VT mapper. This feature can be enabled by setting FRM_T_SUBZERO in FRM_SGR8, Transmit Signaling Global Register 8 (R/W), bit 5, to 1. In that case, those time slots with a signaling state mode of no-signaling (GF = 10) will automatically forward a value of 0 to the VT mapper.

21.18 Transmit Signaling Status Registers

There are two status values which are maintained for each of the links.

21.18.1 Maintenance of CEPT Related Status Bits

There are 2 bits which reflect the status of the CEPT time slot 16 signaling multiframe. These status bits are valid when the source of signaling is set to be the receive line interface (transport mode). The location of these status bits is in FRM_TSLR33, Transmit Signaling Link Register 33 (COR), Table 379 on page273. I The receive signaling register searches for AIS in time slot 16 when time slot 16 alignment is lost. The status of this search is maintained. I The status of TS16 multiframe alignment is maintained.

21.19 Performance Monitoring Functional Integration into Superframer

In the transport mode, both directions are monitored for alarm conditions and error events. ter bits and event counter register, and establishes the functions validity in particular framing modes. Table 586. Performance Monitor Functional Descriptions

2 Provides status for errored seconds, bursty errored

3 Maintains a count of errored seconds, bursty errored

seconds, severely errored seconds, and at the ET.

4 Provides a status indication for a loss of signaling

5 Provides a status indication for an out-of-frame con-

6 Provides a status indication for a loss of time slot 0

7 Provides a status indication for a time slot 0 CRC-4

multiframe alignment signal bit error.

8 Provides a status indication for auxiliary pattern

9 Provides a status indication for detection of the DS1

10 Provides a status indication for detection of an alarm

11 Provides a status indication for detection of an alarm

indication signal at the customer installation (AIS-CI).

12 Provides a status indication for detection of remote

13 Provides a status indication for detection of remote

alarm indication at the customer installation (RAI-CI).

14 Provides a status indication for detection of time slot

16 AIS (FRM_R_TS16AIS (Table 373)).

15 Provides a status indication for detection of remote

multiframe alarm in time slot 16 (RTS16MFA).

16 Provides a status indication for the loss of CEPT

Table 586. Performance Monitor Functional Descriptions (continued)

17 Provides a status indication for detection of remote Japanese

20 Provides a status indication for detection of line format viola-

23 Provides a status indication for detection of excessive CRC

25 Provides a status indication for expiration of CRC-4 multiframe

27 Provides a status indication for detection of Sa7 link identifica-

28 Provides a status indication for detection of an SF line loop-

29 Provides a status indication for detection of an SF line loop-

30 Provides a status indication for detection of an overflow in the

31 Provides a status indication for detection of an underflow in the

34 Maintains a count of received bipolar violations, line code vio-

lations, and excessive zeros.

35 Provides a status indication for detection of a bit-oriented mes-

sage in the ESF data link bits.

37 Provides a status indication for detection of a test-pattern bit

38 Provides a status indication for detection of an ESF-FDL

39 Provides a status indication for detection of the ESF-FDL

payload loopback enable code.

40 Provides a status indication for detection of the ESF-FDL

payload loopback disable code.

41 Provides a status indication for detection of the ESF-FDL

42 Provides a status indication for detection of the ESF-FDL

47 Provides a status indication for detection of an (A, Sa5,

48 Provides a status indication for detection of an (A, Sa5,

49 Provides a status indication for detection of an (A, Sa5,

50 Provides a status indication for detection of an (A, Sa5,

51 Provides a status indication for detection of an (A, Sa5,

52 Provides a status indication for detection of an (A, Sa5,

53 Provides a status indication for detection of an (A, Sa5,

54 Provides a status indication for detection of an (A, Sa5,

55 Provides a status indication for detection of an (A, Sa5,

56 Provides a status indication for detection of an (A, Sa5,

57 Provides a status indication for detection of an (A, Sa5,

58 Provides a status indication for detection of an (A, Sa5,

21.20 Performance Report Message

the fields is given in Table 588.

59 Provides a status indication for detection of an (A, Sa5,

60 Provides a status indication for detection of an (A, Sa5,

61 Provides a status indication for detection of an (A, Sa5,

62 Provides a status indication for detection of an (A, Sa5,

63 Provides a status indication for detection of an (A, Sa5,

64 Provides a status indication for detection of an (A, Sa5,

65 Provides a status indication for detection of an (A, Sa5,

66 Provides a status indication for detection of an (A, Sa5,

67 Provides a status indication for detection of an (A, Sa5,

68 Provides a status indication for detection of an (A, Sa5,

69 Provides a status indication for detection of an (A, Sa5,

71 Provides an indication to frame aligner (does not have to be

based on bit 0 of the NOTFAS frames (except 15 and 17).

75 Provides status indication of parallel bus system interface

mode data and signaling parity errors.

are generated in the HDLC block. there are less than two frame bit errors in a window. Table 587. Performance Report Message Format Table 588. Performance Report Message Field Definition

2 SAPI C/R EA

4 Control

5 G 3L VG 4U 1U 2G 5S LG 6

6 F ES EL BG 1 R G 2 N mN I

7 G 3L VG 4U 1U 2G 5S LG 6

8 F ES EL BG 1 R G 2 N mN I

9 G 3L VG 4U 1U 2G 5S LG 6

10 FE SE LB G1 R G2 Nm NI

11 G3 LV G4 U1 U2 G5 SL G6

12 FE SE LB G1 R G2 Nm NI

15 FLAG

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 May 2001 508 Agere Systems Inc. 21 28-Channel Framer Block Functional Description (continued)

21.21 Performance Monitoring References/Standards

I ANSI T1.231-1997, Digital Hierarchy— Layer 1 In-Service Digital Transmission Performance Monitoring. I ANSI T1-403-1995, Network-to-Customer Installation— DS1 Metallic Interface. I ETS 300 233 Integrated Services Digital Network (ISDN); Access digital section for ISDN primary rate; May 1994. I ETS 300 417-1-1 Transmission and Multiplexing (TM); Generic functional requirement for Synchronous Digital Hierarchy (SDH) equipment; Part 1-1: Generic processes and performance; January 1996. I ITU-T Recommendation G.703, Physical/Electrical Characteristics of Hierarchical Digital Interfaces; 1991. I ITU-T Recommendation G.704, Synchronous Frame Structures used at 1554, 6312, 2048, 8488 and 44736 kbits/s Hierarchical Levels; July 1995. I ITU-T Recommendation G.706, Frame Alignment and Cyclic Redundancy Check (CRC) Procedures Relating to Basic Frame Structures defined in Recommendation G.704; 1991. I ITU-T Recommendation G.732, Characteristics of Primary PCM Multiplex Equipment Operating at 2048 kbits/s; 1993. I ITU-T Recommendation G.733, Characteristics of Primary PCM Multiplex Equipment Operating at 1544 kbits/s; 1993. I ITU-T Recommendation G.775, Loss of Signal (LOS) and Alarm Indication Signal (AIS) Defect Detection and Clearance Criteria; November 1994. I ITU-T Recommendation G.826, Error performance parameters and objectives for international, constant bit rate digital paths at or above the primary rate; August 1996. I ITU-T Recommendation G.963, Access Digital Section for ISDN Primary Rate at 1544 kbits/s; March 1993. I ITU-T Recommendation G.964, V-Interfaces at the Digital Local Exchange (LE) - V5.1 Interface (based on 2048 kbits/s) for the Support of Access Network (AN); June 1994. I ITU-T Recommendation G.965, V-Interfaces at the Digital Local Exchange (LE) - V5.2 Interface (based on 2048 kbits/s) for the Support of Access Network (AN); March 1995. I ITU-T Recommendation O.151, Error Performance Measuring Equipment Operating at the Primary Rate and Above; October, 1992. I ITU-T Recommendation O.152, Error Performance Measuring Equipment for Bit Rates of 64 kbits/s and N X 64 kbits/s; October, 1992. I ITU-T Recommendation O.153, Basic Parameters for the Measurement of Error Performance at Bit Rates Below the Primary Rate; October, 1992. I ITU-T Recommendation O.161, In-Service Code Violation Monitors for Digital Systems; 1993. I ITU-T Recommendation O.162, Equipment to Perform In-Service Monitoring on 2048, 8448, 34 368 and 139 264 kbits/s Signals; October, 1992. I ITU-T Recommendation O.163, Equipment to Perform In-Service Monitoring on 1544 kbits/s Signals; October, 1992. I TTC Standard JT-G704, Synchronous Frame Structures used at 1554, 6312, 2048, 8488 and 44736 kbits/s Hier- archical Levels; July 1995.

21.22 Facility Data Link

21.22.1 Facility Data Link References/Standards

ANSI T1.403-1995— Bit-Oriented Messages (BOM).

21.22.2 Receive Data Link Functional Description

I D bits from the SLC -96 multisuperframe. I Sa bits from time slot 0 in CEPT basic and CRC-4 multiframes. I Data link bits from DDS frames. updates through the interrupt mask registers. I Support clear-on-read status and interrupt bits based on the setting of the input select signal.

21.22.3 SLC -96 Superframe Receive Data Link

I Provides interrupt for stack ready. I Provides host access to stack using processor clock. I Supports loss of frame status. Both basic frame alignment and multiframe alignment must be established before the data can be assumed valid. The SLC -96 Fs bits are stored in the Rx stack as follows. Table 589. Shared Rx Stack Format for SLC -96 Frames

• The value held in the bits left blank should be ignored by the host.

ready interrupt bit is set, the host has approximately 9 ms to read the stack.

21.22.4 DDS Receive Data Link Stack

I Extracts data link bit (bit 6) from time slot 24 and stores into stack. I Provides interrupt for stack ready. I Provides host access to stack using processor clock to provide fast access. I Supports loss of frame status. basic frame alignment must be established for the data link bits to be extracted. The DDS stack is stored in the shared Rx stack as follows.

Table 590. Shared Rx FDL Stack Format for DDS Frames the data link bits collected are invalid. In this case, they will not be made available to the system. When the entire stack has been filled (three superframes) , the host is notified using the Rx stack ready interrupt. After the Rx stack ready interrupt bit is set, the host has approximately 4.5 ms to read the stack.

21.22.5 CEPT; CEPT CRC-4 (100 ms); CEPT CRC-4 (400 ms) Multiframe Sa Bits Receive Stack

I Extracts two multiframes of Sa bits from CEPT links and stores them in internal memory. I Supports loss of frame status. I Provides host access to the stack using the processor clock. I Provides interrupt for stack ready. Sa bits can only be extracted from CEPT links when the proper alignment has been established. alignment determined by the frame aligner block when multiframe frame alignment is established. Table 591. Shared Rx Stack Format for CEPT Frames case, they will not be made available to the system. ready interrupt bit is set, the host has approximately 4 ms to read the stack.

0 D 1D 2D 3D 4D 5D 6D 7D 8D 9 D 1 0 D 1 1 D 1 2 ————

1 D 1D 2D 3D 4D 5D 6D 7D 8D 9 D 1 0 D 1 1 D 1 2 ————

2 D 1D 2D 3D 4D 5D 6D 7D 8D 9 D 1 0 D 1 1 D 1 2 ————

0 SA41 SA43 SA45 SA47 SA49 SA411 SA413 SA415 SA41 SA43 SA45 SA47 SA49 SA411 SA413 SA415

1 SA51 SA53 SA55 SA57 SA59 SA511 SA513 SA515 SA51 SA53 SA55 SA57 SA59 SA511 SA513 SA515

2 SA61 SA63 SA65 SA67 SA69 SA611 SA613 SA615 SA61 SA63 SA65 SA67 SA69 SA611 SA613 SA615

3 SA71 SA73 SA75 SA77 SA79 SA711 SA713 SA715 SA71 SA73 SA75 SA77 SA79 SA711 SA713 SA715

4 SA81 SA83 SA85 SA87 SA89 SA811 SA813 SA815 SA81 SA83 SA85 SA87 SA89 SA811 SA813 SA815

21.22.6 Receive Data Link Stack Idle Modes

21.22.7 Receive Data Link Stack Pointer

time in which the host is prevented from accessing the stack for a particular link. A stack pointer is maintained for each of the links individually. Figure 61. Rx Data Link Block Diagram

amount of overlap will not allow the possibility of a collision. after which the Rx stack ready status bit will be set. access the corresponding stack locations. If that bit is set to 0, the host should poll on that bit until it changes. venting the host from getting the data mixed. The stack ready bit is set to 1, also, when the stack has been filled. The host clears this bit. Figure 62 shows the dynamics of these bits. Figure 62. Stack Available and Stack Ready Bit Formatting switch takes place during the time in which the host is prevented from accessing the stack for a particular link. A stack pointer is maintained for each of the links individually.

21.22.8 Transmit Facility Data Link Functional Description

in the stack with the D bits. This block also provides the capability to transmit BOMs in the data link channel of ESF links. I Support clear-on-read status and interrupt bits based on the setting of the input select signal.

21.22.9 SLC -96 Superframe Transmit Data Link

I Provides storage for D bits and delineator bits for transmission on SLC -96 links. I Provides interrupt for stack empty. I Provides host access to stack using processor clock. I Performs retransmission of stack when update is yet to be performed. 96 Fs frame), which bound the 24 D bits, are also sourced from this block. is determined and indicated by the frame aligner block. The SLC -96 FS bits are stored in the shared Tx stack as shown in Table 592. Table 592. Shared Tx FDL Stack Format for SLC -96 Frames

• The value held in the bits left blank should be ignored by the host.

stack if the D bits need to change. available to be transmitted.

0 at the beginning of the SLC -96 superframe, then the bit will be set to 1, indicating a request for new D bits. the insertion of D bits and the reporting of stack empty to the host.

21.22.10 DDS Transmit Data Link Stack

I Provides three superframes of data link bit storage for transmission on DDS links. I Provides interrupt for stack empty. I Performs retransmission of stack when update has yet to be performed. I Provides host access to stack using processor clock to provide fast access. link bits are stored in the stack. The DDS stack is stored in the shared Tx stack as follows. **Table 593. Shared Tx FDL Stack Format for DDS Frames* The value held in the bits left blank should be ignored by the host.** stack if the data link bits need to change. link bits and the reporting of stack empty to the host. set the Tx stack empty bit to 0. If not, the data link block will transmit the reset state of the stack, which is arbitrary.

21.22.11 Transmit ESF Data Link Bit-Oriented Messages

I Provides capability to transmit bit-oriented messages. link channel transmitted in the odd numbered frames (4 kbits/s). or action, and a 0 (1111_1111_0 in front and 0 behind the 6-bit code). 0 X X X _ X X X 0 _ 1111_1111: (right-most bit being transmitted first). A BOM status bit will indicate when the pattern has been sent 10 times. That status bit will be reset on read. of BOMs bits and the reporting of stack empty to the host.

21.22.12 CEPT, CEPT Multiframe Transmit Data Link Sa bits Stack

I Provides two multiframes of Sa-bit storage for transmission on CEPT links. I Provides interrupt for stack empty. I Performs retransmission of stack when update has yet to be performed. I Provides capability to source Sa bits from blocks other than the data link block. I Provides host access to stack using processor clock to provide fast access. numbered 0 through 15 with the Sa bits located in time slot 0 of the odd numbered frames (NOTFAS frames). The Sa bits are stored in the Tx stack as follows. Table 594. Shared Tx Stack Format for CEPT Frame case, the new Sa bits will be transmitted; otherwise, the previous Sa bits will be retransmitted.

ing a request for new Sa bits. the data link block will transmit the reset state of the stack which is arbitrary.

21.22.13 Transmit Data Link Stack Idle Modes

21.22.14 SLC -96, DDS, or CEPT ESF Frame Alignment

slot 0 or the F bits. Once a link is enabled, the frame sequence always starts at the beginning. Figure 63. Tx Data Link Block Diagra m

21.23 HDLC Functional Description

The Super Mapper framer is capable of inserting and extracting HDLC data to and from multiple logical channels. in these channels. The function of the receive and transmit HDLC sections will be described separately.

21.24 HDLC Operation

adds the CRC and the opening and closing flags, and sends the framed serial bit stream to the transmit framer. on the serial link have the following format. Table 595. HDLC Frame Format cyclic redundancy check (CRC) bits.

21.24.1 Zero-Bit Insertion/Deletion (Bit Stuffing/Destuffing)

is assumed to have been inserted and is deleted (bit destuffing).

21.24.2 Flags

sion, two successive flags will not share the intermediate 0.

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 May 2001 518 Agere Systems Inc. 21 28-Channel Framer Block Functional Description (continued) An opening flag is always generated at the beginning of a frame (indicated by the presence of data in the transmit FIFO and the transmitter enabled). FRM_CFLAGS[1:0] (Table 435) determines which FRM_FCNT[0— 3][4:0] parameter to use. The FRM_FCNT[0— 3][4:0] parameters define the number of idle flags that are sent between HDLC packets. Data is transmitted per the HDLC protocol until a byte is read from the FIFO with Tx HDLC register bits FRM_HTFUNC[1:0] (Table 438) = 01 set. The HDLC block follows this byte with the CRC sequence and a clos- ing flag. The HDLC receiver recognizes the 01111110 pattern as a flag. Two successive flags may or may not share the intermediate 0 bit and are identified as two flags (i.e., both 011111101111110 and 0111111001111110 are recog- nized by the HDLC block). When another flag is identified, it is treated as the closing flag. As mentioned above, a flag sequence in the user data or FCS fields is prevented by zero-bit insertion and deletion.

21.24.3 Aborts

The bit pattern of the abort sequence is 01111111, with 0 transmitted first. A frame can be aborted by writing set- ting Tx HDLC register bits FRM_HTFUNC[1:0] = 01. This causes the last byte written to the transmit FIFO to be fol- lowed by the abort sequence upon transmission. Once a byte is tagged by a write to Tx HDLC register bits FRM_HTFUNC[1:0] = 01, it cannot be cleared by subsequent writes. When receiving a frame, the receiver recognizes the abort sequence whenever it receives a 0 followed by seven consecutive ones. This status results in the abort bit, and possibly the bad byte count bit and/or bad CRC b its, being set in the status of frame status byte which is appended to the receive data queue. The last bytes of user data are assumed to be CRC bits and are placed in the queue in the regular HDLC mode. All subsequent FRM_IDLE or flag bytes are ignored until a valid opening flag is received.

21.24.4 Receive IDLES

In accordance with the HDLC protocol, the HDLC block recognizes 15 or more contiguous received ones as idle. When the HDLC block receives 15 contiguous ones, the receiver FRM_IDLE[7:0] bit, idle is set.

21.24.5 CRC

For a given frame of bits, 16 additional bits that constitute an error-detecting code are added by the transmitter. As called for in the HDLC protocol, the frame check sequence bits are transmitted most significant bit first and are bit stuffed. The cyclic redundancy check (or frame check sequence) is calculated as a function of the transmitted bits by using the ITU-T standard polynomial: x 16 + x 12 + x 5 + 1 At the other end, the receiver performs the same calculation on the received bits after destuffing and compares the results to an expected result. An error occurs if, and only if, there is a mismatch. The transmitter can be instructed to transmit a corrupted CRC by setting the transmit bad CRC bit DXBCRC (DCI-DCR-1-B6). As long as the DXBCRC bit is set, the CRC is corrupted for each frame transmitted by logically flipping the least significant bit of the transmitted CRC. The receiver calculates and verifies the CRC for an incoming frame. The result of the CRC check is reported in bit 7 of the status of frame byte, which is placed in the receive FIFO after the last data byte of the frame. The CRC is stored in the FIFO at all times.

21.24.6 HDLC Mode

FCS bytes of the received HDLC frame are stored into the receive FIFO.

21.24.7 Receive HDLC Transparent Mode

reset command causes the receive to realign to the match character if enabled.

21.24.8 Receive HDLC

can be read by the microprocessor. Figure 64. Receive HDLC Block Diagram

21.24.9 Receive HDLC Features

pattern to be detected before starting. I In HDLC mode, incoming data is correctly formatted and packetized according to the HDLC standard. I In HDLC mode, aborted packets, idle status, and CRC errors are checked for and reported .

grammable FIFO threshold or FIFO overrun. FIFO pointers or interrupts. (or both) frame numbers of any link. I A loopback mode (from transmit HDLC, through HDLC to FIFO) is supported. I Data is ignored if the link/framer is not in basic frame alignment. with a quarter of the channels. Figure 65. Transmit HDLC FIFO Block Diagram

21.24.10 Transmit HDLC FIFO Features

I In transparent mode, simply transform the data to a serial output. I In HDLC mode, correctly format and packetize the outgoing data bits. I In HDLC mode, sends normal packets (close with flag) or abort packets (via command or absence of data). ble FIFO threshold or underrun (FIFO empty in middle of packet). FIFO pointers or interrupts.

both) frame numbers of any link. Table 587, Performance Report Message Format on page 507. Table 596. Performance Report Message Structure ond before that. The FCS is automatically generated by the HDLC. The data normally received from the performance monitor will be initialized to all zeros. transmit HDLC channel count register indicates how many additional bytes can be added to the Tx HDLC FIFO. ister when the TFIFO is below the number of bytes specified in the threshold registers. A Tx HDLC FRM_HTDONE interrupt occurs for each HDLC frame completed. transmitter data is ignored which results in missing data in the frame.

21.25 Framer Phase-Lock Loop (PLL)

E1 from an external system clock (device pin CLKIN_PLL (AD24)). obtain the required line clock frequencies. Figure 66. Framer PLL (MSB), MODE1_PLL (AE24), and MODE0_PLL (AF24) (LSB), as shown in Table 597 below. Table 597. Clock Mode Programming for PLL Mode Device Pins the CHI system clock may be used as the line clock.

000 Reserved (do not use)

21.25.1 Framer Timing Selection

The following diagram shows the framer timing selection. Figure 67. Framer Block Transmit Path Timing Selection I CLKIN_PLL (AD24)— system clock into PLL. I MODE2_PLL (AB21) — PLL input clock frequency select pins. I FRM_MODE[3:0] (Table 422)— framing mode select (per link). I FRM_PLL_BYPAS ( Table 301)— transmit path clock select from PLL or external system interface (global). I FRM_SW_TRN ( Table 301)— switching or transport mode select (global). I tp_rclk— transmit path receive clock. I tp_tclk— transmit path transmit clock. I rs_gtclk— receive system global transmit clock (LINERXDATA[29] device pin D13).

21.26 System Interface

21.26.1 System Interface Introduction

one for the receive direction) are required. This interface can be used, for example, to interface with the TSI device.

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 May 2001 524 Agere Systems Inc. 21 28-Channel Framer Block Functional Description (continued) Parallel Bus System Interface Mode. This interface consists of a 17-bit wide parallel bus operating at 19.44 Mbits/s, 9 bits of which form a byte of data and a data parity bit while the other 8 bits contain the signaling and control information. A clock and frame sync are expected in both the receive and transmit directions. For a 28-link device, only 1/3 of the bytes are populated. In the transmit direction the unpopulated bytes are 3-stated, while in the receive direction they are ignored. Three 28-link devices (Super Mappers) can be connected in parallel to the telecom bus for implementing an STS-3 (STM-1) rate interface. Note: The Tx system is defined as the interface that sends data out of the chip and toward the system (non- SONET) interface. The Rx system receives data from the system. These designations are opposite of the path definitions for the Super Mapper.

21.26.2 System Interface References/Standards

I ITU G.783 characteristics of synchronous digital hierarchy (SDH) equipment functional blocks. I ITU Q.511 exchange interfaces towards other exchanges.

21.26.3 Transmit/Receive System Interface Features

The features supported in the system interface are summarized below: I A global input clock and frame sync (CHI and parallel bus system interface modes). I Byte offset— 2.048 Mbits/s, 0— 31 bytes. I Byte offset— 4.096 Mbits/s, 0— 63 bytes. I Byte offset— 8.192 Mbits/s, 0— 127 bytes. I Bit offset (CHI mode). I 1/2-bit offset (CHI mode). I 1/4-bit offset (CHI CMS mode). I Clock mode select (CMS) (CHI mode). I Associated signaling mode (ASM) (CHI mode). I Double time slot mode, CHIDTS (CHI mode). I Double NOTFAS system time slot, FRM_DNOTFAS (Table 347) (CHI and parallel bus system interface modes). I Sampled clock edge for transmit system frame sync (CHI mode). I Global programmable stuffed time slot position in DS1 mode (CHI mode). I Global programmable stuffed byte in DS1 mode (CHI and parallel bus system interface modes). I Global single time slot loopback address for system or line. I Programmable automatic system AIS (loss of frame alignment). I Programmable automatic system AIS (CEPT CRC-4 multiframe alignment timer expiration). I On-demand transmission of system AIS. I Programmable even/odd parity generation (parallel bus system interface mode).

21.26.4 Double NOTFAS System Time-Slot (FRM_DNOTFAS (Table 347)) Mode

This mode is applicable to the CHI and parallel bus system interface modes. In the default case (FRM_DNOTFAS = 0 ( Table 347)), both the FAS and NOTFAS time slots are transmitted by the transmit system interface and expected by the receive system interface.

to carry NOTFAS data that is repeated twice.

21.26.5 Transparent Mode

first stuffed time slot and inserts it into the framing bit position (193rd bit on the TDM data bus). the CHI (FAS/NOTFAS) into the TS0 of the frame based on the biframe alignment.

21.26.6 Loopbacks

transmitted to the line in place of the looped back time slot. system in place of the looped back time slot. Figure 68. System Loopbacks

21.26.7 System AIS

I CEPT CRC-4 multiframe alignment timer expiration (provisionable using a configuration register bit).

21.26.8 Slip Detection

repeated. In the case of an overflow, an entire frame in skipped.

21.26.9 The Concentration Highway (CHI) Mode

example, to interface with the time slot interchange (TSI) device. Figure 69. CHI Mode of the Transmit System Interface

21.26.10 Nominal CHI Timing

In DS1 frame modes, the CHI frame consists of 24 payload time slots and eight stuffed (unused) time slots. TCHIDATA — output data to system. RCHIDAT A— input data to system. TCHIFS — transmit CHI frame sync. RCHIFS — receive CHI frame sync.

• The position of the stuffed time is controlled by register bit FRM_STUFFL (Table 347). FRM_STUFF = 1 is shown.

Figure 70. Nominal Concentration Highway Interface Timing

8.192 Mbits/s CHI:

4.096 Mbits/s CHI:

2.048 Mbits/s CHI:

24 VALID TIME-SLOTS FRAME 2TCHIDATA

32 VALID TIME-SLOTS

24 VALID TIME-SLOTS

7 STUFFED

1 STUFFED SLOT

21.26.11 CHI Timing with CHI Double Time-Slot Timing (CHIDTS) Mode Enabled

Figure 71. CHIDTS Mode Concentration Highway Interface Timing

8.192 Mbits/s CHI

4.096 Mbits/s CHI

21.26.12 CHI Timing with Associated Signaling Mode Enabled

consist of 32 contiguous 16-bit time slots when the 4.096 MHz CHI data rate mode is selected. In CEPT modes, each frame consists of 32 time slots. Each time slot consists of two octets. Figure 72. Associated Signaling Mode Concentration Highway Interface Timing

21.26.13 ASM 2-Byte Time-Slot Format

Table 598 illustrates the ASM time slot format for valid channels. Table 598. Associated Signaling Mode CHI 2-Byte Time-Slot Format for DS1 Frames face 4.096 Mbits/s bitstream. The rate adoption results in the need for stuffed time slots on the system interface. grammable idle code in register FRM_STUFF[] (default = 7F (hex)).

Table 599. Associated Signaling Mode CHI 2-Byte Time-Slot Format for Stuffed Channels

• The default stuff byte is shown.

21.26.14 CEPT: Time-Slot 16 Signaling ASM 2-Byte Time-Slot Format

Table 600 illustrates the ASM time slot format for valid CEPT E1 time slots. Table 600. Associated Signaling Mode CHI 2-Byte Time-Slot format for CEPT

• In the CEPT formats, these bits are undefined.

21.26.15 CHI Offset Programming

the first bit of time slot 0 is transmitted; CER is defined as the clock edge on which bit 0 of time slot 0 is latched. depend upon the values of the parameters described below. (Table 418). The byte (time slot) offsets are assumed to be zero in the following examples. Table 601. Programming Values for FRM_TOFF[2:0] and FRM_ROFF[2:0] when FRM_CMS = 0 Table 602. Programming Values for FRM_TOFF[2:0] when FRM_CMS = 1 Table 603. Programming Values for FRM_ROFF[2:0] when FRM_CMS = 1

Figure 74. CHI TCHIDATA and RCHIDATA to CHICK Relationship with FRM_CMS = 1 (CEX = 3 and CER = 6,

21.26.16 The Parallel Bus System Interface Mode

Figure 75. Parallel Bus System Interface Mode of the Transmit System Interface

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 533Agere Systems Inc. 21 28-Channel Framer Block Functional Description (continued) At 19.44 MHz, the parallel bus system interface has 2430 clocks per 8 ms frame. To transfer 84 DS1s or 63 E1s requires only 2016 clocks. The difference is made up by inserting stuffs onto the bus every so often. Since multiple devices (three) will drive the bus, the stuff positions are also used to greatly simplify the timing when switching from one device to another. Both DS1 and E1 use the same general method to drive the bus which is: I Send some stuffs, then device 0 sends TS0 for link 1 – n, then I Send some stuffs, then device 1 sends TS0 for link 1 – n, then I Send some stuffs, then device 2 sends TS0 for link 1 – n, then I Send some stuffs, then device 0 sends TS1 for link 1 – n, then I Etc.

21.26.17 Distributed Stuffing: DS1

For DS1, the parallel bus system interface time slot arrangement is as follows: Six stuff TSs | device 0, link 0— 27 | six stuff TSs | device 1, link 0— 27 | five* stuff TSs | device 2, link 0— 2 |, etc. Where * means in TSs 1, 5, 9, 13, 17, 21 six stuff time slots are inserted instead of five. Hence: total time slots = (6 + 28 + 6 + 28 + 5 + 28) * 24 TSs + 6 extra stuff TSs = 2430 TSs.

Table 604 shows the distribution of the time slots and stuffing in the STM-1 frame for the DS1 mode. Table 604. Parallel System Bus Interface Time-Slot Arrangement for DS1

21.26.18 Distributed Stuffing: E1

Where * means in TS 0 three stuff time slots are inserted instead of five. Table 605 shows the distribution of the time slots and stuffing in the STM-1 frame for the E1 mode. Table 605. Parallel System Bus Interface Time-Slot Arrangement for E1 Table 606. PSB System I/O Definition internal framer PLL is not used.

21.26.19 Drive to 3-State and 3-State to Drive Timing

Figure 76. Parallel Bus System Interface Turnaround Timing PSB receive and transmit interface and clock timing parameter specifications.

21.27 Serial Multiplex Interface

Mode 1 uses six primary signals. The six primary signals are composed of three transmit and three receive signals. provide clock, data, and control information. by the receive side of the Super Mapper after traversing the switch side of the system.

21.27.1 Signals (6-Pin Mode)

Figure 77. Signals (6-Pin Mode) I LINERXCLK29 (B13)— Output of the switch, which is the LINETXCLK29, delayed. first bit (start bit) of the LINERXSYNC29 is sent out. I LINERXSYNC29 (A13) — The control data, otherwise known as the serial ID (SID), is generated by the switch. I LINETXCLK29 (R24)— Clock signal generated by the Super Mapper. the first bit (start bit) of the LINETXSYNC29 is sent out. allows the Super Mapper to receive links and data independent from those transmitted by the Super Mapper.

21.27.2 Signals (8-Pin Mode)

Figure 78. Signals (8-Pin Mode)

I LINERXCLK29 (B13)— Output of the switch, which is the LINETXCLK29, delayed. first bit (start bit) of the LINE_RXSYNC29 is sent out. I LINERXSYNC29 (A13) — The control data, otherwise known as the serial ID (SID), is generated by the switch. I LINETXCLK29 (R24)— Clock signal generated by the Super Mapper. the first bit (start bit) of the LINETXSYNC29 is sent out. I RXDATAEN (AB19) — Clock signal generated by the Super Mapper. I TXDAT AEN (W22)— The control data, otherwise known as the serial ID (SID), is generated by the Super Mapper.

21.27.3 Timing Diagrams

the same time the START bit of the LINETXSYNC29 (R26) signal is driven. Figure 79. Network Serial Multiplexed Interface (Single Octet) Table 607. Serial ID when octets are separated, the LINETXSYNC29 line must be driven with a 1. 0 = Start an octet. Bits 1 to 7 follow. 1 = Do not start an octet. Next bit is another bit 0. — 7 Reserved. Must write to 0.

Figure 80. Network Serial Multiplexed Interface (Multiple Octets)

21.27.4 Time-Slot Sequencing

I Link numbers— 28 link numbers, numbered 1 to 28 in T1 mode, and 1 to 21 for E1 mode. cause the link numbers for T1 to be numbered 0— 27 and for E1, 0— 20. I In T1 mode, each of the 28 links has 24 time slots and should be numbered 1 to 24. I In E1 mode, each of the 21 links has 32 time slots and should be numbered 0 to 31. T1 and time slot 0 in E1 mode). switch to keep track of which time slot it receives. Note: The order of the links sent out is in relation to the order in which the Super Mapper framer receives the links. link 5 before link 10 completes its frame. and E1, using an NSMI bus clock of 51.84 MHz (19.3 ns clock period). Max time = (1 link time slot interval) + (27 links * 8 bits * NSMI clk period) + (1 link bit time). Min time = (1 link time slot interval) – (27 links * 8 bits * NSMI clk period). Max time = (1 link time slot interval) + (20 links * 8 bits * NSMI clk period). Min time = (1 link time slot interval) – (20 links * 8 bits * NSMI clk period).

21.27.5 Timing Between Transmit and Receive

doesn’t matter how long, but it must be constant.

8-Pin Mode. As in the 6-pin mode, the Super Mapper sends data and link information through the transmit signals. only requirement is that it receives data at a constant time interval.

21.28 Superframer Host Interface

21.28.1 Superframer Register Addressing

Table 608 summarizes the current number of global and per link/channel registers for each block. Table 608. Current Number of Global and per Link/Channel Registers for Each Block and a per link/per channel select. a block using bits B7— B4, and selecting a register using bits B3— B0.

21.29 Superframer Register Addressing

Table 609. Framer Addressing Map for the Global and Per Link/Channel Registers of the Superframer

21.29.1 Per Link Register Sections in Table 609

SIG = Signaling (see Section 12.9.1 Signaling Per Link Registers on page 267). PM = Performance Monitor (see Section 12.3 Performance Monitor Global Registers on page 247). SYS = System Interface (see Section 12.13 System Interface, Arbiter, and Frame Formatter Mapping on page 292). AR = Arbiter (Framer) (see Section 12.2 Arbiter (Framer) Global Registers on page 245). FF = Frame Formatter (Transmit Framer) (see Section 12.16 Frame Formatter Per Link Registers on page 300). the line encoder and TXP = 1 for the line decoder. page 304); RXP = 0 for the receive HDLC and TXP = 1 for the transmit HDLC.

0 Framer Global Registers

1000 R e s e r v e d

1 Others Reserved

0 Links 1— 28 (00001— 11100) Framer Functional Register Addresses

1 HDLC Channels 1 — 64 (000000— 111111) RXP=0/

22 Cross Connect (XC) Block Functional Description

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 May 2001 544 Agere Systems Inc.

22 Cross Connect (XC) Block Functional Description (continued)

22.1 Cross Connect Introduction

The cross connect block is a highly configurable crosspoint switch for internal DS1/E1/DS2/DS3 signal connections in the Super Mapper. The cross connect allows flexible configuration of the Super Mapper’s internal blocks to sup- port a variety of applications. The internal 28-channel framer, VT mapper, SPE mapper, M13, digital jitter attenua- tor, and test-pattern generator/monitor blocks or external device I/O pins can be interconnected with the independent, nonblocking signal routing of the cross connect block.

22.2 Cross Connect Features

I Configurable crosspoint interconnect for up to 28 DS1 signals or 21 E1 signals to/from the framer (or external pins), and the same number of signal channels to/from the M13 and VT mapper. Also supports up to seven DS2 signals to/from the external pins or M12 MUXes, connecting to the M13 MUX M23 block. Also connects one DS3 signal to/from the external NSMI interface to the SPE, M13, or TPG blocks. Any mix of DS1, E1, DS2, or DS3 sig- nals may be interconnected. I Any transmitter (signal source) may be connected to any receiver (signal destination) in the DS1/E1 cross con- nect. Multicast or broadcast operation (one port to many) is supported. I Jitter attenuation may also be inserted in-line on any DS1/E1 channel. (Note: Cascading of jitter attenuators is not allowed.) I Standard network loopback or straight away facility testing is supported for DS1/E1 and DS3. Any source or transmitter may be replaced by a test-pattern generator capable of injecting idle, standards based pseudoran- dom bit sequence test patterns, or AIS (blue) alarm. Any sink or receiver may be replaced by a test-pattern mon- itor, which can detect/count bit errors in a pseudorandom test sequence, or loss of frame, or loss of sync. I Loopbacks may be configured to sectionalize a circuit for identifying faults or misconfiguration during out of ser- vice maintenance. I Fast alarm channels are supported for VT mapper or M13 to framer interconnects for alarm indication signal (AIS or blue alarm) and VT mapper only for remote alarm indicator (RAI or yellow alarm). This feature reduces the propagation delay of the alarms by eliminating multiple integration of alarm conditions. I Supports M12, M23 or C-bit parity, M13, or VT group modes of operation. I Supports framer-only, transport (framer LIU, M13, and VT mapper), and switching (CHI and PSB) modes of oper- ation.

22.3 Cross Connect Block Diagram

The following diagram illustrates the high-level interface between the XC block and other functional blocks. Figure 81. Cross Connect Block Diagram

vided for selecting the path overhead access channel connection. the configuration registers will interconnect the source group of signals to the destination group of signals.

22.3.1 Framer to Cross Connect Overview

as shown in Figure 82. A brief explanation follows for establishing path and interconnect definition. Figure 82. Framer and Cross Connect FRM_TP_T, FRM_TP_R — Transmit and receive interfaces for the framer transmit path (TP). FRM_RP_T, FRM_RP_R — Transmit and receive interfaces for the framer receive path (RP). FRM_RS — Framer receive system interface (RS). FRM_TS — Framer transmit system interface (TS).

connected from the transmit system interface to the external I/O pins (bottom right side of Figure 82). frame formatter to the external I/O pins (bottom right side of Figure 82) on to the LIUs. be cross connected to the external I/O of the multifunction system interface.

22.3.2 External I/O to Cross Connect Overview

ing the functionality of the Super Mapper from the applications viewpoint. data/clock/sync), DS2 interfaces, channelized (DS0), and multiplexed system interfaces (CHI, PSB, or NSMI). Table 610. Multifunction System Interface Programmable I/O

Table 611. DS3 Interface Programmable I/O The SONET path overhead access channel (POAC) is configurable for access to the SPE mapper or TMUX. Table 612. Transmit and Receive POAC Programmable I/O

22.4 Cross Connect Connectivity Overview

Table 613 below describes the connectivity within the cross connect block. Table 613. Connectivity Within the Cross Connect Block

1. Framer, M13, and VT mapper have limited self-loopback capability (no reordering).
2. RAI paths and frame sync paths supported.
3. Framer also has limited test-pattern capability.
4. Auto-AIS paths (fast AIS) supported.PTRADJ paths supported.
5. Jitter attenuator reordering or cascading (chaining) not expected.
6. Reference clock sources from DJA used by TPG.

% = Primary (expected) modes of operation. SELF = TPG->TPM self-test mode. J = Jitter-attenuated signal mode. & = Represents loopback path.

22.5 DS1/E1 Cross Connect

Figure 83. DS1 Cross Connect Interface

22.5.1 DS1/E1 Connectivity Matrix

Block on page 548 excluding the last row and column. Table 614. DS1/E1 Signal Connectivity Matrix in some cases, RAI or PTRADJ signals.

22.5.2 DS1/E1 Register Definition

used (channel numbers that are even multiples of four are typically disallowed).

001 EXT (External I/O) 101 DJA (Jitter Attenuator)

Table 615. Special XC_PDATA Source IDs for Source Block = 0 Table 616. Special XC_SYNC Source IDs for Source Block = 0 Table 617. Special XC_ALCO Source IDs for Source Block = 0 the independent M12 MUX mode).

1 TEST: DS1 Idle 9 Reserved 17 M23_DMX_DS2_1 25 SPE NSMI*

2 TEST: E1 10 Reserved 18 M23_DMX_DS2_2 26 FRM NSMI*

3 Reserved 11 Reserved 19 M23_DMX_DS2_3 27 Reserved

4 TEST: DS2 12 Reserved 20 M23_DMX_DS2_4 28 Reserved

5 Reserved 13 Reserved 21 M23_DMX_DS2_5 29 Reserved

6 Reserved 14 Reserved 22 M23_DMX_DS2_6 30 Reserved

7 Reserved 15 Reserved 23 M23_DMX_DS2_7 31 Reserved

1 TEST: DS1 Idle 9 M12_DS2_OUT_1 17 M23_DMX_DS2_1 25 SPE NSMI*

2 TEST: E1 10 M12_DS2_OUT_2 18 M23_DMX_DS2_2 26 FRM NSMI*

3 Reserved 11 M12_DS2_OUT_3 19 M23_DMX_DS2_3 27 Reserved

4 TEST: DS2 12 M12_DS2_OUT_4 20 M23_DMX_DS2_4 28 Reserved

5 Reserved 13 M12_DS2_OUT_5 21 M23_DMX_DS2_5 29 Reserved

6 Reserved 14 M12_DS2_OUT_6 22 M23_DMX_DS2_6 30 Reserved

7 Reserved 15 M12_DS2_OUT_7 23 M23_DMX_DS2_7 31 Reserved

1 Reserved 9 Reserved 17 M23_DS2CLKO_1 25 Reserved

2 Reserved 10 Reserved 18 M23_DS2CLKO_2 26 Reserved

3 Reserved 11 Reserved 19 M23_DS2CLKO_3 27 Reserved

4 Reserved 12 Reserved 20 M23_DS2CLKO_4 28 Reserved

5 Reserved 13 Reserved 21 M23_DS2CLKO_5 29 Reserved

6 Reserved 14 Reserved 22 M23_DS2CLKO_6 30 Reserved

7 Reserved 15 Reserved 23 M23_DS2CLKO_7 31 Reserved

22.6 Notes on the DS1 Cross Connect

22.6.1 DS1/E1 TPG

CHANNEL_ID field is set to zero for standard DS1 test-data patterns and one for DS1 (framed) idle data. CHANNEL_ID field is set to two for standard E1 test-data patterns.

22.6.2 M13 DS1/E1 Interface

into the M13 crosspoint configuration registers. nels between the M13 and the framer. the M12 stuff time is determined externally. Figure 84. DS1E1 External I/O to M13

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 553Agere Systems Inc.

22.6.3 VT Mapper DS1/E1 Interface

The user configures the VT mapper DS1/E1 connections from the crosspoint by loading the appropriate SOURCE_IDs into the VT mapper crosspoint configuration registers. The user may connect any valid DS1 or E1 signal bundle from the M13 MUX, framer, external I/O, TPG, or DJA blocks to any VT mapper input. Each of the 28 possible DS1 or 21 possible E1 inputs may be assigned a XC1 source ID for the corresponding XC_VDA TA[1— 28][7:0] (Table 454) byte in the XC_VT_SRC[1— 14] configuration registers. The user must ensure the consistency of the designation of DS1(J1) vs. E1 channels and block interface parameters. The cross connect block automatically supports independent signal paths for remote alarm indication (RAI), alarm indicator signal (AIS), frame sync (byte synchronous mode only), and signaling (out of band signaling) on channels between the VT mapper and the framer.

22.6.4 Digital Jitter Attenuator (DJA) Interface

The DJA block consists of up to 28 DS1 jitter attenuator channels or up to 21 E1 jitter attenuation channels. The DS1 or E1 channels are cross connected from the VT mapper, M13 MUX, framer, external I/O interface, or test interface and the DJA outputs are returned to the crosspoint switch for cross connect to the destination. Test sig- nals from the TPG will not require jitter attenuation, although this capability exits. The crosspoint cannot chain jitter attenuators together serially (that is, DJA to DJA paths are not supported). The user configures the DJA DS1(E1) outputs from the crosspoint by loading the appropriate SOURCE_IDs into the DJA crosspoint configuration registers. The user may connect any valid DS1 or E1 signal bundle from the external I/O pin, M13, VT mapper, framer, or TPG blocks to any DJA input. Each of the 28 possible DS1 (J1) or 21 possible E1 inputs may be assigned a XC1 source ID for the corresponding XC_JDATA[1— 28][7:0] (Table 455) byte in the XC_DJA_SRC[1— 14] configuration registers. The user must ensure the consistency of the designation of DS1(J1) vs. E1 channels. The cross connect is provided with DS1 and E1 reference clocks from the DJA block. These 1X clocks are derived from external AIS clock inputs, and are made available to the test-pattern generator block for use as the test- pattern source clocks. The DJA block is responsible for the correct assignment of reference clocks to jitter attenua- tion channels. When a channel from the VT mapper is cross connected to a DJA channel, the bundled signals include receive pointer adjustment information. For all other sources, the pointer adjustment signal is not required and is disabled. Framer Interface The framer block can pass through a total bandwidth of one DS3. This may be formed from 28 DS1s or 21 E1s or any mix where a group of four adjacent DS1 channels may be substituted by three E1s. The DS1 or E1 channels can be cross connected to the M13 MUX, VT m apper, external I/O interface, or test interface. The framer block pro- vides extensive per link loopback capability based on DS1/E1 standards. As previously stated, special channels for AIS, RAI, frame sync, and signaling are enabled when the framer is cross connected to the VT mapper. The framer presents six interfaces to the cross connect as shown in Figure 82 on page546. Although somewhat flexible, most applications will cross connect the framer interfaces FRM_TP_T (XC1 — source ID = 010) and FRM_RP_R (XC1— destination = XC_RP_RDA TA[1— 28][7:0] (Table 452)) to the M13 MUX or VT mapper. If desired, the digital jitter attenuators may be inserted in this connec- tion.

interface is desired, the sync line is used as the negative-rail data. XC_FRS_SRC[1 — 28][7:0], respectively. Figure 85. Framer Line Interface Cross Connect

22.6.5 Framer System Interface

interface TS/RS usage and any other use. XC_CHI_MODE[1 — 7][1:0] (Table 450) are used to assist with the configuration of the system interface.

22.6.6 Framer System Interface— PSB

XC_PINS_SRC[1 — 14] (Table 465) XC1 crosspoint configuration registers. Figure 86. Framer System Interface— Parallel System Bus (PSB)

22.6.7 Framer System Interface— CHI

connecting of transmit system data outputs to the LINETXSYNC[1— 29] pins. The concentration highway interface can operate at data rates of 2.048 Mbits/s, 4.096 Mbits/s, and 8.192 Mbits/s. 7 combined CHIs or a mix as determined by the specific needs of the application.

trol group see Table 618 on page 556. Table 618. Configuration of the Control Group LINETXSYNC[16]. The LINETXSYNC[15] output can be used for T1/E1 line sync output. Figure 87. Framer System Interface— Concentration Highway Interface (CHI) 00 All four links within the group are normal outputs at 2 Mbits/s or 4 Mbits/s.

01 Links 4i – 3 and 4i – 2 are normal outputs; links 4i – 1 and 4i are combined into a

single output on 4i; output 4i – 1 is used as T1/E1 line output, where i = 1 to 7.

10 Links 4i – 1 and 4i are combined into a single output on 4i; links 4i – 3 and 4i – 2 are

11 All four links are combined into a single output on 4i; the other three outputs are

22.6.8 Framer System Interface— NSMI

section and is shown in Figure 96 on page568.

22.7 DS2 Connectivity

Figure 88. DS2 Cross Connect Interface programmed to the default values.

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 May 2001 558 Agere Systems Inc. The cross connect block supports DS2 mapping to/from the M13 MUX, TPG/TPM, and external pin I/O. Here, the available sources are the M12 MUX or the M23 deMUX, a set of external I/O pins, or the test-pattern generator. The DS2 crosspoint’s connectivity is determined by a smaller set of source 2 identifiers (SOURCE2_IDs), as defined in the following table (covering registers XC2_M23_SRC[1— 7] (Table 460) and XC2_TPM_SRC (Table 461)): The SOURCE2_BLOCK is defined as follows: The CHANNEL2_ID typically ranges from 1 to 7. For test data from the TPG, the SOURCE2_BLOCK is set to 0 and the CHANNEL2_ID value four represents the DS2 test pattern. For DS2 signals routed from external pins to the input of M23 MUX or TPM, the CHANNEL2_ID can range from 1 to 29. The above DS2 source ID definition covers registers beginning with XC2. Note: For certain DS2 signals routed to external pins, the XC1 cross connect is used and a special SOURCE_ID (block 0) is programmed: The SOURCE2_ID is defined as in Table 615 to Table 617. The user must ensure consistency between the use of M13 vs. M12/M23 channels and external I/O channels.

22.7.1 M13 DS2 Interface (DS2 Cross Connect)

The DS2 full split access results in four sets of DS2 signals that can be routed through cross connect, essentially providing access to the path between the seven M12 MUX/deMUXs and the M23 MUX/deMUX.

22.7.2 M12 MUX (Transmit Path)

The M12 MUX assembles three E1s or four DS1s into a DS2. The DS2 output data is clocked out by an external DS2 rate clock as shown in Figure 89. The DS2 rate clock is routed from an external pin, LINETXSYNC[14— 8], through the cross connect to the M12, by programming the XC2_DS2M12CLK[1— 7][7:0] (Table 459) bytes in the DS2 cross connect registers XC2_M12_SRC[1 — 7] (Table 459) with a source2 ID = 11 (external I/O) and a channel select of 1 to 7. The channel select value of 1 to 7 selects the clock from pins LINETXSYNC[8] to LINETXSYNC[14], respectively. The DS2 data is routed through the DS1 cross connect to the external pins, LINETXSYNC[7— 1], by programming the XC_SYNC[1— 29] (Table 465) bytes in the XC_PINS_SRC[1— 14] DS1 cross connect registers with a source ID = 000 and a channel select as defined in Table 616. A channel select value of 9 to 15 selects the external pin LINETXSYNC[1] to LINETXSYNC[7], respectively. B i t 7 6 5 43210 SOURCE2_ID 0 SOURCE2_BLOCK[1:0] CHANNEL2_ID[4:0] Index Block2 Identifier SOURCE2_ID 0 0 0 CHANNEL2_ID[4:0]

Figure 89. M12 MUX DS2 Output Cross Connect ID can be set up based on the following tables. Table 619. XC_PDATA Source IDs for LINETXDATA Routing with Source Block = 111 Table 620. XC_PDATA Source IDs for LINETXCLK Routing with Source Block = 111

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 May 2001 560 Agere Systems Inc. The register XC2_DS2M12CLK SOURCE ID is defined as: The register can be programmed to route DS2 clocks from various sources based on the following table:

22.7.3 M12 DeMUX (Receive Path)

The M12 deMUX disassembles a DS2 into three E1s or four DS1s. The routing of DS2 data and clocks to M12 DeMUX is controlled by the register XC2_M21_SRC[1:7] which are defined as: The routings are based on the following table. When bits 7— 5 of XC2_M21_SRC set to 100, the user also needs to set bits 7— 5 of the related register XC_ALCO_SOURCE_ID(I) to 001 as well as the appropriate channel value to ensure the demand clocking opera- tion. The DS2 input has six connection options as shown in Figure 90 on page561. The external I/O inputs for DS2 clock and data are cross connected by programming bytes, XC2_M21[1— 7][7:0] (Table 459) in configuration registers XC2_M12_SRC[1— 7], with a source2 ID = 11 and a channel select of 1 to 7. The channel select value of 1 to 7 selects DS2 data from device pins LINETXSYNC[15] to LINETXSYNC[21] and selects DS2 clock from LINETXSYNC[22] to LINETXSYNC[28], respectively. A DS2 signal loopback may be performed for the M12 MUX/deMUX by programming the XC2_M21[1— 7][7:0] (Table 459) byte in the XC2_M12_SRC[1— 7] registers with a source2 ID = 01 and a channel select of 1 to 7. Cross connecting among the seven channels is supported. For example, the output of M12 MUX 1 may be connected to the input of M12 deMUX 5. The TPG may be cross connected to the M12 deMUX DS2 inputs by programming the XC2_M21[1— 7][7:0] byte in the XC2_M12_SRC[1 — 7] registers with a source2 ID = 00 and a channel ID = 4. The connection is not useful because the DS2 pattern generator is limited to sending unframed pseudorandom data patterns that cannot be demultiplexed into DS1s or E1s. B i t 7 6 5 43210 SOURCE2_ID 0 SRC2_BLK[2:0] CHANNEL2_ID[4:0] SRC2_BLK CHANNEL2_ID Function 00 1 to 7 DS2 Clocks Sourced from LINETXSYNC[8:14] 01 1 to 29 DS2 Clocks Sourced from LINETXCLK[1:29] 10 1 to 29 DS2 Clocks Sourced from LINERXCLK[1:29]

11 Don ’t care DS2 Clocks Sourced from PIN_DS2_AISCLK

SOURCE2_ID SRC2_BLK[2:0] CHANNEL2_ID[4:0] SRC2_BLK CHANNEL2_ID Function 000 4 DS2DATA/CLK from TPG 001 1 to 7 DS2DATA/CLK from M12 MUX 010 1 to 7 DS2DATA/CLK from M23 DEMUX 011 1 to 7 DS2DAT A/CLK from Pin LINETXSYNC[21:15 ]/LINETXSYNC[28:22] 100 1 to 29 DS2DA TA/CLK from Pin LINERXDA TA [29:1]/PIN_DS2_AISCLK 101 1 to 29 DS2DATA/CLK from Pin LINERXDA TA/CLK[29:1] Others Don ’t care Not Valid

Figure 90. M12 DeMUX Input DS2 Cross Connect

22.7.4 M23 DeMUX (Receive Path)

out to external pins and/or the test-pattern monitor as shown in Figure 91. ID = 000 (binary) and a channel ID = 20 (decimal) XC_PDA TA19 = 00010100 (binary).

• = Channel ID from Table 615.

Figure 91. M23 DeMUX DS2 Output Cross Connect

22.7.5 M23 MUX (Transmit Path)

second mode determines the stuff times from the external application. XC2_M23_SRC3, with a source ID = 11 and a channel select = 6. XC2_MDS2M23DATA3 = 01100110 (binary). 17 and 23 (decimal) to select DS2 DeMUX 1 to 7, respectively.

a source ID = 000 and a channel select = 19. This will output a DS2 clock from M23 DeMUX 3 to LINERXCLK[6].

• Channel ID from Table 617.

Figure 92. M23 MUX DS2 Input Cross Connect

22.8 DS3 Connectivity

Figure 93. DS3 Cross Connect Table 621. DS3 Connectivity Note: DS3 external I/O is supported by dedicated pins. NSMI uses the multifunction system interface. % = Primary (expected) modes of operation. & = represents loopback path.

tifunction system interface to the SPE mapper or M13. (TPG/TPM), the DS3 basic connect, and the NSMI.

22.8.1 DS3 TPG/TPM Cross Connect

Figure 94. For DS3 test signals, the TPG does not supply the source clock. Instead, a source clock and a clock

• DS3 unframed single rail (unipolar) non-return-to-zero (NRZ) data.

Figure 94. DS3 Test-Pattern Cross Connect 00 TPM receives DS3 from external pin*. 01 TPG and TPM are connected to M13 through NSMI interface. 10 TPM receives DS3 from SPE.

22.8.2 DS3 Basic Cross Connect

Figure 95. DS3 Basic Cross Connect 00 M13 inputs/outputs DS3 through external I/O pins. 01 M13 and SPE are interconnected.

10 SPE i nputs/outputs DS3 through external pins and M13 is used as a monitor for the trans-

11 SPE i nputs/outputs DS3 through external pins and M13 is used as a monitor for the

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 567Agere Systems Inc.

22.8.3 NSMI Cross Connect

The Super Mapper cross connect supports interconnection of the network serial multiplexed interface (NSMI) to the SPE mapper, M13 MUX/deMUX, or the NSMI system interface of the framer block as shown in Figure 96. The cross connects are controlled by programming the XC_PDATA[29] (Table 451) and XC_SYNC[29] (Table 465) bytes in registers XC_PIND_SRC15 and XC_PINS_SRC15. As previously discussed, the TPG/TPM can send/receive data using the NSMI interface of the M13. Only the framer block can disassemble the NSMI payload into DS0 channels and signaling. Connectivity to the M13 and SPE mapper is for transport in a proprietary format only. The NSMI crosspoint’s connectivity to the multifunction interface external I/O is determined by a set of XC1 source identifiers (SOURCE_IDs). The NSMI connectivity is defined as a special with the source ID = 000 for XC_PDATA[29] and XC_SYNC[29] bytes in registers XC_PIND_SRC15 and XC_PINS_SRC15, with a CHANNEL_ID restricted to 5, 24, 25, or 26 (see Table 615 and 616): The channel ID is defined as: B i t 76543210 SOURCE_ID 0 0 0 CHANNEL_ID[4:0] CHANNEL_ID Binary (Decimal) Connectivity 00101 (5) DS3 Test Pattern 11000 (24) M13 — NSMI 11001 (25) SPE — NSMI 11010 (26) Framers — NSMI

Figure 96. NSMI Interface Cross Connect

22.9 Transmit and Receive Path Overhead Access Channel I/O Configuration

mapper to the external I/O pins as shown in Figure 97.

Figure 97. TPOAC and RPOAC Cross Connect

23 Digital Jitter Attenuation Controller Functional Description

23 Digital Jitter Attenuation Controller Functional Description (continued)

23.1 Introduction

This section describes the functions of the digital jitter attenuator (DJA) controller used in the Super Mapper device. a wide range to accommodate a number of different system constraints.

23.2 Features

I The DJA block accepts/delivers DS1/E1 clock, data, and AIS indications from/to the cross connect block. order mode is provisionable via registers. Figure 98 shows the DJA block with I/O connections to other blocks within the Super Mapper device. Figure 98. DJA Block with I/O Connections to Other Blocks in the Device

23.3 Functional Block Diagram of the DJA Block

device, are shown in the Figure 99. insert indication as well as the DS1 and E1 AIS clocks for use by other blocks within the device. Figure 99. Basic Functional Flow of the DJA Block

23.4 Digital Jitter Attenuation Controller Operation

(Table 478) is used to determine if the block is operating in the DS1 or E1 mode (1 = DS1, 0 = E1). Table 3, High-speed I/O Pin Descriptions on page15 under the M13 MUX/DEMUX block receive path section). nect, and transmits the data signal (DJA_DATA) as a continuous logic 1. the AIS clock generation block will still generate the correct DS1_AISCLK or E1_AISCLK signals. Underflow Masks (R/W) on page 332.

23.4.1 PLL Bandwidth and Damping Factor Control

values in decimal and hexadecimal terms to achieve these parameter values are listed in Table 622. Table 622. PLL Bandwidth Control Parameters

23.4.2 PLL Order Control

operates in the first-order mode is programmable between 0 ms and 1 second. DJA_E1PTRADJCNT and DJA_DS1PTRADJCNT values are listed in Table 623. Table 623. First-Order Mode Duration Control

23.4.3 DS1/E1 Clock Edge Control

DJA_CLK_CTL1 — DJA_CLK_CTL4, Reference Clock Rate and Edge Transitions (R/W) on page 334.

24 Test-Pattern Generation/Detection Functional Description

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 575Agere Systems Inc.

24 Test-Pattern Generation/Detection Functional Description (continued)

24.1 Test-Pattern Generator Introduction

The TPG block is a configurable set of test-pattern generators and monitors for the Super Mapper. For mainte- nance and troubleshooting operations, TPG feeds one or more T1/E1/DS2 test signals (via data, clock, and FS sig- nal paths) to the crosspoint switch (XC block). The XC block can redistribute or broadcast these signals to any valid channel in the framer, external I/O, M13 mapper, DJA, or VT mapper blocks. Similarly, any channel arriving at the XC may be routed to the test monitor. The TPG can also generate DS3 test signals for use via the M13 and SPE blocks. Single bit-errors can be detected and counted at each monitor. The test-pattern generator and associated monitors receive configuration and setup information from the micropro- cessor control interface. Once the rate and data format are chosen, the test generator outputs are fed to the cross- point (XC). The crosspoint can map the test signals to any valid DS1/E1/DS2 channel in the device, or to a special set of test monitor channels in the TPG block (for loopback testing of the test generator/monitor pair). The monitor waits for the expected test pattern and (after a brief synchronization operation) continually checks the data stream for bit errors. Optionally, a single data-bit or framing-bit error may be generated via a global SMPR_BER_INSRT (Table 65, SMPR_GTR, Global Trigger Register (RW) on page66) control signal, in order to confirm the correct detectability of such an error as it traverses the crosspoint and other system elements. Simultaneous testing of DS1, E1, DS2, and DS3 signals is supported (one test channel at each rate plus one idle channel at DS1). The DL (DS1-ESF data link) and E1 Sa (spare) bit fields are read/writable under software control, allowing for additional system testing control. Test monitors can automatically detect/count data-bit errors and detect framing-bit or CRC errors in a pseudoran- dom test sequence, or loss of frame or loss of sync. The TPG can provide an interrupt to the control system, or it can be operated in a polled mode.

24.2 Features

I Configurable test-pattern generator: DS1, E1, DS2, and DS3 formats. I Pseudorandom bit sequence (PRBS, also known as pseudonoise or PN sequences) based on maximal-length feedback shift register sequences; PN codes selectable from the following options: QRSS, PRBS15, PRBS20, PRBS23, ALT_01, ALL_ONES, USER pattern (16 bits, repeating). I The DS1 and E1 test patterns can be transmitted either unframed or as the payload of a framed signal as defined in ITU-T Recommendation O.150 (see TPG_FRAMEx signals (Table 507 and Table 508)). I Single bit-errors or framing-errors may be injected into any test pattern, under register control. I Any sink or receiving channel may be replaced by a test-pattern monitor, which can detect and count bit errors or misconfigurations, and/or detect idle conditions or AIS. I Data link (DS1-ESF DL) and SSM (E1 multiframe Sa) fields read/writable. I Supports all Super Mapper modes of operation.

24.3 Applications

I Super Mapper self-test, crosspoint verification. I Built-in link and system testing support. I Flexible multicast/broadcast capabilities. I Programmable error insertion. I Idle or test-pattern (DS1 only) generation for each channel. I Idle or test-pattern (DS1 only) bit error or activity monitoring for each channel.

24.4 Block Diagram

The following diagram illustrates the high-level interface between the TPG block and other functional blocks. Figure 100. TPG Block Interface Block Diagram

24.5 Functional Descriptions

24.5.1 Test-Pattern Generation

also supports continuous idle data signals.

24.5.2 TPG Clock Source

24.5.3 TPG Transmit Edge Select

24.5.4 TPG Test-Pattern Framing

frame operation is enabled (DS1 only). Table 624. TPG Framing Controls (TPG_FRAMEx = 1) safely be ignored if not used.

24.5.5 DS1 TPG Framing

TPG_CRC6EINSx bit transitions from 0 to 1.

24.5.6 E1 TPG Framing

TPG_FINV = 1 (Table 507 and Table 508). error event is generated each time that the TPG_CRC4EINSx bit transitions from 0 to 1.

0 DS1 Transparent mode (test sequence bits

1 Continuous idle NA

2 E1 E1 with common channel signaling, CRC-4

4 DS2 Unframed PRBS sequence

24.5.7 DS2 TPG Framing

The DS2 generator provides an unframed DS2 rate test sequence.

24.5.8 DS3 TPG Framing

For DS3 test signals, the TPG provides a raw PN sequence on TPG_DATA[5] using the enabled clock.

24.5.9 Line Encoding/Decoding

puts become the positive rails and the sync inputs/outputs become the negative rails.

24.5.10 TPG Test-Pattern Sequences

datastream also has an associated clock TPG_CLKx and frame-sync signal TPG_FSx (x even, except DS2). and 510) or inverted TPG_TPINVx = 1. Table 625. TPG Test-Pattern Sequences normally the noninverted output of the last (20th) stage. but the test sequence is forced high if the outputs of stages 6 through 19 are low. 100 ALT_01. Alternating sequence of ones and zeros. 101 ALL_ONES. All-ones sequence. Note: If unframed, an AIS signal is generated. 111 User-Defined. Continuously repeating 16-bit pattern from TPG_USER[15:0] (Table 511).

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 579Agere Systems Inc.

24.5.11 TPG Idle Generator

The TPG has one output dedicated to providing a valid, SF framed DS1 idle data pattern. This datastream also has an associated clock TPG_CLKx and frame-sync signal TPG_SYNCx (x odd). This pattern is specified in detail in T1.403 for DS1.

24.5.12 TPG Error Insertion

A single bit error is injected into the test sequence each time that the global control signal SMPR_BER_INSRT (Table 65, SMPR_GTR, Global Trigger Register (RW) on page66) transitions from 0 to 1 while the associated enable bit TPG_BERINSx (Table 501) is set to 1. Similarly, for framed signals, a single framing bit error may be injected into the test sequence each time that the TPG_FERINSx ( Tabl e 5 02) bit transitions from 0 to 1. For certain types of framed signals (that is, DS1 ESF and E1 multiframe), cyclic-redundancy check (CRC) errors may be injected into the test sequence. A single error insertion event is triggered each time that the TPG_CRCEINSx ( Table 500) (for DS1-ESF) or TPG_CRC4EINSx (Table 503) (for E1) register bit toggles from 0 to 1.

24.5.13 TPG Interrupts

There are no interrupts from the TPG at the current time.

24.5.14 Test-Pattern Monitor (TPM)

The test-pattern monitor TPM sub-block contains four self-synchronizing detectors that are provisioned to search for a particular test pattern (one each for signal at DS1, E1, DS2, and DS3). Each of the four monitor blocks searches for the framed or unframed sequence at that rate, as determined by the values of TPM_FRAMEx (Table 507 and Table 508) and TPM_SEQm[2:0] (Table 507, 508, 509, and 510) register bits (defined similarly to the corresponding TPG register bits).

24.5.15 TPM Channel Selection

In normal operation, the user connects one of the available DS1, E1, DS2, or DS3 signals to the corresponding TPM input by configuring the cross connect (XC).

24.5.16 TPM Clock Edge and Data Polarity Selection

The edge of the clocks XC_TCLKx that is used to acquire the test data is provisionable to either the rising edge TPM_EDGEx = 1 (Table 507, 508, 509, and 510) or the falling edge TPM_EDGEx = 0 for each of the four test-pat- tern monitors. The polarity of the input data stream may also be provisioned to normal TPM_TPINVx = 0 (Table 507, 508, 509, and 510) or inverted TPM_TPINVx = 1.

24.6 TPM Framing Acquisition and Synchronization

24.6.1 DS1/E1

For framed data streams TPM_FRAMEx = 1 (Table 507 and Table 508), the monitor searches for the appropriate frame sequence in the selected signal. If no frame is found, TPM_OOFx (Table 496) is set. The TPM_OOFx condi- tion (status) signals default to 1, indicating an out-of-frame condition.

TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 May 2001 580 Agere Systems Inc. A TPM_OOFxD ( Table 482) signal detects and latches delta events (changes or transitions) in the TPM_OOFx sig- nal. The TPM_OOFxD signal is reset to 0 based on the SMPR_COR_COW (Table 67, SMPR_GCR, Global Control Register (RW) on pag e68) global control signal: if SMPR_COR_COW is set, event or delta signals are cleared on any microprocessor read of the event or delta register. If SMPR_COR_COW is 0, each event or delta signal must be written with a 1 to clear it. The TPM_OOFxD signal, if asserted, will generate an interrupt unless the corre- sponding mask bit TPM_OOFxDM (Table 489) is set. Also, synchronization is checked for the designated test patterns. If the TPM monitor detects 32 consecutive matches in its input sequence, the corresponding TPM_OOSx (Table 497) is cleared. Similarly, if the TPM detects four or more consecutive mismatches in the input sequence, the corresponding TPM_OOSx is set. The TPM_OOSx condition (status) signals default to 1, indicating an out-of-sync condition. A TPM_OOSxD ( Tabl e 4 83) signal detects and latches delta events (changes or transitions) in the TPM_OOSx sig- nal. The TPM_OOSxD signal is reset to 0 based on the SMPR_COR_COW global control signal: if SMPR_COR_COW is set, delta signals are cleared on any microprocessor read of the delta register. If SMPR_COR_COW is 0, each delta signal must be written with a 1 to clear it. The TPM_OOSxD signal, if asserted, will generate an interrupt unless the corresponding mask bit TPM_OOSxDM (Table 490) is set. DS2 (x = 4). The DS2 monitor checks for synchronization of the unframed PRBS signals, and for bit errors as above. DS3 (x = 5). The DS3 monitor checks for synchronization of the unframed PRBS signals, and for bit errors as above.

24.6.2 TPM Error Detection and Counting

TPM Bit Errors. While in sync, each data monitor detects and counts the number of times that the input sequence differs from the expected sequence in a 16-bit counter (one per rate). Detection of a bit error causes the TPM to latch a 1 into the TPM_BEREx (Table 490) event register bit. Clearing of this latched event is determined by the SMPR_COR_COW global control signal (if set, the event is automatically cleared on read, otherwise a 1 must be written to the TPM_BEREx register bit to clear it). If the interrupt is enabled (not masked) via TPM_BERMx (Table 491) mask bits, then this event will trigger an interrupt. The error counters accumulate TPM_BEREx events in a set of active counters. The active counter values are transferred to registers upon assertion of global control signal SMPR_PMRESET ( Table 65, SMPR_GTR, Global Trigger Register (RW) on page66). The counter values may be read via the microprocessor control interface via registers called TPM_CNTx[15:0] (Tables 513, 514, 515, and 516). The active counters will roll over or saturate at the terminal count depending on global control signal SMPR_SAT_ROLLOVER (Table 67, SMPR_GCR, Global Control Register (RW) on page68). The counters will clear on read if the global control signal SMPR_COR_COW is set; otherwise, the counter values are not affected by reads and instead must be cleared by explicit writes. The global control signals SMPR_PMRESET, SMPR_SAT_ROLLOVER, and SMPR_COR_COW operate on all six test channels; there are no separate controls per rate or mode. TPM Framing Errors. Framing-bit errors TPM_FEREx (Table 485) events are detected when TPM_FRAMEx is 1 but not counted. The event is latched and may be used to trigger a (maskable) interrupt, or may be polled (the error assertion will last between one and 24 frame intervals). The interrupt mask bit is called TPM_FERExM (Table 492). The global control signal SMPR_COR_COW determines if the TPM_FEREx event is cleared on read or write. TPM CRC Errors. Cyclic redundancy check (CRC) errors TPM_CRCEx (Table 488) are detected when TPM_FRAMEx ( Table 507 and Table 508) is 1 but not counted. CRC-6 errors are valid only for DS1 extended super-frame (ESF) test patterns. CRC-4 errors are valid only for E1 multiframe test patterns. Each CRC error event is latched and may be used to trigger a (maskable) interrupt, or may be polled (the error assertion will last between 1 and 24 frame intervals). CRC-6 errors (DS1-ESF only) are detected via TPM_CRCE0. Interrupts are managed via TPM_CRCE0M (Table 495) bit. The global control signal SMPR_COR_COW (Table 67, SMPR_GCR, Global Control Register (RW) on page68) determines if the TPM_CRCE0 event is cleared on read or write.

corresponding interrupt mask bit TPM_AISxDM (Table 494) is set. are presented to software via registers entitled TPM_ESFDL[15:0] (Table 504). entitled TPM_E1SAx[4:8] (Table 518 and Table 519).

24.6.3 TPM Interrupts

Table 626. TPM Interrupts detection via the TPM_OOFx (Table 496), TPM_OOSx (Table 497), and TPM_AISx (Table 498) indicators directly.

24.7 Microprocessor Interface

24.7.1 Microprocessor Interface Register Map

page 73. All addresses referred to in this section are given in hexadecimal notations in the first column of the table.

25 Philosophies

25 Philosophies (continued)

25.1 Clocking and Power Management Philosophy

Figure 101. Clock and Power Shutdown Diagram

25.2 Maintenance Philosophy

155 MHz Tx

155 MHz Rx

44.736 MHz

16 MHz — 66 MHz

The following tables show how the Super Mapper handles its maintenance tasks. Table 627. Maintenance Tasks Supported by the SMPR

Table 627. Maintenance Tasks Supported by the SMPR (continued)

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 Agere Systems Inc. 587

Applications

26 Applications

Figure 104. Super Mapper Switching Mode for Framer in Concentration Highway Figure 106. Super Mapper Switching Mode CHI Configuration with Byte-Synchronous VT Mapping Enabled ... 598

26 Applications (continued)

26.1 Application Diagrams

Figure 102. Switching Application of the Super Mapper Figure 103. Transport Application of the Super Mapper

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 Agere Systems Inc. 589

26.2 High-Speed Line Interfaces and Clock and Data Recovery

In the receive direction, the Super Mapper accepts either a differential serial data signal at 155.52 Mbits/s (STS-3/STM-1 mode) or a serial STS-1 clock and data at 51.84 MHz (STS-1 mode). For the STS-1 case, the input is retimed with the input clock. A clock and data recovery circuit is used for the 155 Mbits/s case with the high- speed transmit input clock as the clock reference. In the event that external clock and data recovery is provided, this feature can be bypassed. The clock and date circuit can be used for recovering clock at 51 MHz, but a 155 MHz clock reference must still be supplied. On the transmit side, in STS-3/STM-1 mode, the Super Mapper receives a differential 155.52 MHz transmit clock and transmit frame sync signal and outputs a differential serial data signal. In STS-1 mode, it receives a 51.84 MHz transmit clock and frame sync signal and outputs serial data. Loss of input clock or recovered clock is detected, as well as a loss-of-signal condition, by monitoring an external signal pin or internally an all-zeros/ones pattern. Built-in loopbacks at both high-speed interfaces provide maximum flexibility for maintenance testing.

26.2.1 Receive Direction

Terminating the transport overhead (TOH), the Super Mapper performs frame alignment (STS-3/STM-1 or STS-1), B1 BIP-8 check, J0 monitoring, descrambling, F1 monitoring, B2 BIP-8 check, APS and K2 monitoring, AIS-L and RDI-L detection, M1 REI-L detection, S1 sync status monitoring, and transport overhead access channel (RTOAC) drop. The states of the framer as well as all state changes are reported, and, if not masked, cause an interrupt. The B1 and B2 parity check supports bit and block mode. The counters count up to one second worth of BIP errors. They stay at their maximum value in case of overflow or rollover and should be read (and cleared) at least once per second. The J0 monitor supports nonframed, SONET -framed, and SDH-framed 16-byte sequences as well as single J0 byte monitoring modes. APS monitoring is performed on K1[7:0] and K2[7:3]. The value is stored and changes are reported. Bits [2:0] of the K2 byte are monitored independently. Line AIS (AIS-L/MS-AIS) and remote defect indication (RDI-L/MS-RDI) are monitored separately and changes are reported. This information is also sent to the protection device for ADM applications. The M1 monitor operates either in bit or block mode and allows accessing of the remote error indication (REI-L/MS-REI) errored bit count. The S1 byte can be monitored in two modes: as an entire 8-bit word or as one 4-bit nibble (bits 7 to 4). Continuous N times detection counters are implemented for these monitoring functions. All automatic receive mon- itoring functions can be configured to provide an interrupt to the control system, or the device can be operated in a polled mode. The receive transport overhead access channel (RTOAC) provides access to all of the line section overhead bytes. Even or odd parity is calculated over all bytes. It has a data rate of 5.184 Mbits/s and consists of a clock, data, and an 8 kHz sync pulse. Alternatively, only the data communication channels D1— D3 or D4— D12 may transmit a serial 192 kbits/s or a 576 kbits/s data stream.

26.2.2 Transmit Direction

In the transmit direction, the Super Mapper performs transmit transport overhead access channel (TTOAC) inser- tion, sync status byte (S1) insertion, M0/M1— REI-L insertion, K1 and K2 insertion, AIS-L insertion, B2 calculation and insertion, F1 byte insertion, B1 generation and error insertion, scrambler, J0 insert control, and A2 error inser- tion.

590 Agere Systems Inc. TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 May 2001 All insert control functions that are inhibited will optionally insert either all zeros or all ones. The TTOAC allows the users to insert the following overhead bytes: E1, F1, D1— D3, D4— D12, S1, and E2. Even or odd parity is checked over all bytes. Bytes which are not enabled for insertion are set to an all-ones or all-zeros stuff value. The Super Mapper sources a clock and an 8 kHz sync pulse and receives the data at a data rate of 5.184 Mbits/s. Alterna- tively, only the data communication channels D1— D3 or D4— D12 may receive a serial 192 kbits/s or a 576 kbits/s data stream. The insertion (overwrite of TTOAC) of programmed S1, F1, J0, Z0-2, and Z0-3 bytes can be enabled. Automatic insertion of M0/M1 may be inhibited. A protection switch selects the REI-L value for insertion to be taken from the protection board rather than from the receive side. The entire APS value or K2[2:0] can be inserted via microprocessor control. Automatic RDI insertion is supported with individual inhibit for each contributor. A protection switch selects the RDI-L value for insertion to be taken from the protection board rather than from the receive side. B1 and B2 BIP-8 values are calculated and inserted; both values can be inverted.

26.3 Multiplex Section Protection (MSP 1 + 1)

The TMUX block supports a payload 1 + 1 protection switch. In the receive direction, this occurs prior to pointer interpretation. If the protection switch is activated, then the data is selected from the receive protection interface rather than from the high-speed input path. In the transmit direction, the signal is broadcast to the high-speed output path and the protection interface. The interface consists of a 155.52 MHz or 51.84 MHz clock, data, and sync pulse in each direction.

26.3.1 Pointer Interpreter

This state machine implements the pointer interpretation algorithm described in ETS 300 417-1-1: January 1996— Annex B. The pointer interpreter evaluates the current pointer state for the normal state, path AIS state, or LOP (loss of pointer) conditions, as well as pointer increments and decrements. The current pointer state and any changes in pointer condition are reported to the control system. The number of consecutive frames for invalid pointer and invalid concatenation indication is fixed at nine.

26.4 Path Termination Function

The path termination function is performed on either all three STS-1s or on the VC-4 POH only. It includes on the receive side: J1 monitoring, B3 BIP-8 checking, C2 signal label monitoring, REI-P and RDI-P detection, H4 multiframe monitoring; F2, F3, and K3 automatic protection switch monitoring, N1 tandem connection monitoring, signal degrade BER and signal fail BER detection; path overhead access channel (RPOAC) drop, AIS-P/HO-AIS insertion, and automatic AIS generation (with individual inhibit). The J1 monitor provides five modes of operation on a programmable length (1 byte— 64 bytes) of the trace identi- fier: cyclic checking against the last received sequence, compare against a programmed sequence, SONET fram- ing mode, SDH framing mode, and consecutive consistent occurrences of a new pattern. B3 is monitored either in bit or block mode. Provisionable N-times detection counters are implemented for C2, F2, F3, N1, and K3 bytes. The K3 APS byte and N1 TCM byte can be monitored as an entire 8-bit word or two 4-bit nib- bles. The receive path overhead access channel (RPOAC) provides access to all the path overhead bytes. Even or odd parity is calculated over all bytes. It has a data rate of 8 bytes per 8 kHz frame and consists of clock, data, and an 8 kHz sync pulse.

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 Agere Systems Inc. 591 In the transmit direction, J1 path trace insertion, B3 calculation and insertion, C2 signal label insertion, REI-P and RDI-P insertion; F2 insertion, H4 multiframe insertion, F3 path user byte insertion, K3 insertion, N1 byte insertion, and AIS-P insertion via POAC or software control is supported. The transmit path overhead access channel (TPOAC) allows the insertion of all overhead bytes besides B3 which is automatically calculated. Even or odd parity is checked over all bytes. Bytes which are not enabled for insertion are set to an all-ones or all-zeros stuff value. The Super Mapper sources a clock and an 8 kHz sync pulse and receives the data at a rate of 8 bytes per 8 kHz frame.

26.5 STS-3/STM-1 MUX-DeMUX

The STS-3/STM-1 (AU-4) multiplexer provides three modes of operation: STS-3, AU-4, and STS-1. In STS-3 mode, the block multiplexes and demultiplexes up to three STS-1 signals to/from a SONET STS-3 signal. In AU-4 mode, it provides the functionality to MUX/deMUX up to three AU-3 signals to/from a STM-1 (AU-4) signal. In STS-1 mode, it provides the functions to generate and terminate a single STS-1 signal. The STS-3/STM-1 MUX function takes the bytes in the order they are present on the telecom bus and multiplexes them into the high-speed signal. Grooming of the VTs/VCs is performed in the SPE mapper of each of the three devices.

26.6 Telecom Bus Interface— Interfacing to Mate Devices

The Super Mapper can communicate with up to three mate devices via a telecom bus interface. The bus operates at 19.44 MHz for STS-3/STM-1 modes and at 6.48 MHz for STS-1 mode. In the receive direction, the Super Mapper outputs one parallel clock at 19.44 MHz, three sync signals (SPE, J0J1V1, and V1), an 8-bit data bus, and an odd/even parity bit. The data bus carries either three STS-1/TUG-3 sig- nals, each in their own time slot, or it carries one STS-1 signal. It also outputs a 51.84 MHz low-speed clock and sync. The transmit side of Super Mapper drives a clock and three sync signals (SPE, J0J1V1, and V1) onto the telecom bus. These signals control when the internal SPE mapper or one of the mate devices drives the data bus. The Super Mapper receives an 8-bit data bus and an odd/even parity bit from the telecom bus. The data consists of the SPE for up to three STS-1s. Also, a 51.84 MHz low-speed clock and sync are output.

26.7 SPE/AU-3 Mapper (DS3 Mapper)

The SPE mapper block is a highly configurable mapper. It operates either as an AU-3/STS-1 mapper or as a TUG-3 mapper. In both modes, it maps/demaps data from/to either the VT mapper, the M13 MUX/deMUX, the DS3 clear channel, or the DS3 loopback channel. The SPE m apper supports numerous automatic monitoring functions and provides interrupts to the control system, or it can be operated in a polled mode. In TU mapping mode, the SPE mapper provides flexibility down to TUG-2 level for choosing which TUG-2s (out of 7) are mapped/dropped into/from which TUG-3s (between 1 and 3) for generating STM-1 signals. This allows grooming of the VTs/TUs on the STM-1 level (over all three devices). In a full STM-1 application, with two other devices sitting on the telecom bus, care has to be taken for the provisioning of the time slots when each block drives the telecom bus. In DS3 mapping mode, the SPE mapper block accepts/delivers structured DS3 data from/to the M13 block or a clear DS3 signal at 44.736 Mbits/s rate and maps/demaps it asynchronously into/from the STS-1 SPE or a TU-3. The DS3 mapper generates a fixed pointer value of 522.

592 Agere Systems Inc. TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 May 2001 On the receive side, pointer interpretation is performed detecting LO P, AIS, N D F, NORM, INC, and DEC. A DS3 loopback mode allows demapping and remapping of a DS3 signal. It is particularly useful in cases where a DS3 signal mapped as an AU-3/STS-1 signal is needed to be remapped as a TU-3 signal or vice versa. B3ZS encoding/ decoding is included. The same path overhead monitoring functions as described above are implemented in this block. This block also connects to the path overhead access channel (POAC) to insert/drop the path overhead bytes J1, C2, F2, H4, F3, K3, and N1 into the STS-1 SPE or VC-3. The SPE mapper supports unidirectional path switch ring (UPSR) applications as well as N1 tandem connection function.

26.8 VT/VC Mapper

The VT/VC mapper maps any valid combination of DS1 and E1 signals into a stream at a rate of 51.84 Mbits/s (STS-1 or AU-3). The mapping methods (VT1.5, VT2, and VT group in ANSI nomenclature; TU-11, TU-12, and TUG-2 in ITU nomenclature) are analogous. The VT/VC mapper supports the following mappings: I 28 asynchronous, byte- or bit-synchronous DS1 signals are mapped into seven VT groups or TUG-2s. I 28 asynchronous, byte- or bit-synchronous J1 signals are mapped into seven VT groups or TUG-2s. I 21 asynchronous, byte- or bit-synchronous E1 signals are mapped into seven VT groups or TUG-2s. I Maps T1 into VT1.5/TU-11/TU-12, J1 into VT1.5/TU-11/TU-12, and E1 into VT2/TU-12. ADM and unidirectional path switch ring (UPSR) applications are supported via tributary loopback, tributary pointer processing, and low-order path overhead access channel. The VT/VC mapper supports automatic generation or microprocessor overwrite 1-bit RDI, enhanced RDI, 1-bit RFI, automatic downstream AIS generation, and five J2 trace identifier modes. The VT/VC mapper complies with GR-253-CORE, G.707, T1.105, G.704, G.783, JT -G707, GR-499, and ETS 300 417-1-1.

26.8.1 Receive Direction

In the receive direction, the VT mapper terminates the data stream it receives from the SPE mapper. It demulti- plexes the AU-3/TUG-3 into the VTs/TUs and checks the H4 multiframe alignment. Pointer interpreters for up to 28 VTs/TUs detect LOP , AIS, NDF , NORM, INC, and DEC on each channel. The low-order path termination includes V5 byte termination, J2 path trace, Z6/N2 tandem connection, Z7/K4 enhanced RDI and low-order APS monitor, and the payload termination for asynchronous, byte- or bit-synchronous signals. The V5 byte termination performs BIP-2 check (bit- or block-mode), REI count, RFI and RDI detection, sig- nal label monitor, and automatic AIS insertion (which can be inhibited). The J2 monitor supports four different modes as follows: I Cyclic check I SONET framing mode I SDH framing mode I Single byte check. In byte-synchronous modes, the receive demapper generates a frame sync to indicate the DS1 frame bit or the MSB of the E1 time slot 0. Additionally, it provides the framer access to the received signaling bits. Output of the VT mapper is a DS1/J1/E1 signal with a gapped clock. It can be overwritten with AIS automatically or upon micropro- cessor request.

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 Agere Systems Inc. 593

26.8.2 Transmit Direction

In the transmit direction, the VT mapper gets a clock, data, and frame sync from the cross connect. The input is retimed and checked for a digital loss of clock (LOC), an AIS condition, and low zeros-density. In byte-synchronous mode, the input signal is additionally checked for loss of frame sync (LOFS). A transmit elastic store synchronizes the incoming DS1/J1/E1 signals to the local STS-1 clock. In asynchronous and bit-synchronous mode, it works as a bit-oriented (64-bit) FIFO, and in byte-synchronous mode, as a bytewide (8-byte) buffer using a V5 byte marker bit (8— bit). Overflow or underflow conditions are monitored and reported. In asynchronous and bit-synchronous mode, a fixed VT pointer of 78 (VT1.5/TU-11) and 105 (VT2/TU-12) is gener- ated and the payload is mapped into the container using positive/null/negative bit stuffing mechanism (C- and S bits). In bit-synchronous mode, the bit stuffing mechanism is disabled. In byte-synchronous mode, a dynamic VT pointer value is generated using the V5 marker implementing NORM, N D F, INC, and DEC pointers. The VT POH generation comprises V5 byte with BIP2-generation, AIS-, signal label-, UNEQ-insertion, automatic REI-, RFI-, RDI-, and enhanced RDI-generation ( Bellcore, ITU-T), J2 path trace insertion via microprocessor, Z6/N2 byte insertion, and Z7/K4 byte insertion via microprocessor or low-order path overhead (LOPOH) access channel. The data stream is synchronized to the received 2 kHz sync pulse and multiplexed to form the STS-1/AU-3 signal, which is then output to the SPE mapper. When operating in byte-synchronous mode, the phase and signaling bits from the framer are stored and inserted into the mapped frame.

26.9 M13/M23 Multiplexer

The M13 is a highly configurable multiplexer/demultiplexer. It can operate as an M13 in either the C-bit parity or M23 mode, a mixed M13/M23, or an M23. In the C-bit parity mode, the M13 provides a far-end alarm and control (FEAC) code generator and receiver, an HDLC transmitter and receiver, and automatic far-end block error (FEBE) generation. Each internal M12 MUX/deMUX and the M23 MUX/deMUX may be configured to operate as independent MUXs/deMUXs. 28 DS1 inputs in groups of four or 21 E1 input signals in groups of three can feed into individual M12 MUXs, while the M23 MUX can take DS2 signals from outputs of M12 MUXs, or direct DS2 inputs, or loop- back deMUXed DS2s. The M13 supports numerous automatic monitoring functions. It can provide an interrupt to the control system, or it can be operated in a polled mode.

26.9.1 Receive Direction

The receive DS3 is monitored for loss of clock and checked for loss of signal (LOS) according to T1.231. The B3ZS decoder accepts either unipolar clock and data or unipolar clock, positive and negative data. It also checks for bipo- lar coding violations. The transmit DS3 can be looped back into the receive side after B3ZS decoding. The M23 demultiplexer checks for valid DS3 framing by finding the frame alignment pattern (F bits), and then locat- ing the multi frame alignment signal (M bits). Each M frame, the data stream is checked for the presence of the AIS (1010) or idle (1100) pattern. C bits 13, 14, and 15 can be used as a 28.2 kbits/s data link and are available directly at device output via an inter- nal HDLC receiver. It is composed of a 128-byte FIFO, a CRC-16 frame check sequence (FCS) error detector, and control circuits.

594 Agere Systems Inc. TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 May 2001 Within the M23 demultiplexer, there are four performance monitoring counters for F- or M-bit, P-bit, E-bit parity, and FEBE errors. Each M12 demultiplexer contains two performance monitoring counters.

26.9.2 Transmit Direction

The incoming DS1/E1 clocks are first checked for activity or loss of clock (LOC). The data signals are retimed and checked for AIS and activity. DS1/E1 loopback selectors allow DS1 or E1 received within the DS2 or DS3 inputs from the deMUX path to be looped back. This loopback can be performed automatically or the user can force a DS1 or E1 loopback. The four DS1 or three E1 signals for each M12 MUX are fed into single bit 16-word-deep FIFOs to synchronize the signals to the DS2 frame generation clock. The fill level of each FIFO determines the need for bit stuffing its DS1/E1 input. The M13 can handle DS1/E1 signals with nominal frequency offsets of ±130 ppm and up to five unit intervals peak jitter. The DS2/DS3 transmit clock is used to derive the clock source for DS2 frame generation. The M23 multiplexer generates a transmit DS3 frame, and fills the information bits in the frame with data from the seven DS2 select blocks. The M23 MUX can be provisioned to operate in either the M23 mode or the C-bit parity mode. It contains seven DS2 FIFOs each with a depth of 8. The fill level of each FIFO determines the need for bit stuffing its DS2 input. The transmit DS3 output can either be in the form of unipolar clock and data or unipolar clock, positive and negative data. The DS3 data is B3ZS encoded and can be looped back from the receive DS3 input.

26.10 Cross Connect Block

The cross connect (XC) is a highly configurable nonblocking crosspoint switch for DS1/E1/DS2 signals, configura- tion of DS3 signal paths, and configuration of the path overhead access I/O. The cross connect plays a major role in configuring the interconnection of major function blocks to satisfy an application’s implementation. The cross connect provides the flexibly to tie DS1/E1/DS2 channels from the framer or external pins to the M13 mapper or to the VT mapper. It is also capable of multicast or broadcast operation (one port to many), handling injected test patterns, idles, or alarm conditions to any channel, and can provide system loopback testing support. Jitter attenuation may also be inserted in-line on any DS1/E1 channel. The cross connect can interconnect up to 28 individual DS1/E1 channels between the framer, M13 multiplexer, VT mapper, jitter attenuator, or external I/O. The external I/O pins support an application dependent mix of up to 29 T1/E1 interfaces (one dedicated protection channel), seven DS2 interfaces, or one of four available framer sys- tem interfaces. The cross connect supports an independent signal path for remote alarm indication (RAI), alarm indication signal (AIS), and byte-synchronous frame sync signals on channels between the VT mapper or M13 and the framer. Receive pointer adjustment information is routed to the jitter attenuator block for each channel originating in the VT mapper. The cross connect has independent DS2 interfaces for the M12 and M23 blocks of the M13 MUX. Full split access to the external I/O device pins provides the capability to add, drop, or rearrange the DS2 signals within the M13. For DS3 signals, the cross connect supports configuration of interconnects between the M13 and the SPE, or external I/O interconnection to the M13 or SPE, or insertion/monitoring of DS3 test patterns from the test-pattern generator block. The test-pattern generator block (TPG) provides test signals and it monitors inputs (TPM) for signals to and from the cross connect. The TPG can generate a set of test signals or idles at DS1, E1, DS2, or DS3 rates. There is only one test pattern generator and monitor per signal rate. Device pins for the path overhead access channel may be configured to connect to the SPE mapper or TMUX blocks.

Preliminary Data Sheet TMXF28155/51 Super Mapper May 2001 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 Agere Systems Inc. 595

26.11 Digital Jitter Attenuator

The digital jitter attenuator (DJA) contains 28 copies of the digital jitter attenuator block. These digital jitter attenua- tor blocks can operate in two different modes, as a DS1 or as an E1 jitter attenuator. In both modes, the digital jitter attenuator can be provisioned to always operate as a second-order PLL, or it can switch to a act as a first-order PLL during VT pointer adjustments to help meet MTIE requirements. The period of time in the first-order mode is provisionable. The PLL bandw idth is provisionable between 0.1 Hz and 0.5 Hz and the damping factor for these bandwidths varies between 2 and 0.5 to accommodate a number of different system constraints. The block will also insert the proper AIS signal if the primary block AIS control input is active.

26.12 Test Pattern Generator

The test pattern generator and monitor (TPG and TPM) is a set of configurable test pattern generators and moni- tors for local self-test, maintenance, and troubleshooting operations. The TPG feeds one or more T1/E1/DS2 test signals (via data, clock, and FS or AIS signal paths) to the crosspoint switch which can redistribute or broadcast these signals to any valid channel in the framer, external I/O, M13 map- per, or VT mapper blocks. The TPG can also generate DS3 test signals. Any channel arriving at the cross connect may be routed to the test monitor. The test monitors can automatically detect/count bit errors in a pseudorandom test sequence, loss of frame, or loss of sync. The TPM can provide an interrupt to the control system, or it can be operated in a polled mode. Simultaneous testing of DS1, E1, DS2, and DS3 signals is supported (one channel each). Supported test patterns are: pseudorandom bit sequence (PRBS15, PRBS20), alternating zeroes/ones, and an all- ones pattern. The test pattern can be transmitted either unframed or as the payload of a framed signal, as defined in ITU-T rec- ommendation O.150. Single bit-errors may be injected into any test pattern, under register control.

are shown in Figure 107 and Figure 108 (only the major functional blocks are shown). Figure 104. Super Mapper Switching Mode for Framer in Concentration Highway Interface (CHI)

Figure 105. Super Mapper Switching Mode for Framer in Parallel System Bus Configuration

sent from the receive performance monitor block to the transmit HDLC block. Figure 106. Super Mapper Switching Mode CHI Configuration with Byte-Synchronous VT Mapping Enabled

Figure 107. Super Mapper Byte-Synchronous Transport Mode: Passive Performance Monitoring

Figure 108. Super Mapper Byte-Synchronous Transport Mode: Intrusive Performance Monitoring

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26.14 Line Decoder/Encoder

The line decoder/encoder supports either single-rail or dual-rail transmission. In dual-rail mode, the line codes sup- ported are as follows: I Alternate mark inversion (AMI). I DS1 binary 8 zero code suppression (B8ZS). I ITU-CEPT high-density bipolar of order 3 (HDB3). In the single-rail mode, a line interface unit (LIU) decodes/encodes the data. In the dual-rail mode, loss of signal in monitored. In the case of coded mark inversion (CMI) coding (Japanese TTC standard JJ-20.11), the LIU decodes the data, indicating both the CMI coding rule violations (CRVs) and line coding violations as bipolar violations. (In the CMI mode, the framer is in the single-rail mode.)

26.15 Receive Frame Aligner/Transmit Frame Formatter

The receive frame aligner and transmit frame formatter support the following frame formats: I D4 superframe. I SF D4 superframe: FT framing only. I J-D4 superframe with Japanese remote alarm. I DDS. I SLC -96. I ESF . I J-ESF (J1 standard with different CRC-6 algorithm). I Non-align DS1 (193 bits— clear channel). I CEPT basic frame (ITU G.706). I CEPT CRC-4 multiframe with 100 ms timer (ITU G.706). I CEPT CRC-4 multiframe with 400 ms timer (automatic CRC-4/nonCRC-4 equipment interworking) (ITU G.706 Annex B). I Non-align E1 (256 bits— clear channel). I 2.048 coded mark inversion (CMI) coded interface (TTC standards JJ-20.11).

26.16 Receive Performance Monitor

The receive framer monitors the following alarms: loss of receive clock, loss of signal, loss of frame, alarm indica- tion signal (AIS), remote frame alarms, and remote multiframe alarms. These alarms are detected as defined by the appropriate ANSI , AT&T, ITU, and ETSI standards. Performance monitoring as specified by AT&T, ANSI , and ITU is provided through counters monitoring bipolar vio- lation, frame bit errors, CRC errors, errored events, errored seconds, bursty errored seconds, and severely errored seconds. In-band loopback activation and deactivation codes can be transmitted to the line via the payload or the facility data link. In-band loopback activation and deactivation codes in the payload or the facility data link are detected.

602 Agere Systems Inc. TMXF28155/51 Super Mapper Preliminary Data Sheet 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 May 2001

26.17 Signaling Processor

The signaling processor supports the following modes: I Superframe (D4, SLC -96): 2-state, 4-state, and 16-state. I VT 1.5 SPE: 2-state, 4-state, and 16-state. I Extended superframe: 2-state, 4-state, and 16-state. I CEPT: common channel signaling (CCS) (TS-16). I Transparent (pass through) signaling. I J-ESF handling groups. Signaling features supported per channel are as follows: I Signaling debounce. I Signaling freeze. I Signaling interrupt upon change of state. I Associated signaling mode (ASM). I Signaling inhibit. I Signaling stomp. In the DS1 robbed-bit signaling modes, voice and data channels are programmable. The entire payload can be forced into a data-only (no signaling channels) mode, i.e., transparent mode by programming one control bit. Signaling access can be through the on-chip signaling registers or the system interface. Data and its associated signaling information can be accessed through the system in either DS1 or C EPT-E1 modes.

26.18 Facility Data Link (FDL) Processor

The bit-oriented ESF data-link messages defined in ANSI T1.403 are monitored by the receive facility data link unit. The transmit facility data link unit overrides the FDL-FIFO for the transmission of the bit-oriented ESF data-link messages defined in ANSI T1.403-1995. The FDL processor extracts and stores data link bits from three different frame types as follows: I D bits and delineator bits from the SLC -96 multi-superframe. I Data link bits from DDS frames (bit 6 of time slot 24). I Two multiframes of Sa[4:8] bits from time slot 0 in CEPT basic and CRC-4 multiframes. The respective bits will always be extracted from frame-aligned frames and stored in a stack. The processor will have control of being alerted to stack updates through the interrupt mask registers. The transmit FDL block performs the transmission of D bits into SLC -96 superframes, Sa-bits in CEPT frames, and D bits in DDS frames. I In SLC -96 frames, the D and delineator bits are always sourced from this block when the block is enabled for insertion. I In DDS frames, the data link bits are always sourced from this block when this block is enabled for insertion. This block also provides the capability to transmit BOMs in the data link channel of ESF links. I In CEPT frames, the Sa bits are sourced from either the Sa stack within this block or from the system interface. The data link block only responds with valid data when selected by the Sa source control bits.

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26.19 HDLC Unit

The HDLC processor formats the HDLC packets for insertion into the programmable channels. A channel can be any number of bits (1 to 8) from a time slot. The maximum number of channels is 64. The maximum channel bit rate is 64 kbits/s. The minimum channel bit rate is 4 kbits/s. Each channels is allocated 128 bytes of storage. HDLC processing of data on the facility data link (PRMs, Sa bits, or otherwise) is implemented by assigning the FDL bit position to a logic HDLC channel.

26.20 System Interface

The system interface block provides a programmable interface. It can be configured to work in four different modes. I Concentration highway interface (serial time division multiplex interface). — Global frame sync. — 28 transmit and receive data ports; data rates: 2.048 Mbits/s, 4.096 Mbits/s, or 8.192 Mbits/s. I Parallel system bus (parallel time-division multiplex interface/transmit and receive). — Global frame sync. — Global clock: 19 MHz. — Data rate: 19 MHz. — 8 bits of data + associated parity bit. — 4 bits of signaling + 2 bits of signaling control + 1 bit of parity. I Time-division multiplex data rate serial interface. — 28 receive frame sync (per port). — 28 receive clock: 1.544 Mbits/s or 2.048 Mbits/s (per port). — 28 receive ports. — One transmit frame sync. — One transmit clock: 1.544 Mbits/s or 2.048 Mbits/s. — 28 transmit ports. I Network serial multiplexed bus. — 6- or 8-pin serial interface. — Transmit and receive clock and data at 51.84 MHz. — Accommodates 1 DS3 of throughput. — Provides a minimal pin count interface for data and inverse multiplexing for ATM (IMA) applications without slip buffers. — Three modes of operation: framer— NSMI payload assembled/disassembled into DS1/E1s; M13— proprietary transport format with DS3 framing; SPE— proprietary transport format mapped into an STS-1/AU-3.

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Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liabi lity is assumed as a result of their use or application. SLC is a registered trademark of Agere Systems Inc. Copyright © 2001 Agere Systems Inc. All Rights Reserved Printed in U.S.A. June 2001 DS01-167PDH (replaces DS01-078PDH) For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@micro.lucent.com N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC: Agere Systems Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA: Agere Systems (Shanghai) Co., Ltd., 33/F Jin Mao Tower, 88 Century Boulevard Pudong, Shanghai 200121 PRC Tel. (86) 21 50471212, FAX (86) 21 50472266 JAPAN: Agere Systems Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: DAT ALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 3507670 (Helsinki), ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid)