TMUX03155

TMUX03155 AGERE | Alldatasheet

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Technical content

Features

I Multiplexes three STS-1 signals into a SONET STS-3 signal. I Multiplexes three AU-3 signals into an SDH STM-1 (AU-4) signal via a TUG-3 construction. I Demultiplexes three STS-1 signals from a SONET STS-3 signal. I Demultiplexes three AU-3 signals from an SDH STM-1 (AU-4) signal via a TUG-3 deconstruction. I High-speed microprocessor interface configurable to operate with most commercial microprocessors. I Detects STS-3/STM-1 (AU-4) loss-of-signal (LOS) conditions. I Detects STS-3/STM-1 (AU-4) out-of-frame and loss-of-frame (OOF/LOF) conditions. I Provides an 8-bit bus interface at the STS-1/AU-3 rate. I Provides a bit serial, nibble-wide, or byte-wide interface at STS-3/STM-1 (AU-4) rate. I Provides STS-3/STM-1 (AU-4) selectable scram- bler/descrambler functions and B1/B2/B3 genera- tion/detection. I Accepts bit rate, nibble rate, or byte rate high- speed clocks (155.52 MHz, 38.88 MHz, or 19.44 MHz, respectively). I STS-3/STM-1 (AU-4) internal clock and data recovery. Meets type B jitter tolerance of ITU-T G.958. Accommodates 0.5 UI jitter up to 20 MHz. 155.52 MHz input reference clock for on-chip PLL. Has on-chip PLL for clock synthesis, requiring only one external resistor. No output clock drift in absence of data transitions once lock is acquired. I STS-1 termination mode. I –40 °C to +85 °C temperature range. I 208-pin, shrink quad flat pack (SQFP) package. I Complies with GR-253-CORE (12/95), G.707

Applications

I SONET/SDH line termination equipment. I SDH path origination and termination equipment. I SONET/SDH add/drop multiplexers. I SONET/SDH cross connects. I SONET/SDH test equipment.

Description

The TMUX03155 STS-3/STM-1 (AU-4) multiplexer device provides three modes of operation: STS-3, STM-1 (AU-4), and STS-1 modes. In STS-3 mode, the TMUX03155 device provides all of the functions necessary to multiplex and demultiplex up to three STS-1 signals to/from a SONET STS-3 signal. In AU-4 mode, the TMUX03155 provides the functional- ity to multiplex and demultiplex up to three AU-3 sig- nals to/from an STM-1 (AU-4) signal. In STS-1 mode, the high-speed side of the TMUX03155 operates at

51.84 MHz and can be used for STS-1 termination

and for accessing transport overhead in the SONET frame. On the STS-3/STM-1 (AU-4) side, the device can be configured for either a 1-bit serial data inter- face, a 4-bit parallel (nibble-wide) data interface, or an 8-bit parallel (byte-wide) data interface. This allows the device to drive an OC3 optical signal directly or to allow for modular growth in terminal or add/drop applications. On the STS-1/AU-3 side, the TMUX03155 device provides a bus mode that can communicate with up to three STS-1/AU-3 devices at 19.44 Mbits/s. The TMUX03155 is designed to inter- face with the Agere Systems Inc. TMPR28051 device, or equivalent, providing complete mapping/ unmapping from/to an STS-3/STM-1 (AU-4) signal for up to 84 DS1 or 63 E1 signals.

2 Agere Systems Inc. Preliminary Data Sheet April 2001TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer

Table of Contents (continued) Contents Page Agere Systems Inc. 3 Preliminary Data Sheet April 2001 TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer

Agere Systems Inc. 7 Data Sheet April 2001 TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer Description (continued) Automatic receive monitoring functions can be config- ured to provide an interrupt to the control system, or the device can be operated in a polled mode. Built-in loopback at both the STS-1/AU-3 and STS-3/ STM-1 (AU-4) interfaces provides maximum flexibility for use in a number of SONET/SDH products including path termination multiplexers, add/drop multiplexers, and digital cross connects. A high-speed microprocessor interface and full user programmability on STS-1/AU-3 to STS-3/STM-1 (AU- 4) slot insertion and drop provide maximum flexibility for I/O configuration. Nomenclature Assumptions Throughout this document, certain assumptions are made about nomenclature. The transmission path that outputs the STS-3/STM-1 (AU-4) signal is called the transmit direction, while the transmission path that receives the STS-3/STM-1 (AU-4) signal is referred to as the receive path. The low-speed (LS) side of the device transmits or receives the STS-1/AU-3 signals, while the high-speed (HS) side of the device transmits or receives the STS-3/STM-1 (AU-4) signal. The LSB (least significant bit) of a byte is labeled 0 and the MSB (most significant bit) is labeled N – 1, where N is the total number of bits in the word. A signal that ends in [3—1][7:0] implies there are three separate sig- nals, each containing 8 bits. A control bit that has only one function causes that function to be active when the control bit is set to a logic 1. For example, setting RLSCLKINV, 0x57 to a logic 1 causes the low-speed output clock to be inverted. A control bit with two names performs the first choice when set to a logic 0 and the second choice when set to a logic 1. For example, TSONET_SDH, 0x34 when set to a logic 0 puts the transmit direction in the SONET mode and when set to a logic 1 puts the transmit direction in SDH mode. Where necessary to avoid confusion, numbers may be expressed using a format to specify their base. The fol- lowing are examples: I 9\\D = 9 decimal. I 0x04 = 04 hexadecimal. I 11\\B = 11 binary. Block Diagram In the transmit direction, the device outputs a clock and sync and accepts bused data [7:0] and a parity signal from up to three devices. The device outputs one data bundle at the STS-3/STM-1 (AU-4) rate (clock, sync, data [7:0], and parity bit). A local clock and optional frame sync signal are needed for operation of the device. A transport overhead access channel (TOAC) is provided to allow overwriting of the transport over- head bytes in the output STS-3/STM-1 (AU-4) frame. In the receive direction, the device accepts one STS-3/ STM-1 (AU-4) bundle (clock, data, parity). Optional clock and data recovery is available on the STS-3/ STM-1 (AU-4) receive input. The device also accepts a loss-of-signal indication from an external source. The device outputs three STS-1/AU-3 signals over a bus interface (clock, data, J0 time, parity). The STS-3/STM- 1 (AU-4) input clock is used to clock this direction. A transport overhead access channel is provided for additional external monitoring of the incoming transport overhead of the STS-3/STM-1 (AU-4) frame. A pointer interpreter is provided to monitor path functions. The device also has loopback capabilities at the STS- 1/AU-3 and STS-3/STM-1 (AU-4) interfaces. In addi- tion, the device supports STS-1 termination. An 8-bit microprocessor interface, JTAG control logic, and in- circuit test capabilities are also provided.

Figure 1. TMUX03155 Block Diagram

Figure 2. Pinout of 208 SQFP Device The pin descriptions for the 208 SQFP package follow in Table 1 on page 10.

Table 1. Pin Descriptions for the 208-Pin SQFP Package

• Pin order follows symbol order, e.g., pin 170 refers to TLSDATA7I.

puts. LVDS = low-voltage differential signal. ter tap input provides for center-tapped common-mode termination. ground (approximately 0.1 µF). ter tap input provides for center-tapped common-mode termination. ground (approximately 0.1 µF).

148 THSCLKI I

38.88 MHz (nibble) or 19.44 MHz (byte). active-high and is optional.

Table 1. Pin Descriptions for the 208-Pin SQFP Package (continued)

• Pin order follows symbol order, e.g., pin 170 refers to TLSDATA7I.

puts. LVDS = low-voltage differential signal. receive either odd or even parity. placed in a high-impedance state. frame sync is coincident with the first or last bit of the frame. 38.88 MHz for nibble data, or 19.44 MHz for byte-wide data. sync is coincident with the first or last nibble/byte of the frame. either an odd or even parity bit.

39 TTOACDATAI I

• Pin order follows symbol order, e.g., pin 170 refers to TLSDATA7I.

puts. LVDS = low-voltage differential signal. (AU-4) serial clock is 155.52 MHz. ter tap input provides for center-tapped common-mode termination. ground (approximately 0.1 µF). serial data is 155.52 Mbits/s. an external 10 kΩ ±1% resistor.

50 RHSCLKI I

is 38.88 MHz (nibble), or 19.44 MHz for byte-wide data. accept either odd or even parity.

49 RHSLOSEXTI I

d Receive High-Speed Loss of Signal. This is an active-high signal. 19.44 MHz for byte-wide data (bus mode). (logic 1) each time the J0 byte is output. cant bit of the output byte. to source either an odd or even parity bit per byte transfer.

• Pin order follows symbol order, e.g., pin 170 refers to TLSDATA7I.

puts. LVDS = low-voltage differential signal. output pins are placed in the high-impedance state. channel will be interrupted. 153, 154 MODE [1:0] I u, Id Mode Control. Normal STS-3/STM-1 mode set MODE [1:0] = 10. accept demultiplexed (separate) address and data signals. tocol with a separate data strobe and a combined read/write control.

16 MPMODE3ALE I

without being retimed. This is an active-high signal. microprocessor to initiate a write cycle. microprocessor to initiate a read cycle.

• Pin order follows symbol order, e.g., pin 170 refers to TLSDATA7I.

puts. LVDS = low-voltage differential signal. internal 100 kΩ pull-up is on this pin. the microprocessor by setting the appropriate mask bits. impedance state when CS is high. these pins become the multiplexed address/data bus. become the address bus for the microprocessor interface registers. 23 TMS I u JTAG Mode Select. 24 TRST Iu JTAG Reset (Active-Low). 27 SCAN_EN Iu Scan Enable. Place device in scan mode (active-low). 28 TEST_MODE I d Test Mode. Disable all clocks and async resets (active-high). 114 CDR_TSTMUX0 O CDR Test Output. Test purpose only. 129 LVDS_REF10 I 1.0 V Reference for LVDS Buffers. This signal is optional. 128 LVDS_REF14 I 1.4 V Reference for LVDS Buffers. This signal is optional.

• Pin order follows symbol order, e.g., pin 170 refers to TLSDATA7I.

puts. LVDS = low-voltage differential signal. DD I Power Supply for Digital Circuitry. 151, 32 REF5VTOL I 5 V Tolerant Reference Voltage. Table 2. Input/Output Summary

I The type of input signal to expect (low-speed (LS) side—STS-1/AU-3). I The expected high-speed (HS) input/output signal format—STS-3/STM-1 (AU-4), or STS-1. I The default byte value in the outgoing HS frame. These provisioning signals are summarized in Table 3 and Table 4. RSONET_SDH, 0x34, to a logic 0. Table 3. Transmit Mode Control Signals

1. SONET = OOF 0 → 1, 4 times detect; default output byte = 0x00.

STS-1 mode. See STS-1 Mode section for details. 1 = AU-4 0 = SONET* Three AU-3 signals multiplexed to an STM-1 (AU-4) signal.

1. SDH = OOF 0 → 1, 5 times detect; default output byte = 0xFF.

Three STS-1 inputs multiplexed to an STS-3 output. 1 = AU-4 1 = SDH † Three AU-3 signals multiplexed to an STM-1 (AU-4) signal. Table 4. Receive Mode Control

1. SONET = OOF 0 → 1, 4 times detect; default output byte = 0x00; ignore SS bits.

for STS-1 mode. See STS-1 Mode section for details. 1 = AU-4 0 = SONET* One STM-1 (AU-4) input demultiplexed to three AU-3 outputs.

1. SDH = OOF 0 → 1, 5 times detect; default output byte = 0xFF; verify SS bits = 10.

One STS-3 input demultiplexed to three STS-1 outputs. 1 = AU-4 1 = SDH † One STM-1 (AU-4) input demultiplexed to three AU-3 outputs.

enable, STS-3/STM-1 (AU-4) loopback control, and STS-3/STM-1 (AU-4) output interface. abled under software control (TLSV1DISABLE, 0x35). verified per byte transfer (TLSPARE[3—1], TLSPARM[3—1], 0x07, 0x10). tions to be possible. The selected STS-1/AU-3 inputs are labeled S#1T, S#2T, and S#3T in Figure 1. 86 columns of payload. For column byte definitions, see Table 6 on page 18. Table 5. Input Select Control

coincident from all three STS-1/AU-3 inputs) and are allocated as shown in Table 6. Note: X = don’t care (payload). The path overhead (POH) can start anywhere within the SPE and cannot be accessed in the STS-3 mode. byte is the only valid byte in the POH and all other bytes are ignored. until five (SDH)/four (SONET) successive frames separated in time by 125 µs occur with errored framing patterns. logic 1 to the appropriate bit causes the selected STS-1/AU-3 signal to be descrambled.

• Can be provided by the Agere TMPR28051 mapper device.

Table 6. Expected STS-1/AU-3 Input Frame Format

Agere Systems Inc. 19 Data Sheet April 2001 TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer Transmit Direction Overview (continued) Monitor B1 and B2 Errors The device verifies B1 and B2 bit interleaved parity (BIP) values on each selected STS-1/AU-3 input. The device will count BIP errors or block errors under software control (BITBLOCKCNT, TLSB1ECNT[3—1][15:0], TLSB2ECNT[3—2][15:0], TLSB2ECNT1[17:0], 0x34, Page 1 - 0x80—0x85, Page 1 - 0x86—0x88, Page 1 - 0x89—0x8C). These counters will update on LATCH_CNT, 0x04 and are large enough to store at least 1 second’s worth of data. H4 Multiframe and Pointer Monitor (AU-4 Mode Only) In this mode, all three input signals are required to have pointer values (H1, H2) with the same fixed value of 522\\D. This ensures the J1 byte starts in row 1, column 4. The H4[1:0] multiframe bits must be the same from all inputs and equal to the internally expected value. This is required because the output STM-1 (AU-4) signal only has one H4 byte. The device will synchronize its H4 internal expected value to a 1 after detecting an embedded 2 kHz sync in the local frame sync signal (THS(S)J0J1V1I(T/C)). The device will declare a pointer match after two consecutive pointer values of 522\\D are detected 125 µs apart. A pointer mismatch will be declared after five successive frames separated in time by 125 µs occur with errored pointer values (TLSPTRMIS[3—1], TLSPTRMISD[3—1], TLSPTRMISM[3—1], 0x1A, 0x09, 0x12). The device will declare an H4 multiframe match after two consecutive H4 values match the expected value spaced 125 µs apart. An H4 multiframe mismatch will be declared after five successive frames separated in time by 125 µs occur with H4 values not equal to the expected value (TLSH4MIS[3—1], TLSH4MISD[3—1], TLSH4MISM[3—1], 0x1A, 0x09, 0x12).

• Access through transmit TOAC (see Table 17 on page 37).

Note: Bold type within the table is not defined in the standard and is labeled here for clarity. (1) Are set to the fixed stuff value (0x00 (SONET)). (2) Are TOAC value-inserted. (3) Have passed through from the selected STS-1 input, all under software control. The variable values are described beginning on page 30 in the Maintenance Functions section of this document. Table 7. STS-3 Output Overhead Format

• Access through transmit TOAC (see Table 17 on page 37).

Note: Bold type within the table is not defined in the standard and is labeled here for clarity. † Access through transmit TOAC. Table 8. STM-1 (AU-4) Output Overhead Format

2222 Agere Systems Inc. Data Sheet April 2001TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer Transmit Direction Overview (continued) STM-1 (AU-4) Frame Generation (AU-4 Mode) (continued) Path Bytes J1—64-byte programmable sequence TJ1INS, 0x3E, TJ1DINS[64—1][7:0], 0x3E, 0x80—0xBF B3—Variable value BIP-8 C2—TC2DINS[7:0], 0x46 G1[7:4]—REICNT (B3 errors from receive side) TPFEBEEINS, 0x4D G1[3]—RDI indication TPRDIINS, 0x4B G1[2:0]—Default value F2—Variable value TF2DINS[7:0], 0x47 H4[1:0]—Position indicator (multiframe value (00\\B to 11\\B)) Z3—Variable value TZ3DINS[7:0], 0x48 Z4—Default value Z5—Variable value TZ5DINS[7:0], 0x49 Fixed stuff = depends on TSONET_SDH, 0x34 value (SONET = 0x00, SDH = 0xFF) NPI (null pointer indicator—byte 1, byte 2, and byte 3) = (10011011, 11100000, 11111111). NPI is generated for compatibility with older devices. All bytes not specified above, either: (1) Are set to the fixed stuff value 0xFF (SDH). (2) Are TOAC value inserted. (3) Have passed through from the selected AU-3 input, all under user control.

Agere Systems Inc. 23 Data Sheet April 2001 TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer Transmit Direction Overview (continued) Transport Overhead Access Channel (TOAC) Insert The device will allow the insertion of overhead data from the transmit TOAC under user control. (See TTOAC in the Maintenance Functions section, page 36, for more details.) STS-3/STM-1 (AU-4) Scramble Enable Scrambling of the STS-3/ STM-1 (AU-4) signal is provisionable (THSSCR, 0x3D). A frame synchronous scram- bling sequence 1 + x6 + x7 is used. The sequence is reset to 1111111 at the beginning of the byte following the Z0- 3 byte and scrambles all of the STS-3/STM-1 (AU-4) data except all the A1, A2 and J0, Z0 bytes. Writing a logic 1 to this bit causes the signal to be scrambled. STS-3/STM-1 (AU-4) B1, B2, and B3 BIP Generation The device will generate a B1-BIP-8, B2-BIP-24, and a B3-BIP-8 (AU-4 mode only) on the output signal. Each BIP calculator can be programmed to insert an inverted BIP value (THSB1ERRINS, THSB2ERRINS[3—1], THSB3ERRINS, 0x4C). STS-3/STM-1 (AU-4) Loopback Control The output STS-3/STM-1 (AU-4) signal can be replaced by the receive STS-3/STM-1 (AU-4) signal under software control (RHS2THSLB, 0x3D). The output format (bit, nibble, or byte) will be the same as the receive input format not the transmit output port format. Note: The transmit port type must be programmed to be the same as the receive input type. STS-3/STM-1 (AU-4) Output Interface The transmit STS-3/STM-1 (AU-4) output can either be serial at 155.52 Mbits/s, nibble at 38.88 Mbits/s, or byte at 19.44 Mbits/s. This is controlled by writing to THSPTYPE[1:0], 0x3C. The data is clocked out of the device on the rising edge of the clock. This clock can be inverted leaving the device (THSCLKINV, 0x3C). When provisioned in the parallel or nibble mode, an even or odd parity bit is generated per transfer (THSPAROEG, 0x3C). The output sync can be programmed to be active on the first clock cycle of the frame (A1-1 coincident with sync) or the last clock cycle of the frame (THSSA1orEND, 0x3C). The output clock, sync, and data signals can be placed in a high-impedance state under user control ( THSCHIZ = 1, THSSHIZ = 1, THSDHIZ = 1, 0x3D). Unused outputs in serial and nibble mode will be placed in a high- impedance state automatically by the device. Receive Direction Overview The following functions are performed in the receive direction: input retime, clock and data recovery, STS-3/STM-1 (AU-4) framing, loss-of-signal detection, loopback select logic, RSTS-3/STM-1 (AU-4) frame synchronous descrambling, TOAC drop, B1, B2, and B3 checking, monitoring functions, pointer interpretation, data demultiplex and conversion (AU-4 mode only), STS-1/AU-3 output byte control, B1 and B2 generate, STS-1/AU-3 output scramble, output selection logic, and output data formatter.

2424 Agere Systems Inc. Data Sheet April 2001TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer Receive Direction Overview (continued) Input Retime The device accepts either a serial 155.52 MHz-Mbits/s, nibble 38.88 MHz-Mbits/s, or byte parallel 19.44 MHz- Mbits/s clock-data STS-3/STM-1 (AU-4) input. This is controlled by writing to RHSPTYPE[1:0], 0x55. The user can configure which edge of the clock to use to retime the data. RHSEDGE, 0x55 = 1 uses the rising edge; RHSEDGE = 0 uses the falling edge. If in nibble or parallel mode, an odd/even parity bit (RHSVOEPAR, 0x55) is verified per transfer (RHSPARE, RHSPARM, 0x0A, 0x13), otherwise, this indicator is disabled. Clock and Data Recovery The device provides an optional clock and data recovery circuit (CDR) on the serial STS-3/STM-1(AU-4) input. The CDR aligns the STS-3/STM-1 data signal to a local clock and then outputs a retimed data and clock signal. The input data and local clock rates need not be synchronous. The CDR only works at the nominal 155 Mbits/s rate and uses the high-speed transmit input clock (THSSCLKIT/C) as a reference for the local clock. The CDR is enabled by the RHSPORCDRSEL bit, 0x57. STS-3/STM-1 (AU-4) Framing The device will frame on the input STS-3/STM-1 (AU-4) signal. The state of the framer ( RHSOOF), as well as any changes to this state (RHSOOFD, RHSOOFM, 0x0A, 0x13), will be reported. A loss-of-frame (RHSLOF, 0x1B) state bit, as well as any changes to this state (RHSLOFD, RHSLOFM, 0x0A, 0x13), will be reported. Framing Algorithm The 32-bit (A1-2, A1-3, A2-1, A2-2) framing pattern will be used in the frame detection. The device will be consid- ered out of frame until two successive framing patterns separated in time by 125 µs occur without framing byte errors. The device will be considered in frame until five (SDH)/four (SONET) successive frames separated in time by 125 µs occur with errored framing patterns. If the framer transitions to the out-of-frame state, the framer will remain synchronized to the last known frame boundary or the latest detected unerrored framing pattern. The device will be considered in the loss-of-frame state (LOF) when an OOF condition persists for 24 consecutive frames (3 ms). The device will transition out of the LOF state after receiving 24 consecutive frames with the correct framing patterns spaced 125 µs apart and the OOF condition is clear. Loss of Signal The device will detect a loss-of-signal condition by monitoring a unique input signal pin (RHSLOSEXTI) or detect- ing a continuous all-zeros/all-ones pattern for 51.44 ns to 105 µs in 51.44 ns steps (LOSDETCNT[10:0], 0x58— 0x59) before data is descrambled. To recover from the LOS state receiving two consecutive frames with the correct framing pattern spaced 125 µs apart without an incoming LOS all-zeros/ones pattern will cause an LOS state to be cleared. This recovery applies to both internal and external LOS failure causes. The device will report this condition to the microprocessor interface (RHSLOS, RHSLOSD, RHSLOSM, 0x1B, 0x0A, 0x13).

Agere Systems Inc. 25 Data Sheet April 2001 TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer Receive Direction Overview (continued) Loopback Select Logic The device can be configured to loopback the transmit STS-3/STM-1 (AU-4) (THS2RHSLB = 1, 0x55) or accept the local STS-3/STM-1 (AU-4) signal (THS2RHSLB = 0). While in the loopback mode, the RHSOOF, RHSLOF, and RHSLOS (0x1B) state bits are inhibited from causing an alarm indication signal (AIS) from being generated on the STS1/AU-3 output signals. RSTS-3/STM-1 (AU-4) Frame Synchronous Descrambling (SONET/SDH) The device will descramble the received SONET/SDH data (minus the first row of SOH) according to the frame synchronous descrambling polynomial; specifically: f(x) = 1 + x 6 + x7. Under software control, frame descrambling can be disabled (RHSDSCR = 1, 0x55). TOAC Drop This channel drops all of the transport overhead bytes from the STS-3/STM-1 (AU-4) signal. (See RTOAC in the Maintenance Functions section, page 44, for more details (RTOACCLKO, RTOACSYNCO, RTOACDATAO)). B1, B2, and B3 Checking The device will monitor the incoming B1, B2, and B3 values for errors. The error counts will be latched when the LATCH_CNT signal transitions from a low to a high (RHSB1ECNT[15:0], RHSB2ECNT[17:0], RHSB3ECNT[3—1][15:0], Page 1 - 0x8D—0x8E, Page 1 - 0x8F—0x91, Page 1 - 0x92—0x97 ). These counters will either count bit or block errors (BITBLOCKCNT, 0x34). Monitoring Functions The following transport overhead and path overhead bytes are monitored for failures or changes in states ((J0, Z0-2, Z0-3, F1, K1K2 (APS bytes), S1, M1), (J1,C2, G1, F2, H4, Z3, Z5)). The bit error rate of the incoming STS-3/ STM-1 (AU-4) signal is calculated to create signal fail and signal degrade indicators. (See Maintenance Functions Disabled During Failure Conditions in the Maintenance Functions section, page 28, for more details.) Pointer Interpretation The device will evaluate the current pointer state for the normal state, Path AIS (PAIS) state, or loss-of-pointer (LOP) conditions, as well as pointer increments and decrements (that are counted in RPTR_INC[3—1][10:0] and RPTR_DEC[3—1][10:0] counters (0x98—0xA3), respectively). The current pointer state (RLOP[3—1], RPAIS[3—1], 0x1C) and any changes in pointer condition (RLOPD[3—1], RLOPM[3—1], RPAISD[3—1], RPAISM[3—1], 0x0B, 0x14), are reported to the control system. When the device is receiving a concatenated sig- nal (STM-1(AU-3)), the RCONCATMODE, 0x55 bit must be set for the concatenation state machines (CONCAT_STATE[3—2][1:0], 0x1C, 0x1D) on ports 2 and 3 to contribute to pointer evaluation. This state machine implements the pointer interpretation algorithm described in ETS 300 417-1-1: January 1996 - Annex B. The number of consecutive conditions for invalid pointer and invalid concatenation indication are programmable with a range 8—10 (CNTCIP_ICI[1:0], 0x5F).

speed signal is byte demultiplexed and no format conversion occurs.

1. Values from the high-speed STS-3/STM-1 signal can be copied or set to the byte default.
2. Values can be inserted under software control.
3. Values can be inserted under hardware control.

tion provides details for selecting each control mode. 2.Input pass or default value. (POH can start anywhere within the SPE). Note: X = don’t care (payload). B2 values on a per STS-1/AU-3 basis (RB1ERRINS[3—1], RB2ERRINS[3—1], 0x63). Table 9. STS-1/AU-3 Format and Overhead Control Summary

The device allows scrambling of the output signals on a per-output basis (RLSSCR[3—1], 0x57). bits (RSEL[3—1][1:0], 0x56) allow this to occur under software control. See Table 10. 19.44 MHz output clock can be inverted under user control (RLSCLKINV, 0x57). into a common section, a transmit section, and a receive section. Table 10. STS-1/AU-3 Output Select Control

and status information will be disabled and all BIP and far-end bit error (FEBE) counters will be held at 0. The common section addresses maintenance functions that are common to both directions. registers to their default values. A device reset is service affecting. Note: This signal must toggle from 0 → 1 → 0. The device will provide a summary of the device monitoring conditions (INT, 0x00). bits will not be cleared if the corresponding mask bit is cleared. Delta and event bits clear-on-read. Table 11. Monitors Disabled During Failure Conditions

Agere Systems Inc. 29 Data Sheet April 2001 TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer Maintenance Functions (continued) Common Maintenance and Control Functions (continued) Device Version and Device ID Number The device will have a version number (DEVVER[7:0], 0x03). The version increments each time the device func- tionality is changed, from the controller’s perspective. The device ID (DEVID[15:0], 0x01—0x02) is a fixed pattern used to identify the device by software. Scratch Byte The device will provide a 1-byte scratch register for the control interface to verify write capability to the device (SCRATCH[7:0], 0x06). Multibyte Registers If a read value parameter register requires more than 8 bits, the device must prevent the value from changing between 8-bit read commands. In these cases, the controller reads the lowest address byte first and transfers the higher address bytes to a holding register where the value is held until the controller reads them. Similarly, if a multibyte writable register is implemented, the controller writes the lowest address byte first, which is stored in a holding register until the controller writes the highest address byte, and then all of the bytes take effect. To simplify device design, the controller reads or writes all of the bytes of a multibyte register before reading or writ- ing other registers so that the holding registers may be shared among all multibyte registers. This read/write oper- ation is valid on all multibyte registers not controlled by the LATCH_CNT, 0x04 bit. Update Counter Control For performance monitoring purposes, there are a number of BIP, FEBE, and pointer interpreter increment/decre- ment error counters in the receive/transmit section. All of these internal counters are comprised of a running error counter and a hold register that present stable results to the microprocessor. The counts in all of the running counters are latched to the hold registers when LATCH_CNT, 0x04 is written from a logic 0 to a logic 1. This zeros all of the running counters. The results are held to be read by the microprocessor. All of the internal counters have the ability to store more than 1 second’s worth of counts, so as long as the LATCH_CNT occurs every second, or faster, no counts will be lost. In case this doesn’t happen, all of the running counters will hold their maximum value rather than roll over to 0. The following counters 1 are affected by LATCH_CNT: I TLSB1ECNT[3—1][15:0], 0x08—0x85 I TLSB2ECNT[1][17:0], 0x86—0x88 I TLSB2ECNT[3—2][15:0], 0x89—0x8C I RHSB1ECNT[15:0], 0x8D—0x8E I RHSB2ECNT[17:0], 0x8F—0x91 I RHSB3ECNT[3—1][15:0], 0x92—0x97 I RPTR_INC[3—1[10:0], 0x98—0x9D I RPTR_DEC[3—1][10:0], 0x9E—0xA3 I RSFEBECNT[17:0], 0xA4—0xA6 I RPFEBECNT[3—1][15:0], 0xA7—0xAC 1 All addresses for these counters are in Page 1 registers.

3030 Agere Systems Inc. Data Sheet April 2001TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer Maintenance Functions (continued) Common Maintenance and Control Functions (continued) Bit or Block Count The device allows all counters, except the pseudorandom error counter, to either count the actual number of bit errors or the number of blocks (a block equals one frame) that contain an error (BITBLOCKCNT, 0x34). The section and path FEBE counters count the actual number of bit errors or the number of blocks that contain an error (FEBEBITBLOCKCNT, 0x34). Transmit Functions The transmit section addresses maintenance functions that are unique to the transmit direction. Parity (B1, B2, B3) The device will perform a bit interleaved BIP-8 parity (B1) calculation and will write these bits into the B1 section overhead byte. The device will perform a bit interleaved BIP-24 parity (B2) calculation and will write these bits into the B2 line overhead byte. The device will perform a bit interleaved BIP-8 parity (B3) calculation and will write these bits into the B3 path overhead byte (AU-4 mode only). The device can perform a B1 (THSB1ERRINS, 0x4C), B2 (THSB2ERRINS[3—1], 0x4C), and B3 (THSB3ERRINS, 0x4C) parity byte inversion via microprocessor control. A1, A2 Error Enable The device will allow, under software control, from 1 to 32 continuous frames to have errored A1A2 patterns in the outgoing frame (TA1A2ERRINS[4:0], 0x4D and TA1A2ERREN, 0x04). Section Trace/Growth Byte Insert (J0/Z0) The device inserts the data written into TJ0DINS[7:0], 0x3F, TZ02DINS[7:0], 0x40, and TZ03DINS[7:0], 0x41 into the outgoing J0/Z0 bytes. Fault Location Insert (F1) Via microprocessor control of TF1INS, 0x3E and TF1DINS[7:0], 0x42, data information may be inserted into the outgoing F1 byte. Direct microprocessor insert has higher priority than the TOAC insert control bit (TTOAC_F1[1:0], 0x51). Sync Status Byte Insert (S1) Via microprocessor control of TS1INS, 0x3E and TS1DINS[7:0]0x45, data information may be inserted into the outgoing S1 byte. Direct microprocessor insert has higher priority than the TOAC insert control bit (TTOAC_Z1[1:0], 0x51). Automatic Protection Switch (APS) Insertion (K1[7:0], K2[7:3]) The device writes the K1 and K2 bytes into the transmit K1 and K2 overhead bytes (TAPSINS[12:0], 0x43, 0x44). The K1 and K2[7:3] bits will only change when both values are valid. The TAPSINS[4:0], 0x44 byte is the trigger for updating the APS bytes in the outgoing frame.

Agere Systems Inc. 31 Data Sheet April 2001 TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer Maintenance Functions (continued) Transmit Functions (continued) APS Babbling Test Control Setting the TAPSBABLEINS, 0x4D register, via microprocessor control, forces the APS bytes (K1[7:0], K2[7:3]) to an inconsistent state. Line Remote Defect Indication (RDI-L) Insertion (K2[2:0] = 110) The device will write Line RDI into the data signal using the following equation: TLRDIINT =(RILOC AND TRILOC_LRDIINH) OR (RHSLOS AND TRHSLOS_LRDIINH) OR (RHSOOF AND TRHSOOF_LRDIINH) OR (RHSLOF AND TRHSLOF_LRDIINH) OR (RLAISMON AND TRLAISMON_LRDIINH) OR (RHSSF AND TRHSSF_LRDIINH); (See 0x1A, 0x1B, 0x1D, and 0x4A.) Hardware insert of Line RDI will occur when TLRDIINT, 0x1A is active and the software insert control bit (TLRDIINH, 0x4A) is disabled. User-provided data (TK2INS[2:0], 0x43) will be inserted into the K2[2:0] bits in the STS-3/STM-1 (AU-4) frame when TLRDIINH = 0. The insertion of Line RDI consists of writing the pattern 110 into the three LSBs of the K2 LOH byte. Unequipped and AIS Generation (Automatic/Manual) Line AIS or AU4-AIS or TUG-3 AIS can be generated automatically by the hardware under certain failure condi- tions or via microprocessor control only. This is accomplished with the following equations and control signals: FAILURE[3—1] = (( TLSOOF[3—1] AND TLSOOF_AISINH[3—1]) OR (TLSLOF[3—1] AND TLSLOF_AISINH[3—1])) H4PTRMIS[3—1] = (( TLSH4MIS[3—1] AND TLSH4MIS_AISINH[3—1]) OR (TLSPTRMIS[3—1] AND (TLSPTRMIS_AISINH[3—1])) AND STS1_AU4; AU-4 mode only LAIS[3—1] = TLS_LAISINS[3—1] OR FAILURE[3—1] OR H4PTRMIS[3—1]; AU4AISGen = LAIS1 AND LAIS2 AND LAIS3; (See 0x1A, 0x37, 0x39, 0x3B.) Each alarm contribution that can cause AIS generation can be selectively inhibited. Line AIS is generated in the STS-3 mode per STS-1 input when the appropriate FAILURE[3—1] or TLS_LAISINS[3—1] (software enable) sig- nals are active. (Line overhead and the entire payload is set to an all-ones pattern.) In this mode, the H4PTRMIS[3—1] contribution will always be 0. AU4-AIS generation will set all H1, H2, H3, and payload bytes to an all-ones pattern in the output STM-1 (AU-4) signal. TUG-3 AIS generation will force all the data in the selected TUG-3 signal to be set to an all-ones pattern. In the STS-3 mode, an unequipped signal can be generated for any STS1 input under software control (TLS_UNEQUIP[3—1], 0x3B, 0x39, 0x37 and (H1 = 0110SS00 AND H2 = 00000000)) and the selected payload is set to 0). In AU-4 mode, the H1 and H2 bytes will not change from their default values and the entire payload will be set to 0. The SS bits will be set to the value written into register bits (TSS[1:0], 0x3E). AIS generation has higher priority than unequipped signal generation.

3232 Agere Systems Inc. Data Sheet April 2001TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer Maintenance Functions (continued) Transmit Functions (continued) H1 and H2 Corruption Setting the TH1H2CRUPEN[3—1], 0x4E, register, via microprocessor control, allows the outgoing H1 and H2 val- ues to be corrupted for each STS-1 channel. Either an invalid pointer or a continuous new data flag can be inserted (TH1H2CRUPPorNDF, 0x4E). Loss-of-Transmit Clock or Loss-of-Frame Sync The device will detect a loss-of-transmit clock condition for the clock input in the transmit direction. Also, the device was designed to detect a loss-of-frame sync for the frame sync input signal (Note, the loss-of-frame sync (TILOF) feature is not supported in version 3 of the device). The state of TILOC and TILOF (0x19) along with any changes to TILOCFD and TILOCFM (0x07 and 0x10) will be reported to the control system. Transmit Clock Frequency Provisioning The device must be provisioned (THSCLKTYPE[1:0], 0x3C) with the speed (155.52 MHz—bit, 38.88 MHz— nibble, 19.44 MHz—byte) of the transmit clock. This information is needed to set the internal clock divider circuitry and determine valid output port modes (e.g., a byte clock input cannot support a serial output port at 155.52 Mbits/s).

The device will insert SFEBE in the transmitted M1 byte whenever there are bit errors in the received B2 bytes. (SONET). The device can insert a continuous error into the M1 byte under user control (TSFEBEEINS, 0x4D). SFEBE will be inserted into the M1 byte as defined in Figure 3. Figure 3. SFEBE Location The values for SFEBE are summarized in Table 12. Table 12. SFEBE Values

00011001 No errors

STM-1 (AU-4) signal when the TJ1INS signal is active; otherwise, all zeros will be inserted into this byte. The device will allow data to be inserted into the outgoing C2 byte under software control (TC2DINS[7:0], 0x46). The G1 byte contains the PFEBE (B3 errors) as shown in Table 13. The values for PFEBE are summarized in Table 14. Table 13. G1 Byte—AU-4 Mode Only Table 14. PFEBE Values

1001 No errors

Agere Systems Inc. 35 Data Sheet April 2001 TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer Maintenance Functions (continued) Transmit Functions (continued) Path - G1 Status Byte (RDI-P)—AU-4 Mode Only The G1 byte contains the RDI-P bit as shown in Table 13. Path RDI is inserted automatically under hardware control. Each failure contribution can be excluded from the gen- eration equation by setting the appropriate inhibit bit. TPRDIINT =( ( RILOC AND TRILOC_PRDIINH), 0x4B, OR (RHSLOS AND TRHSLOS_PRDIINH), 0x4B, OR (RHSOOF AND TRHSOOF_PRDIINH), 0x4B, OR (RHSLOF AND TRHSLOF_PRDIINH), 0x4B, OR (RLAISMON AND TRLAISMON_PRDIINH), 0x4B, OR (RPAIS1 AND TRPAIS1_PRDIINH), 0x4B, OR (RLOP1 AND TRLOP1_PRDIINH), 0x4B, OR TPRDIINS (software insert)); (See 0x1A, 0x1B, 0x4B.) PRDI can be forced, via microprocessor control, by setting TPRDIINS to a logic 1. Path - User Channel Byte (F2)—AU-4 Mode Only Via microprocessor control of the (TF2DINS[7:0], 0x47), data information may be inserted into the outgoing F2 byte. Path - Growth Byte (Z3)—AU-4 Mode Only Via microprocessor control of the (TZ3DINS[7:0], 0x48), data information may be inserted into the outgoing Z3 byte. Path - Tandem Connection Byte (Z5)—AU-4 Mode Only Via microprocessor control of the (TZ5DINS[7:0], 0x49), data information may be inserted into the outgoing Z5 byte. Pseudorandom Test Pattern Insert—AU-4 Mode Only A pseudorandom test sequence can be inserted into any selected (TSTGEN_PSEL[1:0], 0x4E) TUG-3 within the AU-4 signal. The pattern can be selected from the following two equations: Q23 + Q17 + 1 or Q15 + Q14 + 1 (TPAT23or15, 0x4E). A one shot is provided to inject eight (8) errors into the selected pseudorandom sequence (TSTGENE8INS, 0x04). A value of zero in the TSTGEN_PSEL[1:0] register disables this function.

frame sync. These registers allow movement of the output frame with a granularity of one high-speed clock cycle. must be within the valid ranges for the mode selected (see Table 15). See Table 56 on page 77 for more details. I A 5.184 MHz clock signal, sourced by the device (TTOACCLKO, TTOAC_CLKINV). I A 5.184 Mbits/s data signal received by the device in the transmit direction (TTOACDATAI). bit over the 648 bits of the previous frame. The remaining 7 bits of this byte are not specified. not specified in the standard, but are labeled here for clarity. X symbols indicate don’t cares. Table 15. Value Offset Load Values Table 16. Transport Overhead Byte Access—Transmit Direction

checked (TTOAC_OEPMON, TTOAC_PERRM, TTOAC_PERRE, 0x4F, 0x10, 0x07). STS-1/AU-3 value to be inserted into the outgoing STS-3 frame. Table 17. TTOAC Control Bits

1. See Address 0x50, 0x51 for control bits.

3838 Agere Systems Inc. Data Sheet April 2001TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer Maintenance Functions (continued) Receive Functions A number of the receive maintenance functions require a continuous N times detection (CNTD) of a signal to change an alarm status. All of these continuous N times detect signals require not only that the monitored signal be consistent for N consecutive frames, but also that the frame bytes, A1 and A2, be error free for all N frames before the status can be updated. If there are any errors in the framing pattern, then the consecutive N times detection counters must be reset to 0. N can range from 3 to 15. There is also a signal (CNTDB1SEL, 0x5F) that will cause these continuous N times detection counters to be reset to 0 if there are any errors in the received B1 byte. Continuous N Times Detect B1 Error Reset Enable The following CNTD monitors are affected by this control bit (CNTDB1SEL): 3. K2MON (K2[2:0]) 4. APSMON (K1[7:0], K02[7:3]) Receive Loss of Clock The device will detect a receive loss-of-clock (RILOC, 0x1B) condition for the clock input and notify the control sys- tem of any changes to this condition (RILOCD, 0x0A, and RILOCM, 0x13). Insertion of Line AIS (Automatic/Manual) The device will write Line AIS into each STS-1/AU-3 output signal if either the appropriate alarms occur or the soft- ware insert bit is active. LAIS_COMMON = (( RILOC AND RRILOC_AISINH) OR (RRHSOOF AND RHSOOF_AISINH) OR (RHSLOF AND RRHSLOF_AISINH) OR (RHSLOS AND RRHSLOS_AISINH) OR (LAISMON AND RRLAISMON_AISINH)); (See 0x1B, 0x58.) If (RLAISINS[3—1] = 1 OR LAIS_COMMON = 1), then insert Line AIS on the selected output. When a RILOC condition exists, the transmit clock is used to generate the Line AIS signal downstream, if possible. Insertion of Path AIS (Automatic) The device will write Path AIS into each STS-1/AU-3 output signal if the appropriate alarms occur. PAIS_COMMON[3—1] = ((PAIS[3—1] OR LOP[3—1]) AND PAISLOP_AISINH If (PAIS_COMMON[3—1] = 1), then insert Path AIS on the appropriate output. (PAIS consists of writing all ones into the H1, H2, H3 bytes, and into the entire payload.) B1 BIP-8 Parity The device will perform B1 (BIP-8) calculation and error checking in the receive path. The device will allow access to the B1 errored bit/block (one block is equal to one frame) count (BITBLOCKCNT, 0x34, RHSB1ECNT[15:0], 0x8D-0x8E). This counter will update when LATCH_CNT transitions from a logic 0 to a logic 1.

Agere Systems Inc. 39 Data Sheet April 2001 TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer Maintenance Functions (continued) Receive Functions (continued) B2 BIP-24 Parity The device will perform B2 (BIP-24) calculation and error checking. The device will allow access to the B2 errored bit/block (one block is equal to one frame) count (BITBLOCKCNT, 0x34, RHSB2ECNT[16:0], Page 1 - 0x8F— 0x91). This counter will update when LATCH_CNT, 0x04 transitions from a logic 0 to a logic 1. Signal Degrade BER Algorithm A signal degrade state and change of state indication will be provided to the control interface ( RHSSD, RHSSDD, RHSSDM, 0x1B, 0x0A, 0x13). This bit error rate algorithm can operate on either B1 or B2 errors (SDB1B2SEL, 0x83). Signal degrade is declared when SDLSet[3:0], Page 2 - 0x83 or more bit errors in SDNsSet[18:0], Page 2 - 0x8E—0x90 and frames occur SDMSet[7:0], Page 2 - 0x84 times out of SDBSet[11:0], Page 2 - 0x85—0x86 blocks (one block is equal to one measurement period of SDNsSet[18:0] frames), and it is removed when less than SDLClear[3:0], Page 2 - 0x8A bit errors in SDNsClear[18:0], Page 2 - 0x87—0x89 frames occur SDM- Clear[7:0], Page 2 - 0x8B times out of SDBClear[11:0], Page 2 - 0x8C—0x8D blocks. The above algorithm can detect bit error rates from 1 x 10 –3 to 1 x 10–9. Signal Fail BER Algorithm A signal fail state and change of state indication will be provided to the control interface ( RHSSF, RHSSFD, RHSSFM, 0x1B, 0x0A, 0x13). This bit error rate algorithm can operate on either B1 or B2 errors (SFB1B2SEL, Page 2 - 0x91). Signal fail is declared when SFLSet[3:0], Page 2 - 0x91 or more bit errors in SFNsSet[18:0], Page 2 - 0x8E—0x90 frames occur SFMSet[7:0], Page 2 - 0x92 times out of SFBSet[11:0], Page 2 - 0x93—0x94 blocks (one block is equal to one measurement period of SFNsSet[18:0] frames), and it is removed when less than SFLClear[3:0], Page 2 - 0x98 bit errors in SFNsClear[18:0], Page 2 - 0x96—0x98 frames occur SFMClear[7:0], Page 2 - 0x99 times out of SFBClear[11:0] Page 2 - 0x9A—0x9B blocks. The above algorithm can detect bit error rates from 1 x 10 –3 to 1 x 10–9. Section Trace (J0, Z0-2, Z0-3) Byte Monitoring The device will monitor the section trace bytes (RJ0MON[7:0], RZ02MON[7:0], RZ03MON[7:0], RCDRLOC, 0x1E, 0x1F, 0x20, 0x1B) on the receive input. A new section trace value will be detected after CNTDJ0Z0[3:0], 0x5A and consecutive consistent occurrences of a new pattern in the section trace overhead bytes. Any changes to these bytes will be reported to the control system (RJ0Z0MOND, RJ0Z0MONM, 0x0C, 0x15). Fault Location Monitoring (F1MON) The device will monitor the fault location byte (RF1MON0[7:0], 0x21) on the receive input. A new fault location state will be detected after CNTDF1[3:0], 0x5A consecutive consistent occurrences of a new pattern in the F1 overhead byte. The device will also maintain a history of the previous valid F1 byte (RF1MON1[7:0], 0x22). Any changes to this byte will be reported to the control system (RF1MOND, RF1MONM, 0x0C, 0x15). Automatic Protection Switch (APS) Monitoring The device will monitor the K1 byte and the K2 byte (5 MSBs only) on the input side of the device receive path (RAPSMON[12:0], 0x23, 0x24). After CNTDAPS[3:0], 0x5B consecutive consistent occurrences of new K1 and K2 bytes, the device will notify the control system (RAPSMOND, RAPSMONM, 0x0B, 0x14).

4040 Agere Systems Inc. Data Sheet April 2001TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer Maintenance Functions (continued) Receive Functions (continued) APS Babbling Monitor The device will monitor the APS bytes (K1[7:0], K2[7:3]) in the receive direction and report to the control interface (RAPSBABLEE, RAPSBABLEM, 0x0C, 0x15) when the K1 bytes are inconsistent. Inconsistent APS bytes are defined as CNTDAPSFRAME[3:0], 0x5C (Default = 12) successive frames, starting with the last frame containing previously consistent code, where no CNTDAPS[3:0], 0x5B (Default = 3) consecutive frames contain identical APS bytes. Line AIS (AIS-L) Monitoring The device will monitor line AIS on the receive input (RLAISMON, 0x1D). Line AIS will be detected after CNTDK2[3:0], 0x5B consecutive occurrences of the AIS-L pattern (xxxxx111) in the K2 overhead byte. Any changes to this byte will be reported to the control system (RLAISMOND, RLAISMONM, 0x0C, 0x15). Line Remote Defect Indication (RDI-L) Monitoring The device will monitor an RDI-L condition on the receive input (RLRDIMON, 0x1D). A Line RDI condition will be detected after CNTDK2[3:0] consecutive occurrences of the Line RDI pattern (xxxxx110) in the K2 overhead byte. Any changes to this byte will be reported to the control system (RLRDIMOND, RLRDIMONM, 0x0C, 0x15). K2 Byte Monitoring The device will monitor the K2 byte (3 LSBs only) on the input side of the receive direction (RK2MON[2:0], 0x23). After CNTDK2[3:0], 0x5B consecutive consistent occurrences of new K2 bits, the device will notify the control sys- tem (RK2MOND, RK2MONM, 0x0B, 0x14). Sync Status (S1) Byte Monitoring The device will monitor the sync trace byte (RS1MON[7:0], 0x25) on the receive input. A new sync trace value will be detected after CNTDS1[3:0], 0x5C consecutive consistent occurrences of a new pattern in the overhead bytes. Any changes to this byte will be reported to the control system (RS1MOND, RS1MONM, 0x0C, 0x15). Section FEBE (M1) Monitoring The device will monitor a Section FEBE condition (M1) on the receive input. The device will allow access to the Section FEBE errored bit/block (one block is equal to one frame) count (FEBEBITBLOCKCNT, 0x34, RSFEBECNT[17:0], Page 1 - 0x34, 0xA4, 0xA6). This counter will update when LATCH_CNT transitions from a logic 0 to a logic 1. AU-4 NPI (Null Pointer Indication) Monitoring The device will monitor the three NPI values in the incoming STM-1(AU-4) signal. When five consecutive mis- matches occur (any one of the three NPI values are in error) separated in time by 125 µs, the device will declare an NPI mismatch condition. An NPI match condition is declared when two consecutive matches occur (all three NPI values match), separated in time by 125 µs. The delta, mask, and state bits are RHSNPIMISD, RHSNPIMISM, RHSNPIMIS, 0x0D, 0x16, 0x1D, respectively.

Agere Systems Inc. 41 Data Sheet April 2001 TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer Maintenance Functions (continued) Receive Functions (continued) STM-1(AU-4) H4 Multibyte Monitor The device will monitor the path H4 byte for correct multibyte sequence. Each time the expected value mismatches with the received value, an event indication is set. When a mismatch occurs, the device accepts the new value plus 1 as the expected value for the next frame. The event and mask bits are RHSH4MISE, RHSH4MISM, 0x0D, 0x16. Path Trace Byte (J1) Monitoring The device will monitor the path trace byte (RJ1MON[64—1][7:0], 0xC0—0xFF) on the receive input. Only one J1 byte can be monitored (J1PSELMON[1:0], 0x56) out of the three possible J1 bytes. The device will store a 64-byte sequence and declare a mismatch each time the incoming value does not agree with the stored value ( RJ1MISE, RJ1MISM, 0x0C, 0x15). Path Signal Label (C2) Monitoring The device will monitor the C2 bytes on the receive input (RC2MON[3—1][7:0], 0x28, 0x27, 0x26). After CNTDC2[3:0], 0x5D consecutive consistent occurrences of a new C2 byte, the device will notify the control system (RC2MOND[3—1], RC2MONM[3—1], 0x0D, 0x16). Path FEBE (G1) Byte Error Count The device will monitor for a path FEBE condition (G1[7:4]) on the input signal. The device will allow access to the path FEBE errored bit/block (one block is equal to one frame) count (FEBEBITBLOCKCNT, RPFEBECNT[3—1][15:0], 0x34, 0xA7—0xAC). These counters will update when LATCH_CNT, 0x04 transitions from a logic 0 to a logic 1. Path RDI (Path Yellow (G1[3] or Enhanced Failure Code (G1[3:1]))) The device will monitor the G1 bytes for path yellow condition or for an enhanced failure code (RRDI_MPYorEFC, 0x55) on the receive input (RRDIP[3—1][2:0], 0x32, 0x33). After CNTDG1[3:0], 0x5D consecutive consistent occurrences of a new G1 value, the device will notify the control system (RRDIPE[3—1], RRDIPM[3—1], 0x16). Path User Channel (F2) Monitoring The device will monitor the F2 byte (RF2MON[3—1][7:0], 0x29, 0x2A, 0x2B) on the receive input. A new value will be detected after CNTDF2[3:0], 0x5E consecutive consistent occurrences of a new pattern in the overhead bytes. Any change to this byte will be reported to the control system (RF2MOND[3—1], RF2MONM[3—1], 0x0E, 0x17). Path Growth Byte (Z3) Monitoring The device will monitor the Z3 bytes (RZ3MON[3—1][7:0], 0x2C, 0x2D, 0x2E) on the receive input. A new value will be detected after CNTDZ3[3:0], 0x5E consecutive consistent occurrences of a new pattern in the overhead bytes. Any change to this byte will be reported to the control system (RZ3MOND[3—1], RZ3MONM[3—1], 0x0E, 0x17). Path Tandem Connection Byte (Z5) Monitoring The device will monitor the Z5 bytes (RZ5MON[3—1][7:0], 0x31, 0x30, 0x2F) on the receive input. A new value will be detected after CNTDZ5[3:0], 0x5F consecutive consistent occurrences of a new pattern in the overhead bytes. Any change to this byte will be reported to the control system (RZ5MOND[3—1], RZ5MONM[3—1], 0x0F, 0x18).

the LATCH_CNT, 0x04 signal. The detector will transition to the in-sync-state after 32 consecutive matches occur. The detector will transition from the in-sync-state to the out-of-sync state if 32 consecutive errors are detected. bytes pass through from the input signal. Table 18. STS-1/AU-3 Overhead Control (RA1A2ERRPEN[3—1]) else insert correct framing pattern. 1 = insert error, 0 = insert normal value. E1 1 = pass input data, 0 = insert default value. else set byte to the default value. D1 to D3 1 = pass input data, 0 = insert default value. 1 = insert error, 0 = insert normal value. else insert software value RAPSINS.

Table 18. STS-1/AU-3 Overhead Control (continued)

1. Software enable when all hardware inhibit signals are 1.

D4 to D12 1 = pass input data, 0 = insert default value. S1 1 = pass input data, 0 = insert default value. else output B2 errors per frame from the associated transmit input. E2 1 = pass input data, 0 = insert default value.

1. 5.184 MHz clock signal, sourced by the device ( RTOACCLKO, RTOAC_CLKINV).
2. A 5.184 Mbits/s data signal, sourced by the device ( RTOACDATAO).
3. An 8 kHz synchronization signal, sourced by the device. The sync signal is normally low; during the last clock

significant bit of the first byte, the sync signal can go high (RTOACS_A1orEND, 0x4F). impedance state (RTOACINH, 0x4F). odd/even parity bit over the 648 bits of the previous frame. The remaining 7 bits of this byte are not specified. not specified in the standard, but are labeled here for clarity. Table 19. Transport Overhead Byte Access—Receive Direction

Using the device without internal loopbacks results in a multiplex/demultiplex operation. Figure 4. Line Termination Multiplex

operate at speeds up to 32.768 MHz in interrupt-driven or polled modes without requiring any wait-states. Table 20 highlights the four microprocessor modes controlled by the MPMUX and MPMODE inputs. Table 20. Microprocessor Configuration Modes

• When the MPMODE3ALE input pin = 0, ALE is not used to retime the incoming address.

same set of pins in all modes. Table 21. MODE [1—4] Microprocessor Pin Definitions

Table 21. MODE [1—4] Microprocessor Pin Definitions (continued)

section are given in decimal, with the hexadecimal representation in parentheses. Table 22. Device-Level Register Map

• Shaded blocks are reserved for future or internal use.

Table 22. Device-Level Register Map (continued)

• Shaded blocks are reserved for future or internal use.

• Shaded blocks are reserved for future or internal use.

Table 23. Page 0—J1 Byte Insert and Monitor

• Shaded blocks are reserved for future or internal use.

Table 24. Page 1—Error Counters

• Shaded blocks are reserved for future or internal use.

Table 25. Page 2—BER Algorithm Parameters

indicate if the register is read only (RO), clear-on-read (COR), or read/write (R/W). Table 26. Register 0 (RO) Table 27. Registers 1—3 (RO) Table 28. Registers 4, 5: One-Shot Register 0 → 1 (R/W) Mask Bit Operation on page 28). which uniquely identifies the device. which uniquely identifies the device. will change each time the device is changed. errors into the output STS-3/STM-1 (AU-4) signal. be forced into the normal state. be forced into the failed state. algorithm to be forced into the normal state. algorithm to be forced into the failed state.

Table 28. Registers 4, 5: One-Shot Register 0 → 1 (R/W) (continued) Table 29. Register 6: Scratch Register (R/W) Table 30. Registers 7—15: Delta/Event (COR-RO) hold at least one second’s worth of data. errors into the respective output STS-1/AU-3 signal. without affecting device operation. 7 (0x07) 7 TILOCFD Transmit Input Loss of Clock and Frame Delta. clock (TILOC, 0x19) or frame sync (TILOF, 0x19).

Table 30. Registers 7—15: Delta/Event (COR-RO) (continued) 9 (0x09) 2—0 TLSPTRMISD[3—1] Transmit Low-Speed Pointer Mismatch Delta. RHSSFM, 0x13 and RHSSDM, 0x13.

K2[7:3] bits of the input STS-3/STM-1 (AU-4) frame. Its mask bit is RAPSMONM, 0x14. supported in version 3 of the device. (AU-4) signal. Its mask bit is RPAISM[3—1], 0x14. Only port 1 information is valid in AU-4 mode.

12 (0x0C) 2 RS1MOND Receive S1 (Sync Status) Byte Monitor Delta. frame. Its mask bit is RS1MONM, 0x15. ous F1 value. Its mask bit is RF1MONM, 0x15.

12 (0x0C) 0 RJ0Z0MOND Receive Composite J0, Z0-2, Z0-3 Monitor Delta. frame. Its mask bit is RJ0Z0MONM, 0x15. frame. Its mask bit is RHSNPIMISM, 0x16. 01, 10, and 11 should repeat in consecutive frames. next frame. Its mask bit is RHSH4MISM, 0x16.

Table 31. Registers 16—24: Mask Bits (R/W) port 1 information is valid in AU-4 mode. port 1 information is valid in AU-4 mode. 15 (0x0F) 2—0 RZ5MOND[3—1] Receive Z5 (Tandem Connection) Monitor Delta. port 1 information is valid in AU-4 mode. Mask. See (addr 0x07) for description. (addr 0x07) for description.

Table 31. Registers 16—24: Mask Bits (R/W) (continued) (addr 0x08) for description. (addr 0x08) for description. (addr 0x09) for description. 18 (0x12) 2—0 TLSPTRMISM[3—1] Transmit Low-Speed Pointer Mismatch Mask. See (addr 0x09) for description. (addr 0x0A) for description. (addr 0x0A) for description. (addr 0x0A) for description. (addr 0x0A) for description. (addr 0x0A) for description.

Table 32. Registers 25—51: State Bits (RO) (addr 0x0D) for description. (addr 0x0D) for description. (addr 0x08) for description. (addr 0x08) for description. (addr 0x09) for description. 26 (0x1A) 2—0 TLSPTRMIS[3—1] Transmit Low-Speed Pointer Mismatch (State). See (addr 0x09) for description. clock is missing. This is an active-high signal. (addr 0x0A) for description. (addr 0x0A) for description.

Table 32. Registers 25—51: State Bits (RO) (continued) 27 (0x1B) 4 RHSLOSEXTI Receive High-Speed Loss-of-Signal (External). See (addr 0x0A) for description. (addr 0x0A) for description. (addr 0x0A) for description. (addr 0x0A) for description. (addr 0x0D) for description. Concatenation Pointer State Machine State. 0x55) set to the concatenation mode (1). been detected (CNTDK1[3:0]) times. 1/AU-3 basis in the device receive path.

Table 33. Register 52: Mode Control (R/W) Receive RDI-P Monitor Path Values (G1 Byte). See (addr 0x0D) for description. tie the external mode control pins low. 3 signals multiplexed into an STM-1 (AU-4) signal).

Table 33. Register 52: Mode Control (R/W) (continued) Table 34. Register 53: Low-Speed Transmit Common Signals (R/W) count block errors (a block equals one frame). SONET mode; otherwise, SDH mode. (AU-4) signal demultiplexed into three AU-3 signals). clock before leaving the device. 53 (0x35) 0 TLSVOEPAR Transmit Low-Speed Verify Odd or Even Parity. input; otherwise, even parity is verified.

Table 35. Register 54—59: Transmit Low-Speed Port Input Control (R/W) STS-1/AU-3 input signal to be descrambled.

7 TLS_UNEQUIP[1—3] Transmit Low-Speed Unequipped Insert Con-

6 TLS_LAISINS[1—3] Transmit Low-Speed Line AIS Insert Control. TLS_LAISINS1 is used in AU-4 mode. alarm to contribute to the generation of AIS-L.

2 TLSH4MIS_AISINH

1 TLSLOF_AISINH[1—3] Transmit Low-Speed Loss-of-Frame AIS Inhibit

0 TLSOOF_AISINH[1—3] Transmit Low-Speed Out-of-Frame AIS Inhibit

Table 36. Registers 60, 61: Transmit High-Speed Clock/Port Control (R/W) (THSCLKI, THSJ0J1V1I) are selected. logic 1 causes even parity to be generated. inverted, a logic 0 doesn’t effect the clock. 00 = serial, 01 = nibble, 10 = byte mode).

Table 36. Registers 60, 61: Transmit High-Speed Clock/Port Control (R/W) (continued) Table 37. Register 62: Transmit High-Speed Control Signals (R/W) not scrambled if set to a logic 0. output; loopback is disabled when set to a logic 0. 0 enables the output drivers. of PFEBE. Only valid in AU-4 mode.

Table 38. Register 62, and Page 0, Registers 128—191: Transmit High-Speed J1 Insert (R/W) Table 39. Register 62, 69: Transmit High-Speed Control Signals (R/W) Table 40. Register 62, 66: Transmit High-Speed Control Signals (R/W) Table 41. Registers 63—65: Trace/Growth Bytes (R/W) (AU-4) frame; a logic 0 inserts the default value. (AU-4) frame; a logic 0 inserts the default value.

Table 42. Register 66: Transmit F1 Data Byte (R/W) Table 43. Registers 67 and 68: K1 and K2 Insert Bytes (R/W) Table 44. Register 69: Transmit Sync Status Byte (R/W) Table 45. Register 70: Path Signal Trace Byte (R/W) Table 46. Register 71: Path User Channel Byte (R/W) Table 47. Register 72: Path Growth Byte (R/W) inserted into the STM-1(AU-4) output C2 byte. inserted into the STM-1(AU-4) output F2 byte. inserted into the STM-1(AU-4) output Z3 byte.

Table 48. Register 73: Tandem Connection Byte (R/W) Table 49. Register 74: Transmit High-Speed Line RDI Insertion Inhibit Bits (R/W) Table 50. Register 75: Transmit High-Speed Path RDI Insertion Inhibit Bits (R/W) inserted into the STM-1(AU-4) output Z5 byte. appropriate alarms are active. alarm contributes to the generation of RDI-L. 74 (0x4A) 4 TRLAISMON_LRDIINH Transmit Receive Line AIS Path RDI Inhibit. Line RDI Inhibit. Same as above. Line RDI Inhibit. Same as above. Line RDI Inhibit. Same as above. Path RDI under hardware control. 75 (0x4B) 5 TRPAIS1_PRDIINH Transmit Receive Path AIS Path RDI Inhibit.

Table 50. Register 75: Transmit High-Speed Path RDI Insertion Inhibit Bits (R/W) (continued) Table 51. Register 76: Transmit High-Speed Error Insert Control Parameters (R/W) 75 (0x4B) 4 TRLAISMON_PRDIINH Transmit Receive Line AIS Path RDI Inhibit. Path RDI Inhibit. Same as above. Path RDI Inhibit. Same as above. Signal Path RDI Inhibit. Same as above. the outgoing STM-1 (AU-4) signal to be inverted.

Table 52. Register 77: Transmit High-Speed Error Insert Control Parameters (R/W) Table 53. Register 78: Transmit High-Speed Error Insert (R/W) otherwise, a normal Path FEBE value is sent. a continuous NDF condition (1001) is sent.

Table 54. Register 79: Receive/Transmit TOAC Control (R/W) 79 (0x4F) 6 RTOACS_A1orEND Receive TOAC Sync A1 or Frame-End Align. frame sync with the last bit of the previous frame. parity bit to be even; otherwise, the parity is odd. 79 (0x4F) 2 TTOACSA1orEND Transmit TOAC Sync A1 or Frame-End Align. frame sync with the last bit of the previous frame. 79 (0x4F) 1 TTOAC_OEPMON Transmit TOAC Odd or Even Parity Monitor.

Table 55. Registers 80, 81: Transmit TOAC Control (R/W) AU-3 to pass through unchanged. AU-3 to pass through unchanged. to be inserted into the D1 to D3 bytes, respectively.

Table 55. Registers 80, 81: Transmit TOAC Control (R/W) (continued) overhead bytes without specific insert control bits. STS-1/AU-3 to pass through unchanged. STS-1/AU-3 to pass through unchanged. STS-1/AU-3 to pass through unchanged.

Table 56. Register 83, 84: Transmit High-Speed STS-3/STM-1 Output Frame Offset (R/W) input J0 frame sync pulse (THSSJ0J1V1I (T/C)).

7878 Agere Systems Inc. Data Sheet April 2001TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer Microprocessor Interface (continued) Register Map (continued) Otherwise TLROWCNT = rparm TLCOLCNT = cparm Equation 5. If (THSCLKTYPE = BIT and THSPTYPE = BIT) TLBITCNT = (selected bit from BITCNT Alignment Table, Table 58 on page 80.) Otherwise TLBITCNT = B Equation 6. If (THSCLKTYPE = BIT and THSPTYPE = BIT and B £ 7) If (STS #2) then TLCOLCNT = TLCOLCNT – 1 Else TLCOLCNT = TLCOLCNT If (y = 89 and STS #2 and TLROWCNT = 0) then TLROWCNT = 8 Else if (y = 89 and STS #2) then TLROWCNT = TLROWCNT – 1 Else TLROWCNT = TLROWCNT Otherwise TLSTS1CNT = S Examples 1. Align sync with D3, STS #1, THSCLKTYPE = BYTE, THSPTYPE = BYTE x = 2, y = 2 (from Table 57, A1-1 Alignment Parameters) rparm = 8 – 2 = 6 (equation #2) cparm = 87 – 2 = 85 (equation #3) TLROWCNT = 6 (equation #4) TLCOLCNT = 86 (equation #4) TLBITCNT = 0 (equation #5) TLSTS1CNT = 2 (equation #6)

Agere Systems Inc. 79 Data Sheet April 2001 TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer Microprocessor Interface (continued) Register Map (continued) 2. Align sync with row = 8, column = 89, STS #3 THSCLKTYPE = BYTE, THSPTYPE = BYTE x = 8, y = 89 (from Table 57, A1-1 Alignment Parameters) rparm = 8 – 8 = 0 (equation #2) cparm = 87 – 89 = –2 (equation #3) TLROWCNT = 8 (equation #4) TLCOLCNT = 88 (equation #4) TLBITCNT = 0 (equation #5) TLSTS1CNT = 0 (equation #6) 3. Align sync with row = 5, column = 89, STS #3 THSCLKTYPE = NIBBLE, THSPTYPE = BYTE x = 5, y = 89 (from Table 57, A1-1 Alignment Parameters) rparm = 8 – 5 = 3 (equation #2) cparm = 88 – 89 = –1 (equation #3) TLROWCNT = 3 – 1 = 2 (equation #4) TLCOLCNT = 89 (equation #4) TLBITCNT = 0 (equation #5) TLSTS1CNT = 1 (equation #6)

Table 57. A1-1 Alignment Parameters Table 58. BITCNT Alignment Table Valid for THSCLKTYPE = THSPTYPE only.

Table 59. Register 85: Receive High/Low-Speed Port Control (R/W) wise, the loopback is disabled. the signal is not descrambled. independent pointers are expected. 85 (0x55) 3 RHSVOEPAR Receive High-Speed Verify Odd or Even Parity. wise, even parity is verified.

Table 60. Register 86: Receive J1 and Receive Low-Speed Port Select Control (R/W) Table 61. Register 87: STS-1/AU-3 Receive Control Bits (R/W) 01 = port 2, 10 = port 3, 11 = undefined operation. 01 = port 2 selected, 10 = port 3 selected. wise, the output signal is not scrambled. CDR clock recovery block are used. otherwise, loopback is disabled. AU-3 receive clock is not inverted.

Table 62. Register 88: STS-1/AU-3 Receive Low-Speed AIS Inhibit Control Bits (R/W) Table 63. Registers 88, 89: STS-1/AU-3 Loss of Signal Detector (R/W) Table 64. Register 90—95: Continuous N Times Detect (CNTD) Values (R/W) eration on all STS-1/AU-3 outputs. 88 (0x58) 6 RRHSLOS_AISINH Receive High-Speed Loss-of-Signal AIS Inhibit. 88 (0x58) 5 RRHSLOF_AISINH Receive High-Speed Loss-of-Frame AIS Inhibit. 88 (0x58) 4 RRHSOOF_AISINH Receive High-Speed Out-of-Frame AIS Inhibit. equals 2.3 µs while a value of 0x798 equals 100 µs. frame. The valid range for this register is 0x3—0xF. Invalid values will be mapped to a value of 0x3.

Table 64. Register 90—95: Continuous N Times Detect (CNTD) Values (R/W) (continued) will be mapped to a value of 0x3. 91 (0x5B) 3—0 CNTDK2[3:0] Continuous N Times Detect for K2[2:0] Byte. 92 (0x5C) 7—4 CNTDAPSFRAME[3:0] Continuous N Times Detect for APS Frame Byte. frame. The valid range for this register is 0x3—0xF. Invalid values will be mapped to a value of 0x3. frame. The valid range for this register is 0x3—0xF. Invalid values will be mapped to a value of 0x3. frame. The valid range for this register is 0x3—0xF. Invalid values will be mapped to a value of 0x3. frame. The valid range for this register is 0x3—0xF. Invalid values will be mapped to a value of 0x3.

Table 65. Register 95: Continuous N Times Detect (CNTD) B1 Control Bit (R/W) Z3 value in the incoming STS-3/STM-1 (AU-4) frame. values will be mapped to a value of 0x3. Z5 value in the incoming STS-3/STM-1 (AU-4) frame. values will be mapped to a value of 0x3. wise, B1 errors are ignored.

Table 66. Register 96: Test Pattern Drop Control and Status Table 67. Register 97: Test Pattern Drop Error Counter (RO) Table 68. Register 98: Receive Low-Speed Overhead Control Bits (R/W) 96 (0x60) 7 RTSTDRP_OOS Receive Test Drop Out-of-Sync Indication (RO). errors in the pseudorandom test pattern. otherwise, a Q15 + Q14 + 1 pattern is monitored. 96 (0x60) 1—0 RTSTDRP_PSEL[1:0] Receive Test Drop Port Select Control (R/W).

Table 69. Register 99: Receive Low-Speed BIP Error Insert (R/W) Table 70. Registers 100—102: Receive Low-Speed Overhead Control Bits (R/W) outgoing STS-1/AU-3 signal to be inverted. outgoing STS-1/AU-3 signal to be inverted. signal; otherwise, the default value is inserted.

Table 71. Register 103: Receive Low-Speed L-RDI Inhibit Control (R/W) Table 72. Registers 104—106: Receive Low-Speed C1 Byte (R/W) Table 73. Registers 107—109: Receive Low-Speed F1 Byte (R/W) Table 74. Registers 110—115: Receive Low-Speed K1, K2 Byte Insert (R/W) generation per STS-1/AU-3 frame. RDI-L Inhibit. Same as above. RDI-L Inhibit. Same as above.

Table 75. Registers 116—118: Receive Low-Speed Pass Control (R/W)

Table 76. Register 127: Page Control Register (R/W) Table 77. Page 0 - Registers 128—191: J1 Insert Parameters (R/W) Table 78. Page 0 - Registers 192—255: J1 Monitor Bytes (RO) Table 79. Page 1 - Registers 128—133: STS-1/AU-3 B1 BIP Error Counters (RO) Algorithm Parameters), 11 = Illegal Value. of the STM-1(AU-4) output signal. LATCH_CNT, 0x04 transitions from a logic 0 to 1.

Table 80. Page 1 - Registers 134—140: STS-1/AU-3 B2 BIP Error Counters (RO) Table 81. Page 1 - Registers 141—142: STS-3/STM-1 (AU-4) B1 Error Count (RO) Table 82. Page 1 - Registers 143—145: STS-3/STM-1 (AU-4) B2 Error Count (RO) and 3. These are the B2 BIP error rate counters. LATCH_CNT, 0x04 transitions from a logic 0 to 1. Transmit Low-Speed B2 Error Count Port 1. sitions from a logic 0 to 1. sitions from a logic 0 to 1.

Table 83. Page 1 - Registers 146—151: STS-3/STM-1 (AU-4) B3 Error Count (RO) Table 84. Page 1 - Registers 152—163: STS-3/STM-1 (AU-4) Pointer Increment/Decrement Counter (RO) Table 85. Page 1 - Registers 164—166: Receive High-Speed SFEBE Count (RO) 0x04 transitions from a logic 0 to 1.

Table 86. Page 1 - Registers 167—172: Receive High-Speed Path FEBE Count (RO) Table 87. Page 2 - Register 131 (R/W) LATCH_CNT, 0x04 transitions from a logic 0 to 1. 131 (0x83) 7 SDB1B2SEL Signal Degrade B1/B2 Error Count Select.

Table 88. Page 2 - Registers 128—141 (R/W) Set parameters are used when RHSSD = 0, and the clear parameters are used when RHSSD = 1. SDLSet/Clear[3:0] parameter. of the RHSSD algorithm, and initializes the algorithm to enable recovery declaration. counters of the RHSSD algorithm and initializes the algorithm to enable failure declaration. If SDSET OR SDCLEAR is cleared to 0, do nothing. If SDSET AND SDCLEAR are simultaneously set to 1, do nothing. disable algorithm and set RHSSD, RHSSDD = 0. monitoring block for RHSSD, 0x1B. mining if a monitoring block is bad. monitoring block for RHSSD, 0x1B. mining if a monitoring block is bad. threshold, then RHSSD, 0x1B is cleared.

Agere Systems Inc. 95 Data Sheet April 2001 TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer Microprocessor Interface (continued) Register Map (continued) If (SDB1B2SEL = 0) then use B1 BIP errors in BERR algorithm else use B2 BIP errors in BERR algorithm end if; if (NEWFRAME) then INCR (FRAMECNTR) BIPERR = BIPERR + NEWERR if (BIPERR > SDL) then BIPERR = SDL if (FRAMECNTR = SDNs) then -- Number of frames in monitoring block RESET (FRAMECNTR) if (BIPERR ≥ SDL) then BLOCK = 1 /* indicates bad monitoring period. */ else BLOCK = 0 /* indicates good monitoring period. */ INCR (BTOTCNTR) RESET (BIPERR) If (RHSSD = 0) then if (BLOCK = 1) then INCR (BMONCNTR) if (BMONCNTR ≥ SDM) then RHSSD = 1; RHSSDD = 1 RESET (BMONCNTR); RESET (BTOTCNTR) else if (BTOTCNTR = SDB) then RESET (BMONCNTR); RESET (BTOTCNTR)

9696 Agere Systems Inc. Data Sheet April 2001TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer Microprocessor Interface (continued) Register Map (continued) if (RHSSD = 1) then if (BLOCK = 0) then INCR (BMONCNTR) if (BMONCNTR ≥ SDM) then RHSSD = 0; RHSSDD = 1 RESET (BMONCNTR); RESET (BTOTCNTR) else if (BTOTCNTR = SDB) then RESET (BMONCNTR); RESET (BTOTCNTR) WHERE: NEWFRAME = checks for frame sync signal (internal) to reinitiate BER calculation. FRAMECNTR = count of number of frames since the start of the latest monitoring period. BIPERR = number of composite B1 or B2 errors so far in latest monitoring period. NEWERR = number of composite B1 or B2 errors calculated in latest frame. BLOCK = indication of good (0) or bad (1) latest monitoring period. BTOTCNTR = count of current total number of monitoring periods (good or bad) in latest observation interval. BMONCNTR = count of current number of: bad monitoring periods in latest observation interval if RHSSD = 0, good monitoring periods in latest observation interval if RHSSD = 1.

Table 89. Page 2 - Register 145 (R/W) Table 90. Page 2 - Registers 142—155 (R/W) The set parameters are used when RHSSF = 0, and the clear parameters are used when RHSSF = 1. SFLSet/Clear[3:0] parameter. are used to calculate the error rate. toring block for RHSSF, 0x1B. if a monitoring block is bad. then RHSSF, 0x1B is cleared.

9898 Agere Systems Inc. Data Sheet April 2001TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer Microprocessor Interface (continued) Register Map (continued) Timing requirements: When SFSET is set to a 1, the device sets RHSSF = 1, clears all remaining internal variables and counters of the RHSSF algorithm and initializes the algorithm to enable recovery declaration. When SFCLEAR is set to a 1, set RHSSF = 0, clears all remaining internal variables and counters of the RHSSF algorithm, and initializes the algorithm to enable failure declaration. If SFSET OR SFCLEAR is cleared to a 0, do nothing. If SFSET AND SFCLEAR are simultaneously set to a 1, do nothing. BER algorithm: While (SFL = 0) then disable algorithm and set RHSSF, RHSSFD = 0.

Agere Systems Inc. 99 Data Sheet April 2001 TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer Microprocessor Interface (continued) Register Map (continued) if (SFB1B2SEL = 0) then use B1 BIP errors in BER algorithm else use B2 BIP errors. if (NEWFRAME) then INCR (FRAMECNTR) BIPERR = BIPERR + NEWERR if (BIPERR > SFL) then BIPERR = SFL if (FRAMECNTR = SFNs) then RESET (FRAMECNTR) if (BIPERR ≥ SFL) then BLOCK = 1 /* indicates bad monitoring period. */ else BLOCK = 0 /* indicates good monitoring period. */ INCR (BTOTCNTR) RESET (BIPERR) If (RHSSF = 0) then if (BLOCK = 1) then INCR (BMONCNTR) if (BMONCNTR ≥ SFM) then RHSSF = 1; RHSSFD = 1 RESET (BMONCNTR); RESET (BTOTCNTR) else if (BTOTCNTR = SFB3) then RESET (BMONCNTR); RESET (BTOTCNTR)

100100 Agere Systems Inc. Data Sheet April 2001TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer Microprocessor Interface (continued) Register Map (continued) if (RHSSF = 1) then if (BLOCK = 0) then INCR (BMONCNTR) if (BMONCNTR ≥ MSF) then RHSSF = 0; RHSSFD = 1 RESET (BMONCNTR); RESET (BTOTCNTR) else if (BTOTCNTR = BSF) then RESET (BMONCNTR); RESET (BTOTCNTR) Where: NEWFRAME = checks for frame sync signal (internal) to reinitiate BER calculation. FRAMECNTR = count of number of frames since the start of the latest monitoring period. BIPERR = number of composite B2 errors so far in latest monitoring period. NEWERR = number of composite B2 errors calculated in latest frame. BLOCK = indication of good(0) or bad(1) latest monitoring period. BTOTCNTR = count of current total number of monitoring periods (good or bad) in latest observation interval. BMONCNTR = count of current number of: bad monitoring periods in latest observation interval if RHSSF = 0, good monitoring periods in latest observation interval if RHSSF = 1.

The read and write timing diagrams for all four microprocessor interface modes are shown in Figures 7—14. Table 91. Microprocessor Interface I/O Timing Specifications

106106 Agere Systems Inc. Data Sheet April 2001TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso- lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Handling Precautions Although protection circuitry has been designed into this device, proper precautions should be taken to avoid expo- sure to electrostatic discharge (ESD) during handling and mounting. Agere employs a human-body model (HBM) and charged-device model (CDM) for ESD-susceptibility testing and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used in the defined model. No industry-wide standard has been adopted for the CDM. However, a standard HBM (resistance = 1500 W, capacitance = 100 pF) is widely used and, therefore, can be used for comparison purposes. The HBM ESD threshold presented here was obtained by using these circuit parameters: Parameter Symbol Min Max Unit dc Supply Voltage Range V DD –0.5 4.6 V Power Dissipation P D —— m W Storage Temperature Range T stg –65 125 °C Ambient Operating Temperature Range T A –40 85 °C Maximum Voltage (digital input pins) with Respect to REF5VTOL —— 0 . 3V Minimum Voltage (digital input pins) with Respect to VSS —– 0 . 3— V Device Voltage TMUX03155 2500 V

Table 92. Recommended Operating Conditions

5 V Tolerant Reference Voltage1

1. This input should be connected to 5.0 V when the device interfaces with 5 V and 3.3 V signals, or 3.3 V when the device only interfaces with

1.0 V: LVDS Reference2

1. Use internal reference voltages if LVDS_REFSEL = 0 or external voltage tolerance is > ±5%.

Table 93. Power Measurements (VDD = 3.3 V, 23 °C)

1. 85 °C ambient temperature (not case temperature).

108108 Agere Systems Inc. Data Sheet April 2001TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer

Electrical Characteristics

• All outputs are 2 mA except TLSSPEO, TLSJ0J1VV1TIMEO, TLSV1TIMEO, THSSSYNCO, THSDATA[7:0]O, THSPARO, RLSJ0TIMEO, RLSDATA[7:0]O, and RLSPARO which are 4 mA buffers. The input specification for the remaining (nonbalanced) inputs are specified in Figure 15. See Operational Timing on page 110 5-6032(F)r.2

Figure 15. Single-Ended Input Specification Table 94. Logic Interface Characteristics

Table 95. LVDS Interface Characteristics 3.3 V ± 5% VDD, 0—125 °C, slow—fast process.

• Buffer will not produce output transition when input is open-circuited.

311 MHz

Table 96. Input Clock Specifications

1. When the true and complement inputs are floating, the input buffer will not oscillate.

Table 97. Input Timing Specifications

1. When the true and complement inputs are floating, the input buffer will not oscillate.

The following diagram defines the signal structure of the input signal THSJ0J1V1I. Figure 16. THSJ0J1V1I Signal Structure Definition † MSB = most significant bit, most significant byte, respectively; MSN = most significant nibble.

2430 CLOCK CYCLES/FRAME (125 µs)

4860 CLOCK CYCLES/FRAME (125 µs)

19440 CLOCK CYCLES/FRAME (125 µs)

The output clock specifications are shown in Table 98. Table 98. Output Clock Specifications

1. The specifications for the table are with all loopbacks disabled.
2. The frequency percentages refer to the respective duty cycles.

38.88 MHz ± 5%

19.44 MHz ± 5%

• Propagation delay skew, tPLH—tPHL, is ±200 ps.

Table 99. Output Timing Specifications

specifications are shown in Figure 17. The transmit and receive low-speed bus interfaces are shown in Figure 18. Figure 17. Interface Data Timing

• V1 time occurs once every 500 µs.

† J0 time occurs once per frame (125 µs). Figure 18. Bus Interface Signals

Agere Systems Inc. 117 Data Sheet April 2001 TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer Outline Diagram 208-Pin SQFP Dimensions are in millimeters. 5-2196(F)1.3r.14 DETAIL B 0.17/0.27 0.10 M 0.090/0.200 0.50/0.75 GAGE PLANE SEATING PLANE

1.30 REF

0.25 DETAIL A 156 105 30.60 ± 0.20 157208 53 104 28.00 ± 0.20 28.00 ± 0.20 30.60 ± 0.20 PIN #1 IDENTIFIER ZONE

4.10 MAX

0.08 3.40 ± 0.20 SEATING PLANE 0.25 MIN0.50 TYP DETAIL BDETAIL A

118118 Agere Systems Inc. Data Sheet April 2001TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer

Ordering Information

DS01-194PDH Replaces DS00-213TIC to Incorporate the Following Updates I Version 1 advisory (AY00-002SONT) information incorporated into the datasheet. I Version ID register value changed to 3 (See Device Version and Device ID Number on page 29). I For AU-4 mode, the B3 error count register (REI-P) mechanism was changed so that the transmit clock has enough time to sample the value for application on the outgoing G1[7:4] bits. I The transitioning in the loss of pointer (LOP) state was fixed for the NDF condition. Device Code Package Temperature Comcode TMUX03155 208-Pin SQFP –40 °C to +85 °C 108126368-DB

Agere Systems Inc. 119 Data Sheet April 2001 TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer Notes

Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Copyright © 2001 Agere Systems Inc. All Rights Reserved Printed in U.S.A. April 2001 DS01-194PDH (Replaces DS99-213TIC) For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@micro.lucent.com N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC: Agere Systems Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA: Agere Systems (Shanghai) Co., Ltd., 33/F Jin Mao Tower, 88 Century Boulevard Pudong, Shanghai 200121 PRC Tel. (86) 21 50471212, FAX (86) 21 50472266 JAPAN: Agere Systems Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 Technical Inquiries:GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 3507670 (Helsinki), ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid)