TMPZ84C20AT-6

TMPZ84C20AP-6 TOSHIBA | Alldatasheet

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TMPZ84C20AP-6 / TMPZ84C20AM-6 / TMPZ84C20AT-6 TMPZ84C20AP-8 TLCS-Z80 PIO : PARALLEL INPUT /OUTPUT CONTROLLER 1. GENERAL DESCRIPTION AND FEATURES The TMPZ84C20A (hereinafter referred to as PIO) is CMOS version of Z80 PIO and has been designed to provide low power operation. The PIO is a general purpose parallel input/output port device with two programmable independent 8-bit ports, which provides a direct interface between the Z80 microprocessor (hereinafter referred to as MPU) and peripheral devices. This PIO provides excellent data transfer processing by the interrupt and allows the interrupt in Mode 2 of MPU. The TMPZ84C20A is fabricated using Toshiba’s CMOS Silicon Gate Technology. The principal functions and features of the TMP84C20A are as follows. (1) Compatible with the functions and pin connections of Zilog 280 PIO. (2) Low power consumption 3mA Typ. (@5V @6MHz) --- TMPZ84C20AP-6/AM-6/AT-6 4mA Typ. (@5V @8MHz) «- TMPZ84C20AP-8 10pA Max.(@5V, Stand-by) (3) Operationg temperature —40°C to85°C 6MHz VERSION —10°C to70°C =8MHz VERSION (4) DC to 6MHz operation --- TMPZ84C20AP-6/AM-6/AT-6 DC to 8MHz operation --- TMPZ84C20AP-8 (5) 2 programmable independent 8-bit input/output ports with handshake functions. (6) 4 operation modes for each port: Mode 0 (Byte Output Mode) Mode 1 (Byte Input Mode) Mode 4 (Bit Mode) (7) Built-in interrupt priority control circuit in daisy chain structure (8) Port B outputs capable of driving Darlington transistors (9) Allinput/output lines are TTL compatible. (10) Single 5V power supply. Single-phase clock (11) 40 pin DIP, SOP, 44pin PLCC Package. Note: Z80 is a trademark of Zilog Inc., U.S.A. MPUZ80-165

1. PIN CONNECTIONS AND PIN FUNCTIONS

2.1 PIN CONNECTIONS (Top View)

The pin connections of the TMPZ84C20A are as shown in Figure 2.1, Figure 2.2. 2 1 40 1 D3

07 G2 391 D4 iS

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2.2 PINNAMES AND FUNCTIONS

I/O pin names and functions are as shown in Table 2.1. Table 2.1 Pin Names and Functions (1/3) Number | Input/Output - Pin Name | foi 3-state Function DO~D7 VO 8-bit bidirectional data bus. 3-state Data transfer between MPU and PIO. | Chip enable. | Used for accessing MPU and PIO. CE | 1 Input When MPU selects this PIO, this terminal becomes L level (Refer to 3.4 Basic timing.) Normally, this terminal is connected to the address decoder output. Control/data select. cb 1 | Input Indicates if signal on the data bus is contro! signal or data. Selects | P data at L level and command at H level. Normally, connected to address bit A1 of MPU. 0089 MPUZ80-166

Table 2.1 Pin Names and Functions (2/3) . Number | Input/Output . Pin Name | of bin 3-state Function _ Port A/Port B select. BA Input Selects Port A at L level and Port B at H level. Normally, connected to address bit AO of MPU. AQ~A7 vO Port A bus. 3-state Data transfer between Port A PIO and external device. Port A strobe input RSTB 1 Input Handshake signal from the external device. Signal meaning differs depending upon operation mode. (Refer to 3.4 Basic timing.) Port B strobe input Handshake signal from the external device. BSTB 1 Input Signal meaning is the same as ASTB but differs if Port A is in Mode 2. (Refer to 3.4 Basic timing.) Register A ready Port A ready. ARDY 1 Output Handshake signal to the external device. Signa! meaning differs depending upon operation mode. (Refer to 3.4 Basic timing.) Machine cycle 1. __ When both M1 and IORQ are at L level, indicates that MPU is M1 1 Input executing the interrupt acknowledge cycle (Refer to 3.4 Basic timing.) Normaily, connected to M1 of MPU. VO request. Used to access between MPU and PIO. This terminal becomes L level when /O addresses are on the address in the write cycle and read Input joycle. Further, when IORQ and M7 are both at L level, it indicates jthat MPU is executing the interrupt acknowredge cycle. | (Refer to 3.4 Basic timing.) Normally, connected to IORQ of MPU Read signal. Used to access between MPU and PIO. 1 Input Controls the transfer direction. (Refer to 3.4 Basic timing) Normally, connected to RD of MPU vo Port B bus. BO~B7 3-state Data transfer between Port B of PIO and external device. Capable of driving - 1.5mA (@VoH = 1.5V) Darlington transistors. System clock. Input Signal-phase clock input. CuK 1 P In DC state (either at H or L level), PIO is in a stand-by state and power consumption becomes extermely less. 100489 MPUZ80-167

Table 2.1 Pin Names and Functions (3/3) Number | Input/Output Pinname | of pin 3-state Function Interrupt enable input. Together with IEO and INT, forms daisy chain interrupt control Input signal. Connected to IEO of high priority peripheral LSI.

1 However, to give higher priority than other peripheral LSI's to this

PIO, connect this terminal to the + 5V power. (Refer to 3.3.2 Interruption.) interrupt request. int Output __|interrupt request signal for MPU Connect to INT of MPU. (Open drain) Interrupt enable output. Together with IE! and INT, forms daisy chain interrupt control signal. Output | Connected to IEI or low prioirity peripheral Ls! P However, if this PIO has the lowest priority than any other peripheral LSI’s, this IEO is not used. (Refer to 3.3.2 Interruption.) Port B ready Handshake signal to the external device. BRDY Output —_| Signal meaning is the same as that of ARDY. However, it differs when Port A is in Mode 2. (Rerfer to 3.4 Basic timing.) Power supply 100489 MPUZ80-168

1. FUNCTIONAL DESCRIPTION 3.1. PIO BLOCK DIAGRAM Figure 3.1 shows the PIO block diagram. INTERNAL OPERATION porta > PA0~PA? CIRCUIT vO DATA CONTROL LINE Locicat |_(PORTVOLINE) OPERATION ASTB CIRCUIT ARDY E CONTAOLUIE parasus | USS a LOGICAL INTERNAL BUS CE,M1,IORQ, 6 OPERATION CDBIARO —Consaor | CIRCUIT | 8 LINE porte > PBO~PB7 vO DATA CONTROL LINE LOGICAL (PORTVOLINE) INTERNAL OPERATION BSTB CONTROL cIRCUIT TANDSHAKE BROY OPERATION CONTROL LINE CIRCUIT INT te; — INTERRUPT CONTROL LINE 200489 Figure 3.1 PIO Block Diagram

3.2 PIO SYSTEM CONFIGURATION

The PIO system consists of the four logic circuits: (1) MPU bus I/O logic circuit (2) Internal control logic circuit (3) Interrupt control logic circuit (4) Port I/O logic circuit [1] MPU Bus I/O Logic Circuit The MPU bus I/O logic circuit transfers data between the MPU and the PIO. (2] | Internal Control Logic Circuit The internal control logic circuit controls the PIO operating functions like the PIO selecting chip enable and the read/write circuits. eee MPUZ80-169

{3] Interrupt Control Logic Circuit The interrupt control logic circuit performs the MPU interrupt-associated processing such as determining interrupt priorities. The priorities with other LSI peripherals are determined by the physical location chain connection. [4] Port I/O Logic Circuit The port I/O logic circuits are used to directly connect to peripheral devices. Each consists of the following 7 registers and 1 flip-flop. Data are written in the registers by the MPU as specified in the program. Figure 3.2 shows the internal configuration of the ports. e Data output register (8 bits) e Data input register (8 bits) e Mode control register (2 bits)

0 Interrupt vector register (8 bits)

e Interrupt control register (2 bits) @ = Mask control register (8 bits) e Data W/O control register (8 bits) e Handshake control logic circuit INTERRUPT MODE DATA INPUT/ VECTOR CONTROL NTROL REGISTER REGISTER REGISTER (8817S) (2 BITS) (BITS) DATA INTERNAL BUS OUTPUT REGISTER (8 BITS) DATA CONTROL LINE INTERRUPT MASK DATA CONTROL CONTROL INPUT REGISTER RecisteR f\\WNPUTOATAY gecister (2 BITS) {a3iTS) (8BITS) INTERRUPT HANDSHAKE [aor > HANDSHAKE REQUEST CONTROL CONTROL LINE CIRCUIT 100489 Figure 3.2 Port Internal Configuration MPUZ80-170

(1) Data Output Register This register holds the data to be teansferred from the MPU to peripheral devices. (2) Data Input Register This register latches the data to be transferres from peripheral devices to the MPU. The input data to the MPU is read through this register. (3) | Mode Control Register This register specifies the operation mode. The operation mode is set by MPU control. (4) Interrupt Vector Register This register holds the vector which makes up the address of the table storing the start adress of the interrupt processing routine. This register is used only for interrupt processing. (5) Interrupt Control Register This register specifies how the I/O ports are to be monitored. This register is used only in the PIO mode 3. (6) Mask Control Register This register specifies which I/O port pin is to be monitored. This register is used only in the PIO mode 3. (7) Data I/O Control Register This register specifies whether each port pin is to be used as output or input. This register is used only in PIO mode 3. (8) | Handshake Control Logic This cirsuit controls the data transfer to the peripheral devices connected to the 8-bit I/O ports. 3.3. PIO BASIC OPERATIONS [1] Reset The PIO provides the following two reset capabilities: When PIO is connected with the MPU (TMPZ84CO0A, 01A, 02A) of Z80 series, or ASSP (TMPZ84C011A, 013A, 015A, 710A, 810A), it is necessary to connect with external logic as Figure 3.3. Gi > RESET EXTERNAL MPU / ASSP 100889 Figure 3.3 External Signal Reset Logic MPUZ80-171

(1) Power-on Reset The PIO contains the circuit which automatically resets the PIO at the time of power-on. (2) Hardware Reset Making the MI pin low for 2 system clock periods with the RD and IORQ pins being high resets the PIO on the rising edge of the MI pin. Reset State (a) The operation mode is set to mode 1 for both ports. (b) Interrupt is disabled. (c) All the bits of the data I/O register of each port are reset. (d) All the bits of the mask control register of each port are set and masked. (e) The port I/O lines of each port are put in the high-impedance state (floating). (f) The RDY pin of each port goes low. The reset state is held until the control word is written. For the function of the control word, see Subsection 3.5 “Operational Procedure”. [2] Interrupt The PIO can cause an interrupt when the MPU is operating in mode 2. The interrupt request signal (INT) from the PIO is accepted when the MPU is in the inetrrupt enabled state (caused after the execution of El instruction). Receiving the INT signal, the MPU latches the interrupt vector (8-bit data) sent from PIO, specifies the start address of the interrupt processing routine based on the vector, and calls the routine to start the processing. Thus, since the start address of the interrupt processing routine can be specified by the interrupt vector sent from the PIO, the user can change the vector value to call any desired address. Interrupt processing is terminated when the MPU executes the RETI instruction. The PIO has the circuit to decode the RETI instruction to detect the termination of interrupt processing by constantly monitoring the data bus. The interrupt priority among the Z80 peripharal LSIs is determined by the daisy chain structure. In daisy chain, the peripheral LSIs are connected one after another as shown in Figure 3.4, The more a peripheral LSIs is physically located near the MPU, the higher the priority of the peripheral is. Within the PIO, port A is given higher priority than port B. The Z80 peripheral LSIs have the signal lines IEO and IEI connected to the IZO of a higher peripheral LSIs and IEI of a lower peripheral LSI respectively. However, the IEI of the highest peripheral LSIs is connected to the IEI pin and the IEO of the lowest peripheral LSI is connected to the IEO pin. In this state, the PIO interrupt follows the conditions: MPUZ80-172

e When both JEI and IEO are high, no interrupt has occurred. This time, the interrupt request signal (INT) is high. In this state, the PIO can request interrupt. @ When the PIO sends the INT signal, it sets the IEO line to the low level. When the interrupt request is accepted by the MPU, INT goes back to the low level. e When the IEI goes low, the IEO also goes low. e When the IE] is low, the PIO cannot request an interrupt. e If the IEI goes low during interrupt occurrence, the interrupt processing is suspended. The operations of the four Z80 peripheral LSIs (the states of IEI, IEO and INT signal) daisy-chained as shown in Figure 3.4 are as follows: (1) Before interrupt occurrence Z Vee H iNT H INT H INT H INT (2) Interrupt request from LSI-2 to the MPU

2 Vec

L H INT H INT L INT L INT Vec © JEL gy IEO il @ 10 IL g@ IEO IE g@ 1E0 (3) The MPU acknowledges (enables) the interrupt. Interrupt processing for LSI-2 is performed.

2 Vee

Vv, H INT H INT L INT L INT cc © Il gq EO Il g 10 ll gIEO il g 10 MPUZ80-173

(4) Interrupt request from LSI-1 to the MPU. The interrupt processing for LSI-2 is suspended. Vee L Veo ott INT L INT L INT L iNT cc il gy 1e0 Il gy 10 Il @ IO Il g@ 1EO (5) The MPU acknowledges (enables) the interrupt. Interrupt processing for LSI-1 is performed. Voc ott. INT i INT L INT i INT cc 11g IO ll EO Il g IO El g@ IO (6) Interrupt processing for LSI-1 terminates (upon execution of the RETI instruction). Interrupt processing for LSI-2 is restarted. vy H INT H INT L INT L INT cco 1) ® IEO 1EL @ IEO 1EL 2 1EO ter @ 1EO (7) Interrupt processing for LSI-2 terminates (upon execution of the RETI instruction). L Vee in H t Vee ott INT H INT H INT H INT ee Il gy EO Il gO IE g IEO Il g 10 Interrupt priority is given to LSI-1, LSI-2, LSI-3 and LSI-4 in this order. 100889 Figure 3.4 Signal States in Daisy Chain Structure MPUZ80-174

[3] Operation Modes The PIO operates in one of the 4 operation modes. The mode is selected by writing the mode control word. e Mode 0 (byte output mode) e Mode 1 (byte input mode) ° Mode 2 (byte I/O mode) ° Mode 3 (bite mode) (1) Mode 0 (byte output mode) In mode 0, the PIO sends the data received from the MPU to the external device through the port data output register. The contents of this register can be rewritten by using an output instruction. If the data on the bus change, the register contents remain unchanged until the next output instruction is executed. When the MPU executes an output instruction, the write signal is generated in the PIO in the write cycle. Using the signal, data on the data bus can be latched in the data output register. (2) Mode 1 (byte input mode) In this mode, the PIO sends the data received from the external device to the MPU through the port data input register. The data transfer to the MPU is suspended until the MPU has read the current data. (3) Mode 2 (byte I/O mode) Mode 2 is a combination of mode 0 and mode 1. This mode is used only for port A. In this mode, all 4 handshake control lines are used. Port A’s handshake control lines are used for data output and the port B’s handshake control lines are used for data input. For data transfer, port A is used. Port B is set in mode 3 (bit mode) in which no handshake control line is used. In this mode, the interrupt timing occurs almost at the same time in mode 0 and mode 1. In an input operation, the port B’s handshake control lines are used, so that the interrupt vetor written in port B is transferred. Therefore, the interrupts in input and output can be controlled by different vectors. (4) Mode 3 (bit mode) In mode 3, the 8-bit port I/O lines are controlled for each bit. Since no handshake control lines are used, ordinaly read/write operations can be performed. V/O operations can be performed on the port as well. In a write operation, the data sent from the MPU to the PIO are latched in the data output register corresponding to the bit set for output in the same timing as in mode 0. MPUZ80-175

An interrupt occurs in the interrupt enabled state and when the bit set for input satisfies the condition specified in the interrupt control word. However, if port A is operating in mode 2, port B cannot cause an interrupt in the bit mode. Note that, to use the interrupt capability, the mask control register bit corresponding to the bit set for output must be set to “1” to disable its interrupt. ee MPUZ80-176

3.4 PIO STATUS TRANSITION AND BASIC TIMING

{1] | Status Transition Figure 3.5 shows the PIO status transition diagram. INITIAL SETTING SELECT PORT a <a o NO TODGEMENT MODE O Qe MODE MODE 1 MODE 3 MODE2 NO <n NO YES. DASTA RECEIVE DATA RECEIVE FROM THE DATA RECEIVE DATA RECEIVE FROM MPU EXTERNAL DEVICE FROM MPU EXTERNAL DEVICE WRITE TO OUTPUT WRITE TO INPUT WRITE TO OUTPUT WRITE TO INPUT REGISTER REGISTER REGISTER REGISTER DATA OUTPUTTO COMPOSITION EXTERNAL DEVICE OUTPUT TO MPU DATAS OUTPUT READING MPG YES SINCIDENCE NO —~conoimon INTERRUPTABLE NO YES Yes OUTPUT OF ‘OUTPUT OF INTERRUPT VECTOR INTERRUPT VECTOR 100489 Figure 3.5 (a) PIO Status Transition MPUZ80-177

QF CONTROL WORD. INTERRUPT CONTROL INERRUPT MODE CONTROL CHARACTER VECTOR WORD SETING MODE SETING OF INTERRUPT WRITE OF INTERRUPT CONDITION VECTOR No NO YES DATA RECEIVE YES FROM MPU DATA RECEIVE FROM MPU SETTING OF PORT INPUT/OUTPUT SETTING OF MASK Figure 3.5 (b) PIO Status Transition MPUZ80-178

[2] Write Cycle The IORQ, RD, C/D (AO), and CE(A7 through AO) signals generate the write signal (*WR) inside the PIO. The MPU sets the PIO’s IORQ signal to the low level at system clock T2, to start the write cycle. At this time, to indicate that this cycle is a write sycle, the PIO’s MI signal must be set to the high level. At the same time, the MPU sends signals to the PIO’s B/A (Al) and C/D (AO) to specify the port or select control signal or the data. This allows the port data ouput register of the PIO’s selected port to latch the data at system clock T3. TW is a wait state automatically inserted by the MPU.

1 T2 Tw 13 an

ci, 818 ras OT" (ORQ a RO SSsSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSsSSSSSSSSsSssSssssssse *WR ) ee / *WR = C/D -CE- RD-IORQ toose9 Figure 3.6 Write Cycle Timing {3] Read Cycle The MPU sets the PIO’s, RD pin, CE signal, and IORQ pin to the low level at system clock T2 tu start the read cycle. At this time, to indicate that this cycle is a read cycle, the PIO’s M1 pin must be set to the high level. The PIO outputs data in the CE, IORQ, and RD signals. TW is a wait state automatically inserted by the MPU. MPUZ80-179

A TORQ a a RD \\ / a DATA BUS *RD \\ / *RD =C/D-CE-RD-iORQ 300489 Figure 3.7 Read Cycle Timing [4] Mode 0 (Byte Output Mode) The mode 0 output cycle starts when the MPU executes an output instruction. When an output instruction is executed, he write signal (*WR) is generated in the PIO in the write cycle. This signal latches the data on the data bus to the data output register of the selected port. The RDY pin goes high on the first falling edge of the system clock after the rise of the write signal (*WR). This indicates that the data in the data output register are already on the port I/O pin. The peripheral device sets the RDY pin to the low level on the first falling edge of the system clock after the rise of the STB pin to be input to the PIO to indicate that the peripheral device has received the data from the port I/O pin, waiting for the next output instruction. If, at this time, the PIO is enabled for interrupts, it sets the INT pin to the low level on the rising edge of the STB signal to output the interrupt request signal to the MPU. Figure 3.8 shows the timing chart of mode 0. [5] Mode 1 (Byte Input Made) The input cycle starts when the MPU has completed the previous data read operation. The peripheral device sets the PIO’s STB pin to the lower level, putting data on the port VO line. The RDY pin is driven low on the first falling edge of the system clock after the rise of the STB pin, disabling the peripheral device to send the next data. If, at this time, the MPUZ80-180

{6] Mode 2 (Byte I/O Mode) Mode 2 is a combination of mode 0 and mode 1. The timing for output operation is generally the same as in mode 0 except that, in mode 2, data is output only when the ASTB pin is low while, in mode 0, data is always on the port I/O line. The peripheral device can receive data on the rising edge of the ASTB signal being used as the latch signal. The input timing is the same as in mode 1. The port A handshake line is used as output control and the port B handshake line is as input control. The value of the interrupt vector generated by the BSTB signal during port A input operation is the same as the value of the interrupt vector generated when port B is used in mode 3. Hence, all port B bits are masked by setting the mask contro! word to disable port B for the interrupt capability. CLK ARDY ASTB BRDY BSTB INT iS PORT A INPUT/ OUTPUT LINE *WR \\ ¥ *WR = C/D-CE-RD-IORQ 100489 Figure 3.10 Mode 2 Timing Chart [7] Mode 3 (Bit Mode) In this mode, no handshake line is used. Therefore, the ordinary port read/write operations can be performed, permitting access to the ports any time. The write data from the MPU is latched to the data output register corresponding to the bit set for output in the same timing as in mode 0. Except when port B is used in mode 2, the STB pin of the port operating in mode 3 is fixed to the low level. The transfer data consists of the data in the data output register and in the data input register. That is, the data of the bit set for output and the data of the bit set for input make up the transfer data. MPUZ80-182

An interrupt occurs when the interrupt enabled state is on and the bits set for input safety the condition specified by the mask control word, etc. However, if port A is operating in mode 2, port B is disabled for interrupt in the bit mode. Note that, to use the interrupt capability, the bit on the mask register corresponding to the bit set for output must be set to “1” to disable it for interrupts. An interrupt request occurs when the logic condition becomes true. If the logic condition becomes true immediately before the M1 pin becomes low or while MI pin low, an interrupt request occurs on the rising edge on the MI pin. H ' Th Tr Tw 13 H CLK INT i TORQ a Cy RD a, a PORT INPUT/ INTERRUPT CONDITION |S SATISFIED DATA 11S PUT ON BUS r00889 Figure 3.11 Mode 3 Timing Chart [8] Interrupt Acknowredge Cycle Outputting the interrupt request signal (INT), the PIO sets the IEO signal to the low level, disabling the low-priority peripheral LSIs for interrupt requests. Receiving the interrupt request signal (INT) from the PIO, the MPU sets the PIO’s M1 and IORQ pins to the low level to indicate that the MPU has acknowledged the interrupt request. The IORQ pin goes low 2.5 system clocks later than the MI pin. To stabilize the daisy-chained signal lines (IEI and IEO), the ports and peripheral LSIs cannot change the interrupt request. The RD pin remaines high to make distinction between the instruction fetch and interrupt acknowledge cycles. While the RD pin is high, the interrupt control logic in the PIO determines the interrupt requesting port of the highest priority. When the TORQ pin goes low with the IEI pin being high, the interrupt vector is put on the data bus from the interrupt requesting port. At the same time, two system clocks are automatically inserted by the MPU as a wait state to stabilize the daisy chain structure. MPUZ80-183

jORQ i. Mi oH RD DATA BUS 1EO X 100889 Figure 3.12 Interrupt Acknowledge Cycle Timing Charts [9] Return from Interrupt Cycle Return from interrupt processing is performed when the MPU executes the RETI instruction. This RETI instruction must be used at the end of the interrupt processing routine. When the MPU executes this instruction, the PIO’s IEI and IEO return to the states active before interrupt processing. The RETI instruction consists of two bytes and its code EDH and 4DH. The PIO decodes the RETI instruction to determine whether there is any interrupt requesting port. In the daisy chain structure, the IEI and IEO of the interrupting LSI remain high and low respectively at the time the instruction code EDH has been decoded. If the code following EDH is 4DH, only the peripheral LSI which has sent an interrupt vector immediately before, that is, the LSI whose JEI is high and IEO is low, returns from interrupt processing. This restarts the interrupt processing of the supended peripheral LSIs of lower interrupt priory. MPUZ80-184

fan 12 13 Ta fan Tz 13 Te 1 CLK Mi \\ / \\ / RD \\ / \\ / DATA BUS eee a |EO / ro0aea Figure 3.13 Interrupt Cycle Return Timing Chart

3.5 PIO OPERATIONAL PROCEDURE

To operate the PIO the control words shown below must be written in it as the initial settings. They must be wrriten in the PIO’s ports, A and B, separately. Spesify the I/O address listed in Table 3.1 to write control words and data in the PIO. Table 3.1 1/O Adreesses Port Adata 0 | i} 0 Port B command a) 1 0 Port B data 1 i) i} Port B command ; o1 1 0 ro0ee9 (1) Interrupt Vector Word 7 ] . Lo tt wh Identifies the interrupt vector word. > User-defined interrupt vector 200289 e Using this vector and the contents of the address indicated by the MPU’s register, the MPU generates the start address of the interrupt processing routine. e DO through D7 are written in the interrupt processing register. ° This word is not needed when the interrupt capability is not used. eee MPUZ80-185

(2) Mode Control Word or [pe [esyoe [FFT] T | \\_______» Identifies the mode control word. Don't care Mode Select D7 =0, Dé=0 : ModeO D7 =0, D6=1 : Mode 1 D7=1, D6é=0 : Mode2 D7=1, Dé=1 : Mode 3 o04aa e@ This word specifies an operation mode. e D7 and D6 are written in the mode control register. (3) Data I/O Control Word [or [os [os [oe [03 [2 [5H [OO] [° : Output 1: Input ro0aea e This word is needed only in mode 3. e When mode 3 is specified by the mode control word, the data I/O control word is written after it. e Each port is specified for output or input. e DO through D7 are written in the data I/O register. (4) Interrupt Control Word (er [esos [oe[ oe [a Ta] | Adentifies the interrupt control word. 0 : Mask word not required. | 1: Mask word required. | 0 : Active level is low. | 1: Active level is high. | [° : Interrupt occurs when logic condition is OR. 1: Interrupt occurs when logic condition is AND. [° Interrupt disabled. 1: Interrupt enabled. 10089 MPUZ80-186

e This word is for interrupt control such as interrupt condition setting. e D4, D5, and D6 are used only in mode 3. e With D6=0, interrupt occurs when one of the bits not masked (the bit to be monitored) by the mask control word goes active. e With D6=1, interrupt occurs when all bits not masked (the bit to be monitored) by the mask control word goes active. e With D4=1, the suspended interrupts are all reset regardless of the mode. e D5 and D6 are written in the control register. (5) Mask Control Word ov [oe [os [be [os [52 [01 [00] L_ [° Not masked (to be monitored) 1: Not masked (not to be monitored) 100489 e This word is needed only in mode 3. e When D4=1 is set by the interrupt control word, the mask control word must be written after it. ° This word specifies whether to monitor the port I/O line specified for input by the data I/O control word. e When the bit is set to 0, the corresponding input line is monitored and regarded as the input associated with interrupt occurrence. e When the bit is set to 1, the corresponding input line is masked to provide the input not related to interrupt occurrence. e The PIO checkes only the input line with the bit being 0 to see if the interrupt condition is satisfied. If the condition is satisfied, the PIO requests an interrupt. . DO through D7 are written in the mask control register. When port A is put in mode 2, all 4 handshake lines are used, so that port B must be set in mode 3 which uses no handshake lines. At the same time, all mask control word bits must be set to 1 (masked). Note : Only interrupt enable/disable can be set by the following control word: eee MPUZ80-187

[o7[osjosfostofo jis Tenis te control word which sets only interrupt enable/disable. Don’t care 0 : Disables interrupt 1: Enables interrupt. 100489

3.6 USING PIO

The following is a programming example to operate the PIO’s port in mode 3. This program is followed by the main routine and the interrupt processing program. e The MPU is used in the mode 2 interrupt. e = The table storing the start address of the interrupt processing routine is 0802H. e Interrupts occur when both PIO’s port input lines A6 and A5 go high. e The I/O addresses of the PIO are the address listed in Table 3.1. MPU AoxAy Pox Pr P10 External device ~ t ~ PAO Dp~Dy K —ny po~o7 pao Ao ce />) PAZ AY | BA PAS | Pad | PAS pag be Add = PAT oe . INT INT INT O 100889 Figure 3.14 PIO Connection MPUZ80-188

LD SP,100H --’::: Sets the stack pointer. LM 2 s+ Sets for MPU mode 2 interrupt. LD A,08H ‘++ Writes data in MPU I register. LD IA LD A,02H -++ Writes the interrupt vector word. OUT (01H) A LD A,OCFH +++ Writes the mode control word. OUT (01H) A LD A,62H +++ Writes the data /O control word, Sets PIO. OUT (01H) ,A LD A,F7H ‘++ Writes interrupt control word. OUT(01H),A LD A,9FH “+++ Writes the mask control word. OUT (01H) ,A EI vot Set interrupt enable, MPUZ80-189

1. ELECTRICAL CHARACTERISTICS 4.1. ABSOLUTE MAXIMUM RATING Power Dissipation (6MHz VERSION : TA = 85°C) TSOLDER | Soldering Temperature (10 sec) *¢ TSTG Storage Temperature ~65~150 Ka 6MHz VERSION - 40~85 TOPR Operating Temperature — °C 8MHz VERSION 0089

4.2 DC ELECTRICAL CHARACTERISTICS

6MHz VERSION : Ta=—40°C~85°C, Veoc=5V+10%, Vgsg=0V 8MHz VERSION : Ta=—10°C~70°C, Vec=5V+5%, Vgg=0V SYMBOL } PARAMETER TEST CONDITION min. | TYP. vit |tew input Voltage (scapt CLA ros Lv] Vil" | igh input Voltage (Except cLX) [22 toe bv VOH2 _[Outputigh Voltage tt) |iow= -as0ea”~ Neel = | =v ILo 3-STATE Output Leakage Vsg +0.4 S Vout S Vee _ +10 pA Current in Float 1OHD Darlington Drive Current VOH = 1.5V (a {Paring ve Surren REXT = 1.1KQ “15 ma Voc =5V AP-6/ fews(1) | AM-6/ 3 8 Vic = Vit AT-6 | icc Power Supply Current =0.2V mA Vinc=Vin | AP-8 10 =Vec -0.2V Virc= Vi =0.2 pA Icc2___ | Standly Supply Current Vine =Via = Wee-0.2V 10 Note: (1) fCLK=1/teC(MIN.) (2) Port Bonly 050889 MPUZ80-190

4.3 ACELECTRICAL CHARACTERISTICS

6MHz VERSION : Ta=—40°C~85°C, Voc =5V + 10%, Vgg=0V 8MHz VERSION : Ta=—10°C~70°C, Voc=5V 45%, Vgg=0V aa) No.} SYMBOL PARAMETER (6MHz) (8MHz) | UNIT Lefer fnew eee Low clock pulse width 65 | Hoe esse ET CE, B/A and C/D set-up time for RD, IORQ |= | so - | os | Sf te Sette] [a frie oreancepieetodaae | m= a = | Fajita —fetonmmmoscemete [= p= [po TdRI (DOs) Delay from RD, IORQ rise to data float Ha 12 |taio won Delay fom TORQ fall of INTA cycle to data P= [of = |e) oe | 3 [ramen [t=tseruptimetorcockrise | 70 | = | 50 | = [ns | | 14 [tsa (ch [it=Hset-uptimeforclock fall (WTsycle) | 0 | — | 0 | — | ns | shoe feomnneon [| Delay from El fall to 1EO rise [ — [120 = | 100] ns | Li fans — pr tenreote pea] fro greta] om] = fom] =| =| 19 |Tc0() (in case of making READY to active by next! 170 | — | 120 | — | ns cycle) | | Delay from clock fall to READY rise [ = [170 | - [150] ns | Hi fitarn —peremasetemore—[= [ort = pepo fee fmm TTB“ pene epee] ve = | =| 23 | TssTB() (in case of making READY to active by next | 150 100 | — | ns cycle) | 700089 MPUz80-191

(2/2) ‘AP-6/AM-6/ AT-6 AP-8 NO, SYMBOL PARAMETER (6MHz) (gmHz) | UNIT Delay from IORQ rise to port data stable | TT 4 24 |TdI0 (PD) (Mode o) 160 140 | ns | 25 | TsPD (STB) Data set-up time for STROBE rise (Mode 1) | 190 | ~ | 150] — | ns | 26 | taste (PD) Output data delay time from STROBE fall 130 | — | 150] ns (Mode 2) 27 |rasts (eon Delay from STROBE rise to data float 120 | ns (Mode 2) 28 |TaPD NT) Delay from port data match to INT fall 430 350 | ns (Mode 3) 29 | Taste (INT) Delay from STROBE rise to INT fall |_| 350 250 | ns (Mode 2) 200883 Note: 1 Item with * mark (No.7) is not compatible with NMOS 280 PIO. 2 (1) Ifthe daisy chain is at N stage, 2.5 TeC >(N-2)TAIEIQEON +TdM1(1EO) +TsIEIMO) + TTL buffer delay must be satisfied. (2) In Mode 2, TwSTB>TsPD(STB) must be satisfied. (3) Attestcondition: Input: VIH=2.4V, VIHC=VCC-0.6V, VIL=0.4V, VILC=0.6V Output : VOH=2.2V, VOL=0.8V, CL=100pF

4.4 CAPACITANCE

TA=25°C CCLOCK | Clock Input Capacitance | + ime | - | - | 10 | pF Input Capacitance Allterminalsexceptthattobe [| —~ | — | 5 | pF 950889 MPUZ80-192

4.5 TIMING DIAGRAM

Numbers shown in the following figures correspond with those in the 4.3 A.C Electrical Characteristics Table. Qi Ql_O CLOCK yi i oe 8 | BIA, C/D, CE Ons Sato RD, fORQ | x [Xp [tee out qT) " a a — wel oe — ef st READY (ARDY OR BRDY) STROBE — fe (ASTB OR BSTB) f a { Moves 6) | MODE1 A0~A7 ® Kon | MODE2 Oo. MoDE3 int osoaes Figure 4.1 Timing Diagram MPUZ80-193

1. PACKAGE DIMENSION 5.1 40-PIN PLASTIC PACKAGE DIP40-P-600 Unit: mm 40 21 = 5 _ 3 N S| IS SF hs -8 - 37 1 20 S 50.7+0.2 $f i err o 5 (" oF a NA ARNAAA HAA oh ohm } > site i z ° 1.22TYP 1.4201 OSt01 uy 270289 Note 1 : This dimention is measured at the center of bending point of leads. Note 2:Each lead pitch is 2.54mm, and all the leads are located within +0.25mm from their theoretical positions with respect to No.1 and No.40 leads. MPUZ80-194

5.2 40-PIN SMALL OUTLINE PACKAGE SSOP40-P-450 Unit: mm 49 2 PERE REE EERE LEE EEE EE I om -~ I os =| = ET EEL EUTTEDECELEE Tea ~ | GHOBR REE OUOG RBH SdH lh 20 vtstye| | 0.3540.1 1.15TYP [os] rr ( | 17.5402 {3 x Scar Coommmuonomnonsnnr*| CTT 2 ( = 8 a #P. z im et 0.8402 270289 Note: Package Width and length do not include Mold Protrusions. Allowable Mold Protrusion is 0.15mm. MPUZB0-195

5.3. 44-PIN PLCC PACKAGE QFJ44-P-S650

17.5240.2 Unit: mm

| 16.6+0.2 | | 6 1 4a 40 nonmnoommomnr —__ Lo? 70 []39 a a q U S q H al oa ” q H S| SI le] q es 4 P1 £ qd ir . | # qj J ia q O S qj a vty [29 8 + ° 18 28 “8 oF nn or a | 0.71#0.1 ei) 15.76£0.2 MPUZ80-196