TMPZ84C015B

TMPZ84C015BF-10 TOSHIBA | Alldatasheet

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Technical content

Features

e Built-in TLCS-Z80 series MPU, CTC, SIO, PIO,CGC and watchdog timer features. e High speed operation (10MHz operation) e@ Built-in clock generator (CGC: Clock Generator Controller) ¢ Built-in standby capability (with the controller built in) provides 4 operation : modes: | Run mode (Normal operation) Tdle-1 mode (Only clock oscillation goes on. ) Idle-2 mode (Wake-up by CTC enabled. ) Stop mode (Clock oscillation stopped; standby state) © Wide operational voltagerange | (5V+10%:10MHz VERSION) supported. @ — Wide operating temperature range (—40°C to + 70°C : 1OMHz VERSION) Low power dissipation In operation : (RUNmode) 45mA TYP. at 10 MHz In idle : (IDLE-1 mode) 2.5mA TYP. at 10 MHz (IDLE-2 mode) 19mA TYP. at 10 MHz Instandby : (STOP mode) 500nA TYP. e Built-in TLCS-Z80 series SIO capability MPUZ80ASSP-1

© A pair of independent full duplex channels supports the asynchronous as well as synchronous byte-oriented (monosyne and bisync) and bit-oriented HDLC and CCITT-X. 25 protocols. — Built-in CRC generation and check capability. e Data transfer rates of up to 2000 K bits/sec (10 MHz). © — Built-in TLCS-Z80 series CTC capability Four independent built-in channels. ‘The timer or counter modes can be set . Also available as the SIO baud rate generator. ¢ Built-in TLCS-280 series PIO capability ‘Two programmable independent 8-bit I/O ports having handshaking capability One of 4 operation modes can be selected for each port by using the program: Mode 0 (byte output mode) Mode 1 (byte input mode) Mode 2 (byte input/output mode) Mode 3 (bit mode) e Built-in watchdog timer | © — Programmed daisy-chain interrupt control © Built-in dynamic RAM refresh controller @ = ~=TTL/CMOS compatible © — Housed compact standard 100-pin mini-flat package © The Toshiba real time emulator (RTE80) and the Z80 ICE commercially available can be used (the TMPZ84C015B used as the evaluator). @ — The Toshiba evaluator board installed. note: Z80 isa trade mark of Zilog Inc. Sere MPUZB80ASSP-2

1. PIN ASSIGNMENT AND FUNCTIONS 2.1. Pin Assignments (Top View) 222277722288 53588855 as oP * ” * 80 ICLKTRGD ot" — | id EScuxrtnca — Seuxrtecs — = xer103 atts icrto2 i— 3201001 | certo mo [rout tt — — ae 10 = wat 70 Jamee ama =e wo -—cixout | f—ev ong C15 ‘TMPZ84C015BF-10 i) xtaz — ve | vss Fat 7 — =a oe as i oe tas ——e — = — =r | pas tos = — ss a Ere: — = pao -— wrove Waovk 30 Fo 5 “ s 0. << [qi <iciaciar ur peimele etels = 110680 Note: TheICT pin is the test pin, Do not make anyexternal connection to this pin. Figure 2.1.1 Pin Assignments. MPUZBOASSP-3

2.2. (A) Pin Functions (1/6) Pe [eam [mn 00-07 8 Input/output | The 8-bit bi-directional data bus. (82-89) 3-state A0-A15 16 Output | The 16-bit address bus. (91-100) 3state [These pins specify memory and I/O port (1-6) addresses. During a refresh cycle, the refresh address is output to the low-order 7 bits and ATRF. 1 Output | The Machine Cycle 1 signal. (8) 3-state | In an operation code fetch cycle, this pin goes : “0” with the MREQ signal. At the execution of a | 2-byte operation code, this pin goes “0” for each operation code fetch. In a maskable interrupt acknowledge cycle, this pin goes “0” with the TORQ signal. When the EV signal is applied, this pin is put in the high-impedance state. 1 Output | The Read signal. It indicates that the MPU is (a) 3state | ready for accepting data from memory or /O device. The data from the addressed memory or VO devices is gated by this signal onto the MPU data bus. When the BUSREQ signal is applied, this pin is put in the high-impedance state. WR 1 Output —_| The Write signal. This signal is output when the (13) 3-state data to be stored in the addressed memory or /O. device is on the data bus. When the BUSREQ signal is applied, this pin is put in the high- impedance state. MREQ 1 Output |The Memory Request signal. When the 7) 3-state | execution address for memory access is on the address bus, this pin goes “0” . During a memory refresh cycle, this pin also goes “0” with RFSH signal. TORQ 1 Output —_| The Input/Output Request signal. This pin goes (15) 3-state | "0" when the address for an /O read or write ‘operation is on the low-order 8 bits (AQ through A7) of the address bus. The TORQ signal is also output with the M17 signal at interrupt acknowledge to tell an 1/0 device that the interrupt response vector can be placed on the data bus. Note that the interrupt priority among the TMPZ84C015B CTC, and SIO is selected by a program. 170889 eS MPUZ80ASSP-4

(2/6) ae oe ee 1 The interrupt Enable Output signal. in the daisy 71) chain interrupt control, this signal controls the interrupt from the peripheral LSIs connected next to the TMPZ84C0158. The IEO pin goes “1” only when the IE! pin is “1” and the MPU is not servicing an interrupt from the built-in peripheral LSI. XTALI 2 Input —_| The crystal oscillator connection. XTAL2 (65) Output Connects an oscillator having the oscillation (66) frequency 2 times as high as the system clock (CLKOUT) frequency. CLKIN input _| The Single-phase Clock Input. When the clock input is placed in the DC state (continued "1" or “0” level), this pin stops ‘operating and holds the state of that time. Normally, this pin is connected with the CLKOUT pin. However, to operate the system with the external clock, connect the external clock to the CLKIN pin. CLKOUT The Single-phase Clock Output. When a Halt instruction is executed in the Stop or Idle-1 mode, the CLKOUT output is retained at “0”. In the Run and Idle-2 mode the clock is kept output. This pin provides the clock to other peripheral ICs. 1 Input |The Reset signal input. This signal resets the (9) internal states of the TMPZ84C015B. This signal is also used to return from the standby state in the Stop or Idle mode. INT 1 Input | The Maskable Interrupt signal. An interrupt is (19) caused by the internal CTC, SIO PIO or the peripheral LSI. An interrupt is acknowledged when the interrupt enable flip-flop (IFF) is set to "1" by software. The INT pin is normally wire-ORed and requires an external pullup resistor for these applications. This signal is also used to return from the stand- by state in the Stop or Idle mode. WAIT Input | The Wait Request signal. This signal indicates the MPU that the addressed memory or /O device is not ready for data transfer. As long as this signal is “O" , the MPU is in the Wait state. 170869 MPUZ80ASSP-5

a ——S™P728400158 (3/6) Qty [rT fen [_ BUSREQ The Bus Request signal. The BUSREQ signal forces the MPU address bus, data bus, and control signals MIREQ, IORQ, RD, and WR to be placed in the high-impedance state. This signal is normally Wire-ORed and requires an external pullup resistor for these applications, BUSACK Output | The Bus Acknowledge signal. In response to the BUSREQ signal, the BUSACK signal indicates to the requesting peripheral LSi that the MPU address bus, data bus, and control signals MREQ, TORQ, RD and WR have been put in the high- impedance state, HALT Output | The Halt signal. This pin goes “0” when the MPU 3state | has executed a Halt instruction and is in the Halt state. It is put in the high-impedance state when the EV signal is applied. RFSH 1 Output | The refresh signal. When the dynamic memory 7) refresh address is on the low-order 8 bits of the address bus, this signal goes “0” . At the same time, the MREQ signal also goes active ("0"). This pin is put in the high-impedance state when the EV signal is applied. CLKATRGO 4 Input |The external clock/timer trigger. These 4 ~CLK/TRG3 | (78-81) CLK/TRG pins correspond to 4 channels. In the counter mode, the down counter is decremented by 1 and in the timer mode, the timer is activated at each active edge (a rising or falling edge) of the signal which are input by these pins. It can be selected by program whether the active edge is a rising oF falling edge. zaToo0 4 Output | The Zero Count/Timer Out signal. In either the ~ZC703 (74-77) Timer mode, or counter mode, pulses are output from these pins when the down counter has reached zero. 1 Input | The Interrupt Enable Input signal. This signal is (72) used with the IEO to form a priority daisy chain when there is more than one interrupt-driven peripheral LsI. Nw 1 The Non-maskable interrupt Request signal. (63) This interrupt request has a higher priority than the maskable interrupt and 1s not dependent on the interrupt enable flip-flop (IFF) state. This signal is also used to return from the stand-by state in the Stop or idle mode. 170409) eee MPUZB80ASSP-6

(4/6) Ce [ee EV 1 The Evaluator signal. When this signal is active, (67) the M1, HALT, and RFSH pins are put in the high- impedance state. In using the TMPZ84CO15B as an evaluator chip, the MPU is electrically disconnected (put in the high-impedance state) after one machine cycle is executed with the EV . signal being “1” and the BUSREQ signal being 0", and follows the instructions from other MPU (such as the MPU of ICE). The signals of the disconnected MPU are A00 through A15, DO through D7, MREG, IORG, RD, WR, M1, HALT, and RFSH. BUSACK needs to be disconnected by an externally connected circuit. The evaluator board is available to use the TMPZ84C015B as an evaluator chip. ATRF 1 Output |The 1-bit auxiliary address bus. This pin outputs (70) the same signal as the bit 7 (A7) of the address bus. However, during a refresh cycle, this pin outputs the address which is the most significant bit of the 8-bit refresh address signal linked to the low-order 7 bits of the address bus. ASTB Input —_| The Port A Strobe Pulse From Peripheral Device. This signal is used at the handshaking between port A and external circuits. The meaning of this signal depends on the mode of operation selected for port A. (See “PIO Basic Timing”) BSTB 1 The Port B Strobe Pulse From Peripheral Device. (61) This signal is used at the handshaking between port B and external circuits. The meaning of this signal is the same as the ASTB signal except when port Aisin the mode 2. (See “PIO Basic Timing”. ) ARDY 1 Output | The Register A Ready signal. This signal is used at (20) the handshaking between port A and external circuits. The meaning of this signal depends on the mode of operation selected for port A. (See “PIO Basic Timing”.) BRDY 1 The Register B Ready signal. This signal is used at (62) the handshaking between port 8 and external circuits, The meaning of this signal is the same as the ARDY signal except when port A is in the mode 2. (See “PIO Basic Timing”. ) PAO-PA7 Input/Output | The Port Data A signal. 3state | These signals are used for data transfer between port A and external circuits. 170809 MPUZ80ASSP-7

(5/6) Q'ty ‘ | re (Number) Type Function PBO-PB7 8 Input/Output | The Port Data B signal. (53-60) 3state | These signals are used for data transfer between port B and external circuits. WIRDYA 2 Output | The Wait/Ready signal A and the Wait/Ready WIRDYB (30, 52) signal 8 These signals can be used as the Wait or Ready depending on SIO programming. When these signals are programmed as “Wait”, they go ) active at "0" to indicate to the MPU that the addressed memory or V/O devices are not ready | for data transfer, requesting the MPU to wait. When these signals are programmed as “Ready”, | they go active at “0” to determine when a . peripheral device associated with a DMA port is ) ready for a read or write data. The DMA is requested to transfer data. SYNCA Input/Output | The Synchronization signal. In the asynchronous SYNCB receive mode, these signals act as the CTS and : DCD signals, In the external sync mode, these ) signals act as inputs and in the internal sync | mode, they act as outputs. RXDA 2 Input —_ The Serial Receive Data signal. RXDB (32, 50) RXCA Input | The Receive Clock signal. In the asynchronous RXCB mode, the Receive Clocks may be 1, 16, 32 or 64 times the data transfer rate. TRA 2 Input —_| The Transmitter Clock signal. TXCE (34, 48) In the asynchronous mode, the Transmitter Clocks may be 1, 16, 32, or 64 times the data transfer rate. TXDA 2 The serial transmit data signal TXDB (35,47) DTRA 2 Output | The Data Terminal Ready signal. These signals BTRE (36, 46) indicate whether the data terminal is ready to receive serial data or not. When it is ready, these signals go active to enable the transmitter of the terminal. When it is not ready, these signals go inactive to disable the transfer from the terminal. RISA 2 The Request to Send signal. These pins are “0” RTSB (37,45) when transmitting serial data. That is, to transmit data, these signals are made active to enable their receivers. 170809 eee MPUZB80ASSP-8

(6/6) Q'ty i, CSA 2 The Clear To Send signal. When these pins are cTsB (38, 44) "0", the modem having transmitted these signals is ready to receive serial data. When it is ready, these signals go active to enable the transmitter of the terminal. When it is not ready, these signals go inactive to disable the transfer from the terminal . DCDA 2 The Data Carrier Detect signal. When these pins | DoDB (39, 43) are “0 the receive of serial data can be enabled. That is, to transmit data, these signals are made active to enable their receivers. ) (ct 2 Output | The test pins. To be used in the open state. | (40,42) | worouT 1 Output | The Watchdog Timer signal. ) (73) The output pulse width depends on the . externally connected pin. | vec 2 The power supply (+5 V) pins. (41, 90) vss 1 The ground (0 V) pins. (16, 64) 170009 2.2 (B) TMPZ84C015B Internal I/O Address Map vO Address crc (Counter Timer) ch A Send/Receive buffer slo ch A Command/Status Register [ #19 | (Serial /O) ch B Send/Receive buffer [#1 | ch B CommandiStatus Register [#1 ‘A Port Data #1¢ PIO A Port Command # 1D (Parallel /0) B Port Data # 1E B Port Command #F Watch Dog Timer Stand-by mode Register WOTER, WOTPR, HALTMR command Register disable command (B14) Daisy-chaine interrupt _ precedence Register Only use bit2~Bitd ro MPUZ80ASSP-9

1. OPERATIONAL DESCRIPTION

3.1 Block Diagram and Operational Outline

3.1.1 Block Diagram

| XTALL XTALZ. MT RAT cLKour. Ev BUSREQ BUSACK ‘CLKIN CLK REQ: Msi HAT eo Hat mt MT [ fuse coc wif [a "Tess | | Demme “7 _— raul meu ase Pp pf FE o~D7 2C/TOo INT CLK IK Aoo~A1s 2/703 i ial | | RD IORQ WR RFSH ~~ TL i CLK TRG ss RF 5 [| wR CURITRGS aay H Ee HH] Be word Fr CTC RESET fd DOOR | Bes IEl ram 5 RD ~D; WIRDYA e 5 ti CLK ROTORG_Do~D7 | Sp |_| 8 K RESET SYNC cs; 8 FH a iNT Je FCA Pt ele ag El PT Oe tes x08 Pe TXB pp] fA} pin Ico |< RCE Tet I FHT 1 > te |<— RXDB co ttt | Nees <> syns 7STE | yaa &Uleva WiRBYE Do~D7 Hea m ARDY vac ALN] opt 7] <a] rs ioral-—4 as bar van no TT oe | | oe M7 RESET IE| WR RFSH PaO wi a ad Mt 2 — Do~D7 1EO worour

7 CLK CLK ir

BRODY =| [| = }-| #0 Watchdog timer ATRE fad mae 8 & ir BIE cD mae 8 fl gi registers Ic BIR Lay id & Lee MI- RESET Ms1,Ms2 SS & yd] Dy~Dy Asg~Ars tose Figure 3.1.1. Block Diagram of TMPZ84C015B ee MPUZBOASSP-10

3.1.2 Operational Outline

The TMPZ84CO15B largely consists of a processor (MPU), a counter/timer circuit (CTO), a serial input/output controller (SIO), a parallel input/output controller (PIO), a watchdog timer (WDT), and a clock generator/controller (CGC). | © The MPU provides all the capabilities and pins of the Toshiba TLCS-280 MPU | (TMPZ84CO0A) to play the role of the TLCS-280 microprocessor perfectly. © The CTC provides the capabilities of the Toshiba TLCS-280 CTC (TMPZ84C30A) | and has the pins required to perform the necessary operations as a TLCS-Z80 peripheral LSI. The four independent timer channels are I/O-addressed internally. © The SIO provides the capabilities of the Toshiba 'TLCS-Z80 SIO (TMPZ84C43A) | and has the pins required to perform the necessary operations as a TLCS-280 | peripheral LSI. The two independent serial channels are I/O-addressed internally. | © The PIO provides the capabilities of the Toshiba TLCS-Z80 PIO (TMPZ84C20A) and has the pins required to perform the necessary operations as a TLCS-280 peripheral LSI. The two independent parallel ports are I/O-addressed internally. © The WDT incorporates one-channel watchdog timer and the read/write-enabled | watchdog timer control registers indispensable for control applications. The WDT | also has the register to determine interrupt priorities, allowing the user to set the daisy-chain interrupt priorities by program. Additionally, the WDT has the IEI | and IEO pins required to process the daisy- chain interrupts caused by the | peripheral LSIs to be added both inside and outside the TMPZ84C015B. © The CGC provides the four operation modes to control the entire TMPZ84C015B chip; the Run, Idle-1, Idle-2, and Stop modes, They are program-selectable. This chip has two clock pins: CLKOUT to supply clock from the CGC and CLKIN to get clock from the outside. Therefore, the TMPZ84C015B can be operated on the clock supplied from the outside at the CLKIN pin without using the CGC. The following briefly describes the four operation modes of the CGC with the CLKOUT and CLKIN pins connected: © In the Run mode, the clock generated by the CGC is supplied to the TMPZ84C015B and peripheral LSIs to perform the normal programmed microcomputer operations. © Inthe Idle-1 mode, clock oscillation is going on but the clock is not supplied to the ‘TMPZ84C015B and peripheral LSI, thereby saving the system power consumption and shortening the time required for system restart. MPUZBOASSP-11

© In the Idle-2 mode, clock oscillation is performed and the clock is output from the CLKOUT pin. The clock is supplied only to the CTC in the TMPZ84C015B, permitting a wake-up operation by the CTC. Like the Idle-1 mode, the Idle-2 mode saves the system power consumption and shortens the time required for system restart. © In the Stop mode, clock oscillation is not performed and the system operation can be stopped completely. In this mode, the system can be restarted with the internal data retained with an extremely low power consumption level unique to the CMOS technology. Note that these modes can be set only when the MPU has executed a HALT instruction. Additionally, the TMPZ84C015B has also the EV pin which is used with the BUSREQ pin to put the MPU in the high-impedance state for electrical disconnection, thus functioning as an evaluator chip. That is, the MPU in the TMPZ84C015B is electrically disconnected by these two pins to implement the emulation by the signal from the in-circuit emulator (ICE). For emulation, one machine cycle is performed on the MPU in the TMPZ84C015B with EV being “1” and the BUSREQ being “0” then the emulation is performed as instructed by the MPU. The MPU signals to be disconnected are AQ0 through A15, DO through D7, MREQ, IORQ, RD, MI, HALT, and RFSH, BUSACK needs to be disconnected by an externally connected circuit. a MPUZBOASSP-12

3.2. MPU Operations This subsection describes the system configuration, functions and the basic operation of the MPU of the TMPZ84C015B.

3.2.1 Block Diagram

Figure 3.2.1 shows the block diagram of the MPU. CLK IN [“feseg__[- Fas | vw) | Bregister [register a S) | Bregister | D’resister__| \\x/ BN Eregister | E’register | 5 7 8 3 z 2 = S| [_tregister [register | E i do~os} |Z (~) 8 g < Ee 4 gs Eg 2%) — instruction 5) decoder s| FA (88 ev one Control Control soe Lied an Control bus controller Nv INT TORQ. «HAIT WAIT MREQ RD WR BUSREQ BUSACK vr Figure 3.2.1. MPU Block Diagram MPUZ80ASSP-13

3.2.2 MPU System Configuration

The MPU has the configuration shown in Figure 3.2.1. The address signal is put on the address bus via the address buffer. The data bus is controlled for input or output by the data bus interface. Both the address and data buses are put in the high-impedance state by the BUSREQ signal input to make them available for other peripheral LSIs. ‘The Opcode read from memory via the data bus is written to the instruction register. This Opcode is decoded by the instruction decoder. According to the result of the decoding, control signals are sent to the relevant devices. Receiving these control signals, the ALU performs various arithmetic operations. The register array ) temporarily hold the information required to perform operation. ‘The following describes the MPU’s main components and functions which the user | must understand to operate the TMPZ84C015B: | [1] _ Internal Register Groups The configuration of the internal register groups is as follows: (1) Main registers A,F,B,C,D,E,H,L (2) Alternate registers A’,F,B,C’,D’, EH’, L? (3) Special purpose registers LR, IX, IY, SP, PC Figure 3.2.3 shows the configuration of the internal register groups. The register groups, each being of a static RAM, consists of eighteen 8-bit registers and four 16-bit registers. The following describes the function of each register: (1) Main registers (A, F, B, C, D, E, H, L) (a) Accumulator (A) The accumulator is an 8-bit register used for arithmetic and data transfer operations. (b) Flag register (F) (see Figure 3.2.2) ‘The flag register is an 8-bit register to hold the result of each arithmetic operation. Actually, the 6 of the 8 bits are set(“L”)/reset(“0”) according to the condition specified by an instruction. ee MPUZBOASSP-14

$$$ EEO e Sign flag (S) When the result of an operation is negative, the S flag is set to “1”. Actually, the content of bit 7 of accumulator is stored in this flag. © = Zero flag (Z | When all bits turn out to be “0” s after operation, the Z flag is set to “1” . Otherwise, it is set to “0” . With a block search instruction (CPI, CPIR, CPD or CPDR), the Z flag is set to “1” if the source data and the accumulator data match. With a block I/O instruction (INI, IND, OUTI or OUTD), the Z flag is set to “1” if the content of the B register used as the byte counter is “0” at the end of comparison. @ — Parity/overflow flag (P/V) This flag has two functions. One is the parity flag (P) that indicates the result of a logical operation (AND A, Betc.). The P flag is set to “1” if the parity is even as a result of the operation on signed values by two’s complement. It is reset to “0” if the parity is odd. With a block search instruction (CPI, CPIR, CPD or CPDR) and a block transfer instruction (LDI or LDD), the P flag indicates the state of the byte counter (register pair B and C). It is set to “1” if the byte counter is not “0” and reset to “0” when the byte counter becomes“0” (at the end of comparison or data transfer). The content of the interrupt enable flip-flop (IFF) is saved to the P flag when the contents of the R register or I register are transferred to the accumulator. The other use of the P/V flag is the overflow flag (V) that indicates whether an overflow has occurred or not as a result of an arithmetic operation. The V flag is set to “1” when the value in the accumulator gets out of a range of the maximum value +127 and the minimum value —128 and therefore cannot be correctly represented as a two's complement notation. Whether the P/V flag operates as the P flag or V flag is determined by the type of the instruction executed. e Carry flag (¢; The C flag is set to “1” if a carry occurs from bit 7 of the accumulator or a borrow occurs as a result of an operation. The following two flags are not available to the programmer for the test and set (“1)/reset (“0”) purposes. They are internally used by the MPU for BCD arithmetic operations. e@ = Halfcarry flag (H, ‘The H flag is used for holding the carry or borrow from the low-order 4 bits of a BCD operation result. When a DAA instruction (decimal adjust) is executed, the MPU automatically uses the H flag to adjust the result of a decimal addition or SS MPUZB8O0ASSP-16

subtraction. © — Add/subtract flag (N. In BCD operation, algorithm is different between addition and subtraction. The N flag indicates whether the executed operation is addition or subtraction. For change of the flag state depending on the instruction, see 3.2.4 “TMPZ84CO15B Instruction Set”. () General-purpose registers (B, C, D, E, H, L) General-purpose registers consist of 8 bits each. They are used as 16-bit register pairs (BC, DE, HL) as well as independent 8-bit registers to supplement the accumulator. The B register and the register pair BC are used as counters when a block I/O, block transfer, or search instruction is executed. The register pair HL has various memory addressing features as compared with the register pairs BC and DE. (2) Alternate registers (A’, F’, B’, C’, D', E’, H’, L’) The configuration of the alternate register is exactly the same as that of the main registers. There is no instruction that handles the alternate registers directly. The data in the alternate registers are processed by moving them into the main registers by means of exchange instructions as shown below: EX AF, AF’ (Ae A’, FoF) EXX (BeB,CeC, DoD, EER, H+H,L+L) When a hign-speed interrupt response has been requested within the system, these instruction can be used to quickly move the contents of the accumulator, flag registers, and general-purpose registers into the corresponding registers. This eliminates the need for transferring the register contents to/from the external stack during execution of the interrupt handling routine, thereby shortening the interrupt servicing time greatly. (3) Special purpose registers (I, R, IX, 1Y, SP, PC) (a) Interrupt page address register (|) ‘The TMPZ84C015B provides two kinds of interrupts: maskable interrupt (INT) and non-maskable interrupt (NMI). The maskable interrupt provides three modes (0, 1, and 2) in which the interrupt is handled. These modes can be selected by instructions IMO, IMI, and IM2 respectively. In Mode 2, any memory location can be called indirectly depending on the interrupt. For this purpose, the I register stores the high-order 8 bits of the indirect address. The low-order 8 bits are supplied from the interrupting peripheral LSI. This scheme permits calling the interrupt handling routine from any memory location in an extremely short access MPUZ80ASSP-17

time. For the details of interrupts, see [4] “Interrupt Capability”. (b) Memory refresh register (R) ‘The R register is used as the memory refresh counter when the dynamic RAM is used for memory. This permits using of the dynamic memory in the same manner as the static memory. This 8-bit register is automatically incremented for each instruction fetch. While the MPU decodes and executes the fetched instruction, the contents of the R register are synchronized with the refresh signal to place the low-order 7 bits and A7RF on the address bus. This operation is all performed by the MPU and, therefore, dose not need a special processing by program. The MPU operation is not delayed by this operation. During refresh, the contents of the I register are placed on the high-order 8 bits of the address bus. (Index registers (IX, IY) The two independent index registers IX and IY hold the 16-bit base address when used in the index addressing mode. In this addressing mode, the memory address obtained by adding the contents of an index register to the displacement value (for example, LD IX+40H) is specified. This mode is convenient for using data tables. Also these registers can be used separately for memory addressing and data retaining registers. {d) Stack pointer (SP) The stack pointer is a 16-bit register to provide the start address information in the stack area in the external RAM. The content of the stack pointer is decremented at the execution of a CALL instruction or PUSH instruction or interrupt handling and is incremented at the execution of a RET instruction or POP instruction. At the execution of a CALL instruction or interrupt handling, the current content of the program counter is saved into the stack. At the execution of a RET instruction, the content is restored from the stack to the program counter. These operations are all performed by the MPU automatically, However, the other registers are not saved or restored automatically. For the storing of the contents of these registers, an exchange instruction (BX or EXX) for alternate register, a PUSH or a POP instruction must be used. When a PUSH instruction is executed, the contents of the specified register are saved into the stack. When a POP instruction is executed, the contents of the stack are moved to the specified register. These data are restored on a last-in, first-out basis. Use of the stack permits processing of multiple-level interrupts, deep subroutine nestings, and various data manipulation very easily. The stack pointer is not initialized in the hardware approach. Therefore, it is required to allocate the stack area in RAM to specify initialization (at the highest address of the stack area) in the initial program. MPUZ80ASSP-18

(ex) MEMORY The contents of the SP MEMORY ADDRESS i ADDRESS before the instruction (HEX) HEX) INSTRUCTION oor ted, 5 § LOWER g Py 1230 CALL. «1500H_FFF1 FFEB 3s £ i | free [oe | 5 ° 1600 PUSH AF FFEF ; As05, Fe23 Freo | 23 | g 5 1501 PUSH BC FFED ; B=B2, C=CO Free | 05 | & 2 B | FEF 2 i FFFO | i 1600 PoP BC FFEB HIGHER : | 1601 POP AF FFED

1602 RET FFEF

The foregoing example shows the stack pointer and stack operations in which the instructions starting with the CALL at address 1230H and ending with the RET at address 1602H have been executed. However, it is assumed that there is no instruction or interrupt other than shown above that uses the stack during the execution. When the value of the stack pointer before executing the CALL instruction at address 1230H indicates address FFF 1H, address 1233H is stored at | addresses FFFOH and FFEFH because the CALL instruction consists of 3 bytes, | then the stack pointer is decremented. Similarly, the data are saved or restored | sequentially according to the instructions. These stack and stack pointer | operations are all performed automatically. . (e) Program counter (PC) ‘The program counter holds, in 16 bits, the memory address of the instruction to be executed next. The MPU fetches the instruction from the memory location indicated by the program counter. When the content of the program counter is put on the address bus, the program counter is incremented automatically. However, it is not incremented with a jump instruction, a call instruction, or interrupt processing. Instead, the specified new address is set on it. With a return instruction, the content restored from the stack is set on the program counter. These operations are all performed automatically and therefore, no care is required for programming. [2] Halt Capability When a HALT instruction has been executed, the MPU is put in the halt state. The halt capability can be used to halt the MPU against the external interrupts, thereby reducing the power dissipation. In the halt state the states of MPU’s internal registers are retained. The halt state is cleared by reset or when an interrupt is accepted. MPUZ80ASSP-19

For the details of halt operation, see [3] “Basic Timing.” (1) Halt operation When a HALT instruction has been executed, the MPU sets the HALT signal to “0” to indicate that the MPU is going to be put in the halt state. Actually, the MPU in the halt state automatically continues executing NOP instructions if there is the system clock input. However, the program counter is not incremented. This Keeps the refresh signal generated when the dynamic memory is used. During halt, the MPU’s internal states are retained. The TMPZ84C015B contains the clock generator/controller, easily implementing the clock input control for these halt operations. (2) Releasing the halt state The halt state is cleared by accepting an interrupt (the INT or NMI signal input) or by reset (the RESET signal input). When an interrupt is accepted, the halt state is cleared and the interrupt handling routine is executed. However, a maskable interrupt (INT) cannot be accepted unless the interrupt enable flip-flop (IFF) is set. Note that when the halt state is cleared by the RESET signal, the MPU is reset and the program counter is set to “0”. [3] RESET Signal Holding the RESET pin at the low level (“0”) under the following conditions, the MPU’s internal states are reset: (1) The supply voltage level is within the operational voltage range. (2) System clock stabilization. (3) Holding the RESET signal at the low level (“0”) for at least 3 full clock cycles. When the RESET signal goes high (“1”) , the MPU starts executing instructions from address 0000H after at least 2T state dummy cycles. When reset, the MPU performs the following processing: (1) Program counter 0000H is set. (2) Interrupt ‘The interrupt enable flip-flop (IFF) is reset to “0” to disable the maskable interrupt. For the maskable interrupt processing, mode 0 is specified. eee MPUZB8O0ASSP-20

(3) Control output. . All control outputs are made inactive (“1”) . Therefore, the halt state is also cleared. (4) _ Interrupt page address register (I register) ‘The content of the R register becomes 00H. | The content of the R register becomes 00H. The contents of the registers other than above and the external memory do not change. | Therefore, they must be initialized as required. | [4] _ Interrupt Capability | The interrupt capability is used to suspend the execution of the current program and ) execute the processing of the requested peripheral LSI. Normally, this interrupt | processing routine contains the data exchange and transfer of status and control | information between the MPU and the peripheral LSI. When this routine has been ) completed, the MPU returns to the state active before the interrupt has been accepted. The TMPZ84CO15B provides the non-maskable interrupt (NMI) and maskable interrupt (INT) capabilities which are detected by the NMI and INT interrupt request signals, respectively. A non-maskable interrupt, when caused by a peripheral LSI, is accepted unconditionally. This interrupt is used to support critical functions such as the protection of the system from unpredictable happening including power failure. A maskable interrupt can be enabled or disabled by program. For example, if the timer is used and, therefore, an interrupt is not desired, the system can be programmed to disable the interrupt. Table 3.2.1 lists the processing by interrupt source. (1) Interrupt enable/disable A non-maskable interrupt cannot be disabled by program, while a maskable interrupt can be enabled or disabled by program. The MPU has the interrupt enable flip-flop (IFF). A maskable interrupt can be enabled or disabled by setting this flip-flop to “1” (set) or “0” (rest) through an EI instruction (enable) or a DI instruction (disable) in program. Actually, the IFF consists of two flip-flops IFF1 and IFF2. IFF1 is used to select between the enable and disable of a maskable interrupt. IFF2 holds the state of IFF1 before a maskable interrupt has been accepted. Both IFF1 and IFF2 are reset to “0” when any of the following conditions occurs, disabling an interrupt: MPUZB0ASSP-21

CSP ZB4'CO15B @ MPU reset © Execution of DI instruction © Acceptance of maskable interrupt Both IFF1 and IFF2 are set to “1” when the the following condition occurs, enabling an interrupt: Execution of El instruction Actually, the waiting maskable interrupt request is accepted after the execution of the instruction that following the El instruction. This delay by one instruction is caused by accepting an interrupt after completion of the execution of a return instruction if the instruction following the EI instruction is a return instruction. | In the above operation, the contents of IFF1 and IFF2 are the same. Table 3.2.1. Processing by Interrupt Source | Interrupt Interrupt Source Priority | Programmed condition Vector addres ._ Feturn instructio ) Non-maskable interrupt None Address 66H RETN ) (the falling edge of NM) Instruction from Maskable interrupt (INT Mode | peripheral LsI. (Note) becomes “0” at Normally, CALL or RST RETI instruction’s last clock) instruction. [ tod [addres36n The address indicated by the data table (memory) Mode2 | atthe address specified by I register (high-order 8 bits) and data from peripheral LSI (low- order 8 bits, LSB = 0"). Note: Mode 0 applies when the instruction from peripheral LSI is CALL or RST instruction. 170089 eee MPUZ80ASSP-22

TOSHIBA ‘TMPZ84C015B ah hl (RETN) (LDA, lor LD A, R) , weal enebie IFF2 (foar holding IFF1) | Idisable) Executed instruction || ) 0 0 =: MPUreset Di instruction INT acceptance 1 1: Elinstruction : RETN instruction | when IFF2=1. | 0 state of IFF1 : NMlacceptance | before NMI acceptance 70889 Figure 3.2.4 Interrupt Enable Flip-Flop (IFF) When a non-maskable interrupt has been accepted, IFF1 is reset to “0” (interrupt disable) until an EI or RETN instruction is executed, so as to prevent from accepting the next interrupt. For this purpose, the state (interrupt enable/disable) of IFF1 immediately before non-maskable interrupt acceptance must be stored. This state is copied into IFF2 upon acceptance of a non-maskable interrupt. The content of IFF2 is copied into the parity flag at the execution of the following instructions, so that the copied data can be tested or stored: @ The load instruction (LD A, I) to load the contents of the I register into the accumulator. The load instruction (LD A, I) to load the contents of the R register into the accumulator. When the return instruction (RETN) from the non-maskable interrupt is executed, the contents of the current IFF2 are copied back to IFF1. If an operation which changes the contents of IFF2 (due to the execution of EI or DI instruction, for example) has not been performed during interrupt handling, IFF1 automatically returns to the state immediately before the interrupt acceptance. Table 3.2.1 lists the states of IFF1 and IFF2 after execution of interrupt-related instructions. a MPUZB80ASSP-23

Table 3.2.2 State of IFF1 and IFF2 [treniorawme [mn [me | eam MPU reset 0 ) El 1 1 NMI acceptance 0 1 LDA! * * Parity flagtFF2 RETN 1 1 IFFI-IFF2 LDA,R * * Parity flageIFF2 ) INT acceptance 0 0 RETI . * El 1 1 ) NMI acceptance 0 1 DI 0 ° RETN * * 170089 Note: * =no change. (2) Interrupt processing With a non-maskable interrupt, the internal NMI flip-flop is set to “1” on the ) falling edge of the interrupt signal, NMI. The state of this flip-flop is sampled on ) the rising edge of the last clock of each instruction to accept an interrupt. A maskable interrupt is accepted if the interrupt signal INT is low (“0”) on the rising edge of the last clock of each instruction and the interrupt enable state (IFF=1 and BUSREQ signal=inactive (“1”) ) is on. The following is the processing to be performed after a non-maskable interrupt and a maskable interrupt are accepted: (a) Non-maskable interrupt (NMI) When a non-maskable interrupt has been accepted, the MPU performs the following processing: 1 The internal NMI flip-flop is reset to “0”. 2 IFF1 is reset to “0”, disabling the maskable interrupt. ‘The contents of the IFF1 immediately before the interrupt acceptance are copied into the IFF2 3 The contents of the current program counter are saved into the stack.

4 The instructions starting from non-maskable interrupt vector address 66H are

executed. The non-maskable interrupt processing program terminates after executing the RETN instruction. This return instruction performs the following: 1 The contents of the current IFF2 are copied into IFF1. ee MPUZ80ASSP-24

When an interrupt is accepted in mode 1, restart is performed from address 0038H. Therefore, the service routine for this interrupt is programmed from the address 0038H . Interrupt in mode 1 Address 0038H Execution of RET! instruction 170489 Figure 3.2.7 Interrupt Processing in Mode 1 @ Mode2 The interrupt processing in mode 2 requires a 16-bit pointer consisting of the high-order 8 bits of the I register and the low-order 8 bits (with the LSB="0”) of the data fetched from the interrupting CTC or TLCS-Z80 family peripheral LSI. Therefore, the necessary value must be loaded in the I register beforehand. This pointer is used to specify the memory address in the table. The contents of the specified address and the next address provide the start address of the service routine. Therefore, use of this mode requires the table of the service routine’s start address (16 bits) to be set at appropriate location under software control . This location can be anywhere in memory. The LSB of the table pointer is set to “0” because a 2-byte data is needed to specify the service routine start address in 16 bits and start that address from an even-number address. In the table, the start that address begins with the low-order byte followed by the high-order byte as shown in Figure 3.2.8, Se MPUZ80ASSP-26

Execution of ordinary program Table Execution of i Lower instruction [case [6 [2] Iregister CTC or TLCS-280 family byte peripheral LSI | | 170089 Figure 3.2.8 Interrupt Processing in Mode 2 Mode 2 is used in the daisy chain interrupt processing using the CTC and TLCS- 780 family LSI. The CTC and TLCS-Z80 family peripheral LSIs all contain the interrupt priority controller in daisy chain structure. In this interrupt structure, the interrupt request signals are connected one after another and given priorities for processing when two or more maskable interrupt requests occur at a time. Only the interrupt vector from the peripheral LSI having the highest priority is put on the data bus. By receiving the interrupt vector in mode 2, the processing for that peripheral LSI can be performed. When an interrupt requested by a peripheral LSI having a priority higher than that of the current peripheral LSI during the execution of the interrupt processing routine, the higher priority interrupt can be enable by the EI instruction to form a interrupt nesting. The maskable interrupt processing program terminates by executing an RETI instruction. This return instruction performs the following processings: | © Restores the content of the program counter from the stack. © Notifies the requesting peripheral LSI of the termination of interrupt processing. MPUZ80ASSP-27

TOSHIBA ‘TMPZ84C015B ee

3.2.3 MPU Status Transition Diagram and Basic Timing

‘The following describes the MPU status transition and the basic timing of each MPU operation. [1] Instruction Cycle Each TMPZ84CO15B instruction is executed by combining the basic operations of memory read/write, input/output, bus request/acknowledge, and interrupt. These basic operations are performed synchronizing with the system clock (the CLK signal). One clock period is called a state (T). The smallest unit of each basic operation is called a machine cycle (M). Each instruction consists of 1 to 6 machine cycles and each machine cycle consists of 3 to 6 clock states basically. However, the number of clock states in a machine cycle can be increased by the WAIT signal described later on. Figure 3.2.9 shows an example of the basic timing of a 3-machine-cycle instruction. The first machine cycle (M1) of each instruction is the cycle in which the Opceode of the instruction to be executed next is read (this is called the Opcode fetch cycle). The Opcode fetch cycle basically consists of 4 to 6 clock states. In the machine cycle that follows the Opcode fetch cycle, data is transferred between the MPU and the memory or peripheral LSIs. This operation basically consists of 3 to 5 clock states. Teycle cLK m1 | 12 | 13] Ta Maachine cycle a ee M2 M3 | (Opcode fetch) (Memory read) (Memory write) Cycle instruction vroaes Figure 3.2.9 Example of MPU Basic Timing (3-Machine-Cycle Instruction) SS MPUZB80ASSP-28

[2] Status Transition Diagram | RESET = 0 wo <iee-> 3&1: M1 IMMEDIATELY AFTER ACCEPTING INT? YES <wieasr> yes { wo wo }w jw we {rw “Ww hw fear <a ye No NO NO <a> B a <Bsr state yes No <mnerced > Yes No. <aqitions> ves. NO , i <Suasn> ves ko eae yes 15 <Es state o> YES wt TXWaIT NO NO <name> Yes, <r accent > yes 70409 Figure 3.2.10 Status Transition Diagram MPUZ80ASSP-29

[3] Basic Timing (1) Opcode fetch cycle (M1) In the Opcode fetch cycle, MPU fetches an Opcode in the machine-language codes in memory. This is also called the M1 cycle because it is the first machine cycle to execute each instruction. Figure 3.2.12 shows the basic timing of a basic Opcode fetch cycle. In clock state T1, the content of the program counter is put on the address bus. ‘The MI signal goes “O”, indicating to the MPU that this is the Opcode fetch cycle. At the same time, MREQ and RD signals go “0”. When the MREQ signal goes “0”, the address signal has already been stabilized. Therefore, this signal can be used for the memory chip enable signal. The RD signal indicates that the MPU is ready to accept the data from memory. By these signals, the MPU accesses memory to fetch the Opcode in the instruction register. The MPU samples the WAIT signal on the falling edge of clock state T2. If the WAIT signal is “O” on the falling edge of clock state T2 and the following wait state (TW), the next state becomes clock state TW. Figure 3.2.13 shows the delay state of the Opcode fetch cycle caused by the WATT signal. The data (Opcode) on the data bus is fetched on the rising edge of clock state T3 then, the MREQ, RD, and MI signals go “1”. In clock state T3, a memory refresh address is put on the 8 bits consisting of the low-order 7 bits of the address bus and the A7RF corresponding to bit 8 and the RFSH signal goes “0” and the MREQ. signal goes “0” again. This signal indicates that the memory refresh cycle is on. | At this time, the contents of the I register are put on the high-order 8 bits of the address bus and the 7 bits of the R register contents and the A7RF signal corresponding to bit 8 are put on the low-order 8 bits of the address bus. By using the RFSH and MREQ signals, memory refresh is performed in clock state T3 and T4. However, the RD signal remains “1” because the contents of the memory refresh address are not put on the data bus. The address bus of 8 bits consisting of the address low-order 7 bits of address (A6 through AO) and the A7RF are used as the 8-bit refresh address. That is, when AT7RF is used for the refresh address, signals “00H” through “FFH” are output. In cycles other than the refresh cycle, the signal equivalent to A7RF are output. However, at reset, the signals to be output are uncertain. Figure 3.2.11 shows the refresh timing. SSS MPUZ80ASSP-30

1 T2 TW ™w 13 Ta

Ao~Ais [XT Program counter [|| X__Refreshagares 1) mt] | TTA] + | © Qe annean | Perri | "Y= aan . WAIT J TN IZ Gt} —J : RFSH | 70889 ) Figure 3.2.13 Opcode Fetch Timing Including Wait State (2) Memory read/write operations Figure 3.2.14 shows the basic timing of memory read/write operations (except for the Opcode fetch cycle) in the same diagram for convenience. In each operation, the memory address signal to read/write data on the address bus is output in clock state T1. The operation in which the WAIT signal is sampled in clock state T2 and the following TW state is the same as the Opcode fetch cycle. In memory read, memory data is put on the data bus by the address MREQ, and RD signals. The MPU reads this data. In memory write, the memory address signal is put on the address bus then the MREQ signal is set to “0” to put the write data onto the data bus. When the data bus has been stabilized the WR signal is output in clock state T2. The WR signal can be used as the memory write signal. eee MPUZBOASSP-32

1 T2 3 1 T2 3

Ao~Ais |X| Memoryaddress_ TXT Memory address) eS Do~D7 Oe ed war —| dE J VE LD 170489 Figure 3.2.14 Memory ReadMrite Cycle Timing | (3) Input/output operations | Figure 3.2.15 shows the basic timing of input/output operations. The feature of | the I/O operation timing is that, regardless of the state of the WAIT signal in clock | state T2, the I/O cycle automatically goes in the wait state (TW*) after clock T2. ‘The WATT signal is sampled on the falling edge of TW*. If the WATT signal is “0” on the falling edges of TW* and the following clock state, the I/O operation enters into clock state TW*. Clock state TW* is inserted because the IORQ signal goes “0” in clock state T2, so that it is too late to sample the WATT signal after decoding the /O port address. In each of input and output operations, the I/O port address is put on the low-order 8 bits of the address bus in clock state T1. On the high-order 8 bits, the contents of the accumulator or B register are output. In clock state T2, the TORQ signal goes “0” instead of the MREQ signal. The IORQ signal can be used as the chip enable signal for a peripheral LSI. In an input operation, the contents of the input port are read onto the data bus by the address, IORQ, or RD signals. The MPU reads this data. In an output operation, the output port address and the output data are respectively put on the address bus and data bus in clock state TI, then the JORQ and WR signals go “0” in clock state T2. The WR signal can be used as the output port write signal. MPUZ80ASSP-33

1 T2 Tw* 3 71

“of MMH OS Ao~Ay [XT ortadaress [DY ora — oa, RD an Read cycle we . ry [| (output) Do~Dy eS Te 170089 Figure 3.2.15 1/O Operating Timing (4) Bus request and bus acknowledge operations | Figure 3.2.16 shows the basic timing of bus request and bus acknowledge operations. The address bus (AQ through A15), data bus (D0 through D7), MREQ, IORQ, RD, and WR signals controlled by the MPU can be put in the high-impedance state (floating) to electrically disconnect them from the MPU. This operation, after sampling the BUSREQ signal on the rising edge of the last clock of each machine cycle, starts on the rising edge of the next clock if this signal is found “0”. Subsequently, these buses are controlled by external peripheral LSIs. For example, data can be directly transferred between memory and these peripheral LSIs. This state is cleared if the BUSREQ signal is found“1”after sampling it on the rising edge of each subsequent clock state (TX), and enters into the next machine cycle. During the floating state, the BUSACK signal goes “0” to indicate it to the peripheral LSIs. In this state, however, no memory refresh is performed and, therefore, the RFSH signal is set to “1”. Hence, to maintain this state for a long time with a system using dynamic memory, memory refresh must be performed by the external controller. Note that, in the floating state, neither maskable interrupt (INT) nor non- maskable interrupts (NMI) can be accepted. eee MPUZB0ASSP-34

sate 1x ™ ™ 1 | Floating state Ao~ Ars ee ee elated Catlett rs ee | Floating state Do~D7 ee iets taleatetal mega, ange = | Po RFSH a | 170889 : Figure 3.2.16 Bus Request and Bus Acknowledge Timing | (5) Maskable interrupt acknowledge operation Figure 3.2.17 shows the basic timing of the maskable interrupt acknowledge. The MPU samples the maskable interrupt request signal (INT) on the rising edge of the last clock of each instruction execution. If the INT signal is found “0”, a maskable interrupt is accepted except in the following cases: © The interrupt enable flip-flop is reset to “0”. © The BUSREQ signal is “0”. When a maskable interrupt has been accepted, a special Opcode fetch cycle is generated. In this cycle, 2 clock states of wait state (TW*) is automatically inserted after the clock state T2. The WAIT signal is sampled on the falling edges of the second clock state TW* and the following clock state TW and, if the WAIT signal is found “0”, the instruction cycle enters in the next clock state TW. In this Opcode fetch cycle, the IORQ signal goes “0” in the first TW* state instead of the MREQ signal while, in a normal Opcode fetch cycle, the MREQ signal goes “0” in clock state T1. This indicates to the maskable interrupt requesting LSI that the 8- bit interrupt vector can be put on the data bus. The MPU reads this data to perform interrupt processing. Therefore, the contents of the program counter put on the address bus are not used. Unlike an ordinary I/O operation, the RD signal does not go “0”. a MPUZBOASSP-35

The Opcode fetch cycle for non-maskable interrupt request acknowledge is generally the same as the ordinary Opcode fetch cycle. However, the Opcode on the data bus at the time is ignored. The contents of the current program counter are saved into the stack in the subsequent machine cycles (M2 and M3). In the following machine cycle, the operation jumps to address 0066H, the non-maskable interrupt vector address. The machine cycles after these depend on the contents of ) the fetched Opcode. || — fast cycle. |= + }&-— + 6 LastT state 1 12 3 4 La CLK nimi Ty, 7 NMtinternal ~ ~ | latch | Ao~Ais _| | | X__Programcounter |X Refresh address |X| . SE = RFSH x | | 70489 Figure 3.2.18 Non-Maskable Inpterrupt Acknowledge Timing (7) Halt operation When a HALT instruction is fetched in the Opcode fetch cycle, the MPU sets the HALT signal to “0” synchronized with the falling edge of clock state T4 to indicate it to the peripheral LSI and stops operating. If the system clock is kept supplied in the halt state, the MPU continues executing NOP instructions. This is done to output refresh signals when the dynamic memory is used. The NOP instruction execution cycle is the same as the ordinary Opcode fetch cycle except the data on the data bus are ignored. ‘The halt state is cleared when an interrupt is accepted or the RESET signal is set to “0” to reset the MPU. Figure 3.2.19 shows the halt state clear operation by interrupt acknowledge. An interrupt is sampled on the rising edge of the last clock (clock state T4) of the NOP instruction. A maskable interrupt can be accepted when the INT signal is “0”. A non-maskable interrupt is accepted when the internal NMI flip-flop which is set on the falling edge of the NMI signal is set at iY MPUZBOASSP-37

(9) Evaluation operation Each of the MPU signals (AO through A15, D0 through D7, MREQ, TORQ, RD, WR, HALT, MI, and RFSH) can be put in the high-impedance state by EV and . BUSREQ signals to electrically disconnect them from the MPU. Each M cycle Evaluation modestate _,| LastT sone ™ x ™ 1 Floating star Ao~Ais, es es etaieied woe 11-1... Mt HALT a es ee Dy Sohail EV 170009 Figure 3.2.22. Evaluation Timing | Figure 3.2.23 shows the block diagram of the TMPZ84C015B operating as an evaluator in the evaluation mode. ‘The operations controlled by signals from the external MPU in the evaluation mode are the same as those of each device constituting the TMPZ84CO15B. (However, for the watchdog timer operations, see “WDT Operational Description” because the watchdog timer is of random logic configuration.) For the electrical characteristics and timing of each device, see “Inactive State”, eee MPUZ80ASSP-40

XTALI — XTAL2 MT HALT = CLKOUT CLKIN CLK MS2_ coc amt NMI Ni NMI Ao~As — rT {| De-by ZUTO9 INT CLK | ml :

20703 ToRg

Do~D7 WR CLK/TRG, | famed rh ,_T RSH cuxTRG morale. IT] G Et CTSA | ie | ith | fren | iE0 wt | peers orma ras Fa CLK RD Do~D7 WIRDYA oo TORO SYNCA ) So a 8 K | LH reset ORO RXOA crc CS | ANT a Chir A Pr) ee Teen Ho an CLG | 1E0, le! RS tel TTR te RXDB Ico iNT I 8 Mb S¥NCB ss jaa 3 Clea WiROYE ROY aad TT A> ores PA IN RD Tf [—P- Re ° oN ora} —TT1 Be PA i BoB PBo ‘M1 RESET lel WR RFSH -—— wt Dy~D7 1EO Br mn worour oxo CLK Watchdog timer AIRE ROY rT fad 1 Ea #FO &reagisters ict 5ST8 c/D He g #Ft ier vro8es Figure 3.2.23 Block Diagram of the TMPZ84C0158 Functioning As Evaluator a MPUZB0ASSP-41

3.2.4 TMPZ84C015B Instruction Set

This subsection lists the TMPZ84C015B instruction codes and their functions. The table below lists the symbols and abbreviations used to describe the instruction set. The symbols which require special attention are described in the locations in which they appear. © — Symbols (1/2) a Register ng Register B,C,D,E,H, L.A, t Register pair BC, DE, HL Stack pointer sP q Register pair BC, DE, HL, AF Pp Register pair BC, DE Index register Ix Stack pointer sP s Register pair BC, DE Index register Ng Stack pointer SP tH Higher register of register pair (8, D,H) ) Higher 8 bits of stack pointer (SP) aH Higher register of register pair (B,D, H, A) XH Higher 8 bits of index register IX Yu Higher 8 bits of index register lY PCH Higher 8 bits of program counter (PC) tt Lower register of register pair (C,E,L) Lower 8 bits of stack pointer (SP) a Lower register of register pair (C,E,L,F) x Lower 8 bits of index register IX Me Lower 8 bits of index register IY PCy Lower 8 bits of program counter (PC) rb Bit b (0-7) of register (8, C, D, E, H, L, A) rey eee MPUZ80ASSP-42

© Symbols (2/2) [evsinaion [smi [tenn Memory mn Memory address represented in 16 bits. m indicates higher 8 bits and n, lower 8 bits. (HU)b Bit b (0-7) of the contents of the memory address indicated by register pair HL. (X+ dp Bit b (0-7) of the contents of the memory address indicated by the value obtained by adding 8-bit data d to the content of index register IX. (UY +d)p Bit b (0-7) of the contents of the memory address indicated by the value obtained by adding 8-bit data d to the content of index register IY. Flag change symbol o Reset to “0” by operation. 1 Set to "1" by operation. : No change . Affected by operation x Undefined P Handled as parity flag. P=0: odd parity P=1: evenparity v Handled as overflow flag. V=0: No overflow V=1: Overflow Operator e Transfer * Exchange + Add - Subtract A Logical and between bits. v Logical or between bits. ® Exclusive or between bits Others FF Interrupt enable flip-flop cy Carry flag z Zero flag 7120089 ce MPUZB0ASSP-43

TMPZ84CO15B Instruction Set (1/9) ss frrsane |_| ae ee Ce ae a ee ee ed wna 0 rrr tio” fobsex8’ Tren eee Sees de) bea ees toe (Hoa cee tia Pesta | eee TSE] ee ib" Cineay AN oat tod Yoo re ieea Shee eree re lit}epyey 21m Ot cre 110 | aBsexe ppb i 0 | ore wj.04 ded ddd |e ey srrnessesfeeeseadevsedsceduatfenanedeed fou wo eevee Ya ain ter” Pro w(iea HSER PT PIES Se] too ot ere 110 [assrxe ae i tf tot a eee A a : eee eee wees ed to (ixed) ce" ait on aor] o0 (tirdjer SPTECPIEP PPI Pie or 110 eee | 2060 PEE ici to ives) fea a ton Po” (i¥sdyer prix sie POPIPIy Sis ° 01 110 err [7060 pa i © fib Giese os ito tio fae (iio SPSS Pe PS Pee ly ay ge [tO Gixed) 0" a cis tar Tbe Giese Sn em PIETY epg < 00 110 110 | 36 bo : < ad dad aad fd PPG ae ett ae Cer spl sbepo poh ot sti r oo 110 110 | 36 Ppa d bod 2 ad ded ads fe Pep boi [ie A Gey" 00" aot aio! | ox Pacee ne Pe es Sree ee ed Bd to."A, (06) | 00,44 O10 "Tn 12 eee ere eee dO (0, (an) 00 tit o10 | 3a #(an) SPSS PSPSPS Py BBE) ACY 8 0 one 08 eek fe gehts i” (0k),A"”” [6010 cio] 12 “[eopea “ Ses eee Seno ae) i “(en),a" 60" ito 016" 32 no) meen Pope DPS Pip apis eS ne Rie Te “oo ee Cicer er sr Sia ees iri eof Qh OO [7 - tip decbodueduund = Ca ti ot tor” | eo me SOSERT OTS ae oP IP SPs osceeef SEOUL 144.1 BE. scree oe ee a wR tod tet "fe “we SPliy Pre oroecpapeg BRK avai wor Peo Rca SUDEP PTY PSP Ip ape ot oon lar pep <a] ten 00 to oot forsexto er Pas annan sna | Pb bod ee as om nee man |i po bd a foo co Ce A SeShyiorybrpers or for = 0 100 001 Jz pod wlio : sn-nan nan | Pibbi sel Note: hgmeansany of the tegsters, B,C,9, 4.1 'FFin “Flag” column indicates that the content ofthe intrtuptenablefp-fop scoped into the PN lag 120489 oe MPUZBOASSP-44

TMPZ84C015B Instruction Set (2/9) ee [tea | nee | nose |_| val w) mwiwie Ue WY Gm) Pow 101 ig 2m eae Spree rege rly l ye] ie] afer to GK, (enya ors 101 Poo ‘Tye (enti) ~~ 7 SPIE PLE PIL ETy eT 20] : 00 101 010 | 28 1Xpe(an) Sto a Gan YE ia dor Yo ‘iyetansi webb Dee PrP yey ae ean (CS Ce VG ~ DPI PTE SETS Ty ey ie i Gane Pi tor ter Yeo | (ens bjt ey pay Pl yl ye) ao. Lal or tro 01 asvexto | (anyety i i we [id (enj tix rat Uae (Seen te es ot cn eee ieee eee ers yD - 00 100 010 2 (0 eX t Z H to Gm) ctv ae ay aon FO Gnsij tty SPIT PIE PELE) ] 20 00 100 010 | 22 (nn yey, i iw soya Ania oor | Fa gee Signe Sipe ape lo” SP. 1Y in iit 101 FO ‘SPely SPstereix: -ber-P 210 . soon AE ATL 00E,, . 1 ee ee 11 400 101, | es SPesP2 . idk Se of we] t0 ea Jan bosesbnng ow ree CL ETERS ME bes MPUZ80ASSP-45,

TMPZ84C015B Instruction Set (3/9) ioe | erary [vex | Fa ae Cr ed B fer Gaye "ay oir tor” Poo i= (Sei) DPD PE PP PT Tt = ee AE 100001 LER PMO (SP) Se sdcubasedeeed S fee aya Par iy ior” Yo TYye(SPei) ~ Ps Pees ixPopsys 2 11 100 011 Jes YL o(5P) i i i tor 11 101 101 JED (DE }+(HL),DEDEHT —PaTKTOiKi io: 16 ) we 119.100 000 | a9 of MEEMLA BCOBC=A So a Se See Se en : tore Ab t02 tor PEO oe ye (HL) DERE mp TEMEOEXE O FOE 21] *[8C< > 0} 10 110 000 | 80 HL+HL+1 ,8CeBC-1 Repeat unti Pi i 16] (8-0) ) & fio rior Tar Pee foe cL) ae Serer reeves sia arier} ca an 439.101 000, tae Lot oe oe en Pa ra 2 | kbaH tee to Peo oe jot EME E SESE SOT RE OTST IP ST aa] ecece 20 es ro sss 000 [as HLeiL=1, 8680-1 Repeat uni 16] -{0c-0) wx fe i iat i] wii) wyivivhybyiitcpata 8 fermen 20.400.902. Jak Pmbemet mea t E oe fevie iF ibt ii feo AGL) MLC WET PSE SE TTT Y Sai] tees oe a Fe cnn $0,410,004, Repent An) or 6, oshaptisetndonfet te] ofery ed tie ii ior ier” eo aH) eee Cees Wr) etl Rea hat CPOR 11 101 108 ia A-(HL) HL+HL=1,8C*8C-1 SimeK ee ya 21) +(BC< >0 & so1s 001_|a9 Repent unt Ax(Hi.)orBC+0 pops wef Ae > cH) ee enn Ca eae ee eC A | noo" Rla "PHY 900 10" fee fcken TEPER Es 60 AC." Y a0" 900: 13986 Lacasgay eg eave eb apa] pe wo "AS (Lied [HY 0it tot” Poo acne tkeay PEDTyee yew e rey sie Stee . 0 000 110 | as ppidd | ot < $8.80 Nl gsi nmnanannnnnadindandametemtfendcceicel rh a] 0 | O10 Sas a HRSaS PAT TAT Bo” Pra Rea aa ee ee Se eC rir) Bed bon ® 10 000 110 | a6 i ri {seo [a a CT Sb ae Oa an Eis Sn ee RE Sean ES TEA WS OO PT g fae ae ii oot a0" Jc” ReaeaecY POSES DEP AT S face aia ii wii Gor Yo0 ono ikea o6¥ SHIP were elie 5 10 001 10 | ae i mens E pase aaa eae ier Pre wens ieedj ce eee ee eae ice ira ry 5 10 001 110 | ee i i a ae th Ce ee eee ah = Psu n it 910 130" fos hea SPE VTP ep oe Ee Cece ee ea re Od sus" (ixedy Pid vii Het oo ik (Hed) SOP PVT ET STi wo o10 110 | 96 : cance $M 849,488 Ld — ae ee ee ‘sue (ved) Ya tt 101 TF aeAR( TV) PESTLE TTPO Sy is! 10 010 110 | 96 PoE EOE Poi ee «ss ca |e id Note: *M PrvfagisOif the result of C-1 «0, otherwise PV = SN Zilagist A=) otherwise 2-0 | lindiates the total condition ofthe number of ecles and sats indicated by ro {meant any ofthe epstersA,8.C,0.6 4.0 120889 a eeeeeSSSSSSSSSSSSSSSE MPUZB0ASSP-46

TOSHIBA ‘TMPZ84C015B TMPZ84C015B Instruction Set (4/9) hen [weary [nex | ca Tone en PEEL ee LL] ee seca or aie oe peeed STRSTR EV Tee 2) 7/8 ooo gee io ca Tao fe reecnesy POSTE EV ET ES eT Gd oro SbCA: (ded A8 wait “aot” foo Yaa ikea) ev SPST VT Te bey ia] e fou

10 O11 110 | 9E boi ‘4/100

dds des | doce so . I ecadecedeseefcseceeeeuesseh of [10 Be A CAVSG) PHT ior 6 Perrine seetyeetgiviiis spi] alin wo 011 110 [oe me 6 996, 484. | . ene ee ee < [aon 11 too" 10” Jee eR SPST REY X De Toro] 2 7 eC a eee ee er er a rd Oe) © faioGikedy | ir ais “tot "Foo TRA Dked PVE eo of sp is ° 0 100 110 [a6 H co fio Give Ton feo BARS PEPPTT ECE ere spas z 10 100 110 JAB < 4e.ee4, ave. |e ne eae a ee es . a es CC LS Seer rore ee Tore |e] 7 [SER ae io aa ag aca) So eee] z= [OR (ix+e) ii 011 101 oo Aeay( 1X8) eee OK: P 0 fO) 5) 19 z we 10 110 |6 i ~ Ika Ce soe Eessssbeecesdessennbensebeeredfeceerdhonsea ee faa Gaieay PA Ga at "PB aoaeaeay SSO TR TOE] ep is < 10 110 110 | 86 H H . sf aad, | 8 ee Oe bad 7 [oa = io ior rer [ABer LRokye ol ae oe oe Oe ee ee et = [ions ii ior tio" Yee ike eeere ere ere fap 7 © Pie (wey aa tor tno fae Faeyr eae ha Py ion” beeay "iY 048 HoH" Toned died Peer rola were | S| io ro io io [ae pe i wow avsay ie tin ter” TFB aaa SEPT TTR OTe ep ie 10 101 110 | AE : i eee Cee ee | Se ew eae enn tite" ie PEE WET ET PF Can ee CLL CCT eee ee ieee Oe) cP (axed) 11011 101 |oD A-( Died) eee ee Wp oe slag roan uo fae i a 00, 406 |e nn ested ea Pi a orf aiWe8 PESTS EW ET TE ep a 10 111 110 [BE i 4 ded dod. | . shssefesedessnec sender cena Nc” (Hi) 90110 "100" | 34 ecips! AR ae en ee eee Bd Ld INC (1X48) iL 011 101 | 00 (Died )e( Died 42 eee ERE WM LOEH | 6) 2s oo 110 100 | 34 a4 00a 460 _|¢ Note: rmeantanyot therepstersA.8,6.0,61,L 10889 MPUZ80ASSP-47

$$ Aa RS TMPZ84CO015B Instruction Set (5/9) re [inary [nex | re ee opine tieay ar it tor] FO Ceara Tiviaieie vot] ef a = oo 110 100 | 4 rt joi fore Gay 90 Hi9 “aor “Lae Pike ica eLERED RE WEEE a Ta 8 [ooo eS foec tavern tor P00 (iX+8) (0048) -1 Spee OEE VW Tato 23] c | oor ba oo 140 aor [as Pip: i: oJoto ie) ee ee Se a ae E fou

2 Poe asaya Han “tos "0 *Y iveayeaveay se SES LSE WTTTED ep aa] wlio

ee oo t10 101 |35 ppppitl Laon crs dd ddd dae |e i i i Ajit Bp ene] 00,400, Et [27 [aeiaal adjust sccumvlater| ss xi ei xi RinasL ape ee a Plecee eT B 5 | Nes it tor tor” feo ROA POSSE Py Ty Te 6 “Teer Yoo asa air Par eer Sn Rees CEES SOPEN EE 4 BSCE 90" aa0 tin P37 a sennenmnfitabemg ROE Ru bhp fA we =| Noe" G9" G00 “aaa” foo no operation [wg wx te 4 & ofr Ce a Sc for ae aoon “Yes ere eo eeee eee eee lie) Fe] bs nnn ECan Le Le ree Se ee rd jin oO 11101 101 | £0 ‘Set interrupt modeO sPeieperx po PlTl 8 oar wu }.92000 120 | 45 eu i Fecndon ania SELB ae tar tor Pad Set incest Wade Po ghee é oe 91 910 110. [56 . 1 dbeecdomadond & fiw e Ay Yor 201 PEO" Set inteiapt made PSP erty rhs 3 o< or oi 110 | se H i HD, MLjt_]00 eet oon _foseaxio [wernt wo fahst ke ktk nets) ape moe Wee tan “tod” feo airaentcag Pee eyo fe Pa as | wefoo arse ow farcxio | . een oe | or a ae a1 toi “ior [eo “Patent =iMey SPE M TCP V TTS 15] RL) 10 . pmef Qh t80,.010, [eavexto fo see nee ee Oe solu [moo HP onion” Pao ie SEE Seep a Gs z Sn on be a a ee SE fae ave a ator Pao iveives SPIER TN WPT Tebe [apis] weyeo e{ Joost oo Josesxto | con buedowbonbowndo dol velox fie Ef a0 tee oat Posee eto Laser” onmennnfern tik ic Epc dcp f 8) Bef 10 ep twe Ge 11011 107”) 00 Veen SPIE PIER PIPL PS io] split al. vneeved09,300 023 [29 . ee . ° like a¥ i iit tei "Fo iveiie more open S Til) alto] Tyee 2 ... 99.490, 01, | 23 soso ecedenbmedeundaed sc] 00 Bee Joo eer oat Foasteie fee Jue Peepyprby pips é] oefor bee Te it ot7 ior foo tei SELEY PSP PD TIES io] ty/10 foo ton er fae bo dodundadoduocd _ sel bee ivan ior "Pro faved worry er Pll 15 oo 101 a1_|29 Lu [ij en Pema PL x Note : ssisany oftheregister pas BC.DE, HL, SP. PPIs any ofthe register pairs BC, 0. IK SP ‘uisany ofthe register pas BC.O€.1¥,5P 120499 eee MPUZB0ASSP-48

TMPZ84C0158 Instruction Set (6/9) | einany [vex | om RA oo a0 ant {a7 Chaetreoy) 2-0 x - oe] . i rca oo oo an for Gostbraq [-i-ixcoix:-i0:+] 1 maa oo on ant [ir GGSTRIRP J-i-:cco ki - ofa z aie? oe rarer iren (2) Pere oP RE RO eT 2 F [ere 00 000 rrr | O0+r sessed | 8 | 000 BE GE YT 008 On" co SELLE TEV ER TOTS P GY Gel c foot sf OB, 908,220, 08, Jjowefuainnefns fone gungee 9 Jous aie Ges OAT H6 "0 pee PP ey ep aa) e fon . toot on fe ie 1 | 100 . as ded aed |e © (HL), (1X+6) , (T¥+d), H |} ton = J, 99,090, 110. [06 ee ee alin = fie Give Ya dN oro stotyretere terre : “ 11 oot o11 [ce . de vas ast | i i : wpa ay oat ate SOPOT PTTL GE | © fae wy YE aL skew shebyiereh Pere e : “ fop.ore. 10, [te J sabearbndagdondud ae Gea Yaa ond t0r' "oo See yrerye Pw Pere pe 44 ded des {a F(R), (Dea) (ved) | E poe ap 019 110. | 16 a a ae ave YA HAT Han" Severe eee Le roa ont |e i . aa aot aaa |e i ) woo fe} Boe dundune wie ai'oar aii] SPEYER TTL SE | wae (HL a 00a Yew SESTY TOTS pote Te ses ceceerne) 00,008, MO LOE | Fo) hosed eee neeeedceedncebnsefne es ass eed | a pad oor 110 [oe Landa od wee (iva Ya an aoe” fr See PTET s 1x00 on [ce ea oes ood | a go oor 110 | ae mosntentntsetnanfasefesed ene desneeeudernebecr dec ee weer Lae oot one mee sree ee eps e0oi1, rer [180 : ne ai) ii oor" 'o11” Jc ern i fa (ise) if 011 “tor Joo F(R), (ase) Peon to x Pio s) 6 tt 001 ot |ce 44 ddd ddd fo i : oo on 9 fie i ane Note: rmeansany tthe registers 8.0.6.1, 120869 MPUZBOASSP-49

TMPZ84C0158 Instruction Set (7/9) oe [sy [nex | “ babe aay pa iat Po Tee aT ae aes ase fe (iva i E 00 O11 120. | 1e = ' hess deaasdonwebeetdeessndeandenae on aa i001 oii fee” 7 SVEN EO ERT PR TOTO + [ere ses 00.100 rer | oer edecndeeed ee ae 8} 900 BR ES YEE ot "LT fw sivtyigivee tare lapiel ¢ foot 5 ~ 00300 300 a8. mjeseecpeseefeecesfnssefenescedieanefwnnef nen oa bend Sia (aKa YT ot tar” Poo er er hr ee er eee iy e fou 11001 o11 Jee ees: i poi 4 | 190 6a de des fe TANSEY, ved) Pid trot oo 100 110 foe sehen feadncdecbedeade Alani ‘Sia (1¥+a) in tit got Pro” elelk ork: Pore] 6 11001 on feo : as cae aes fa pid : ‘sta if 008 O11 [co ™ ee ee ee eee i ay ‘SRA (inc) “Ptr oor ort ea” . wearer ee eye Baa Pay ont tat] 0 PTO STOP 11 oot 01: [co rEXy, i : as cae aes fa [4 i pad soopeungenn 208 10 fre | emp Caaeay staves) fo Bia aay aT aE ior Peo SS OTE PTT TTS

11001 O11 }cB fi: PoE

ad dde add jo zo: Pog sna) Q@,401, 120, 2, oe B edeeederad ad. | aie" ii dot oii "Yes Creer ee ee eee air) veneered 99,441 00 [3846 ee eee nen | BLES YT aH OE” Tes Cree ee eee ea ir) : ve oof $0.29. 138. 138 ses ae ae oe en ae PiU AY OnE ior” Yoo weiner Te

11001 O11 [cB : i H

pend OO, LE, 120 | 36 Fa (HL), (14d), (1¥48) a oe oe oo oo aa (aay aL tor” feo PEPE O TRE RTS PEP S 1s oot oi: [ca i dd add ddd fo i aio “Ta tor tor feo” a Cee er he ce ee ee ay ” on tor ant | oe af ao) Fao}m)} | PoE: RO EP Sy Bar petencetc rte cb spall + on 100 a11 | 67 sa) LEA ws i i Ao are Tr 001 oi fee Xe ek fox? OTS 0 | 000 id nen Ca Ce Bese Joc sbocual 3 foot gait eam fav ear ous” Ys me Pe TT eT 2 oro 5 on vob 110 fatwexs | 2GiTjy : : a fou Ee 4| 100 58 : : sro 6 | 10 Note "1: Rotate digit left and right between the accmulator and location (HL). 2 fast The content ofthe upper half ofthe accumulator sunettected Thenotation tL indates bit 0t0 7 within the contents ofthe Legs pal ee MPUZBOASSP-50

TMPZ84C0158 Instruction Set (8/9) | inary [vex | & Tre ieeay | On Tero ee ae ed u1 opt 11 jee (Tap poeE EMM ae ass ase |e PEpb ad aie Saves Pr Lan "aon "Peo LOST EYED TOPE SY a + 11 001 o11 [ce (ioe ii pil ° a eae os |e PEE:G me PseR BE A oor “oni” Yew eet spriyereyP raves pape] Zhe see wie YF oor “oN” Yew ii ige " SPIEYPSE TELE | aa] c foot < se 32, bbb 120, Leesbreg cvvnsnmnnenesnn Lewdicsbaeducsdanebenbenfeandenn| 2 1010 BeBe) PA GN tar" oo Gineajgei whrnypriyer?sbsy spas] elon ® 11001 ont foe pid 1 | 100 . és dod dad | 6 Pa EPG GE tL} ton Pa 14 bbe MO. fesebx 8. | nnn fife funda donned nfo | ALE ce [see Garey ion” Pro (aveaigey Spree esi SPs s Page 11 oot ont | co Pb Poi [ebb + ad ods dee | a i pi 0 | 000 Ee 11 oot oi cB red SPPEYPLEVE OD ESEL YS a 2 [oso — [RES b,(HL) | 11 or ont [cB (HL)peo SPeixieixi = i-i-] 4] asf 4] 100 - wo} 30,008, 130, [86408 |. an Se Se SO es ORR HF OFT iat "Yoo (iieajyes SPrtyeriy Precio eyed 6 ja 11 oot O11 [cB PGP: Pod Beses 46 46 aos | 6 Pi dd wes SiN Pa LAE tor" Giveajee shryirigprpsrcy spas 11001 11 [co ii i i 43 686 ass | pd Pid 10 bbb 110 | 86+bx8_ bo H Ha an i 000-011 Yea cor TT pape a aan nen | (Oniywhen conditions met) DS pod relative ae HY 00 eat 000" 18 pore} DPDEPPIEY ET ELECP SY ie made. ane-2 = [See 00 iit 000" a8 ii gcas continua SELES eS jftwo's 2 ceonad 22,882, 200, [a westpcsee PE PIP SEES 2 [complement SR WEE Y60"Fi0 "000°" 30 ‘geo, Boose CPEESEXE SER DEES ES [a a2 feumber inthe SREB P00 “et “O00 | 28 F250, continue eas See See 7] -126<e<129 . ce 8 ae, a0 La oc 5s oe ede De SR NTI SSe"" 00100" O00” | 20 if 20, PC+S+0 Terierciey silat a Ae Et iWtteontinge SESE Sahar Cras ‘00 °6i0 000 10 | BeB-1, 8-0, continue PLP ETE Ts ea e2a aa |e. BeB-i, #BC6, contmve eae eink ce 13 eT For “aoe fea ro DEDECEE EE ESE. ‘ [eed] Condition Note: © ae-2inthe Opcode proviesan effective adress of PC asPCisincremented by 2beforethe addivonote. at sod Nowzew ‘© Sinacates the reference tothe location counter value ofthe crrent segment Teorl done ‘©The notation (Ly (K+ ey inciates it (0 07) within the contents ofthe register par. nel oto neceary {The notation rincicates bt (Oto 7within ther regiter | oul coos # awe-zinthe opcode prondeseftective address of PC +088 PC's incrementedby 2 prior tothe ation of 0} 0d] ood Panty ¢| 103] Even Paty | 11d signostve L111 sign Negative 7048s MPUZBOASSP-51

TMPZ84C015B Instruction Set (9/9) mw

7 Tron er TST

= 14,101, 001 ss ved nn derefnsdenebeeh > it tit tot -i-ixioiabe pers = 11.101 001 i i — CALL oan 11001 101 [CO (SP-1)+PCy, (SP-2)*PCL_ ei-inieixi - beste Ww kkk « me one em | w SPesP-2 i Lock _] 99H j 002 2 feat" eee 100 casei” if condition is met same ar TPT PIPEP OPIS 17 | 10H | o10 a fin ann nnn {a cAttma ii | LY] sen fon © mason inne |e |ifconditioncis not met;continue |= 2 = KEES 10 | 20H | 100 et 11 061 001") ca PCLH(SP), PCye(SPet) epee PI PII. 19 | 28H | 101 2 ‘SheShe2 bo reefers ntbensede evretadeeere be bedid ete = [RPE Ga cee “aio Peasexa”” Liteondtoncinmet ame sener POST TTT |e pa] sew ao [RET it 101 101 | eo Return from interrupt Processing | === ix =i xi = ia be | ed ree = eccstseene) OF O01 201 LAD | eoutine: oo ee ee ee eee 8} coo < [Rew i dot tor Peo Return iromnon-masabie | = Xs va] coor vy 01 000 101. | as interrupt Processing routing. 2d pf oto ‘aij Wake iene] Garctjeogucareyecg PoeTageregP reser by py] elon Peyea,Peyrjash-sP-2 PPE | t00 Rayon mn) SSRITRT ST cdi a msrnonereeg a, 2AM, BRM, 1S. LB=tAOrAT AeAG=AIS i. sipeebeasticceed es mE WF ey 1 161 101 Yeo “'Vee(C) ifr=t20, onlythefiags |e 8 xe xt poe 2 5 ir “Tin aor ter “feo Gicjoe) BOHEME EY ERE ETE eT is = of 19,100, 030. | m2 le . dsodusebeedeangnnndun & PINTER 11 101 108 | 0 (HL)*(C) BB~1, HLM +t KOLiM KEKE KaiK 21] (800) >|. _...} 0,110,010, 82 Wepeatuntie=0 [ee ee Oe 1s] feo) er ° [ino 11101 101 | ED (HL) +(C) ,BeB-1, HL -1 Kim k KIRKE KR Gaik 16 2 | INDR 1 t01 101 | ED (HU}*(C),BeB=1,HLeHL=1 Ridikinixi x fain a] [860] < seesvnsnf 10.311 010] 88 RepeatuntiiB=0 5s adosmubuedeoedeeadeoh 18] +[80) OUT Gaye 11 Gio O18 fos) (nye ~ ees Ses eee ein ry ia . an.aan ona | nf QPAO~A? Aca AB-A15, wd J ecudesue 2 our (eye a1 to1 ¥09" eo (cer eres cies sees 2 z coves 92. err 001. | aterae aceon rbesss bases facensbeeeentivene foe . = iti iv ior" ion Jeo fein eaMM TP ee eee Tie Orit it 11 tor [ed (SAG) ea TL ep eee TTY ai] too) | see 40.110 011, | 83 Repeat until=0. vd : Eoendod ag | +fa-0) |* ‘ure i ior 301 eo (Cpe (HL) BeB—1, WHEL Rig EERE TTY 16 sss 29,401 088 | 8 sree a oe i . ‘oro if toi tot” Peo (CoC) Bay HE eevee yep eT Sx 21] (800) itt 10 Los egeaturciond i ta} (0-0) & aDthvough At indicate the adres bor “es: | soe #1 Jindcatesthe total conlbon ofthe umber ol ces andstates nefore | ne eaey indeated yor [ou | cory pe 10 | evenvarty wl tit | sgnnegatse 120489 eee MPUZB0ASSP-52

TMPZ84C0158 Instruction Map (1/7) MPU Instruction Table ( I ) | : ee os ee ee ee ) w ] w | me bec nica] x | soo | wo orc | to | ac,mn | @C.A} aC 8 Ara | HCC | A.{BC) c ca DE, mn | (DE).A] OF > wie | aoe) | OF € cy be | oc | oo OH Om} OA | EB ix4 BL | ED ) 7 w lo oO wo w uw | Har] to wo wo Lo wo wo wo w | (HUB } CHE). | (HU,D | (HL) E | (HL). | (HLL HUA] AB AC AE AH AL [AGU] AA Note D~@®: Multi-Opcode Instructions (ref. Table (II )~()) MPUZ80ASSP-53

TMPZ84C0158 Instruction Map (2/7) ® Byte 1“CB” Instruction Table ( II ) (Byte 2 of 2-byte Opcode) SE e me [mc | me | mc | me | me | mc nc | anc rac | arc cfofet w]e fowl a ofe of] ww apa la mu fom mR me sfc |o Lf ow c “ny sta] sua | sta SRA tfow | a c sa | sm | sm | sm se | sm e{[cliol|e wu fia ar ar | or ar | ar ox [or [on [or | or | om | on ac ot | on anny | 0.8 wc fino fue fae foe [ow] va on | er ent en | ar ar at | or | er | or ne | 20 2M 2c) | 2.4, 30 au] 3c f[s.ou] aa er | or ar or | ar at | ar or | en 40 | 4e 400) sa | sc se | sm same | 5.8 7 ar on | en or | or oT at | or | on Exa se | 6H ei | 6A 70 a | 7 | raw es mes | nes | es | nes es nes | nes oc on | or foow| oa ne a) nes es es ) 2.04) 3.0 at a | aes | acs | nes Res aes Res aa [ac] ao aL sc Su aes | nes es nes | nes | res | nes nes | nes | aes 68 | 6c 6. ne | zc} 70 | ne 7 [rd | 7A ser ser | ser | ser | ser | ser | ser ser | ser 08 on | or foo] oa | ne | rc eo) ser | ser | ser ser | ser [ser | ser [ser [ser [ser [ser | ser | ser | ser 26 | 2c | 20 2H | 2c femu} 2a | ae | ac | ao | ae | an | ae [aw ser | ser | ser ser | ser | ser | ser ser] ser set_| ser ae | ac | ao an fae feo} oa sc | 5.0 sic | 5.0 ser | ser ser ser | ser | ser ser [ser | se | ser | ser 6c | 60 6H a | 70 | 2c nef zm | ra frou] 7a 120888 eee MPUZ80ASSP-54

TMPZB4C015B Instruction Map (3/7) ® Byte1“ED” Instruction Table ( III ) (Byte 2 of 2-byte Opcode) L PPE Ee PEPE PEE ete Tt ] our | sec ca W no coe | Hac co Huse RA w | ou | sec re our | aoc | [efemfefssfel | [fe tafelas.ey [esl w | our w | our | ac | w Ho | OM ut |. | HOM | mine 7 © w | our | ene avo | Or Perret Tt ele ret tt tT Pie eer Tet cette ey rey ey rt ee T2048 a MPUZ80ASSP-55

TMPZ84C0158 Instruction Map (4/7) ® Byte1 “DD” Instruction Table (IV ) ( Byte 2 of 2-byte Opcode) fe Ee Ppt PT er 7 poy felts TTT TT etets| yy] 1 oa we | vec | w +6) | ora | oxe@ we (xed) 5 We. OH, wu (+4) Wee) to > IDA, (ed) (x+8) (K+ o a (Koa) sue seca. Pp PT TT fe) es] AND (ced) oR a (+a) mo) ep PT TP re x PUSH ” yo tey fel Pel et wo PET TT PPP et Pry 120489 Note ©: Speciat 2 byte Opcode Instructions (ref. Table (VI)) a eee ee MPUZB80ASSP-56

TMPZ84C015B Instruction Map (5/7) @® Byte1“FD” Instruction Table ( V ) (Byte 2 of 2-byte Opcode ) v FE ‘00 = | | w | o | me 400) w | EC vyznn | omer | 1 ree | seem | we | vec | wo 400 | vee | ered) | vee vs? | ‘ ioe, we PT es et Do. WE. wes wd woh, wo. (ree iz) wo] of} wo] ol wo] wo wv+6 | orca [oven | arse | ovee | ave a fc | of] ie [ow | ‘200 ‘AD0C (wee «so sua suac A wee, wie AND xOR Wed) ws | on o wee) wed EPP ere yet et Pet te POP x PUSH ° sev ” ™ a sei 120889) Note ©: Special 2 byte Opeode Instructions (ref. Table (V1) a MPUZ80ASSP-57

TMPZ84C015B instruction Map (6/7) ® Byte1“DD” Byte 2 “CB” Instruction Table (VI) ( Special case of 2-byte Opcode : Byte 3) FS me PT TT Pes | mw Oro mA Py TT ee | PET Pe ort, xe oz, ar, ome owe are ams, EP tT Pes are, a, me oe) my, (X40) sz, m3 Pt TT TP eee] PET yes ee m6 m7, xe) xa ¢ sro, sri, K+) ox+8 we, aT, () xa sre 3ET5, ome oma Tease eee MPUZB0ASSP-58

TMPZ84C015B Instruction Map (7/7) © Byte1 “FD” Byte 2 “CB” Instruction Table ( VII) (Special case of 2-byte Opcode : Byte 3) | fe ee ee mc aR (Ved) Wed um (ved | wa RA ) (ed) +d) | SAL | ose | Wed) wee er, wed) ora, ved) ane, a7, area we 50, wed nes, E53. (ed) ores mse, ESS, aed) wed nese, m7, aves) wed c sE¥0, st, (ved) aed sera, ser, ved) wea sere, ses. ved) wed sere, ser7, (ree) wed ory MPUZBOASSP-59

3.3. CGC Operations This subsection describes the system configuration, functions, and basic operations of the clock generator/controller (CGC).

3.3.1 Block Diagram

| Figure 3.3.1 shows the block diagram of CGC. HALT MODE SETTING REGISTER FATT (HALTMR : bit 4, bit 3) INT NM Mi RESET fg | = | 68 cLkK | wal VS CONTROL CIRCUIT | xray | |S ° | 8z Ce 10889 Figure 3.3.1 Block Diagram

3.3.2 CGC System Configuration

The internal configuration of the CGC is shown in Figure 3.3.1. The waveform from the external oscillator oscillated by the internal oscillator and divided by the divider is converted into the square wave for clock. The clock is controlled by the control circuit and the counter to be sent to the outside the CGC. The following describes the CGC’s main components and their functions. (1) Clock Generation (2) Operation Modes eee MPUZ80ASSP-60

TOSHIBA ‘TMPZ84C015B ee [1] Clock Generation ‘The CGC contains an oscillation circuit. By connecting oscillator to external pins (XTALI and XTAL2), the required clock can be generated easily. The CGC provides the clock whose frequency is 1/2 of the osicillation frequency. Figure 3.3.2 shows an example of oscillator connection. | cs XTALI XTAL2 | ) in | Cin FT Cou 170889 boc Rs yroes Figure 3.3.2 (a) Example of Crystal Figure 3.3.2 (b) Oscillator Connection Equivalent Circuit (1) For the quartz crystal oscillator, use the MR8000-C20 (oscillation frequency 8 MHz) or MR12000-C20 (oscillation frequency 12 MHz) manufactured by Tokyo Denpa Company Ltd., or the equivalent; Quartz Crystal product No. [Holder] Frequency | cin |Cout| Parameter (Typ) _| Drive Level [Toad Type (MHz) (pF) | (pF) Gi(pF | Co(PF) (mW) Mrgoo0-ci4_|HC-49|~ gs _— | 20 | 20 [oorss| 3.87 | 60 [os | 1267 | Ul 233 [33 | — [400 [25.0 [PT [mrizooo-cra |(TR-49)[ 12 | 20 | 20 Jooiso] 381 | 69 [os | 1255 | [20 Faof 20| [4.00 [ 25.0 0s [14.00] T0780 Note: The load capacitance in the condition does not include any stray capacitance. (2) For the ceramic resonater, use the CSA8.00MT, CST8.00MT (oscillation frequency 8 MHz) or CSA12.00MT, CST12.00MT (osillation frequency 12 MHz) manufactured by Murata MFG Co., Ltd. Gin (pF) _Cout (pF) [csasoor | S| [cstgoomr | [csaizomT | 88 [cstizomT ft L_csazo.oomxoao [20S S| Note: ‘The CST8.00MT and CST12.0MT need no outer capacitance. a MPUZ80ASSP-61

[2] Operation Modes The CGC has the capability to control 4 operation modes; Run, Idle 1, Idle 2, and Stop. Any one of them can be selected through the mode setting register (#F0: bit4, bit3: HALTMR). These modes become valid when the MPU executes a HALT instruction. Fetching a HALT instruction, the MPU sets the HALT signal to “0”, indicating that it has been put in the halt state. After the execution of the HALT instruction, the CGC performs the operation in the specified mode. Table 3.3.1 shows the operations in each mode. Table 3.3.1 CGC Operation Modes Halt mode setting register ; (#F0:HALTMR) Operational Description - Mode ae Only the internal oscillator operates, stopping the IDLE1 Mode —_| supply of clock outside. The clock output (CLKOUT) isheld at “0”. The internal oscillator continues operating with the supply of clock outside (CLKOUT) continued. When ' 'PLE2Mode pins CLKOUT and CLKIN are connected, only the supply of clock (CLKOUT) to the CTC is continued. | All internal operations are stopped. The clock [tL 1 [Run Mode |The supply of clock outside is continued, To%e9 The restart from the clock stop state in Idle 1, Idle 2 (these two modes are referred to as Idle mode hereafter), or Stop mode is performed by reset (RESET signal) or acknowledge of maskable interrupt (INT signal) or non-maskable interrupt (NMI signal). eee MPUZ80ASSP-62

[3] Warm-up Time for Restart (from Stop mode) Releasing the halt state by interrupt acknowledge, the MPU begins executing interrupt processing. Therefore, when restarting the clock by the NMI or INT restart signal in the Stop mode, the oscillation must be fully stabilized before supplied outside. The CGC provides, by means of the internal counter, the warm-up time enough for the clock to stabilize frequency. The warm-up ends on the rising edge of the internal counter output dividing the oscillation frequency to start clock output. The warm-up time is ; . equal to the time derived by dividing the frequency of the externally attached oscillator | by 214. relationship between the oscillation frequency and the warm-up time. In the restart by the RESET signal, no warm-up is performed for the quick operation : at power-on. Therefore, expand the width of the RESET signal adequately to provide the warm-up time. | | ccc | & | i [Je : H A \\> H > Cour ixma Alo J H 4 215 5} () Cin TXTALT CONTROL |, CLK OUT H circuit "(fo Hi CONTROL H ciRcUIT Figure 3.3.3. Block Diagram of internal Counter Table 3.3.2. Warm-up Time | os | aay te [27m | 4 ms | *fe=fxraL/2 ‘vows MPUZB80ASSP-63

3.3.3 CGC Status Transition Diagram and Basic Timing

The following describes the status transition and basic timing to be provided when the CGC operates. {1] Status Transition Diagram NO ae YES YES NO aoc ourrur . SUCcESSION <Rn moved NO OLE YES <woot STOP MODE CLOCK OUTPUT INTERNAL RAE IDLE MODE WaRANGUP CLOCK OUTPUT See Figure 3.3.4 Status Transition Diagram ee MPUZ80ASSP-64

a eesSssSSSS——S————SOT MP 78400158

14 T T2 73 T4

HALT instruction . Opecode fetch cycle —+— NOP exection —}— CLK Stopped ———> 70409 Figure 3.3.6 Basic Timing in idle and Stop Modes (2) Clock output restart from each mode The clock stopped state in the Idle or Stop mode is cleared by setting any of the following signals to “0” (for the system restart operation, see Subsection 3.3.4) : e INT (evel trigger input) e@ = NMI (edge trigger input) | © RESET (level trigger input) | (a) Clock output restart from Idle mode Figure 3.3.7 (a) shows the basic timing for the sequence of the output restart from the clock stopped state in the Idle 1 mode. In the restart in the Idle 1 mode, the clock output is restarted in a relatively short delay time because the internal oscillator operates even in the clock stopped state. CLK OUT 14 1 2 73 ‘ (Clock stopped state) MPU clock ————-“S*oppedstate) DL Racy: ——O a ne INT NMI a RESET t7o8e9 Figure 3.3.7 (a) Basic Timing for Sequence of Restart from Clock stopped State (idle 1 Mode) eee MPUZ80ASSP-66

(b) Clock output restart from Stop mode Figure 3.3.8 shows the basic timing for the sequence of the restart from the | clock stopped state in the Stop mode. When restarting by setting the INT or NMI signal to “0”, the warm-up time is automatically created by the internal counter. In the restart by the RESET signal, oscillation restarts without warm-up. CLK OUT l 4 1 72 13 yey (Clock stopped state) T~LIe-LyY1 HALT oe Mt TTT SY INT NMI RESET tosses | Figre 3.3.7 (b) Basic Timing for Sequency of Restart from | Clock stopped State (Idle 2 Mode) ) 11 2 13 CLK OUT J Fatt 2" a time i INT H i Warm-up ' time ‘ 170489 Figre 3.3.8 Basic Timing for Sequency of Restart from Clock stopped State (Stop Mode) MPUZ8OASSP-67

$$ eee IP 2BACONSB

3.3.4 Relationship with MPU

The following describes the relationship between the CGC and the MPU mainly in terms of the halt clear operation. [1] _ RESET Signal Figure 3.3.9 shows an example of the timing for the restart from the Stop mode on the TMPZ84C015A using RESET signal for both the MPU and CGC. To reset the MPU, the | RESET signal must be set to “0” for at least 3 stable clocks. When the RESET signal goes “1”, the MPU releases the halt state after a dummy cycle of 2T clock states to start executing instructions from address 0000H. To restart the clock output by the RESET signal in the Stop mode, the internal counter to determine the warm-up time does not operate. | Therefore, if the MPU does not restart correctly due to the unstable clock output immediately after the restart of the internal oscillator, or the unstability of the crystal at power-on, the RESET signal must be held at “0” for a time long enough for the MPU to be reset securely. NOP Dummy Execution from [—— execution —" cycle. *|—™ address 0000H T] 11 12) «73 «14 tT 120 «13 cux out] |, Atl ml l HALT oY vra8e9 Figure 3.3.9 Example of clock Restart Timing by RESET Signal [2] _ Releasing Halt State by Interrupt Signal The CGC restarts the clock output from the Idle or Stop mode by the input of INT or NMI signal. By this clock, the MPU starts operating. However, when the CGC restarts the clock output, the MPU is still in the halt state executing NOPs. To clear the halt state, the interrupt signal must be entered into the MPU (in the case of the INT signal) for at least one instruction. The MPU interrupt is detected on the rising edge of the last clock of each instruction (NOP for the halt state). Sse MPUZ80ASSP-68

(1) When using non-maskable interrupt (NMI) MPU’s non-maskable interrupt is edge trigger input. The MPU contains the flip-flop to detect an interrupt. The state of this internal NMI flip-flop is sampled on the rising edge of the last clock of each instruction. Therefore, when a short active low (“0”) pulse has been inserted before the interrupt detection timing, the interrupt is acknowledged. The NMI input of the TMPZ84C015A is connected to the NMI input of the MPU via the CGC, performing the same operations as above. (See Figure 3.3.11) (2) When using maskable interrupt (INT) With a maskable interrupt, the maskable interrupt enable flip-flop (IFF) must be set to “1” by program before the INT input signal is detected “0”. Even if the | CGC accepts the INT signal to restart supply of the clock, no interrupt is ) acknowledged unless the INT signal is kept inserted until one instruction (NOP) . has been executed. Figure 3.3.10 shows the timing for clearing the halt state by the interrupt signal. | ma oT 12 13 14 i 2 BM T ) CLK OUT FALT en i ut | a i MPU NMI. ee : p----- —— H it i 7 INTERRUPT SAMPLING TIMING 70609 Figure 3.3.10 Timing for Clearing Halt State by Interrupt Signal MPUZBOASSP-69

3.4 CTC Operational Description

The CTC has 4 independent channels. To these channels, addresses are allocated on | the TMPZ84C015A’s I/O map, permitting the read/write of the channels in the MPU’s 1/0 cycle. (See Figure 3.4.1) This subsection mainly describes the CTC operation to be | performed after accessed. | 3.4.1 CTC Block Diagram Figure 3.4.1 shows the block diagram of the CTC. TNTERNAL CONTROL ZEIT ot { CLK/TRGo MPU BUS | vo Zorro; LOGICAL INTERNAL BUS CHANNEL 1 ) CONTROL OPERATION CLK/TRG) | CE (A7~A2). CIRCUIT ) So (Ao) ZeT02 : CS; (Ai) CHANNEL 2 | mt TNTERNAL CLKTRG2 | TORR cout | ro ogre" e103 ) CHANNEL 3 ) CLK/TRG3 1EO tel INT 70809 Figure 3.4.1 Block Diagram of CTC

3.4.2 CTC System Configuration

The CTC system consists of the following 4 logic circuits: (1) MPU bus I/O logic circuit (2) Internal control logic circuit (3) Interrupt control logic circuit (4) Four independent counter/timer channel logic circuits [1] MPU Bus VO Logic Circuit This circuit transfers data between the MPU and the CTC. [2] _ Internal Control Logic Circuit This circuit controls the CTC operational functions such as the CTC selecting chip enable, reset, and read/write circuits. MPUZ80ASSP-71

(3) Down-counter The contents of the time-constant register are loaded into the down counter. In : the counter mode, these contents are decremented for each edge of the external ) clock; in the timer mode, they are decremented for each prescaler clock output. ) The contents of the time-constant register are loaded at initialization or when the down-counter has reached zero. ) ‘The contents of the down-counter can be read any time. Also, the system can be programmed so that an interrupt request is generated each time the down-counter has reached zero. (4) Prescaler | The prescaler, used only in the timer mode, divides the system clock by 16 or 256. The dividing number is programmed by channel control word. The output of the prescaler becomes the clock input to the down-counter.

3.4.3 CTC Basic Operations

[1] Reset The state of the CTC is unstable after it is powered on. To initialize the CTC, the low level signal needs to be applied to the RESET pin. On any channel, the channel control word and time-constant data must be written to be started before it is started in the counter or timer mode. To program the system to enable interrupts, the interrupt vector word must be written in the interrupt controller. When these data have been written in the CTC, it is ready to start. [2] Interrupt The CTC can cause an interrupt when the MPU is operating in the mode 2. The CTC interrupt can be programmed for each channel. Each time the channel’s down-counter has reached zero, the CTC outputs the interrupt request signal (INT). When the MPU accepts the CTC’s interrupt request, the CTC outputs the interrupt vector. Based on this interrupt vector, the MPU specifies the start address of the interrupt processing routine and calls it to start interrupt processing. The MPU specifies the start address of the interrupt processing routine by the interrupt vector output from the CTC, so that the user can change the vector value to call any desired address. The interrupt processing is terminated when the MPU executes an RET! instruction. The CTC has the circuit which decodes the RETI instruction. By constantly monitoring the data bus the CTC can detect the termination of the interrupt processing. MPUZ80ASSP-73

‘The order of interrupt priority with the 280 peripheral LSIs is determined by the daisy chain connection. That is, the peripheral LSIs are connected one after another and the one physically near the MPU is given a higher priority. The priority of the Z80 peripheral LSIs (CTC, PIO, and SIO) contained in the TMPZ84CO15A is determined by the contents of the interrupt priority register (#F4: bits 2 through 0). Inside the CTC, channel 0 is given the highest priority, followed by channels 1, 2 and 3 in this order. The CTC and other peripheral LSIs on the TMPZ84C015A have the signal lines IEO and IEI. Connect the IEO of a higher peripheral LSI to the IEI of a lower perpheral LSI. Connect the IEI of the highest peripheral LSI to VCC. Leave the IEO of the peripheral LSI unused. In this connection, the CTC interrupt is caused under the following conditions: ¢ When both IEI and IEO are high, no interrupt is caused. At this time, the INT signal is high. An interrupt can be requested in this state. | © — When the CTC outputs the interrupt request signal (INT), the IEO of the CTC | becomes low. When the MPU accepts the interrupt, the INT goes high again. | @ ~~ When the IEI goes low, the IEO also goes low. ¢ — While the IET is low, no interrupt can be requested. © When the IEI goes low while an interrupt is being serviced, the interrupt processing is aborted. [3] Operation Modes ‘The CTC operates in either the counter mode or the timer mode. Mode is selected by writing the channel control word. (1) Counter mode In the counter mode, the number of edge of the pulses applied to the channel’s CLK/TRG pin is counted. When pulses have been input, the contents of the down- counter are decremented synchronizing with the rising edge of the next system clock. The pulse’s rising edge or falling edge to be counted can be specified by the channel control word. When the contents of the down-counter has reached zero, the high level pulse is output from the ZC/TO pin. When the interrupt is enabled by the channel control word, the INT pin goes low and an interrupt is requested. When the contents of the down-counter has reached zero, the time constant data written in the time constant register is automatically loaded into the down-counter. To load a new time constant value into the down-counter, write the data to the time constant register, and it is loaded into the down-counter after the current count operation is terminated. eee MPUZBOASSP-74

(2) Timer mode In the timer mode, the time intervals which are integral multiples of the system clock period. A timer interval is measured according to the system clock. The | system clock is supplied to the prescaler which divides it by a factor of 16 or 256. | The output of the prescaler provides the clock to decrement the down-counter by 1. | ‘The time constant data is automatically loaded into the down-counter each time it | has reached zero as in the counter mode. When the contents of the down-counter has reached zero, the high level pulse is output from the ZC/TO pin. This pulse period is given by the following expression: te*P*TC Where, te = System clock period P = Prescaler value (16 or 256) TC = Time constant data (256 for 00H) | ‘The user can select, by means of the channel control word, to start the timer | automatically or to start the timer on the edge of the pulse at CLK/TRG pin. In case the user select the CLK/TRG pin, the user can also select the rising edge or ) falling edge of the pulse. MPUZBOASSP-75

TOSHIBA ‘TMPZ84C015B ee BACOTSB

3.4.4 CTC Status Transition Diagram and Basic Timing

[1] Transition Diagram Figure 3.4.3 shows the CTC status transition diagram. YES CHANNEL : DESIGNATION DESIGNATION | DOWNCOUNTER | AESEMET—_NO _ INTERRUPT VECTOR YS CHANNEL CONTROL WRITE OF CHANNEL| WORD | waite OF INTERRUPT ‘CONTROL WORD VECTOR WORD <ai> NO Yes TIME CONSTANT DATA DATA RECEIVE WRITE OF TIME CONSTANT INT TIMER MODE COUNTER MODE DIVIDE THE MEASUREMENT OF ‘SYSTEM CLOCK INPUT EDGE PULSE OUTPUT OF INTERNAL NUMBER TIME OF THE CLOCK DOWN COUNTER = 0? PULSE OUTPUT FROM ZCTO INTERRUPT VECTOR OUTPUT TIME CONSTANT Load i ae 70889 Figure 3.4.3 (a) CTC Transition Diagram (a) SS MPUZ80ASSP-76

[6] Return from interrupt processing Return from the interrupt processing is performed when the MPU executes the RETI instruction. This RET! instruction must be used at the end of the interrupt processing routine. When this instruction is executed by the MPU, the CTC’s IEI and IEO return to the state active before the interrupt has been serviced. The RET! instruction is a 2-byte instruction. Its code is EDH 4DH. The CTC decodes this instruction to check if there is the next interrupt request channel. In the daisy chain structure, the interrupting LSI’s IEI and IEO are held high and low | respectively at the time the instruction code EDH has been decoded. | The code following EDH is 4DH, only the peripheral LSI which has sent the last | interrupt vector (that is, the LSI whose IEI is high and IEO is low) returns from the interrupt processing. This restarts the processing of the suspended interrupt of the | peripheral LSI of the next higher priority, | 71 T2 3 14 v1 T2 3 T4 CLK IN l | > \\ rN _ Do~D7 LI 1EO oMWlq0WL’*~ Ia Figure 3.4.9 Interrupt Return Timing eee MPUZBOASSP-80

3.4.5 CTC Operational Procedure

To operate the CTC in the counter mode or the timer mode, the channel control word and time-constant data must be written in the CTC. To enable interrupts by the channel control word, the interrupt vector must be written in the CTC. [1] VO Address and Channel Control Word To write the channel control word in the CTC, the channel must be specified by the corresponding channel I/O address. Table 3.4.1 Channel I/O Addresses #10 #12 #13 170889 The channel control word to be written in the CTC consists of 8 bits. The system data bus DO through D7 correspond to bit 0 through 7 respectively. Figure 3.4.10 shows the | meaning of each bit. Table 3.4.2 shows the function of each bit. . b7 Dé DS D4 D3 D2 D1 bo Counter’ Time [swt | Sime” [Pee [ce | wom | oti | tee || 170888 Figure 3.4.10 Channel Control Word For the channel control word, D0 must always be 1. Table 3.4.2. Meanings and Function of Channel Control Words (1/3) [| ‘Meaning and function Bit7 | Disables channel interrupt Enables channel interrupt. In either (07) counter or timer mode, the interrupt is requested every time the down-counter has reached zero. When this bit is set to “1”, the interrupt vector must be written in the CTC before the down-counter starts. When the channel control word whose D7 bit is "1" is written in an already operating channel, the interrupt occurs only when the down-counter has reached zero for the first time after the writing of ‘the new channel control word. 170889 MPUZ80ASSP-81

(273) Pe | > Bit6 | Puts the channel in the timer mode. Puts | Puts the channel in the counter mode. (D6) | the system clock into the prescaler and |The down-counter is decremented for outputs the divided signal to the down- | each edge trigger applied to the CLK/TRG counter. pin. In the counter mode, the prescaler is | not used. BitS Used only in the timer mode. The|Used only in the timer mode. The {D5) | prescaler is set to divide the system clock j prescaler is set to divide the system clock by 16. by 256. Bit4 In the timer mode, the timer operation |In the timer mode, the timer operation (D4) starts on the falling edge of the trigger |starts on the rising edge of the trigger PULSE (CLK/TRG). In the counter mode, pulse (CLK/TRG). In the counter mode, the the down-counter is decremented at the |down-counter is decremented at the falling edge of the external clock pulse |rising edge of the trigger pulse (CLK (CLK/TRG) /TRG). Bit3 | Used only in the timer mode. Used only in the timer mode. The timer (03) |The timer oparation starts on the rising | operation is started at the leading edge of edge of the trigger pulse clocks after a| the external trigger pulse that inputs 2 time constant is loaded onto the down- system clocks after a time constant is counter. loaded onto the down counter. when a time lag between the system clock and trigger pulse satisfies a setup time, the prescaler starts to operate from the second leading edge of the trigger pulse. Ifa time lag between the system clock and trigger pulse dose not satisfy the setup ‘time, the prescaler starts to operate at the leading edge of the trigger pulse after 3 system clocks. If the trigger pulse is input before loading of a time constant, the operation is the same as that when Sit 3=0. Bit2 | This bit (0) indicates that there is no time | This bit (1) indicates that there is a time (D2) |constant written after channel contro! |constant written immediately after a word, However, when the channel is in | channel control word. If a time constant is ‘the reset state and this bit cannot be|written while the downcounter is changed to “0” in the channel control operating, a new time constant is set in word which is given first after the channel | the time constant register. The counting reset. To change other state without |which is in progress is carried out changing a time constant, input a|continuously when the downcounter channel control word with this bit |becomes zero, and a new time constant is changed to 0. loaded onto the downcounter. 170089 SS MPUZBOASSP-82

(3/3) Bit a Bit1 | Continues the current channel operation | Stops the down-counter operation. (D1) When this bit is set to “1, the channel operation stops but all the channel control register bits remain unchanged. When bit 2 = “1” and bit1 = “1”, the channel operation remains stopped until a new time constant is written. Channel restart is set up after the new time constant is programmed. The channel is restarted acoording to the state of bit 3 When bit 2 = “0” and bit 1 = “1", the channel operation does not start until a new channel control word is written. 770088 | [2] Time-Constant Data In either the time mode or the counter mode, the time-constant data must be loaded into the time constant register. When bit 2 (D2) of the channel control word is “1”, the | time constant is loaded into the time constant register immediately after the channel : control word is written. A time-constant value must be an integer in a range of 1 to 256. . When the 8 bits of a time constant are all “0s, such a time constant is assumed to be | 256. Figure 3.4.11 shows the bit configuration of time-constant data. [97 [56 | os | 04 | 03 | 2 | 01 | 00 | Tc? 1TC6 TCS TCA TC3 TC2 TC! TC soee9 Figure 3.4.11 Time-Constant Data [3] Interrupt Vector In interrupt in the MPU mode-2, the interrupting channel must give an interrupt vector to the MPU. An interrupt vector is written in the channel-0 interrupt vector register with bit 0 (D0) =“0”. The vector is written in the same way as the channel control word is written on channel 0. However, bit 0 (D0) of the vector should always be “0”. Bit 7 (D7) through bit 3 (D3) are user-defined values. Bit 2 (D2) and bit 1 (D1) are automatically given and contain the code of the interrupt-requesting channel having the vector bit configuration. a MPUZ80ASSP-83

Table 3.4.3. Channel Codes 0 (High) 3 (Low) 70889 (we Tse tex tx to} L Fixto “0” Channel codes interrupt vector given by user 170889 Figure 3.4.12 Interrupt Vector

3.4.6 Using CTC

{1] Counter Mode ‘The following describes how to use the CTC by referring to a program using channel 0 with interrupt disabled. (a) The counter programming procedure is shown in Figure 3.4.13 LOAD OF CHANNEL CONTROL WORD LOAD OF TIME CONSTANT = 170489 Figure 3.4.13, Counter Programming Procedure SSS MPUZ80ASSP-84

3.5 PIO Operational Description

The PIO has two independent, programmable 8-bit ports. These ports are assigned addresses on the TMPZ84C015B’s /O map and therefore can be read/written in the MPU’s I/O cycle. This subsection mainly describes the operations that take place after accessing the PIO. ) 3.5.1 PIO Block Diagram | Figure 3.5.1 shows the PIO block diagram eonTROL A —— 17 te OBPRATION Pont TSRTACONTROLURE ORCUTT LOGICAL | (PORT VO LINE) OPERATION ASE ) crcut apsnaKe ‘ARDY ) Do~Dy MPU BUS ‘CONTROL LINE . vo | OATABUS LOGICAL INTERNAL BUS OPERATION TE, Mi, TORQ 6 cIRCUIT : 10, 0/8, RB ~CONTROLLINE ——— er) PORTB o~PBy yO | DATACONTROLLINE tocicat | (PORT UO LINE) EONTROL BE CIRCUIT CONTROLLINE INT 18) —“TNTERUPT CONTROLLINE 70489 Figure 3.5.1 PIO Block Diagaram

3.5.2 PIO System Configuration

The PIO system consists of the four logic circuits: (1) MPU bus I/O logic circuit (2) Internal control logic circuit (3) Interrupt control logic circuit. (4) Port I/O logic circuit [1] MPU Bus /O Logic circuit The MPU bus I/O logic circuit transfers data between the MPU and the PIO. [2] Internal Control Logic circuit The internal control logic circuit controls the PIO operating functions like the PIO selecting chip enable and the read/write circuits. SSS MPUZBOASSP-87

[3] Interrupt Control Logic circuit The interrupt control logic circuit performs the MPU interrupt-associated processing such as determining interrupt priorities. The priorities with other LSI peripherals are determined by the physical location in daisy chain connection. [4] Port VO Logic Circuit The port I/O logic circuits are used to directly connect to peripheral devices. Each consists of the following 7 registers and 1 flip-flop. Data are written in the registers by the MPU as specified in the program. Figure 3.5.2 shows the internal configuration of ) the ports © Data output register (8 bits) © Data input register (8 bits) | © Mode control register (2 bits) ) © Interrupt vector register (8 bits) | © Interrupt control register (2 bits) © Mask control register (8 bits) © Data I/O control register (8 bits) © Handshake control logic circuit INTER ‘Mooi DATAINPUT/ ISTER ISTER (ears) (ears) Nouns iy! OUTPUT ENABLE MODE INTERNAL BUS CONTROL (8BITS) DATA CONTROL LINE INTERRUPT MASK DATA CONTRO! iT ps | meron (2BITS) (8 BITS) (8 BITS) it vawoswaK® [READY see INTERRUPT INTERRUF <— contro \\ sr CONTROL LINE 170889 Figure 3.5.2 Port Internal Configuration Se MPUZ80ASSP-88

(1) Data Output register ‘This register holds the data to be transferred from the MPU to peripheral devices. (2) Data input register This register latches the data to be transferred from peripheral devices to the MPU. ‘The input data to the MPU is read through this register (3) Mode control register ‘This register specifies the operation mode. The operation mode is set by MPU control. (4) Interrupt vector register This register holds the vector which makes up the address of the table storing the start address of the interrupt processing routine. This register is used only for interrupt processing. (5) Interrupt control register This register specifies how the I/O ports are to be monitored. This register is used only in the PIO mode 3. {6) Mask control register This register specifies which I/O port pin is to be monitored. This register is used only in the PIO mode 3. (7) Data l/O control register This register specifies whether each port pin is to be used as output or input. This register is used only in PIO mode 3. (8) Handshake control logic This circuit controls the data transfer to the peripheral devices connected to the 8-bit I/O ports.

3.5.3 PIO Basic Operations

[1] Reset The PIO provides the following two reset capabilities: (1) Power-on reset The PIO contains the circuit which automatically resets the PIO at the time of power-on. a MPUZBOASSP-89

(2) Hardware reset Making the RESET pin low for 2 system clock periods with the RD and IORQ pins being high resets the PIO on the rising edge of the RESET pin. This hardware reset inside the TMPZ84CO15B by external pin is possible because the output of the AND circuit between the RESET and MI pins is put on the MT signal of the PIO. Reset state (a) The operation mode is set to mode 1 for both ports. (b) Interrupt is disabled (c) -All the bits of the data I/O register of each port are reset. (d) All the bits of the mask control register of each port are set and masked. (e) The port I/O lines of each port are put in the high-impedance state (floating) . () The RDY pin of each port goes low. The reset state is held until the control word is written. For the function of the control word, see Subsection 3.5.5 “Operational Procedure”. [2] Interrupt : The PIO can cause an interrupt when the MPU is operating in mode 2. The interrupt | request signal (INT) from the PIO is accepted when the MPU is in the interrupt enabled state (caused after the execution of E1 instruction). Receiving the INT signal, the MPU latches the interrupt vector (8-bit data) sent from the PIO, specifies the start address of the interrupt processing routine based on the vector, and calls the routine to start the processing. Thus, since the start address of the interrupt processing routine can be specified by the interrupt vector sent from the PIO, the user can change the vector value to call any desired address. Interrupt processing is terminated when the MPU executes the RETI instruction. The PIO has the circuit to decode the RET! instruction to detect the termination of interrupt processing by constantly monitoring the data bus. The interrupt priority among the Z80 peripheral LSIs is determined by the daisy chain structure. In daisy chain, the peripheral LSIs are connected one after another as shown in Figure 3.5.3. The more a peripheral LSI is physically located near the MPU, the higher the priority of the peripheral is. Actually, the priority of the Z80 peripheral LSIs (CTC, PIO, and SIO) on the TMPZ84CO15B is specified by the contents of the interrupt priority register (# F4 bits 2 through 0). Within the PIO, port A is given higher priority than port B. SSSA MPUZ80ASSP-90

The TMPZ84C015B’s PIO and peripheral LSIs have the signal lines IEO and IEI connected to the IEO of a higher peripheral LSIs and the IEI of a lower peripheral LSI respectively. However, the IEI of the highest peripheral LSI is connected to the IEI pin and the IEO of the lowest peripheral LSI is connected to the IEO pin. In this state, the PIO interrupt follows the conditions: © When both IEI and IEO are high, no interrupt has occurred. This time, the interrupt request signal (INT) is high. In this state, the PIO can request interrupt. . @ When the PIO sends the INT signal, it sets the IEO line to the low level. When the interrupt request is accepted by the MPU, INT goes back to the low level. e When the IEI goes low, the IEO also goes low. e@ When the IEI is low, the PIO cannot request an interrupt. | © If the IEI goes low during interrupt occurrence, the interrupt processing is ) suspended. | The operations of the 4 Z80 peripheral LSIs (the states of IEI, IEO and INT signal) daisy-chained as shown in Figure 3.5.3 are as follows: (1) Before interrupt occurrence

9 Vec

———— mpu INT tel ico} LIEN tcol Let leo) ) @ (3) (4) (2) Interrupt request from LSI-2 to the MPU

9 Vee

MPU INT] tel te) 1 ze) ze) o) oO) @) @ MPUZB0ASSP-91

(3) The MPU acknowledges (enables) the interrupt. Interrupt processing for LSI-2 is performed. ¢ Vee ae ae JEL 1EO| JEL JEO} a) (2) (3) (4) (4) Interrupt request from LSI-1 to the MPU. The interrupt processing for LSI-2 is | suspended. ) 9 Vee a MPU INT] Vvece ay INT INT INT INT tel leo} IE! tco} [EL ico] te! IEO a) (2) (3) (4) (5) The MPU acknowledges (enables) the interrupt. Interrupt processing for LSI-1 is performed. a Ver? 4 INT INT INT INT lel ico} [EL igo] LIE! 10] [et EO) (1) (2) (3) (4) (6) Interrupt processing for LSI-1 terminates (upon execution of the RETI instruction). Interrupt processing for LSI-2 is restarted. g Vee ———— MPU _ INT JEL 10] tet 1EO) HEL ize) JEL 1EO} a) (2) (3) (4) eee MPUZ80ASSP-92

(7) Interrupt processing for LSI-2 terminates (upon execution of the RETI | instruction). @ Vcc oo 1EL JEO} JEL JE} JEL 1EO} @ @ @ @ Interrupt priority is given to LSI-1, LSI-2, LSI-3 and LSI-4 in this order. 170089 Figure 3.5.3 Signal States in Daisy Chain Structure | [3] Operation Modes ‘The PIO operates in one of the 4 operation modes. The mode is selected by writing the | mode control word. ) © — Mode 0 (byte output mode) © — Mode 1 (byte input mode) ) © — Mode 2 (byte 1/0 mode) © = Mode 3 (bit mode) (1) Mode 0 (byte output mode) In mode 0, the PIO sends the data received from the MPU to the external device through the port data output register. The contents of this register can be rewritten by using an output instruction. If the data on the bus change, the register contents remain unchanged until the next output instruction is executed. When the MPU executes an output instruction, the write signal is generated in the PIO in the write cycle. Using the signal, the data on the data bus can be latched in the data output register. (2) Mode 1 (byte input mode) In this mode, the PIO sends the data received from the external device to the MPU through the port data input register. The data transfer to the MPU is suspended until the MPU has read the current data. (3) Mode 2 (byte 1/0 mode) Mode 2 is a combination of mode 0 and mode 1. This mode is used only for port A. In this mode, all 4 handshake control lines are used. Port A’s handshake control lines are used for data output and the port B’s handshake control lines are used for data input. For data transfer, port A is used. Port B is set in mode 3 (bit mode) in which no handshake control line is used. MPUZBOASSP-93

ou eeeeeSSSSSSSSSSSSSSSSSSSSTP 28400158 In this mode, the interrupt timing occurs almost at the same time in mode 0 and mode 1. In an input operation, the port B’s handshake control lines are used, so that the interrupt vector written in port B is transferred. Therefore, the interrupts in input and output can be controlled by different vectors. (4) Mode 3 (bit mode) In mode 3, the 8-bit port I/O lines are controlled for each bit. Since no handshake control lines are used, ordinary read/write operations can be performed. V/O operations can be performed on the port as well. In a write operation, the data sent from the MPU to the PIO are latched in the data output register corresponding to the bit set for output in the same timing as in mode 0. An interrupt occurs in the interrupt enabled state and when the bit set for input satisfies the condition specified in the interrupt control word. However, if port A is | operating in mode 2, port B cannot cause an interrupt in the bit mode. Note that, to use the interrupt capability, the mask control register bit corresponding to the bit set for output must be set to “1” to disable its interrupt. ee MPUZBOASSP-94

3.5.4 PIO Transition and Basic Timing

[1] _ Statis Transition Figure 3.5.4 shows the pio status transition diagram. | | war <i © NO. JUDGMENT ) MODE 2 : YES NO ) WRITE TO OUTPUT WRITE TO INPUT ‘WRITE TO OUTPUT WRITE TO INPUT REGISTER REGISTER REGISTER REGISTER ara oxTe Lo COMPOSITION Kea | Yes COINCIDENCE IN ERRUPTABLE Oe NO Yes. ‘OUTPUT OF INTERRUPT VECTOR Figure 3.5.4 (a) PIO Status Transition a MPUZ80ASSP-95,

OF CONTROL INTERRUPT CONTROL INTERRUPT CHARACTER VECTOR MODE CONTROL WORD TING OF CONDITION VECTOR Yes Yes DATA RECEIVE DATA RECEIVE FROM MPU FROM MPU SETTING OF PORT SETTING OF MASK INPUT/OUTPUT 200589 Figure 3.5.4(b) PIO Status Transition eee MPUZB80ASSP-96

[2] Write Cycle The IORQ, RD, C/D (AO), B/A (Al), and CE (A7 through A2) signals generate the write signal (*WR) inside the PIO. ‘The MPU sets the PIO’s IJORQ signal to the low level at system clock T2, to start the write cycle. At this time, to indicate that this cycle is a write cycle, the PIO’s MI signal must be set to the high level. At the same time, the MPU sends signals to the PIO’s BAA (A1) and C/D (AO) to specify the port or select control signal or the data. This allows the port data output register of the PIO’s selected port to latch the data at system clock T3. TW isa wait state automatically inserted by the MPU.

11 T2 TW 13 T1

(Ao) (An) Cc Te (A2~A7) SS *WR OT NY * WR=C/D-CE-RD-IORQ 170489 Figure 3.5.5 Write Cycle Timing [3] Read Cycle The MPU sets the PIO’s, RD pin, CE signal, and JORQ pin to the low level at system clock T2 to start the read cycle. At this time, to indicate that this cycle is a read cycle, the PIO’s M1 pin must be set to the high level. The PIO outputs data in the CE, IORQ, and RD signals. TW is a wait state automatically inserted by the MPU. MPUZ80ASSP-97

$A TP28400158

1 R Tw 3 1

cD, BK (0) a), > Cc TON (Az~Ay) TORQ rr a RD a 3. ES DATA BUS Coureur) RON *RD=C/D -CE-RD-iORQ ¥70888 Figure 3.5.6 Read Cycle Timing | [4] Mode 0 (Byte Output Mode) ) The mode 0 output cycle starts when the MPU executes an output instruction. When an output instruction is executed, the write signal (*WR) is generated in the PIO in the write cycle. This signal latches the data on the data bus to the data output register of the selected port. The RDY pin goes high on the first falling edge of the system clock after the rise of the write signal (*WR). This indicates that the data in the data output register are already on the port I/O pin. The peripheral device sets the RDY pin to the low level on the first falling edge of the system clock after the rise of the STB pin to be input to the PIO to indicate that the peripheral device has received the data from the port I/O pin, waiting for the next output instruction. If, at this time, the PIO is enabled for interrupts, it sets the INT pin to the low level on the rising edge of the STB signal to output the interrupt request signal to the MPU. Figure 3.5.7 shows the timing chart of mode 0. [5] Mode 1 (Byte Input Mode) The input cycle starts when the MPU has completed the previous data read operation. The peripheral device sets the P1O’s STB pin to the lower level, putting data on the port W/O line. The RDY pin is driven low on the first falling edge of the system clock after the rise of the STB pin, disabling the peripheral device to send the next data. If at this time, the PIO is enabled for interrupts,it sets the INT pin to the low level on the rising edge of the STB pin, making an interrupt request to the MPU. When the MPU executes the input instruction in the interrupt processing routine, the read signal (*RD) is generated eee MPUZBOASSP-98

in the PIO in the read cycle. This signal puts the data in the data input register of the selected port on the data bus. The MPU receives this data. The PIO sets the RDY pin to | the high level on the first falling edge of the system clock after the rise of the read signal (*RD) to wait for the input of the next data. Figure 3.5.8 shows the mode 1 timing chart. T2 TWA 73 CLKIN || RDY sT8 WT ORT INBUT, —erOTSOATA SATA FROMTArS ) WR | *WR=C/D-CE-RD-iORQ 170489 : Figure 3.5.7 Mode 0 Timing Chart

2 Tw 3

OUTPUT LINE -==——— is *RD=C/D-CE-RD-1ORQ vv048s Figure 3.5.8 Mode 1 Timing Chart MPUZ80ASSP-99

— CSTPZBACO1SB [6] Mode 2 (Byte VO Mode) Mode 2 is a combination of mode O and mode 1. The timing for output operation is generally the same as in mode 0 except that, in mode 2, data is output only when the ASTE pin is low while, in mode 0, data is always on the port I/O line. ‘The peripheral device can receive data on the rising edge of the ASTB signal being used as the latch signal. The input timing is the same as in mode 1. The port A handshake line is used as output control and the port B handshake line is as input control. The value of the interrupt vector generated by the BSTB signal during a port A input operation is the same as the value of the interrupt vector generated when port B is used in mode 3. Hence, all port B bits are masked by setting the mask control word to disable port B for the interrupt capability. CLKIN e t ARDY AS oe ASTB -_ |] iNT — | _\\ PORT A INPUT JOUTPUT LINE Courpur_ > <_inpur_> *WR f *WR=C/D-CE-RD-iORQ 170088 Figure 3.5.9 Mode 2 Timing Chart [7] Mode 3 (Bit Mode) In this mode, no handshake line is used. Therefore, the ordinary port read/write operations can be performed, permitting access to the ports any time. The write data from the MPU is latched to the data output register corresponding to the bit set for output in the same timing as in mode 0. Except when port B is used in mode 2, the STB pin of the port operating in mode 3 is fixed to the low level. The transfer data consists of the data in the data output register and in the data input register. That is, the data of the bit set for output and the data of the bit set for input make up the transfer data. eee MPUZBOASSP-100

An interrupt occurs when the interrupt enabled state is on and the bits set for input satisfy the condition specified by the mask control word, etc. However, if port A is operating in mode 2, port B is disabled for interrupt in the bit mode. Note that, to use the interrupt capability, the bit of the mask register corresponding to the bit set for output must be set to “1” to disable it for interrupts. An interrupt request occurs when the logic condition becomes true. If the logic condition becomes true immediately before the MI pin becomes low or while MI pin is . low, an interrupt request occurs on the rising edge of the MI pin. ! i m1 T2 TW 3 1 enw LLL Lk RQ a PORT INPUT/ OUTPUT LINE — SS DATA BUS INTERRUPT CONDITION ¢ DATA 11IS PUT ON BUS IS SATISFIED 170489 Figure 3.5.10 Mode 3 Timng Chart [8] Interrupt Acknowledge Cycle Outputting the interrupt request signal (INT) , the PIO sets the IEO signal to the low Jevel, disabling the low-priority peripheral LSIs for interrupt requests. Receiving the interrupt request signal (INT) from the PIO, the MPU sets the PIO’s MI and TORQ pins to the low level to indicate that the MPU has acknowledged the interrupt request. The IORQ pin goes low 2.5 system clocks later than the MI pin. To stabilize the daisy-chained signal lines (IEI and IEO), the ports and peripheral LSIs cannot change the interrupt request. The RD pin remains high to make distinction between the instruction fetch and interrupt acknowledge cycles. While the RD pin is high, the interrupt control logic in the PIO determines the interrupt requesting port of the highest priority. When the TORQ pin goes low with the IEI pin being high, the interrupt vector is put on the data bus from the interrupt requesting port. At the same time, two system clocks are automatically inserted by the MPU as a wait state to stabilize the daisy chain structure. MPUZBOASSP-101

m |_| RD DATA BUS |EO X oo aasss_—I 70889 Figure 3.5.11. Interrupt Acknowledge Cycle Timing Charts [9] Return from interrupt Cycle Return from interrupt processing is performed when the MPU executes the RETI instruction, This RETI instruction must be used at the end of the interrupt processing ) routine. When the MPU executes this instruction, the PIO’s IEI and IEO return to the states active before interrupt processing. The RETI instruction consists of two bytes and its code are EDH and 4DH. The PIO decodes the RET! instruction to determine whether there is any interrupt requesting port. In the daisy chain structure, the IEI and IEO of the interrupting LSI remain high and low respectively at the time the instruction code EDH has been decoded. If the code following EDH is 4DH, only the peripheral LSI which has sent an interrupt vector immediately before, that is, the LSI whose IEI is high and IEO is low, returns from interrupt processing. This restarts the interrupt processing of the suspended peripheral LSI of lower interrupt priority. eS MPUZ80ASSP-102

71 T2 3 Ta 171 T2 3 T4 171

MT \\ / \\ J : | DATA BUS eee ee ee 8 (ri Ico a 70089 Figure 3.5.12. Interrupt Cycle Return Timing Chart

3.5.5 PIO Operational Procedure

To operate the PIO the control words shown below must be written in it as the initial settings. They must be written in the PIO’s ports, A and B, separately. Specify the /O address listed in Table 3.5.1 to write control words and data in the PIO. Table 3.5.1 /OAddresses Port A data #1 Port A command #1D Port B data #i1E Port 8 command #1F 170889 ) (1) Interrupt vector word [ov [os [os [04 [os [oz [or | 0 | CL Identifies the interrupt vector word. User-defined interrupt vector 70489 Using this vector and the contents of the address indicated by the MPU’s I register, the MPU generates the start address of the interrupt processing routine. © D0 through D7 are written in the interrupt vector register. © This word is not needed when the interrupt capability is not used. a MPUZ80ASSP-103

CT PZBA'CO1SB (2) Mode control word [or [os Tos TosTs Ts [117] Don't care Mode Select D7 =0,D6=0 : Moded D7=0,D6=1 : Mode1 D7=1,D6=0 : Mode2 D7=1,06=1 : Mode3 ross © This word specifies an operation mode. © — D7and D6 are written in the mode control register. (3) Datal/O control word Lo7 | 06 | os | oa [ oa | oz | 1 [ 00 | 0: output 1: input 170089 © This word is needed only in mode 3. © When mode 3 is specified by the mode control word, the data I/O control word is written after it. © — Each port is specified for output or input. © DO through D7 are written in the data /O register. eee MPUZ80ASSP-104

(4) interrupt control word | [or Tos TosTos To [Tits]: | Identifies the interrupt control word. 0 : Mask word not required. 1: Mask word requied. 0 : Active level is low. 1: Active level is high 0: Interrupt occurs when logic condition is OR. | 1: Interrupt occurs when logic contidion is AND. 0 : Interrupt disabled. : 1: Interrupt enabled voces | © This word is for interrupt control such as interrupt condition setting. | © — D4,D5, and D6 are used only in mode 3. © With D6=0, interrupt occurs when one of the bits not masked (the bit to be monitored) by the mask control word goes active. © — With D6=1, interrupt occurs when all bits not masked (the bits to be monitored) by the mask control word go active. © With D4=1, the suspended interrupts are all reset regardless of the mode. © — D5and D6 are written in the control register. (5) Mask control word [or [os | os | oa | os [oz | on | 00 | 0 : Not masked (to be monitored) 1: Masked (not to be monitored) soa © This word is needed only in mode 3. © — When D4=1 is set by the interrupt control word, the mask control word must be written after it. © — This word specifies whether to monitor the port I/O line specified for input by the data I/O control word. © — When the bit is set to 0, the corresponding input line is monitored and regarded as the input associated with interrupt occurrence. MPUZBOASSP-105

TOSHIBA ‘TMPZ84C015B ST MP 2840158 © — When the bit is set to 1, the corresponding input line is masked to provide the input not related to interrupt occurrence. © The PIO checks only the input line with the bit being 0 to see if the interrupt condition is satisfied. If the condition is satisfied, the PIO requests an interrupt. © D0 through D7 are written in the mask control register. When port A is put in mode 2, all 4 handshake lines are used, so that port B must be set in mode 3 which uses no handshake lines. At the same time, all mask control word bits must be set to 1 (masked). Note: Only interrupt enable/disable can be set by the following control word: (or [os [os Tos To Toli 7] Identifies the control word . which sets only interrupt enable/disable. Don'tcare 0: Disables interrupt. 1: Enables interrupt. 170489

3.5.6 Using PIO

The following is a programming example to operate the PIO’s port in mode 3. This program is followed by the main routine and the interrupt processing program. © — The MPU is used in the mode 2 interrupt. © The table storing the start address of the interrupt processing routine is 0802H. ¢ Interrupts occur when both PIO’s port input lines AG and AS go high. © — The I/O addresses of the PIO are the addresses listed in Table 3.5.1. AO~A7 DO~D7 MPU PIO External device Do~D 2~ PAO

7 K | Ft D2~D7 Pat

Ao : — co PA3 iL] Pad ie cal ress PAG nora? e par INT INT INT Ch 170489 Figure 3.5.13 PIO Connection SSS MPUZBOASSP-106

LD SP, 100H =» Sets the stack pointer. . iM 2 se» Sets for MPU mode 2 interrupt. : LD A, 08H «Writes data in MPU I register. lw ILA LD A, 02H ss» Writes the interrupt vector word. OUT (10H) , A LD A, OCFH ss Writes the mode control word. ouT (10H) , A LDA, 62H ++ Writes the data I/O control word, Sets PIO. OUT (10H) , A 1D A, OFTH «+ Writes interrupt control word. OUT (10H) , A | Lo A, OFH ++ Writes the mask control word. . ouT (10H) , A EL «+ Sets interrupt enable.

3.6 SIO Operational Description

‘The SIO has two independent, programmable full-duplex serial ports. These ports are assigned addresses on the TMPZ84C015B’s I/O map. This subsection mainly describes the operations that take place after accessing the SIO.

3.6.1 SIO Block Diagram

Internal Read/Write [7 } data control register Channel [_ shock i A <> circuit (Channel A) SYNC aby (— MPU control > } control ine Bus (Channel A) vo S10 control line ma} data Sh, M1, IRQ channel [S’crock » BIA, RD Internal Readrite Bee SYNC aay control register circuit (Channel 8) N External O control Control line Iel (Channel 8) Interruput control line 70809 Figure 3.6.1 SIO Block Diagram a MPUZ80ASSP-107

3.6.2 SIO System Configuration

As shown in Figure 3.6.1, the SIO consists of the MPU bus interface, the internal controller, the interrupt controller, and two independently operating full-duplex channels. Each channel has the read register, the write register, and the external controller which controls the connection with peripheral LSIs or external devices. The TMPZ84CO15B contains all the functions and pins of the 40-pin, DIP-type TMPZ84C40A (SIO/0), TMPZ84C41A (SIO/1), and TMPZ84C42A (SIO/2). However, when using the SIO of the TMPZ84CO15B, the SI0/0, SIO/1, or SIO/2 must be used alone. The pin assignments are as shown in Figure 3.6.2. saa ms bee re: ma ' wen 0 _— aa iS </S]< <[s]c|ele bv HJele jeje eae o (a) sio/o 14 | ma o> ma os maa mi ms mo rao mn WRDYA 30 so SYNCS > IS S{SIS SISISISISS & CISISICIE SESS () sion ne ene - fo mae mo a nore WaDYA 30 SYNC —> Nc S SISIS SISISISISS & SIBIeyaie spel (Q stor HAN vn Figure 3.6.2 SIO Pin Assignments eee MPUZ80ASSP-108

Table 3.6.1 shows the types and functions of the SIO registers. Each channel has 8 write registers and 3 read registers. (1) Communication data path Figure 3.6.2 shows the communication path of each channel’s transfer data.

1 Receive operation

The receiver has an 8-bit receive register and a 3-stage 8-bit buffer register in FIFO configuration. This saves time in high-speed data block transfers. The receivers also have the receive error FIFO which holds the status information such as parity and framing errors. The receive data follow different paths according to the operation mode and character length as shown in Figure 3.6.3. Table 3.6.1(a) Write Regosters Write registerO (RO) Resets CRC. Sets pointers of registers, and commands. | Write register! (WR1)_/Sets the interrupt mode. Write register2 _ (WR2) |Sets the vector to be transmitted at interrupt. Write register3 (WR3)_| Provides the parameters to control the receiver. ) Write register4 (WR4) | Provides the parameters to control the receiver and transmitter. | Write registers (WRS) [Controls the transmitter. Write register6 _(WR6) | Sets the sync character or the SDLC address field. Write register? (WR7)_| Sets the sync character or the SDLC flag 170888 Table 3.6.1 (b) Read Regosters [ome Cincom SSCS*d Read registerO (RRO) _| Indicates the receive/transmit buffer state and the pin state Read register? (RR1)__ | Indicates the error status and the end-of-frame code. Read register2 (RR2) | Indicates the interrupt vector contents. (Channel B only) 170888 MPUZ80ASSP-109

‘Omternal data bus: Receiving | { Receiving wr7 wre Transmission ~vpve==>d b==zaa---4 | synchronous || synchronous data __Data | | Error register register ro | [avo i II ie 20-bit | | Start transmission | Shiftregistaer | bit ) synchronous | Hunt eode bivsehronows) ene ancgerorons ; : spicdata inioieee Delete Receiving multiplexer | TDA RxDA | 1-bit pees bit i bide i shiftregister 2bit delay Seley IT] register (airs) ZERO INSERTION t] (bits) Asynchronous data souc.crc syncharohous cre RC Receiving delay register . ETA clock ers Bynchrenous cRe Tranmission | cq circuit at GENERATOR check [-S ‘SDLCERE checker Assemble CRC sos Figure 3.6.3. Transfer Data Path (Channel A) @ Asynchronous mode In the asynchronous mode, the receive data enters the 3-bit buffer if the character length is 7 or 8 bits or the 8-bit receive shift register if the character length is 5 or 6 bits. © Synchronous mode In the synchronous mode, the data path depends on the receive processing phase at the time. The receiver operation starts from the hunt phase. In this mode, the receiver searches the receiver data for the bit pattern which matches the specified sync character. If the SIO is set in the monosync mode, the receiver searches for SSS MPUZ80ASSP-110

TOSHIBA ‘TMPZ84C015B the bit pattern which matches the sync character set in WR7;if the SIO is set in the bisyne mode, the receiver searches for the bit pattern which matches two consecutive syne characters set in WR6 and WR7. When synchronization has been established, the subsequent data enter the 3-bit buffer by bypassing the sync register. e — SDLC mode In the SDLC mode, the syne register constantly monitors the receive data performing zero deletion as required. When the sync register detects 5 “1”s consecutively in the receive data, the following bit is deleted if it is “O”. If it is “1”, the bit that follows is checked. If it is “0”, it is assumed as a flag, if it is “1”, it is assumed an abort sequence (7 consecutive “1"s). ‘The reformatted data are put in the receive shift register via the 3-bit buffer. When synchronization has been established, the subsequent data follow the same path regardless of the character length.

2 Transmission

‘The transmitter has an 8-bit transmit data register and a 20-bit transmit shift register. The 20-bit transmit shift register holds the data from the WR6, WR7, and transmit data register. e Asynchronous mode In the asynchronous mode, the data in the 20-bit transmit shift register are | added with the start and stop bits to be sent to the transmit multiplexer. | e@ Synchronous mode | In the synchronous mode, the WR6 and WR7 hold the sync character. The ) contents of these registers are sent to the 20-bit transmit register as the syne . character at the transmission of data blocks or as the idle sync character if a transmitter underrun occurs in data block transmission. ¢ — SDLC mode In the SDLC mode, the WR holds the station address and the WR7 holds the flag. The flag (WR7) is sent to the 20-bit transmit register at the start and end of each frame. For each of the other data fields, one “0” follows five consecutive “1"s. MPUZ80ASSP-111

$$ OE (2) VO functions To transfer data from the MPU, the SIO must be set in the polling, interrupt, or block transfer mode. e Polling ‘To operate the SIO in the polling mode, all interrupts mode must be disabled. In the polling mode, the MPU reads the status bits D0 and D2 in each channel’s RRO to check for reception or transmission. e@ Interrupts There are 3 types of SIO interrupt: transmit interrupt, receive interrupt, and external/status interrupt. These interrupts can be enabled by program. The receive interrupt is further divided into the following three: © Interrupt on the first received character Interrupt on all received characters © Interrupt on special receive conditions Higher priority is given to channel A than channel B. On the same channel, higher priority is given to reception, transmission, and external/status in this order. The SIO provides the daisy-chained interrupt priority control feature and the interrupt vector generating feature. Further, it provides the “status affected vector” feature. This feature outputs 4 interrupts depending on the interrupt source. e@ Block transfer The SIO has the block transfer mode to adapt to the MPU"s block transfer and the DMA controller. For block transfer, the W/RDY line is used. For the MPU’s block transfer, this line is used as the wait line;for the DMA block transfer, it is used as the ready line. The SIO’s ready output indicates to the DMA controller that the data is ready to transfer. The SIO’s wait output indicates to the MPU that the SIO is not ready for data transfer and therefore requesting the extension of the output cycle. ee MPUZ80ASSP-112

3.6.3 SIO Basic Operations

(1) Asynchronous mode For data transfer in the asynchronous mode, the character length, clock rate, and ) interrupt mode must be set. These parameters are written in the write registers. Note | that WR4 must be set before the other registers are set. ) Data transfer does not start until the transmit enable bit is set. When the auto enable bit is set, the SIO starts transmission upon the CTS pin’s going “0”, allowing the programmer to send a message to the SIO without waiting for the CTS signal. Figure 3.6.4 shows the data format of the asynchronous mode. | rpator toe rae Marking BO O12 ag OM Marking i re | Start bit Parity bit Stop bit ) Message direction sae. 7048s Figure 3.6.4 Data Format of Asynchronous Mode . 1 Transmission Serial data are output from the TxD pin. Its transfer clock rate can be set to one of 1, 1/16, 1/32, and 1/64 times the clock rate ot be supplied to the trandmit clock input (TxC). The serial data are output on the falling edge of TxC.

2 Reception

‘The receiver operation in the asynchronous mode starts when the receive enable bit (DO of WR3) is set. When the receive data input RxD is set to “O” for the duration of at least 1/2 bit time, the SIO interprets it as the start bit, sampling the input data at the middle of the bit time. The sampling is performed on the rising edge of the RxC signal. When the receiver receives the data whose character length is not 8 bits, it converts the data into the one composed of the necessary bits, the parity bit and the unused bit set to “1”. trample: asbitcraracer [4 » [os ]|ba]oa]o2 or [oo] MPUZ80ASSP-113

When the external/status interrupt is enabled and a break state is detected in the receive data, the interrupt is generated and the break/abort status bit (D7 of RRO) is set and the SIO monitors the transmit data until the break state is cleared. The interrupt is also generated when the DCD signal is in the inactive state for more than the specified pulse width. The DCD status bit is set to “1”. : In the polling mode, the MPU must refer the receive character valid bit (DO of RRO) to read the data. This bit is automatically reset when the receive buffer is read. In the polling mode, the transmit buffer status must be checked before writing data in the transmitter to avoid overwrite. (2) Synchronous mode ‘There are 3 kinds of character synchronization : monosyne, bisync, and external sync. In each of these synchronous modes, the times 1 clock rate is used for both transmission and reception. The receive data is sampled on the rising edge of the receive clock input (RxC). The transmit data changes on the falling edge of the transmit clock input. ‘Synchronous cRC CRC | fee Monosynchronous mode Synchronous | Synchronous - RC RC character character Data field 1 2 Bisynchronous mode pave fed Message direction External synchronous mode 70889 Figure 3.6.5 Data Format of Synchronous Mode MPUZ80ASSP-114

1 Monosyne

| In this mode, synchronization is established when a match with the sync character (8 bits) set to WR7 is found, enabling data transfer. 2. Bisync In this mode, synchronization is established when a match with 2 consecutive sync characters set to WR6 and WR7 is found, enabling data transfer. In this mode as well as the monosyne mode SYNC is active during the receive clock period in which the sync character is being detected. | 3. External sync | In this mode, synchronization is performed externally. When synchronization is established, it is indicated by the SYNC pin. The SYNC input must be kept to “0” until the character synchronization is lost. Character assembly starts from the rising edge of the RxC after the falling of the SYNC. After reset, the SIO enters the hunt phase to search for the sync character. If synchronization is lost, the SIO sets the enter-hunt-phase-bit (D4 of WR3) to reenter the hunt phase. e =‘ Transmission (a) Data transfer using interrupt When the transmit interrupt is enabled, the interrupt is caused upon the transmit buffer’s being emptied. For the interrupt processing, other data are written in the transmitter. If these data are not ready for some reason, the transmit underrun condition occurs. (b) Bisync mode In the bisyne mode, if the transmitter runs out of data during transmission, supply characters are inserted. This is done in two methods. In one method, sync characters are inserted. In the other, characters generated so far are transmitted followed by sync characters. Either of these methods can be selected by the reset transmit underrun/EOM command in WRO. (c)__ End of transmission Break can be performed by setting bit D4 of WR5. When break is performed, the data in the transmit buffer and the shift register are lost. When the external/status interrupt is enabled, the SIO generates the interrupt depending on the transmitter state and outputs the vector. This mode can be used for block transfer. MPUZB80ASSP-115,

: e Transmission | (a) Data transfer using interrupt When the transmit interrupt has been set, the interrupt occurs each time the transmit buffer becomes empty. In the SDLC mode, data are sent to the SIO by this interrupt. (b) Data transfer using wait/ready ‘The wait function in the wait/ready capability is used to make the MPU extend the output cycle when the SIO’s transmit buffer is not empty. The ready function indicates to the DMA that the SIO’s transmit buffer is empty and therefore ready to receive data. If no data has been written in the transmit shift register before transmission, the SIO goes in the underrun state. This capability permits data transfer to the SIO. (Transmit underrun/EOM. The SIO automatically ends the SDLC frame if there is no data to be transmitted to the transmit data buffer. To implement this, the SIO sends a 2-byte CRC when there is no data to send, then the SIO transmits one or more flags. After reset, the transmit underrun/EOM status bit is set to prevent the CRC character from being inserted when there is no data to be sent. Using this function, the SIO starts frame transmission. Here, the transmit underrun/EOM reset command must be set in advance between the transmission of the first data and the data end. Thus, the SIO goes in the reset state at the end of each message with the CRC character being sent automatically. (d) CRC generation For CRC calculation, the CRC generator must be reset before transmission (bits D6 and D7 of WRO). CRC calculation starts when the address field is written in the SIO (WR6). The transmit CRC enable bit (DO of WR5) must be set before the address field is written. (e) End of transmission When the transmitter is disabled during transmission, the data currently transmitted is all transmitted to its end. The subsequent data is put in the marking state. When the transmitter is disabled, characters remain in the buffer. However, the abort sequence is made active when the abort command is written in the command register, deleting all data. MPUZBOASSP-117

2880'S e Reception As in the transmit mode, several parameters must be preset in the receive mode. The address field is written in WR7 and the flag character in WRT. Receiving the open flag, the receiver compares the contents of the following address field with the address set in WR6 or the global address (“1111 1111”). If the contents of the address field in frame matches either of these address, the SIO starts reception. (a) Interrupt on the first received character This mode is generally used for the block transfer using the wait/ready capability. In this mode, the SIO generates the interrupt only on the first character. The status flag of this interrupt is latched, so that command 4 (to be enabled by the next received character) of WRO must be preset for re-initialization. When the external/status interrupt is set, an interrupt occurs every time the DCD changes. This interrupt also occurs when the special receive condition is satisfied. (b) Interrupt on all received characters In this mode, the SIO generates an interrupt on all received characters. When the status affect vector has been set, the SIO generates a special vector on the special receive condition interrupt. (©) Special receive condition interrupt Using the special receive condition, the interrupt on the first received character or the interrupt on all received characters must be selected in advance. The receive overrun status of the special receive condition interrupt is latched. The status bit can be reset by the error reset command (WRO command). (d) CRC check The receive CRC check is reset when the open flag at the head of a frame is received. CRC calculation is performed on the subsequent characters up to the close flag. In the SDLC mode, the transmit CRC is inverted, so that a special check sequence is used. The check must end with “0001 1101 0000 1111.” Since SIO handles the CRC character as a data, the MPU must discard it after reading it. (e) End of transmission When the SIO receives the close flag, the end-of-frame-bit is set to indicate that the close flag has been received. When the status affect vector has been set, the special receive condition interrupt occurs and the interrupt vector is output. Any frame can be aborted by abort transmission. When the external/status interrupt has been set, the interrupt occurs and the break/abort bit in RRO is set. eee MPUZ80ASSP-118

3.6.4 SIO Status Transition Diagram and Basic Timing

| [1] Status Transition Diagram Figure 3.6.7 shows the SIO status transition diagram. (C Poweron _) ‘ASynchronous mode transmission c/b=1 NO. TE,iORG=0 Status read RRO RD=0 ciB=0 ~ GTORQ=0 | gata character Setcommand interrupt write mode ‘Transmission (WRO-WR7) (TxD) oi ) NO start bi | ves /—— | YES external /Statusinterrupt NO. Lu YES transmission ‘transmission a70009 No Figure 3.6.7 (b) State Transition Diagram mode YES Mono oF Ne transmission transmission. transmission. transmission Figure 3.6.7 (a) SIO Status Transition Diagram a MPUZ80ASSP-119

‘tanamission TxD telminals Wempur [meee | SYNCH (00D feed (10) SYNCH2 (00~D7) cost RD=0 cid=0 - =o Write transmission | mages = Transmission interrupt : (Txd) End of No | ranamission? ves React Yes ves re fe character feed SYNCH2 (DO~D7) Eadot Frame transmission 188 Figure 3.6.7 (c) State Transition Diagram eee MPUZ80ASSP-120

| TxD terminal TxC INPUT ‘Open flag Open flag inte’ oo character (7EH) ciD=1 ‘TE, FORQ=0 ‘Status read RRO RD=0 <Eie ene YES ) Sato Transmission interrupt {00-D7) =< faon> YES (7EH) Figure 3.6.7 (d) SIO Status Transition Diagram oo MPUZ80ASSP-121

<em> vo <Ken> no eS Crom") < Synchronous «|e sic sg SS <> No Kee a | Ss es a vs <> <> 1 imsereep yes Koen > 10 Side) a Figure 3.6.7 (e) State Transition Diagram eee MPUZ80ASSP-122

m7 —\\ S/S Vw Sf— a eed 170489 Figure 3.6.11. Return Timing from Interrupt oo MPUZ80ASSP-125

SSS’

1 The SIO has made an interrupt request

ayn “ye “ye oy [INT “o" IL 1EO El 1EO IEl 1EO IEl 1EO El 1EO 2 The SIO is servicing the interrupt. 3. The PIO has made an interrupt request immediately before "EDH” is decoded by the SIO. By the PIO’s interrupt request, PIO’s IEO is set to “0”. aye ow lint on «gr “gr 4 Because “EDH" has been decoded, the PIO’s interrupt request is not acknowledged. Therefore, PIO's IEO returns to “1” | “4 oy INT a “ye “gr . 5 Because “4DH" has been decoded, the SIO’sIEO is set to “1” “ye ew Wow “yn “ye 6 The PIO's interrupt request is acknowledged and the PIO’s IEO is setto “0”. a ee i 170089 Figure 3.6.12 Daisy Chain at Execution of RETI Instruction SSS MPUZBOASSP-126

3.6.5 SIO Operational Procedure

The following mainly describes the meaning of each bit of the write and read : registers. Special attention should be directed to the fact that the parameters of the write register (WR4) should be set before the others. Some registers can use only a signal channel. The I/O addresses listed in Table 3.6.2 must be specified to write the control word and read/write data on the SIO. Table 3.6.2. 1/0 Addresses || Channel A data #18 Channel A command #19 Channel B data #1A : Channel B command #18 | Toes | (l] Write Registers | 1 [WR 0; Write register 0 : Table 3.6.3 Configuration of Write Register 0 D7 D6 DS D4 D3 D2 Oo DO | vrose9 Bits DO through D2: Register pointer bits ‘These bits specify the register on which read/write is performed by the next byte. When read/write is completed, the register pointer points to WRO. Bits D3 through D5: Basic command bits © Command 0 (=000): No operation ‘This command only sets the register pointer without making the SIO operate. It is used to invalidate the command in the command chain for the SIO or hold the location at which a command is inserted in the command chain if required. © Command 1(=001): Abort sequence generation This command is used to generate the abort sequence (7 or more consecutive “1”s). Note that command 1 is used only in the SDLC. a MPUZ80ASSP-127

© Command 2(=010): External/status interrupt reset Once an external interrupt or a status interrupt has occurred, the status bit of RRO is latched. This command is issued to enable the RRO’s status bit in order to enable the interrupt again. © Command 3 (=011): Channel reset This command performs generally the same operation as when the RESET pin is set. The difference is that reset is performed only on a single channel. The command for channel A resets the interrupt priority circuit as well. © Command 4(=100): Enable the interrupt at the next character reception. This command is used to enable an interrupt when the end of block a data block has been detected followed by the reception of the next block. © Command 5(=101): Reset transmit interrupt pending If the transmit buffer becomes empty in the transmit interrupt enable mode, an interrupt occurs. This command is used to disable the transmit interrupt when there is no data in the transmit buffer. @ ~~ Command 6 (=110): Error reset The error (parity or overrun error) caused in block transfer is latched in bits D4 and D5 of RR1. This commands is used to clear these bits. © Command 7 (=111): Return from interrupt This command performs the same operation as the operation required to execute the RETI instruction on the SIO’s data bus. Therefore, non-Z80 MPUs (that is, systems using no RETI instruction) can use the daisy chain in the SIO. This command is available only on channel A. Bits D6 and D7: CRC reset code ‘These 2 bits allow the programmer to select between the receive CRC checker reset, the transmit CRC generator reset, and the transmit underrun/EOM reset. Table 3.6.4 List of Reset Command Codes [—teseconnena | o? | oe] [ieopeaion dt [reseinercenecnceheder | 0 | 1 [Reet te vanmtcncoeewior [1 | 9 | [eset vosmitunderonreom |r| 1] 170889 SSS MPUZ80ASSP-128

| 2 [WR1; Write register 1 Table 3.6.5 Configuration of Write Register 1 D7 D6 Ds D4 D3 D2 DI DO eceivin seen WESRERG MIE] MCS) RB oe Enable function ) 70089 Bit D0: External/status interrupt enable | When this bit is set, an interrupt is generated at the start of sync character transmission even if the execution is terminated upon detection of break/abort, the DCD, CTS or SYNC signal has changed, or the transmit underrun/EOM latch is set. Bit D1: Transmit interrupt enable When this bit is set, a transmit interrupt is generated upon the transmit buffer | becoming empty. Bit D2: Status affect vector When this bit is set, bits D1 through D3 (V1 through V3) of WR2 is changed. When this bit is not set, the same interrupt vector as the contents of WR2 issued. Note that this bit is available only on channel B. Bits D3 and D4: Receive interrupt mode ‘These bits are used to select a receive interrupt mode. Bits D5 through D7: Selection wait/ready functions These 3 bits are used to select a W/RDY pin function. The wait or the ready function is selected by program and they are not used simultaneously. The meaning of these bits are: ®@ When D5 is set to “1” , it indicates that the W/RDY pin responds to the receive buffer; when D5 is reset to “0”, it indicates that the pin responds to the transmit buffer. © When D6 is set to “1”, the W/RDY pin functions as the READY pin; when D6 is reset to “0”, the pin functions as the WAIT pin. MPUZBOASSP-129

© — When D7 is set to “1”, the wait/ready function is enabled;when D7 is reset to “oO”, the function is disabled. For example, when D7, D6, and D5 are “1”, “1”, and “0” respectively, and the transmit buffer is full, the READY pin goes “1”, when the transmit buffer is empty, the pin goes “oO”. Table 3.6.6 shows the summary of the above description of bits D3 and D4 and D5 through D7. Table 3.6.6 List of Receive Interrupt Mode Codes [recrveinerontmede sd] [Recveierptdiabe SS SSSSCSCS~sd Interrupt on first received character or special receive condition® foo | a | ) Interrupt on received character or special receive condition ) * (except for parity error) 170089 *Special receive conditions: @ — End of frame (in SDLC mode only) | © — Receive overrun error © = Parity error e@ = Framing error Table 3.6.7 Wait / Ready Select Function (D5 through D7) Freie ovtenee [or] [war [ewe Te pisaBLe a Low __ | The transmit buffer is full and WAIT the SIO data port is selected. | Floating |The transmit buffer is empty. READY [High |The transmit buffers full. 1 The transmit buffer is empty. | Floating |The receive buffer is full. Wait The receive buffer is empty low | and the SiO data port is. selected, READY The receive buffer is full. Le 170089 eee MPUZ80ASSP-130

3 [WR2; Write register 2 Table 3.6.8 Configuration of Write Register 2 D7 D6 Ds D4 D3 D2 D1 bo || Subject to change under different interrupt conditions if the status- affect vector bit is set. 170089 This write register is the interrupt vector register. When bit D2 of WRI (B channel) is not set, the interrupt vector is issued. When bit D2 of WR1 (B channel) is set, bits D1 through D3 (V1 through V3) are changed depending on the interrupt generation condition. This time, the contents of WR2 remain unchanged. Because WR2 is available only on channel B, WR2 must be programmed even if only channel A of the SIO is used. Table 3.6.9 shows the WR2 bit states in the interrupt condition with the status affect vector being set. Table 3.6.9 Channel interrupt Condition Codes a [change ofexternal/stauws [of [| Received character condition available Def |] [Special receive condition [| | Transmit butterempty Tt To fo [change ofexternal/staus———SCi| CSF (| [Received characteravaiable ——+| + | + | © | [Speciatreceivecondition® [1 | 111 170089 *Special receive conditions: e. End of frame (in SDLC mode only) . Receive overrun error © Parity error © = Framing error MPUZBOASSP-131

$$ eS 28400158 4 [WR 3; Write register 3 Table 3.6.10 Configuration of Write Register 3 D7 D6 0s D4 D3 D2 01 bo Prohibit ‘ving bi Enter | Enable | Address Receiving bit Auto abl synchro- | Enable Tcharaceer enable pent recere 9 search ches, | receiving load 170889 Bit DO: Receive enable When this bit is set, the receive operation starts. Because this bit is used to start the receive operation, it must be set after the receive-associated programming has been all completed. Bit D1: Sync character load inhibit When this bit is set in the sync mode, the sync character is not loaded into the receive buffer. This bit is used to remove the sync character and idle syne from the received characters. Bit D2: Address search mode When this bit is set in the SDLC mode, any message having a programmed address or an address other than the global address (FFH) is not received by WR6. Therefore, the receive interrupt does not occur unless an address match occurs. Bit D3: Receive CRC enable When this bit is set, CRC calculation starts at the start of the last data transfer from the receive shift register to the receiver buffer. Bit D4: Enter hunt Phase When the establishment of synchronization is required, set this bit to enter the SIO into the hunt phase. The hunt phase is automatically cleared upon establishment of synchronization. Bit D5: Auto enable When this bit is set, the transmitter is enabled at the time the CTS pin is “0”. When the DCD pin is “0”, the receiver is enabled. SSeS MPUZBOASSP-132

Bits D6 and D7: Receive character length These bits are used to specify the number of receive bits which make up one character (character length). Table 3.6.11 shows the number of bits per character. Table 3.6.11 Receive Character Length Codes [twine [oF [os] a a | a | or) | ——— | 5 Table 3.6.12 Configuration of Write Register 4 D7 D6 DS D4 D3 b2 DI DO Clock mode Synchronous mode Stop bit Parity Even /Odd ) Enable 70089 Bit D0: Parity enable When this bit is set, 1-bit transmit data is added to the number of bits specified by D6 and D7 of WR3 and the data is received in the resulting number of bits. If a character length other than 8 bits is selected, the added parity bit is set to the MSB side to be transferred to the receive data FIFO. When the 8-bit character length is selected, the parity bit is not transferred to the receive data FIFO. Bit D1: Parity even/odd This bit is used to determine whether to perform transfer and check in even or odd parity. (Even parity =“1”, odd parity =“0") Bit D2 and D3: Stop bit length These bits are used to select the stop bit length in the asynchronous mode. In the synchronous mode, both D2 and D3 must be set to “0”. MPUZBOASSP-133

Table 3.6.13 Stop Bit Length Codes [sero [sremode Te | [isopsivcwaer fe] +] [rssenbisrawecer fs | 0 | [2soptisicseaer | + J 1 170889 ) Bits D4 and D5: Sync mode | These bits are used to select the sync mode. | Table 3.6.14 Sync Mode Codes | [synod Tos | [setmnemoae id [resisncnedetamenadey fe | 1 | Fsoicnede tag ebaawri7e | 1 | 9 | [eeratsnemese | 170889 Bits D6 and D7: Clock mode These bits are used to select the factor between the transmit/receive clock and the data transfer rate. In the synchronous mode, the X1 clock mode must be set. In the asynchronous mode, the transmit side and the receive side must have the same factor. Table 3.6.15 Clock Mode Codes [|__wetinafiny TT] [aiamovenieroe | 8 po [xiedsovensrrte ——fe | ] [xszdaauenteroe fs | [xsdna vanterae | 3 170889 MPUZ80ASSP-134

| 6 |WRS; Write register 5 Table 3.6.16 Configuration of Write Register 5 D7 D6 DS D4 D3 D2 DI DO TT i Break Enable CRC-16 Enable mission mission mission 770888 Bit DO: Transmit CRC enable When this bit is set at the time the transmit data is loaded from the transmit data buffer into the transmit shift register, the CRC calculation is performed on that data. If this bit is not set, the CRC calculation and transmission are not performed in the transmit underrun state in the synchronous or SDLC mode. Bit D1: Request to send When this bit is set, the RTS pin goes “0”. When this bit is not set, the RTS pin goes | “1”, In the asynchronous mode, the RTS pin goes “1” when the transmit buffer becomes | empty. In the synchronous or SDLC mode, this bit state is followed by the RTS pin state. | Bit D2: CRC-16/SDLC | When this bit is set, the CRC-16 polynomial (X!6+xX15+X?+1) is selected. When | this bit is reset to “0”, the CRC-CCITT polynomial (X16+X!2+X®5+ 1) is selected. | Bit D3: Transmit enable When this bit is set, the transmitter is enabled. Even if this bit is reset to “O” after the start of transmission, the sync character and the data being transmitted are transmitted to the last. Bit D4: Transmit break When this bit is set, transmitting any data forcibly puts the transmit data line (TxD pin) in the space state. When this bit is reset to “0”, the TxD pin is put in the marking state. Bits D5 and D6: Transmit character length These bits indicate the character length of transmit data. MPUZBOASSP-135

Table 3.6.17 Transmit Character Length Codes [—sisrowaaer es | [estan eo] a es ec As shown in Table 3.6.17, for the transmission of less than 5 bits (4 bits or 3 bits) per character, D6 and D5 are “0” and “0”, which do not indicate how many bits the transmit data consists of. To solve this problem, the data characters must be processed by the format shown in Table 3.6.18. Note that D indicates data. Table 3.6.18 Data Transfer Format with Transmit Data Consisting of Less than 5 bits [rensmibisroncer [OF [oe | Os] oe] oe | a | or | oe Pp ee Bit D7: Data terminal ready This bit indicates the DTR pin state. When this bit is set, the DTR pin goes “0”, when itis reset, the DTR pin goes “1”. 7 [WR6; Write register 6 Table 3.6.19 Configuration of Write Register 6 D7 Dé DS D4 D3 D2 DI DO SYNC 7 6 5 4 3 2 1 oO a MPUZ80ASSP-136.

‘This register is programmed as follows: | @ = Intheexternal syne mode : Transmit sync character | © Inthemonosynemode —: ‘Transmit sync character | e = Inthe bisync mode : First syne character e Inthe SDLC mode : Slave station address a 8 [wnr7; Write register 7 Table 3.6.20 Configuration of Write Register 7

07 D6 Ds D4 D3 2 D1 Do

15 14 13 12 " 10 9 8 70809 This register is programmed as follows: @ Inthe monosynemode : Receive sync character e@ Inthe bisync mode : Second sync character e Inthe SDLC mode : Flag character (7EH) This register is not used in the external sync mode. [2] Read Registers 1 |RRO; READ REGISTER O Table 3.6.21 Configuration of Read Register 0

07 D6 DS D4 03 D2 01 0

synchro- rasmission Receiving Break | underrun Interrupt cTs nize DcD buffer in character se PR) [oar] fs Used with the external /status interrupt 0889 MPUZ80ASSP-137

TT ——— CMP 200158 Bit DO: Receive character available This bit is set when the receive buffer holds characters of 1 byte or more. This bit is reset when the buffer becomes empty. | Bit D1: Interrupt pending This bit is set when an interrupt occurs in the SIO regardless of the interrupt condition type. This bit is available only on channel A. Bit D2: Transmit buffer empty This bit is set when the transmit data buffer becomes empty or the SIO is reset. However, in the syne and SDLC modes where the CRC character is being transmitted, bit D2 is reset. Bit D3: Data carrier detect This bit indicates the DCD pin input state. This bit is latched when the external/status interrupt occurs. Bit D4: Sync/hunt The meaning of this bit depends on the operation mode: | (i), Asynchronous mode Bit D4 indicates the SIO's SYNC pin state. When the SYNC pin state changes, the external/status interrupt occurs. (ii) External sync mode When synchronization has been established by the detection of external synchronization, the last bit of the sync character must be set to “0” at the second R&C falling edge from the rising edge of the received RxC. That is, to set the SYNC input to “O” by the external circuit after the detection of synchronization, full 2 receive cycle clocks must be awaited. When the SYNC input goes “0”, the sync hunt bit is set. When synchronization is lost or the end of message is detected, the enter hunt phase bit is set. (iii) Internal sync mode In the monosyne and bisync modes, bit D4 is initialized to “1” by the enter hunt phase command (D4 of WR3). This bit is reset when the SIO detects the syne character. (iv) SDLC mode Bit D4 is set when the receiver is disabled or the enter hunt phase command is issued. Then, when the frame open flag is detected, this bit is reset. eee MPUZBOASSP-138

Bit D5: Clearto send This bit indicates the opposite of the CTS pin input state. Bit D6: Transmit underrun/EOM OO ‘This bit is set when the SIO is reset (including channel reset). Only the reset transmitter underrun/EOM latch command (WRO bits D7, Dé=“1”, “1”) can reset this bit. When the transmit underrun state occurs, the external/status interrupt is generated. Bit D5 is also used to control transmission in the sync or SDLC mode. Bit D7: Break/abort In the asynchronous mode in reception, this bit indicates the break state detection. When the break state is detected, this bit is set, generating the external/status interrupt. This bit is reset by the external/status interrupt reset command. After break, the external/status interrupt is generated again. In the SDLC mode, bit D7 is set when the abort sequence is detected, generating the external/status interrupt. 2 [RR 1; READ REGISTER 1 Table 3.6.22 Configuration of Read Register 1

07 D6 D5 D4 D3 02 D1 00

Endof | framing | Receiving , Feed frame error | overrun | Parity Fraction all error characters 170889 | Bit DO: All sent In the asynchronous mode, this bit is set when all characters are sent from the transmitter or there is no transmit data in the SIO. In the synchronous mode, this bit is always set. Bits D1 through D3: Fraction codes Normally, I field is an integral multiple of character length. If it is not, these bits show the number of fraction bits. These codes are effective only for the transmission for which the end of frame bit is set in the SDLC mode. Example: Figure 3.6.13 shows examples of fractions in which the number of bits/character at the end of I field is 8 bits (1) and 4 bits (2). MPUZ80ASSP-139

tla % | I field | 170089 Figure 3.6.13 Examples of Fraction Bits Field Table 3.6.23 (a) shows the fraction codes for the receive character whose character length is 8 bits. Table 3.6.23 (a) Bit Patterns by Fraction Bits at End of | Field Number of fraction bits at end of | field a a a Lo 8 a 770088 The same table can also be provided for each character length when the receive character length of I field is other than 8 bits. Table 3.6.23 (b) Bit Patterns by Number of Bit / Character (No Fractions) a 5 bits / Character 0 0 6 bits/ Character 0 1 7 bits / Character 0 0 8 bits / Character 0 1 170889 SSS MPUZBOASSP-140

Bit D4: Parity error This bit is latched when the parity select bit (DO of WR4) is set and a parity error is | detected in the receive data. Latch can be cleared by the error reset command (WRO bits Bit D5: Receive overrun error The receive data FIFO holds up to 3 characters. When more characters are received without read out by the MPU, the excess character is set to the receive FIFO. When this character is read by the MPU, this receive overrun error is set. Once set, bit D5 latches that state. When the error reset command (command 6 of WRO bits D3 through D5) is written, this bit is also reset. | Bit D6: CRC/framing error | In the asynchronous mode, this bit is set when a framing error is detected in the | received character. Because this bit is not latched, it is always updated. In the synchronous and SDLC modes, this bit indicates the transmitted CRC check result. This bit is reset when the error reset command (command 6 of WRO0 bits D3 through D5) is written. | Bit D7: End of frame ) This bit is set when the end flag is detected in the receive data and the CRC check and the fraction code are found normal. This bit is reset when the error reset command (command 6 of WRO bits D3 through D5) is written. This bit is used only in the SDLC mode and is updated when the first character of the next frame is received. . 3 |RR2; Read register 2 Table 3.6.24 Configuration of Read Register 2

07 D6 Ds ba D3 D2 D1 Do

” “ “ “ ° ne et Subject to change under different interrupt conditions if the status-affect bit is set vroae9 MPUZ80ASSP-141

TOSHIBA ‘TMPZ84C015B TP 2840158 When the status affect vector bit (D2 of WRI (Channel B) ) is set, bits V3 through V1 are changed depending on the interrupt condition at the time. The vector to be read is determined by the interrupt condition having the highest priority at the time of read. When the status affect vector bit is reset, the contents of this register are the same as those of WR2.

3.6.6 Using SIO

The following describes some system examples using the SIO. Figure 3.6.14 shows an inter-processor communication system. In this example, the MPU on the left side | controls the data transfer with the modules on the right side. Both diagrams shown in | Figure 3.6.14 (a) and (b) are communication systems. As shown, the SIO is used to | interface with external devices in data communication. The greatest advantage of the | SIO is the smaller number of data lines than parallel communication. RSXYZ z80 : 280 | dri coal ele 780 780 RSXYZ rN ry driver fy MPU S10 KON ireceiver SF] In a 780 7280 river ‘tecewer KTV) sto. Ko) pu 0489 Figure,3.6.14 (a) Example of Data Communication Between Processors ‘hannel No.1, CHa Modem 780 780 Kp 852326 (=) Synchro: | ata linking —N ‘rl drivers ) none for remote MPU SIO receiver K—— synchro- processor CHB \\7——V) nous) Ichnnel No.2! 170489 Figure 3.6.14 (b) Example of Data Communication Between Processors eee MPUZBOASSP-142

3.7 Standby Capability

When a HALT instruction is executed, the TMPZ84C015B is put in one of the Run, Idle-1, Idle-2, or Stop mode depending on the contents of the halt mode setting register (#FOQ:bit 4, bit 3:HALTMR). (However, the TMPZ84C015B is put in the Run mode immediately after the reset operation by the RESET pin.) The halt mode setting register is set as follows. For the description and timing of each mode, see Subsection 3.3 “CGC ) Operations. ” || ) ‘The halt mode setting register is assigned to bits 4 and 3 of address F0 in the /O address area. The halt mode is releasad by the interrupt (the nonmaskable interrupt by the NMI pin or the maskable interrupt by the INT pin) or by the reset through the RESET pin. A maskable interrupt is accepted when the MPU is in the EI state (in the state after the execution of EI instruction). A nonmaskable interrupt is accepted unconditionally. When an interrupt is accepted, the interrupt processing starts. When the MPU is in the DI state (after the reset operation and the execution of DI instruction) with maskable interrupt, the TMPZ84C015B returns to the halt mode after executing a HALT instruction (actually a NOP instruction).

3.7.1 Setting Halt Mode

| Duplicate control is provided to prevent the stop of the watchdog timer operation which may be caused by the halt mode setting error due to program runaway. The halt mode is set by the halt mode setting register (HALTMR) and the halt mode . control register (#FL:bits 7 through 0: HALTMCR). Figure 3.7.1 shows the contents of the halt mode control register (HALTMCR). Figure 3.7.2 shows the contents of the halt mode setting register (HALTMR). MPUZBOASSP-143

| [wove [ coc [ wru [cre | ro | so | net hiBth IDLE1 x x IDLE2 x x sToP x x RUN fe) [e) ) O + Operating vos || | x “Stop | Note : CLKOUT and CLKIN must be connected. Figure 3.7.3 Device States in Halt State For the halt mode in which the clock is supplied from the CLKIN pin (with the CGC ! oscillator unused), the Run mode must be used.

3.7.2 Halt Mode Setting procedure

After reset, the halt mode is changed to the Run mode. Figure 3.7.4 shows the procedure to set a new mode. Write Data “DB” into F1 address {HALTMCR) . Write new mode into address FO. 170889 Figure 3.7.4 Setting Halt Mode MPUZB0ASSP-145

3.8 Watchdog Timer

The watchdog timer (WDT) detects an operation error caused by the program runaway to return to the normal operation.

3.8.1 Block Diagram of Watchdog Timer

Figure 3.8.1 shows the block diagram of the watchdog timer. WOTOUT #F0 woTPR—>| enable (Bits 6 and 5) —>| “er ® 22-step binary counter Q (WOTCLK}—>! for watchdog timer rs reset y reset Bin Wore | PLM 4EH write write ) Watchdog timer contro! Watchdog timer i enable ister register #F1 (WDTCR) “#0 (WDTER) Internal data bus 170889 Figure 3.8.1 Block Diagram of Watchdog Timer See MPUZBOASSP-146

3.8.2 Setting Watchdog Timer

(1) Enabling the watchdog timer The watchdog timer can be set by the watchdog timer enable register (#FO:bit : 7:WDTER) and the watchdog timer periodic register (#F O:bit 6, bit 5: WDTPR). 7 6 5 4 3 2:1 ~«0 Address FO | Winter] waiee [wafer [0 [71 [7 | | oo See 3.7 Always write “011” Standby functivon

0 O = TeCe216

O 1 = TeCe218 1 0 = TeCe220 TT T6622 rec imaster clock) 4 : rable (Note) * : State after reset | 170889 | Figure 3.8.2 Enabling Watching Timer ) (2) Disabling the watchdog timer The watchdog timer can be disabled by disabling the watchdog timer enable register (WDTER) then writing data “B1” in the watchdog timer control register (#F1:bit 7 through bit 0:;WDTCR). This function has a duplicate structure to prevent the watchdog timer setting error, which may lead to the watchdog timer operation stop, caused by program runaway. 7 6 5 4 3 2 1 ~«0 Address FO Wie oral_wahoe Loaton [oT] a 0 =Disable see3.7 Always write "011". Standby junction Address F1 Write only 704s Figure 3.8.3. Disabling Watchdog Timer MPUZ80ASSP-147

(3) Clearing the watchdog timer The watchdog timer can be cleared by writing data “4E” in the watchdog timer control register (WDTCR). Address F1 7 6 5 4 3 2 u ° cal Write only be 70889 Figure 3.8.4 Clearing Watchdog Timer Address FO 7 6 5 4 3 2 1 0 (ead) fra] wojon [oat TOT a [7 | a see 3.7 Read out writen data“011" Standby function ) O = TeC+216 0 1 = TeCe218

1 O = TeC+220

1 1 = TeC+222 0=Disable 1=Enable 170889 Figure 3.8.5 Reading Watchdog Timer Setting Register

3.8.3 Watchdog Timer Output

When the enabled watchdog timer is used, the “0” level signal is output to the WDTOUT pin after the duration of time specified in the watchdog timer periodic register (WDTPR). The output pulse width is one of the following two types depending on the WDTOUT pin connection: (1) The WDTOUT connected to the RESET pin:The “0” level pulse of 5TcC (System clock) is output. (2) The WDTOUT connected to a pin other than RESET pin :The “0” level pulse is kept output until the watchdog timer is cleared by software or reset by the RESET pin. eee MPUZ80ASSP-148

3.9 Interrupt Priority

The programmable interrupt priority register (#F4:bits 2 through 0:INTPR) is . provided to determine the interrupt priority for the CTC, SIO, and PIO in the | TMPZ84CO15B. | 3.9.1 Setting Interrupt Priority | Figure 3.9.1 shows the register to determine the daisy chain interrupt priority for the | CTC, SIO, and PIO. Address Fa ? 6 5 4 3 2 1 ° (INTPR) Write only Priority order High————Low * CTC- SIO - PIO = CY) 0 oO SIO - CTC- PIO = Qo 0 1 CTC- PIO- SiO = oO 1 0 PIO - SIO - CTC = oO 1 1 PIO - CTC- SIO = 1 0 oO SIO - PIO- CTC = 1 0 1 (Note) + State after reset 170489 Figure 3.9.1 Interrupt priority Register (INTPR) Example: When “101” is written in address F4 (INTPR), the daisy chain interrupt priority is given as shown in Figure 3.9.2. ( --{_]ito [| ll SIO 10 Il CTC EO 70009 Figure 3.9.2. Daisy Chain Interrupt Priority MPUZBOASSP-149

1. ELECTRICAL CHARACTERISTICS 4.1. Maximum Ratings [see [eee] \\Vec Supply Voltage with respect to Vss [#0 [rower isipston (OMmVERSON:TAzTO | 20m | Soldering Temperature (Soldering Time 10 sec) . 020790

4.2 DC Electrical Characteristics

10MHz VERSION : TOPR=—-—40°C to +70°C, VCC=5V+10%, VSS=0V (12) Clock input Low Voltage we (CLKIN) v Clock input High Voltage _ VIHC (CLKIND VEC - 0.6 vec+03 | v Input Low Voltage Input High Voltage vIK (except XTAL1. RESET) 22 vec v Input Low Voltage VILR RESET) v Input High Voltage . VIHR (RESED) vec -0.6 vec v ‘Output Low Voltage . voLc (euKouT) 1OL=2.0mA v Output High Voltage __ _ vOHC ev eiKoUn IOH = -2.0mA vec -0.6 v Output Low Voltage _ vou (except CLKOUT) 1ok=2.0mA v Output High Voltage 1 _- VOH1 (except €LKOUT) JOH = -1.6ma 24 v Output High Voltage 2 _. Z VOH2 (except CLKOUTS IOH= ~250pA vec -0.8 v [i [irouteskage corent wszvneves | =f = | ae pa | 3-state Output Leakage | Vss= Vout ILo £10 Current in Float svcc 220790 eS MPUZ80ASSP-150

(2/2) vec=5v ) fCLK =( 1) | eVIHR= ) icc1_ | Power Supply Current |VIHC=VIHR=VIH_ | ag.ag 45 =VCC-0.2V, VILC = VILR =ViIL=0.2V vec =5V fclk=( 1) 1cc2_| Stand-by Supply Current | VINC=VIH = VIHR pA (See Note (2)) EVCCO2V, VILC = VIL =VILR=0.2V vec =5v fCLK =( 1) 1cc3._|PowerSupply Current | VINC=VIH=VIHR 5 (IDLE1Modey | = VCC-0.2V, VILC = VIL =VILR =0.2V vec=5V fcLk=( 1) VIHC = VIH = VIHR 1cca | Power Supply Current (IDLE 2 Mode) =VCC-0.2V, AF-10 ViLC = VIL =VILR =0.2V | Tom | Notel: CLK =1/TeC (MIN) | Note2: 1CC2Stand-by Supply Current is guaranteed only when the supplied clock is stopped ata low level during T4 state of the following machine Cycle (M1) next to OP code fetch Cycle of HALT instruction. Except SYNCA=0 or SYNCB=0 state a MPUZBOASSP-151

4.3 AC Electrical Characteristics (1) (in Active State)

10MHz VERSION : TA=-40°C~70°C, VCC=5V+10%, VSS=0V

4.3.1 AC Characteristics of MPU (in Active State)

(12) SYMBOL PARAMETER (10MHz) UNIT Plo | om Ee ca [2 [wer leoacrusewiantia | asf = Poe | wm | | Ec | [-# [ne ecarottine i = | fo | | ca Co | [5 [rscct) —|oactiondsenvenaoeiy | = [= [75 | m | [7 fran wnsan — [aaares vata REO Joey | ef = f= Pw | [= frscromean leoacsomm@ioeey | = |= | stm] [= [racrmean [coc trommearoeay | = P= | 5] m | [io wiwneon [REO Pusewirn ok) |p = P= | ww | [x wear [REO Pe wish iow | ms = b= fo | [2 [racroweah [eto stoneGpoxy | = [= | lm | [fraction [eoacsieRByoeny ————~iP = f= P ef | [1 fracrion —[eoactiow5poeay t= P= | ssh os | [5 [roe ontaseuptinevocoa? | asf = | - | mw | [is Jomo) Jotsneidtinew At fof = | = Pm | [7 [rawarrich—|Wasewprinetocoary | asf = [=m | [1 |rawarten [WaT Hotineatercoky | wl =f = [om | [2 fracriwin —[accktiomijoewy iP = [= Pst | [20 fracrimie— [eoactrowtitoewy P= [= | sf om | [21 [racemes JetocettomsR Oey «t= P= | wo oe | [22 frscraesi[eoktiontsnpoeey [= P| ws | [22 fraction —Jeoacsiewtoeey dt = P= | [2 [recr@on —[eoactieRByoeuy P= [= bs] ww | eo [mas [fT Le T1080 MPUZBOASSP-152

(2R) : SYMBOL PARAMETER (10MHz) UNIT ne el [a [raceoroy[earweretoms | -[- | | =| [2s [eo —[oxasabirrorowny | «| — [= | w | fan fractowno | coacsrowtsoemy | - [= | S| os | a | [ae racrwats —[cecrstowroemy —[- [=| s| w | | [3s [raotwan | ones rerowaiy | =a — | - | w | | [3e frac [cert ioWonay [| - | 39] ws | | [ae [rawaro) | onesie omvtt | w= [= | ws | | [ae [ocr atn—[eoerstoratrtory = | m0] we | [sr fiw airusewan | sf [= [| [se [rssncorey | RREG wuptineeceay || = [=| | [ae [ravine | aeteav Tine atercoat |e [ — [= | w | [ao rec musncen [cow tiomtEACKuowy | - |= | 75] ws | [ar fracrousaccn | coacsontsReKt vay | = | — [5] oe | [a2 [recon | con ison nononey | — [| es] ow | fo facets | aed eae oct "| = [= | oo | [ae [acre | coartioatrentionoany | ~ [= | | w= | | [esac | Ricdioanmenomemete |e] = | - | | [ae [rnesri@) [Reece tseusine | [|= | w | [ar riser co —[REETn coc traTine | wf — | — | w | Fae funrten | rtochactsewprine sof — | = | w | [2 romeo —[wttociartwourine [0 [= | | w | [ae frawveonan_[Wrs RGioemy Pf — |= | w | [si ractnoron [ease oNGyoeay | - = | 8] | [ae rac voran feos tiioRatovwy | = | = | ss] | [55 racy [eas toon vaiaoniy | =| = [vol | MPUZ80ASSP-153

4.3.2 AC Characteristics of CGC (in Active State)

SYMBOL PARAMETER (10MH2) UNIT [han [re [| [se [ca Joupconcwe | - [we] -[ =] CLKOUT restart time by 2144 [9 [stows | INT (STOP. Mode) [> Baeel = [= | CLKOUT restart time by NMI (STOP 2144 ) CLKOUT restart time by 2.5 | |e | TRST(INT)! Tint (OLE 1/2 Mode) | = | Tec [- |= | CLKOUT restart time by NMI (IDLE 1/2 25 | 62. | TRST(NMI)| Mode) one CLKOUT restart time by RESET | | TASTORESET)! | oie 1/2 Mode) Tee 020790 Se MPUZ80ASSP-154,

4.3.3 AC Characteristics of CTC (in Active State)

SYMBOL PARAMETER (10MHz) UNIT [mane [re [wa Delay from M1 fall to |EO fall TdM1 (IEO) (in case of generating only interrupt . immediately before M1 cycle) : [ss | TdIEI (EOF) Delay from IE! fall to 1E0 fall [- [= [| = | Delay from IE! rise to EO rise fee rareeon (after ED decode) | - {=| | CLK/TRG setup to TL f for detection of | TcC interrupt +100 tsCTR (c) Satisfied +768 +748, 67 | IscLK (INT) tsCTR (<) not Satisfied 2TeC +100 +768 +748 TecTR CLK/TRG Frequency ore | (counter mode) [lien fewrmenimene P= T= a | TwCTR1 CLK / TRG Pulse Width (Low) [»|-[-[ =| Pfc fenrmensewanoan [t= |= | w | CLK/TRG ¢ to Clock Setup Time for 73 |TSCTR (Cs) Immediate count 110 ns (counter mode) CLK/TRG 7 to Clock 7 Setup Time for 74 |TSCTR (CT) enabling of Prescaler on following clock } (timer mode) | 75 [rac (2c/TOr) | Clock 4 to ZC/TO 7 Delay [= [= [re] ss | 710690 MPUZ80ASSP-155,

4.3.4 AC Characteristics of PIO (in Active State)

SYMBOL PARAMETER (1OMHz) UNIT Fe [a Td M1 (IEO) Delay from MT fall to EO fall | = [= [00 [ns | IEI Set-up time for IORQ fall 78 | TsiEI (10) (INTA cycle) ns TdIEl (EO) Delay from IE fall to IEO fall | - | - [so] ns | | | 80 |Tatei eon) Delay from IEI rise to IEO rise | = [= [120 [as | | | 81 [Tac(Rove) | Delay from clock fall to READY rise [ - | = [150 | ns | | | 82 [Tac(RDYA) _| Delay from clock fall to READY fall | - | = [a0] as | ) | 83 |TwstB(c) STROBE pulse width [100 [= | - | ns | ) Set-up time of STROBE rise for clock fall TssTB(¢) {in case of making READY to active by next cycle) Delay from IORO rise to port data TdlO (PD) stable (Mode 0) Port Data set-up time for STROBE rise | | TsPD (STB) (Mode 1) Output Port data delay time from 87 | TdSTB (PD) STROBE fall - (Mode 2) Delay from STROBE rise to data float TesTe (D0 (Mode 2) |- [=| pe |» | STROBE setup to TL f for detection of 350 | | IsSTRB interrupt +748 Port data stable setup to TL Tfor 350 detection of inter-rupt +748 (Mode 3) Data Hold time for STROBE rise Lo: | mre rs) (Mode 1) Pel-[-|*] Troe eee MPUZ80ASSP-156

4.3.5 AC Characteristics of SIO {in Active State)

(12) ‘TMPZ84C0158F-10 | SYMBOL PARAMETER (OMH2) UNIT [man [e.[ae | | IE! | to TORQ | Setup time a TSIEL (10) (INTACK cycle) Mi | to 10 | Delay || Ten (eo) (interrupt before M7) - [off | IEI} to IEO } Delay [2s frseicon | (after ED decode) [- | - [=f | 97 |Tdio (winws) TORQ | or CE | to WIRDY | Delay (Wait mode) Clock f to WIRDY | delay | | TAC(WIRRA) | Ready Mode) Clock | to WIRDY float delay foafrene | tortesme ids > = | [ios frwnecr [ae wet aw feol- [=| | [roefrwrich [Tee wis belle le | 105 ftdtxc (TxD) —_| THC Lto TxD delay (x1 mode) TdTxC (WRRf) | TxC | to WIRDY | delay (Ready mode) Ps] - | 2 [ck [iorfrae__[Rtaaeime Si f= | me | foe aici [seamen Si wm f= | | iow asc [Rac wie Pet= t= [os | TsRxD (Rxc) RxD to RxC T Setup time (x1 mode) ThRxD (Rxo) RxC f to RxD hold time {x1 mode) RxC f to WIRDY | delay CLK | TARxCOW/RRA | (eeaciy mode) Periods RxC } to SYNC | delay CLK 193 |TARKC (SYN) | Ont mode) 7 | periods 710680 MPUZ80ASSP-157

(2) TMPZ84C0158F-10 SYMBOL PARAMETER (0MH2) UNIT [nan [ re. [wa | SYNC | to RxC 7 Setup [| TSSYNC(RX®) | (external SYNC modes) IsTxe TxC | Setup to TL f for detection of 5471 9471 interrupt +748 +748 RKC f Setup toTL f fordetectionof | 104T1 1BaT1 interrupt +148 +748 110690 | 4.3.6 AC Characteristic of WOT (in Active State) : TMPZ84C015BF-10 SYMBOL PARAMETER (10MHz) UNIT [nan [ve [wa Tde (WDTF) Clock to WOTOUT | Delay [ - | = [120 [ns | Tde (WOT) Clock t to WOTOUT 7 Delay [= [= [2s [ons | WOTOUT Out put period WOT Mode 0 14216| 119 |TewoT WOT Mode 1 14218] WDT Mode 2 14220 WOT Mode 3 14222 10690 Note 1: ‘Timing Measurements are made at the following voltage. Input VIH=2.4V, VIL=0.4V, VIHC=VCC -0.6V, VILC=0.6V Output VOH =2.2V, VOL=0.8V (Exept CLKOUT) CL=100pF ee MPUZB80ASSP-158

44 AC Timing Charts (1) (in Active State)

4.4.1 AC Timing Charts of MPU (in Active State)

these charts correspond to the numbers in the number column of the AC Electrical | Characteristics Tables. T1 2 TW 3 4 6 i aon Od |KO Aoror 1 Program Counter i, IO) | oe OkyO Olly ® MREQ \\ Om: y ° er Oi Pal | | wart | we [e#—— oO) @l-l| +1 —-@ Do~p7 fo gx H CD RFSH | som Figure 4.4.1 Opcode Fetch Cycle MPUZ80ASSP-159

“to bh EE [= © A0~A15 i 4 Program¢ounter _|| a He= [oo | of & MRE i

7 Ta] at

@ @, WAIT a | ye | ie Read operation ie) e-] input data D0~D7 oc Gl Cl =x ae 1G) WR i © 5 @\\— Write operation @) >! = @ | DO~D7 Data output senses Figure 4.4.2. Memory Read /Write Cycle

12 Tw* Tw 3

CLKIN fi i" h lot bk’ HS ao~a7 [RTT Portaddress | ota | @ i 8! ol etre I ¢+-+e war N*N Hf woe ig: iT it ome +1@ | ® 3 Input data Do~D7 Tt CK C7} om ® l@ Output oars. PSs 9 ie) DO~D7 output data Note 1: wait state (TW*) is inserted automatically by MPU. 300389 Figure 4.4.3 1/0 Cycle eee MPUZ8OASSP-160

|<— m1 —-+----- | CLKIN 4 a 72 oxfys eo RESET L/ a®O\\< Mi 7 RD, WR TORQ RFSH BUSACK HALT 300389 Figure 4.4.8 Reset Cycle

4.4.2 AC Timing Charts of CGC (in Active State)

The following Figures show the timings in each operation mode with the CLKOUT pin connected to the CLKIN pin. | Ore +! Figure 4.4.9 CLKOUT Waveform

1 T2 3

CLKOUT ™4 © @-+- +l-@ INT e——| NMI 300289 Figure 4.4.10 Clock Restart Timing (STOP Mode) MPUZ80ASSP-163

4.4.3 AC Timing Charts of CTC (in Active State)

. | Mi — a 1E1 | 1EO | | @-| i @ | cLK/TRGO-3 " ; {Counter mode) . (gukTeGo3 imer mode! ZC /TOo-3 eee 200388 Figure 4.4.14 CTC Timing Diagram TL akin JS \\ S/S Lig | er aan INT ee er | i . CLK /TRGO-3 ———— TL: Laststate of instruction 300308 Figure 4.4.15 CTC Interrupt Occurrence Timing MPUZ80ASSP-165

4.4.4 AC Timing Charts of PIO (in Active State)

QiQ)|_O CLK IN om © im TOR’ mi + te! @ rl eo —lsy—le, | | eye (ARDY Of 'BADY 4 i) (ARI PR NY) Sreowe ‘) 2 (ASTB OR BSTB) + | MODEO on PAO~PA7 } MODE? y y ) PBO~PB7 —, mopé2 es Figure 4.4.16 PIO Timing Diagram Tt a a (ASTB OR BSTB) PBO~PB7 MODE3 $A TL: Last state of instruction 300388 Figure 4.4.17 PIO Interrupt Occurrence Timing eee MPUZ80ASSP-166

4.4.5 AC Timing Charts of SIO (in Active State)

CLKIN T4173 aa) alo! - || 2] |@.| mt | ol | ® 1EO WIRDY es K \\ 300389 Figure 4.4.18 (a) SIO Timing Diagram a MPUZB0ASSP-167

FS, BCD, SYNE ep ee os Oe -—— © Tx @ (C) (c) 2) TxD W/RDY a @ [-—®@ -—e ~@ 9 SYNT @B co) 3oo3e9 Figure 4.4.18 (b) SIO Timing Diagram MPUZ80ASSP-168

akin J \\H_/ \\g 11, iiatestestaieatetenteteteteieteenetate senate ae + © — pa RXC TL: Last state of instruction 300289 Figure 4.4.19 SIO Interrupt Occurrence Timing

4.4.6 AC Timing Charts of WDT (in Active State)

Figure 4.4.20 WDT Timing Diagram oe MPUZ80ASSP-169

4.5 AC Electrical Characteristics (2) (in Inactive State)

. TA=—40°C~ +70°C, VCC =5V+10%, VSS=0V | 45.1 AC Characteristics of CGC (in Inactive State) TMPZ84C015BF-10 SYMBOL PARAMETER (10MHz) UNIT [anc [wv [ra [= [rwcnere —Jouiparcearwnaniany | = | | = | | [4 Irie Joutntcioaatine f= | wf = fw | [5 [recie Joudoarraetine | = | | | | Clock (CLKOUT) restart Time by INT. 24+ «| TRST(INDS _l’sToP mode) 2.5TcC Clock (CLKOUT) restart Time by NMI 2144 7 [TRSTINMDS [STOP mode) 2.5Tcc Clock (CLKOUT) restart Time by INT 25 | | TRST(INT | lGDLE172 mode) aTec ‘Clock (CLKOUT) restart Time by NMI 25 | Le | TRST (NMI | (IDLE 1/2 mode) Tce Clock (CLKOUT) restart Time by RESET : | | TRST (RESET) I (IDLE 1/2 mode) 1TcC Lis [rsnaurom [HatTsetuptime fo | = | | me | 070790

4.5.2 AC Characteristics of CTC (in Inactive State)

(1) ‘TMPZ84C015BF-10 SYMBOL PARAMETER (1oMHz) UNIT | mn. | rve. [wax | [2 fc Tetecxeyeetine [too f= = [oe | [23 [rwcn [roe with gm | [= [= [os | Clock width (Low) | 38 | = |= Pos | [ss [ric [clock tating time [= | fe [os [16 [rc fetockrsngtine P| | oe | Jz fm roidtime to P= f= Pe | [18 [recs estar. aorsetuptinetococet | 100 | = | — | m | | 19 [rsce( |eetar~aaysetupemetocoat [so | = | — | mm | TORQ Set uptime to dock h [es [= T= [is | w2079 ee MPUZBOASSP-170

SYMBOL PARAMETER (10MHz) UNIT Law [ve ae | ee eran Ts T-.- Pe] | 22 [tac (00) Clock to Data Valid Delay [— | - [0] as | | Tdc (DOz) TORO, RD} to Data Float Delay [= | - | a5] ns | | | 24 [tacr(mif —_ [Data input set up time to clock [ ao | - | = | ns | [2s [omc ——[atsetiptneweearg | ss [= [= [| Mi | to EO | Delay 26 | TdM1 (IEO) (in case of generating only interrupt immediately before M1 cycle) TAIEI(IEOA [IE to EO | Delay [- |= | | os | TAIEI(IEOA) _|IEITt01EO Delay (after EDdecode) | — | — | 160| as | ICLK/TRG 7 to INT | Delay | Tec TSCTR (c) Satisfied +H10 | + ' 31 | TdA (lORQF) 2TcC TsCTR (c) not Satisfied + Ww [a fea [errs teaomg re = [as fem ———Jerrrmerinsine” == wf | ICLK/TKG f to clock 7 Setup 37 | TsCTR (CS) Time for Immediate Count 110 (counter mode) ICLK/TRG To clock Setup Time for enabliling of Prescaler on TSCTR (CT) following clock t 110 (timer mode) Tdc(Zc/TOr) | Clock t to 2C/TO f Delay [ - [| - [10 | ns | 0790 MPUZBOASSP-171

4.5.3 AC Characteristics of PIO (in Inactive State)

SYMBOL PARAMETER (10MHz) UNIT Pan [rw CE(A7 to A2), B/A(A)), C/D(Ao) Set up «| TSS (RN Time to RD, IORO [ae fe oatine [sao fs ascpinewaeat fa [=] =| | [ee fra00)—R6.0R04 womowtory | = [= [am | w | TdRI (DOs) IRD, TORQ 7 to Data float Delay [- |= | 7] ms | [ 46 [TsD1(c) Data Set up time to clock P [ 40 | = | - | os | TdlO (DO!) TOR® J to Data out Delay INTACycle) | — | — | a5 | ns _| [ss [raney iy Seopinesocsaet | P= P= | IMT | tolEO | Delay 50 |TdN1 (IEO) (interrupt immedi-ately receding Mii |) TdIEI (IEOF) IEl | tolEO | Delay [- |= | 7] os | | 54 [Taio TORQ Set up time to Clock J [20 [ = | - | ns | [55 rscwova eon swntaort ovey [= [=m | | TwsTB (C) STROBE Pulse width | 0 [ - | — | ns | Set up time of STROBE rise for clock fall TSSTB (C) {in case of making READY to active by next cycle) Delay from IORQ rise to Port data stable Port data set up time for STROBE rise | TsPD (STB) fede Output Port data delay time from | | TASTB(PD) STROBE fall (Mode 2) Delay from STROBE rise to Port data 62 | TdSTB (PDr) float (Mode 2) 120 ns TdPD (INT) Delay from port data match to INT fall 350 (Mode 3) | 64 [Taste (int) [Delay from STROBE rise to INT fall | - [ = | 250 | 070790 eee MPUZ80ASSP-172

4.5.4 AC Characteristics of SIO (in Inactive State)

(12) TMPZ84C015BF-10 ! SYMBOL PARAMETER (10MHz) UNIT | Fin [ve [| CE (A7 to A2) ,C/D (A), | [ee frm [ore WsetvpTinewoaort | ss [- | - | we | | [er [recor |eoetioontououroemy | - |= [wo | = | Data input set up time to clock t oe | TSDI(C) (write cycle or Mi cycle) [os [rano(608 AB Twooswoerowoeay |= |= | w| =| TORQ | to Data out put Delay | 70 |TdiO (DON) (INTACK cycle) | [fame |isetsptmetooat | [= [=| =| TsIEI (10) TEI Set up time to TORO | (INTACK Cycle) | 80 | — | — | as | IMT | tolEO | Delay 73 [Tam (Eo) (interrupt before M1) rasiicon fmiyonouomy | - | - | | = | TORQ, CE (A7 to A2) | to _ 77 |TdIO(W/ RWE) WIRDY | Delay (Wait Mode) 130 ns Clock | to WIRDY Float Delay , (Wait Mode) |- |-[ [| Th, Th (Cs) Any unspecified hold When set up is specified [a2 [wer [rue wien tow [200 [= [= [| [a fine [towered f= fo | [86 [Tdtxc(TxD) _|TxC | to TxD Delay (x1 Mode) [= | = | 180 | ns | re Sto WIRDY | Delay (Ready mode) Ps | - | 2 pc [as [rave fiecyaerme is T= | | w20790 MPUZB80ASSP-173

(22) TMPZ84C0158F-10 SYMBOL PARAMETER (0MHz) UNIT an [ve oa TsRxD (RxC) RxD to RxC 7 Set up time (x1 mode) | of - | - [ms | | 93 [thax (exc) [RKC toRADHoldtime(tmode) | 80 | — | — | vs | |e | TdRxC (W/RRF) |RxC f to WIRDY J Delay (Ready mode) [| - [=| pate. ds

25 TdRxC (INT) RXC f to INT | Delay le] -[*] rents

2s | TdRxC (SYNC) [RKC to SYNC J Delay (output modes) l«[-{ 7] pain ‘is SYNC | to RxC } Set up Time

97 J TSSYNC(RXC) _Texternal sync modes)

| 98 | TsAdd (Cr) Address Set up time to clock | 50 [ - [= [ns | | 99 |ts10 (cn TORO | Set up time to clock f [| 7 | - [= [os | [ 100 | TARD (Cr) RD | Set up time to clock [7 [ = [= | ns | | 101 |Técr Do) Data out Delay to clock f [ - | - | 130] os | TdlORDr (Doz) _|Data Float Delay to1ORQ} , RD? | - | - |] ns | TsWR (Cr) WR | Set up time to clock } [|= | - [ms | TsDI (Cr) Data Input Set up time to clock ? | o[-|[- | - | [ 105 | TdlOwRg (D) Data Hold time to TORQ 7, WRT [ 2 - | — | os | corse eee MPUZ80ASSP-174

4.5.5.AC Characteristics of WDT (in Inactive State) ‘TMPZ84C015BF-10 SYMBOL PARAMETER (10MHz) UNIT | [ean [ye [wa | | worourt oe f= |= [ws | | |WOTOUT out put period \\WDT Mode 0 T12, | me WDT Mode 1 T12, 108 | TwoT 218 WOT Mode 2 Ti, 220 WOT Mode 3 TI, 222 ‘20790 Notel: Timing Measurements are made at the following voltage. Input VIH=2.4V, VIL=0.4V VIHC=VCC-0.6V, VILC=0.6V Output VOH=2.2V, VOL=0.8V (Except CLKOUT) | CL=100pF MPUZ80ASSP-175

4.6 AC Timing Charts (2) (in Inactive State)

4.6.1 AC Timing Charts of CGC (in Inactive State)

The following Figures show the timing charts in each operation mode with the CLKOUT pin connected to the CLKIN pin. CLKOUT = -O- 300309 Figure 4.6.1 CLKOUT waveform

1 T2 13

CLKOUT ™ —O® One +0 wr NMI 300389 Figure 4.6.2 Clock restart timing (STOP mode) ee MPUZ80ASSP-176

Figure 4.6.3 Clock restart timing (IDLE1 mode) act S VHS VS VS m1 ir) INTERNAL 4 cuK es a TNT ko ———| nwt mt 300389 Figure 4.6.4 Clock restart timing (IDLE2 mode) Nh cLKOUT reseed rill el eels reser 300389 Figure 4.6.5. Timing of clock restart by RESET (IDLE1, IDLE2 mode) Ta th i Ts Te ak J/J~\\_fP VS VS VY NN HALT \\ @ soo3e9 Figure 4.6.6 Clock suspension timing (IDLE1,IDLE2 and STOP modes) MPUZ80ASSP-177

4.6.2 AC Timing Charts of CTC (in Inactive State)

©) ® ‘CLKIN: i Gh =e fA | tes M es Se a =e : | Fe r4 te | ke= tet DATA | ft oe |e — tt 7 6 Go.1 A SS | Se g |" a a l-K=s ot - ee | ees ——— ao DATA a a _ [Pea wm @ sagow| sg = _ Ki} _ [== a ait, ©7| SS us Le) ols eH crimer moos zie ot Lol Figure 4.6.7. CTC timing diagram (Inactive) ee MPUZ80ASSP-178

4.6.3 AC Timing Charts of PIO (in Inactive State)

| Qi @/.@ | CLKIN = TE(A7~A2) @ | | B/A(AN),C/B (A0) | ON Set et || | RD, TORO De ee, | | or out a ovor{ ete 'N a — =~— 1,24 4 wn I ot tel © le, | | @ Lele, |e READY f= —\\ | (ARDY OR BRDY) u (STB ORBSTS) @— Pao~Paz, me a rac INT _@_. Figure 4.6.8 PIO timing diagram (Inactive) a MPUZ80ASSP-179

TOSHIBA ‘TMPZ84C015B TOSHIBA tna

4.6.4 AC Timing Charts of SIO (in Inactive State)

Oy |e _ CLKIN caFea2y dt Od) h [o! 2 ile & Do~D7 {PF ms fey TORQ Ho] Te MT re} tel 1EO ~—-@ INT WIRDY Figure 4.6.9 SIO timing diagram (a) (Inactive) eee MPUZBOASSP-180

-__@ Ser ee | | TxD | WIRDY Be ® }-@: ® 'WIRDY w ei 300389 Figure 4.6.9 $IO timing diagram (b) (Inactive) MPUZBOASSP-181

4.6.5 AC Timing Charts of WDT (in Inactive State)

(The mode setting and daisy chain interrupt setting registers on WDT) T71 T2 Tw 3 CLKIN I Ay~Ag K | TORS id Re © “ow Po 5 | Ar~Ao K | | TORO re | Wr (Oe = WDTOUT Figure 4.6.10 RD/WRITE, WOTOUT timing Diagram a MPUZ80ASSP-182

4.7 Pin Capacitance

SYMBOL ITEM TEST CONDITION [ min. | tye. | max. | unit | Clock Input Capacitance [- | -] F=1MHz | Ailtermnalsexceptthatto |= | > | 78 COUT | Output Capacitance be measured be earthed [- | - | 220790 a MPUZ80ASSP-183

1. EXTERNAL DIMENSIONS QFP100-P-1420A,

23.8403 Unit : mm

80 1) £ HON ONOANRONOORONOGHLADCAONND st sei Ea 5 ne u I 30 « x E23 :| = fos 28203} ee MPUZ80ASSP-184

TOSHIBA (UC/UP) L3E D m™.9097249 OO17b80 T i _ TOSHIBA TMPZ84C015A TOSHIBA __rrezaconsan 5. EXETERNAL DIMENSIONS T-49-17-07 QFP100-P-14208 3 Unit: mm 0.65 wong coy ee ignaomapamno tonnigg = = Liang = = = | ni EVEDEPEUEUPUEEUPE RUT UU SUR EU TEENY Ho WOOO UOIUO {7 14.020.1 No.s0 16.220.4 LEDS Van 28, 3 fe 3 JN CE é 19.640.3 / MPUZ80-757